WO2022170661A9 - 阵列基板及其显示面板和显示装置 - Google Patents
阵列基板及其显示面板和显示装置 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 283
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 107
- 239000004065 semiconductor Substances 0.000 claims description 161
- 239000003990 capacitor Substances 0.000 claims description 56
- 238000003860 storage Methods 0.000 claims description 42
- 239000000463 material Substances 0.000 claims description 33
- 230000006641 stabilisation Effects 0.000 claims description 30
- 238000011105 stabilization Methods 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 239000010410 layer Substances 0.000 description 509
- 238000010586 diagram Methods 0.000 description 34
- 230000000694 effects Effects 0.000 description 18
- 238000000034 method Methods 0.000 description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 12
- 230000008569 process Effects 0.000 description 9
- 230000033228 biological regulation Effects 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 238000005265 energy consumption Methods 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 230000004044 response Effects 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000002834 transmittance Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910001182 Mo alloy Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000001808 coupling effect Effects 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000368 destabilizing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001782 photodegradation Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- -1 region Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
Definitions
- Embodiments of the present disclosure relate to the field of display technologies, and in particular, relate to an array substrate, a display panel thereof, and a display device.
- Organic light-emitting diode Organic Light-Emitting Diode, OLED
- OLED Organic Light-Emitting Diode
- Embodiments of the present disclosure provide an array substrate and related display panels and display devices.
- an array substrate including a substrate.
- the array substrate also includes a plurality of sub-pixels disposed on the substrate and arranged in multiple rows and columns. At least one of the plurality of sub-pixels includes a pixel circuit.
- Each pixel circuit includes: a driving circuit, a voltage stabilizing circuit, a driving reset circuit and a light emitting reset circuit.
- the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to provide a driving current to the light emitting device.
- the voltage stabilizing circuit is coupled to the control terminal, the first node and the voltage stabilizing control signal input terminal of the driving circuit, and is configured to control the driving circuit under the control of the voltage stabilizing control signal from the voltage stabilizing control signal input terminal. terminal and the first node conduction.
- the driving reset circuit is coupled to the driving reset control signal input terminal, the first node and the driving reset voltage terminal, and is configured to control the driving reset voltage terminal from the driving reset voltage terminal under the control of the driving reset control signal from the driving reset control signal input terminal.
- the reset voltage is provided to the voltage stabilizing circuit to reset the control terminal of the driving circuit.
- the lighting reset circuit is coupled to the lighting reset control signal input terminal, the light emitting device and the lighting reset voltage terminal, and is configured to reset the lighting from the lighting reset voltage terminal under the control of the lighting reset control signal from the lighting reset control signal input terminal
- a voltage is supplied to the light emitting device to reset the light emitting device.
- the array substrate also includes driving reset voltage lines and light emitting reset voltage lines.
- the driving reset voltage line is coupled to the driving reset voltage end to provide a driving reset voltage.
- the light-emitting reset voltage line is coupled to the light-emitting reset voltage end to provide a light-emitting reset voltage.
- the driving circuit includes a driving transistor.
- the voltage stabilizing circuit includes a voltage stabilizing transistor.
- the drive reset circuit includes a drive reset transistor.
- the light emission reset circuit includes a light emission reset transistor.
- the first pole of the driving transistor is coupled to the first terminal of the driving circuit, the gate of the driving transistor is coupled to the control terminal of the driving circuit, and the second pole of the driving transistor is coupled to the second terminal of the driving circuit.
- the first pole of the voltage stabilizing transistor is coupled to the control terminal of the driving circuit, the gate of the voltage stabilizing transistor is coupled to the voltage stabilizing control signal input end, and the second pole of the voltage stabilizing transistor is coupled to the first node.
- the first pole of the drive reset transistor is coupled to the drive reset voltage terminal, the gate of the drive reset transistor is coupled to the drive reset control signal input terminal, and the second pole of the drive reset transistor is coupled to the first node.
- the first pole of the light-emitting reset transistor is coupled to the light-emitting reset voltage terminal, the gate of the light-emitting reset transistor is coupled to the light-emitting reset control signal input terminal, and the second pole of the light-emitting reset transistor is coupled to the first end of the light-emitting device .
- the active layer of the voltage stabilizing transistor includes an oxide semiconductor material. Active layers of the drive transistor and the drive reset transistor include silicon semiconductor material.
- the active layer of the light emitting reset transistor includes an oxide semiconductor material.
- the array substrate further includes: a first active semiconductor layer on the substrate, the first active semiconductor layer includes a silicon semiconductor material; A second active semiconductor layer on one side and insulated from the first active semiconductor layer, the second active semiconductor layer includes an oxide semiconductor material.
- the first active semiconductor layer includes an active layer driving a transistor and an active layer driving a reset transistor.
- the second active semiconductor layer includes first and second portions arranged in a column direction.
- the first portion of the second active semiconductor includes the active layer of the voltage regulator transistor.
- the second portion of the second active semiconductor includes the active layer of the light emitting reset transistor.
- the first portion of the second active semiconductor is aligned with the second portion of the second active semiconductor in a column direction.
- the pixel circuit further includes a data writing circuit, a compensation circuit, a storage circuit, and a light emission control circuit.
- the data writing circuit is coupled to the data signal input end, the scan signal input end and the first end of the driving circuit, and is configured to provide the data signal from the data signal input end under the control of the scan signal from the scan signal input end. to the first terminal of the drive circuit.
- the compensation circuit is coupled to the second terminal of the drive circuit, the first node and the compensation control signal input terminal, and is configured to perform threshold compensation on the drive circuit according to the compensation control signal from the compensation control signal input terminal.
- the storage circuit is coupled to the first power supply voltage terminal and the control terminal of the driving circuit, and is configured to store a voltage difference between the first power supply voltage terminal and the control terminal of the driving circuit.
- the lighting control circuit is coupled to the lighting control signal input terminal, the first power supply voltage terminal, the first terminal and the second terminal of the driving circuit, the lighting reset circuit and the light emitting device, and is configured to receive the lighting control signal from the lighting control signal input terminal. Applying the first power supply voltage from the first power supply voltage terminal to the driving circuit under control, and applying the driving current generated by the driving circuit to the light emitting device.
- the data writing circuit includes a data writing transistor.
- the compensation circuit includes a compensation transistor.
- the storage circuit includes a storage capacitor.
- the light emission control circuit includes a first light emission control transistor and a second light emission control transistor.
- the first pole of the data write transistor is coupled to the data signal input end, the gate of the data write transistor is coupled to the scan signal input end, and the second pole of the data write transistor is coupled to the first end of the drive circuit. catch.
- the first pole of the compensation transistor is coupled to the second terminal of the driving circuit, the gate of the compensation transistor is coupled to the compensation control signal input terminal, and the second pole of the compensation transistor is coupled to the first node.
- the first pole of the storage capacitor is coupled to the first power supply voltage terminal
- the second pole of the storage capacitor is coupled to the control terminal of the driving circuit, and is configured to store a voltage between the first power supply voltage terminal and the control terminal of the driving circuit Difference.
- the first electrode of the first light emission control transistor is coupled to the first power supply voltage terminal
- the gate of the first light emission control transistor is coupled to the light emission control signal input end
- the second electrode of the first light emission control transistor is connected to the drive circuit.
- the first end is coupled.
- the first electrode of the second light emission control transistor is coupled to the second end of the driving circuit
- the gate of the second light emission control transistor is coupled to the light emission control signal input end
- the second electrode of the second light emission control transistor is connected to the second end of the drive circuit.
- the first pole of the light emitting device is coupled.
- the first active semiconductor layer includes an active layer of a data write transistor, a compensation transistor, a first light emission control transistor, and a second light emission control transistor.
- the light emission reset control signal and the light emission control signal are the same signal.
- the scan signal and the compensation control signal are the same signal.
- the array substrate further includes a first conductive layer.
- the first conductive layer includes a drive reset control signal line, a scan signal line, a gate of a drive transistor, a first pole of a storage capacitor, and a light emission control signal line arranged in sequence along the column direction.
- the drive reset control signal line is coupled to the drive reset control signal input end and is configured to provide the drive reset control signal thereto.
- the scan signal line is coupled to the scan signal input end and the compensation control signal input end, configured to provide a scan signal to the scan signal input end, and configured to provide a compensation control signal to the compensation control signal input end.
- the first pole of the storage capacitor is integrated with the gate of the driving transistor.
- the light emission control signal line is coupled to the light emission control signal input end and configured to provide the light emission control signal thereto.
- the overlapping portion of the orthographic projection of the drive reset control signal line on the substrate and the orthographic projection of the first active semiconductor layer on the substrate is the gate of the drive reset transistor.
- the overlapping portion of the orthographic projection of the scanning signal line on the substrate and the orthographic projection of the first active semiconductor layer on the substrate is the gate of the compensation transistor and the gate of the data writing transistor.
- the overlapping portion of the orthographic projection of the light emission control signal line on the substrate and the orthographic projection of the first active semiconductor layer on the substrate is the gate of the first light emission control transistor and the gate of the second light emission control transistor.
- the array substrate further includes a second conductive layer located between the first conductive layer and the second active semiconductor layer and insulated from the first conductive layer and the second active semiconductor layer .
- the second conductive layer includes voltage stabilization control signal lines arranged along the column direction, a second pole of the storage capacitor, a first power supply voltage line and a light emission reset control signal line.
- the voltage regulation control signal line is coupled to the voltage regulation control signal input end and is configured to provide a voltage regulation control signal thereto.
- the first power supply voltage line is coupled to the first power supply voltage terminal and configured to provide the first power supply voltage thereto.
- the second pole of the storage capacitor at least partially overlaps the orthographic projection of the first pole of the storage capacitor on the substrate.
- the second pole of the storage capacitor is integrally formed with the first power supply voltage line.
- the light-emitting reset control signal line is coupled to the light-emitting reset control signal input end and configured to provide a light-emitting reset control signal thereto.
- the overlapping portion of the orthographic projection of the voltage stabilizing control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the first control electrode of the voltage stabilizing transistor.
- the overlapping portion of the orthographic projection of the light emission control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the first control electrode of the light emission reset transistor.
- the array substrate further includes a third conductive layer located on a side of the second active semiconductor layer away from the substrate and insulated from the second active semiconductor layer.
- the third conductive layer includes voltage stabilization control signal lines, light emission reset control signal lines, and light emission reset voltage lines arranged along the column direction.
- the overlapping portion of the orthographic projection of the voltage stabilizing control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the second control electrode of the voltage stabilizing transistor.
- the overlapping portion of the orthographic projection of the light emission control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the second control electrode of the light emission reset transistor.
- the light-emitting reset voltage line is coupled to the second active semiconductor layer through the via hole to form the first pole of the light-emitting reset transistor.
- the array substrate further includes a fourth conductive layer located on the side of the third conductive layer away from the substrate and insulated from the third conductive layer, the fourth conductive layer includes a first connection portion, The second connection part, the third connection part, the fourth connection part, the fifth connection part, the sixth connection part, the seventh connection part, and the eighth connection part.
- the first connection portion serves as a driving reset voltage line.
- the first connection portion is coupled to the drain region of the drive reset transistor through the via hole, forming a first pole of the drive reset transistor.
- the second connection part is coupled to the light-emitting reset voltage line through the via hole.
- the third connection portion is coupled to the drain region of the data writing transistor through the via hole, forming a first pole of the data writing transistor.
- the fourth connecting portion is coupled to the source region of the drive reset transistor and the source region of the compensation transistor through the via hole, forming a second pole of the drive reset transistor and a second pole of the compensation transistor respectively.
- the fourth connection portion is coupled to the source region of the voltage stabilizing transistor through the via hole to form a second pole of the voltage stabilizing transistor.
- the fifth connection part is coupled to the gate of the driving transistor and the first pole of the storage capacitor through the via hole, and the fifth connection part is coupled to the drain region of the voltage stabilizing transistor through the via hole to form a first electrode of the voltage stabilizing transistor.
- the sixth connection portion is coupled to the drain region of the first light emission control transistor through the via hole to form a first electrode of the first light emission control transistor.
- the seventh connection part is coupled to the source region of the second light emission control transistor through the via hole to form the second pole of the second light emission control transistor
- the seventh connection part is coupled to the source region of the light emission reset transistor through the via hole. connected to form the second pole of the light-emitting reset transistor
- the eighth connection portion is coupled to the source region of the light-emitting reset transistor through the via hole to form the first pole of the light-emitting reset transistor.
- the array substrate further includes a fifth conductive layer located on a side of the fourth conductive layer away from the substrate and insulated from the fourth conductive layer.
- the fifth conductive layer includes data signal lines, first power supply voltage lines, and second power supply voltage lines arranged along the row direction.
- the data signal line extends along the column direction and is coupled to the third connection portion of the fourth conductive layer through the via hole.
- the first power supply voltage line extends along the column direction and is coupled to the third connection portion of the fourth conductive layer through the via hole.
- the second power supply voltage line extends along the column direction and is coupled to the seventh connection portion of the fourth conductive layer through the via hole.
- a display panel includes the array substrate according to any one of the first aspects.
- a display device comprises a display panel according to any one of the second aspects.
- FIG. 1 shows a schematic block diagram of an array substrate according to the present disclosure
- Fig. 2 shows a schematic block diagram of a sub-pixel according to an embodiment of the present disclosure
- FIG. 3 shows a schematic diagram of the pixel circuit in FIG. 2 according to an embodiment of the present disclosure
- FIG. 4 shows a timing diagram of signals driving the pixel circuit in FIG. 3 according to an embodiment of the present disclosure
- FIG. 12 shows a schematic plan layout of a pixel circuit including a stacked active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer;
- FIG. 13 shows a schematic cross-sectional structure diagram of the array substrate taken along line A1A2 in FIG. 12 according to an embodiment of the present disclosure
- FIG. 14 shows a schematic cross-sectional structure diagram of the array substrate taken along line A1A2 in FIG. 12 according to an embodiment of the present disclosure
- FIG. 15 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure
- FIG. 16 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure
- FIG. 17 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure.
- FIG. 18 shows a schematic plan layout of a pixel circuit including a stacked shielding layer, an active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer;
- Fig. 19 shows a schematic structural diagram of a display panel according to an embodiment of the present disclosure
- FIG. 20 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure
- Fig. 21 shows a schematic diagram of a pixel circuit according to an embodiment of the present disclosure
- Figure 22 shows a schematic diagram of an occlusion layer according to an embodiment of the present disclosure
- FIG. 23 shows a planar layout of a pixel circuit of an embodiment of the present disclosure
- FIG. 24 shows a planar layout of a pixel circuit of an embodiment of the present disclosure
- FIG. 25 shows a planar layout of a pixel circuit of an embodiment of the present disclosure
- FIG. 26 shows a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present disclosure
- FIG. 27 is a schematic circuit diagram of a pixel driving circuit in an exemplary embodiment of an array substrate of the present disclosure
- FIG. 28 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 27;
- FIG. 29 is a structural layout of an exemplary embodiment of an array substrate of the present disclosure.
- FIG. 30 is a structural layout of the light-shielding layer in FIG. 29;
- FIG. 31 is a structural layout of the first active layer in FIG. 29;
- FIG. 32 is a structural layout of the first gate layer in FIG. 29;
- FIG. 33 is a structural layout of the second gate layer in FIG. 29;
- FIG. 34 is a structural layout of the second active layer in FIG. 29;
- FIG. 35 is a structural layout of the third gate layer in FIG. 29;
- FIG. 36 is a structural layout of the first source-drain layer in FIG. 29;
- FIG. 37 is a structural layout of the light-shielding layer and the first active layer in FIG. 29;
- FIG. 38 is a structural layout of the light-shielding layer, the first active layer, and the first gate layer in FIG. 29;
- FIG. 39 is a structural layout of the light shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG. 29;
- FIG. 40 is a structural layout of the light-shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG. 29;
- FIG. 41 is a structural layout of the light-shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG. 29;
- Fig. 42 is a structural layout of an exemplary embodiment of an array substrate of the present disclosure.
- FIG. 43 is a structural layout of the second source-drain layer in FIG. 42;
- FIG. 44 is a structural layout of an exemplary embodiment of an array substrate of the present disclosure.
- FIG. 45 is a structural layout of the second source and drain layer in FIG. 44;
- Fig. 46 is a schematic structural diagram of a second initial signal line in another exemplary embodiment of an array substrate of the present disclosure.
- Fig. 47 is a schematic structural diagram of a second initial signal line in another exemplary embodiment of an array substrate of the present disclosure.
- FIG. 48 is a partial cross-sectional view along dashed line B in FIG. 42 .
- a reset voltage is provided by the same reset voltage line to reset the light emitting device and the pixel circuit.
- the value of the reset voltage is set in consideration of the energy consumption level of the pixel circuit and the display effect after compensation, and under the condition that the reset light-emitting device is kept in an unlit state. In this case, the energy consumption of the pixel circuit, the display effect after compensation, and the charging time of the light-emitting device after reset cannot be in the optimal state at the same time, which will affect the energy consumption, response speed, accuracy, and display of the pixel circuit. Effect.
- At least some embodiments of the present disclosure provide an array substrate including two reset voltage lines, a driving reset voltage line and a light emitting reset voltage line.
- the driving reset voltage line is coupled to the driving reset voltage end to provide the driving reset voltage.
- the light-emitting reset voltage line is coupled to the light-emitting reset voltage end to provide a light-emitting reset voltage.
- the driving reset voltage may be set in consideration of the power consumption level of the pixel circuit and the reset effect. In the case of a relatively low power consumption level, the pixel circuit is reset more thoroughly, thereby improving the display effect.
- the light-emitting reset voltage line is coupled to the light-emitting reset voltage end to provide a light-emitting reset voltage.
- the light-emitting reset voltage can be set under the condition that the light-emitting device is just not turned on, thereby reducing the charging time of the light-emitting device before emitting light, thereby improving the response speed of the pixel circuit to the light-emitting signal, shortening the response time, and improving the probability. Accuracy.
- FIG. 1 shows a schematic diagram of an array substrate 10 according to the present disclosure.
- the array substrate 10 includes a substrate 300 and a plurality of sub-pixels SPX disposed on the substrate 300 and arranged in multiple rows and multiple columns.
- the substrate may be a glass substrate, a plastic substrate, or the like.
- the display area of the substrate 300 includes a plurality of pixel units PX, and each pixel unit may include a plurality of sub-pixels SPX, for example three.
- the sub-pixels SPX are arranged at intervals in the row direction X and the column direction Y.
- the row direction X and the column direction Y are perpendicular to each other.
- At least one of the subpixels SPX includes a pixel circuit.
- the array substrate 10 also includes driving reset voltage lines and light emitting reset voltage lines.
- the drive reset signal line is coupled to the drive reset voltage terminal and configured to provide the drive reset voltage thereto.
- the light-emitting reset voltage line is coupled to the light-emitting reset voltage terminal and configured to provide the light-emitting reset voltage thereto.
- each pixel circuit includes: a driving circuit, a voltage stabilizing circuit, a driving reset circuit, a light emitting reset circuit, a data writing circuit, a compensation circuit, a storage circuit and a light emitting control circuit.
- the pixel circuit will be described in detail below with reference to FIG. 2 .
- Fig. 2 shows a schematic block diagram of a sub-pixel according to some embodiments of the present disclosure.
- the sub-pixel SPX includes a pixel circuit 100 and a light emitting device 200 .
- the pixel circuit 100 includes: a driving circuit 110 , a voltage stabilizing circuit 120 , a driving reset circuit 130 and a lighting reset circuit 140 , a data writing circuit 150 , a compensation circuit 160 , a storage circuit 170 and a lighting control circuit 180 .
- the driving circuit 110 includes a control terminal G, a first terminal F and a second terminal S.
- the driving circuit 110 is configured to provide driving current to the light emitting device 200 under the control of the control signal from the control terminal G.
- the voltage stabilizing circuit 120 is coupled to the control terminal G of the driving circuit 110 , the first node N1 and the voltage stabilizing control signal input terminal Stv.
- the voltage stabilizing circuit 120 is configured to conduct the control terminal G of the driving circuit 110 with the first node N1 under the control of the voltage stabilizing control signal from the voltage stabilizing control signal input terminal.
- the drive reset circuit 130 is coupled to the drive reset control signal input terminal Rst1 , the first node N1 and the drive reset voltage terminal Vinit1 .
- the drive reset circuit 130 is configured to provide the drive reset voltage from the drive reset voltage terminal Vinit1 to the voltage stabilizing circuit 120 under the control of the drive reset control signal from the drive reset control signal input terminal Rst1 to control the drive circuit 110. G to reset.
- the light-emitting reset circuit 140 is coupled to the light-emitting reset control signal input terminal Rst2 , the light-emitting device 200 , and the light-emitting reset voltage terminal Vinit2 . Further, the lighting reset circuit 140 is also coupled to the lighting control circuit 180 . The light-emitting reset circuit 140 is configured to provide the light-emitting reset voltage from the light-emitting reset voltage terminal Vinit2 to the light-emitting device 200 under the control of the light-emitting reset control signal from the light-emitting reset control signal input terminal Rst2 to reset the anode of the light-emitting device 200 .
- the data writing circuit 150 is coupled to the data signal input terminal Data, the scan signal input terminal Gate and the first terminal F of the driving circuit 110 .
- the data writing circuit 150 is configured to provide the data signal from the data signal input terminal Data to the first terminal F of the driving circuit 110 under the control of the scan signal from the scan signal input terminal Gate.
- the compensation circuit 160 is coupled to the second terminal S of the driving circuit 110 , the first node N1 and the compensation control signal input terminal Com.
- the compensation circuit 160 is configured to perform threshold compensation on the driving circuit 110 according to the compensation control signal from the compensation control signal input terminal Com.
- the scanning signal from the scanning signal input terminal Gate and the compensation control signal from the compensation control signal input terminal Com may be the same signal.
- the storage circuit 170 is coupled to the first power supply voltage terminal VDD and the control terminal G of the driving circuit 110 .
- the storage circuit 170 is configured to store a voltage difference between the first power supply voltage terminal VDD and the control terminal G of the driving circuit 110 .
- the light emission control circuit 180 is coupled to the light emission control signal input terminal EM, the first power supply voltage terminal VDD, the first terminal F and the second terminal S of the driving circuit 110 , the light emission reset circuit 140 , and the light emitting device 200 .
- the light emission control circuit 180 is configured to apply the first power supply voltage from the first power supply voltage terminal VDD to the driving circuit 110 under the control of the light emission control signal from the light emission control signal input terminal EM, and apply the driving current generated by the driving circuit 110 applied to the light emitting device 200 .
- the light emission reset control signal from the light emission reset control signal input terminal Rst2 and the light emission control signal from the light emission control signal input terminal EM may be the same signal.
- the light-emitting reset control signal from the light-emitting reset control signal input terminal Rst2 and the scanning signal from the scanning signal input terminal Gate may be the same signal.
- the light emitting device 200 is coupled to the second power supply voltage terminal VSS, the light emitting reset circuit 140 , and the light emitting control circuit 180 .
- the light emitting device 200 is configured to emit light driven by the driving current generated by the driving circuit 110 .
- the light emitting device 200 may be a light emitting diode or the like.
- the light emitting diode may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).
- the voltage stabilization control signal, scanning signal, drive reset control signal, light emission reset control signal, compensation control signal, light emission control signal, and compensation control signal can be square waves, and the value range of the high level can be
- the value range of the low level is 0 ⁇ -15V, for example, the high level is 7V, and the low level is -7V.
- the value range of the data signal may be 0-8V, such as 2-5V.
- the value range of the first power supply voltage Vdd may be 3-6V.
- the value range of the second power supply voltage Vss may be 0 ⁇ -6V.
- FIG. 3 shows a schematic diagram of the pixel circuit 100 in FIG. 2 .
- the driving circuit 110 includes a driving transistor T1
- the voltage stabilizing circuit 120 includes a voltage stabilizing transistor T2
- the driving reset circuit 130 includes a driving reset transistor T3
- the light emitting reset circuit 140 includes a light emitting reset transistor T4
- the data writing circuit 150 includes The data writing transistor T5, the compensation circuit 160 includes a compensation transistor T6, the storage circuit 170 includes a storage capacitor C, and the light emission control circuit 180 includes a first light emission control transistor T7 and a second light emission control transistor T8.
- the first pole of the driving transistor T1 is coupled to the first terminal F of the driving circuit 110
- the second pole of the driving transistor T1 is coupled to the second terminal S of the driving circuit 110
- the gate of the driving transistor T1 It is coupled with the control terminal G of the driving circuit 110 .
- the first pole of the voltage stabilizing transistor T2 is coupled to the control terminal G of the drive circuit 110, the gate of the stabilizing transistor T2 is coupled to the voltage stabilizing control signal input terminal Stv, and the second pole of the stabilizing transistor T2 is connected to the first node N1 coupling.
- the first pole of the drive reset transistor T3 is coupled to the drive reset voltage terminal Vinit1, the gate of the drive reset transistor T3 is coupled to the drive reset control signal input terminal Rst1, and the second pole of the drive reset transistor T3 is coupled to the first node N1 .
- the first pole of the light-emitting reset transistor T4 is coupled to the light-emitting reset voltage terminal Vinit2
- the gate of the light-emitting reset transistor T4 is coupled to the light-emitting reset control signal input terminal Rst2
- the second pole of the light-emitting reset transistor T4 is coupled to the anode of the light-emitting device 200. catch.
- the second pole of the light emission reset transistor T4 is also coupled to the second pole of the second light emission control transistor T8.
- the first pole of the data writing transistor T5 is coupled to the data signal input terminal Data
- the gate of the data writing transistor T5 is coupled to the scanning signal input terminal Gate
- the second pole of the data writing transistor T5 is connected to the first pole of the driving circuit 110.
- One end F is coupled.
- the first pole of the compensation transistor T6 is coupled to the second terminal S of the driving circuit 110 , the gate of the compensation transistor T6 is coupled to the compensation control signal input terminal Com, and the second pole of the compensation transistor T6 is coupled to the first node N1 .
- a first pole of the storage capacitor C is coupled to the first power supply voltage terminal VDD, and a second pole of the storage capacitor C is coupled to the control terminal G of the driving circuit 110 .
- the storage capacitor is configured to store the voltage difference between the first power supply voltage terminal VDD and the control terminal G of the driving circuit 110 .
- the first pole of the first light emission control transistor T7 is coupled to the first power supply voltage terminal VDD, the gate of the first light emission control transistor T7 is coupled to the light emission control signal input terminal EM, and the second pole of the first light emission control transistor T7 is connected to the first power supply voltage terminal VDD.
- the first end F of the driving circuit 110 is coupled.
- the first electrode of the second light emission control transistor T8 is coupled to the second terminal S of the driving circuit 110, the gate of the second light emission control transistor T8 is coupled to the light emission control signal input terminal EM, and the second electrode of the second light emission control transistor T8 The pole is coupled to the anode of the light emitting device 200 .
- the active layers of the voltage stabilizing transistor T2 and the light emitting reset transistor T4 may include an oxide semiconductor material, such as a metal oxide semiconductor material.
- Active layers of the driving transistor T1, the driving reset transistor T3, the data writing transistor T5, the compensation transistor T6, the first light emission control transistor T7, and the second light emission control transistor T8 may include a silicon semiconductor material.
- the light emission reset transistor T4 may be a different type of transistor from the first light emission control transistor T7 and the second light emission control transistor T8.
- the light emission reset transistor T4 may be an N-type transistor
- the first light emission control transistor T7 and the second light emission control transistor T8 may be P-type transistors.
- the regulator transistor T2 can be an N-type transistor.
- the driving transistor T1, the driving reset transistor T3, the data writing transistor T5, and the compensation transistor T6 may be P-type transistors.
- the light emission reset transistor T4 and the data writing transistor T5 are the same type of transistor.
- the light emission reset transistor T4 and the data write transistor T5 may be P-type transistors.
- the regulator transistor T2 can be an N-type transistor.
- the driving transistor T1, the driving reset transistor T3, the compensation transistor T6, the first light emission control transistor T7 and the second light emission control transistor T8 may be P-type transistors.
- the transistors used in the embodiments of the present disclosure can all be P-type transistors or N-type transistors, and it is only necessary to refer to the poles of the selected type of transistors as the corresponding transistors in the embodiments of the present disclosure.
- the poles are correspondingly connected, and the corresponding voltage terminal provides a corresponding high voltage or low voltage.
- the input terminal is the drain and the output terminal is the source, and its control terminal is the gate;
- the input terminal is the source and the output terminal is the drain, and its control terminal is the gate. pole.
- the level of the control signal at the control terminal is also different.
- the oxide semiconductor may include, for example, Indium Gallium Zinc Oxide (IGZO).
- the silicon semiconductor material may include low temperature polysilicon (Low Temperature Poly Silicon, LTPS) or amorphous silicon (such as hydrogenated amorphous silicon). Low-temperature polysilicon generally refers to the situation where the crystallization temperature of polysilicon obtained from amorphous silicon crystallization is lower than 600 degrees Celsius.
- the pixel circuit of the sub-pixel may include other numbers of transistors besides the 8T1C (that is, eight transistors and one capacitor) structure shown in FIG. 4 .
- the structure, such as 8T2C structure, 7T1C structure, 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure, is not limited in the embodiments of the present disclosure.
- FIG. 4 is a timing diagram of signals driving the pixel circuit in FIG. 3 .
- the working process of the pixel circuit 100 includes three stages, which are respectively the first stage P1 , the second stage P2 and the third stage P3 .
- the light-emitting reset control signal and the light-emitting control signal are the same signal
- the voltage-stabilizing control signal and the scanning signal are the same signal
- the voltage-stabilizing transistor T2 and the light-emitting reset transistor T4 are N-type transistors
- the driving transistor T1, the driving reset transistor T3, and the data writing Taking the input transistor T5 , the compensation transistor T6 , the first light emission control transistor T7 and the second light emission control transistor T8 as P-type transistors as an example, the working process of the pixel circuit in FIG. 4 will be described in conjunction with FIG. 3 .
- a low-level drive reset control signal RST in the first stage P1, a low-level drive reset control signal RST, a high-level scan signal GA, a high-level light emission control signal EMS, a high-level voltage stabilization control signal STV and Low level data signal DA.
- the rising edge of the light emitting control signal EMS is earlier than the starting point of the first phase P1 , that is, earlier than the rising edge of the voltage stabilizing control signal STV.
- the gate of the drive reset transistor T3 receives a low level drive reset control signal RST, and the drive reset transistor T3 is turned on, thereby applying the drive reset voltage VINT1 to the first node N1.
- the gate of the voltage stabilizing transistor T2 receives the high-level voltage stabilizing control signal STV, and the stabilizing transistor T2 is turned on, so that the drive reset voltage VINT1 at the first node N1 is applied to the gate of the driving transistor T1 to The gate of the driving transistor T1 is reset, so that the driving transistor T1 is ready for writing data in the second phase P2.
- the value of the driving reset voltage VINT1 can be set to be lower, for example, the voltage opposite to the first power supply voltage Vdd is larger, so that the gate of the driving transistor T1 is connected to the second phase in the second phase.
- the voltage difference of the first pole is larger, thereby speeding up the process of data writing and compensation in the second stage.
- the influence of the driving reset voltage VINT1 on the driving transistor T1 tends to saturate as the driving reset voltage VINT1 increases inversely. The process of data writing and compensation will be described in the second phase P2 below.
- the voltage of one pole of the storage capacitor C is the first power supply voltage Vdd
- the voltage of the other pole is the drive reset voltage VINT1
- the storage capacitor C is charged.
- the value range of the driving reset voltage VINT1 can be - 1 ⁇ -5V, for example, -3V. This can shorten the time required for data writing and compensation while keeping the energy consumption of the circuit low, thereby improving the compensation effect during a fixed period of time, such as the second phase P2, thereby improving the display effect.
- the gate of the light emission reset transistor T4 receives a high-level light emission control signal EMS, and the light emission reset transistor T4 is turned on, so that the light emission reset voltage VINT2 is applied to the anode of the OLED to reset the anode of the OLED, so that This makes the OLED not emit light before the third stage P3.
- the value of the light emitting reset voltage VINT2 is set to make the OLED be in a state of just not emitting light, that is, the OLED is forward biased to a state close to being turned on.
- the value range of the lighting reset voltage VINT2 may be -2 to -6V, for example, equal to the second power supply voltage Vss, which is 0 to -6V. .
- This can reduce the charging time of the PN junction before the OLED is turned on, and reduce the response time of the OLED to the light emitting signal. In the case of consistent required brightness, the probability of OLED brightness difference is reduced. Therefore, brightness uniformity can be improved, low-frequency flicker and low-grayscale mura can be reduced.
- the gate of the data writing transistor T5 receives a high-level scan signal GA, and the data writing transistor T5 is turned off.
- the gate of the compensation transistor T6 receives the high-level scan signal GA, and the compensation transistor T6 is turned off.
- the gate of the first light emission control transistor T7 receives the high level light emission control signal EMS, and the first light emission control transistor T7 is turned off.
- the gate of the second light emission control transistor T8 receives the high level light emission control signal EMS, and the second light emission control transistor T8 is turned off.
- the high-level driving reset control signal RST, the low-level scanning signal GA, the high-level light emission control signal EMS, the high-level voltage stabilization control signal STV and the high-level data signal are input. da.
- the gate of the data writing transistor T5 receives a low-level scanning signal GA, and the data writing transistor T5 is turned on, thereby writing the high-level data signal DA into the first electrode of the driving transistor T1, That is, the first terminal F of the driving circuit 110 .
- the gate of the compensation transistor T6 receives the low-level scan signal GA, and the compensation transistor T3 is turned on, so as to write the high-level data signal DA of the first terminal F into the first node N1.
- the gate of the voltage stabilizing transistor T2 receives the high-level voltage stabilizing control signal STV, and the voltage stabilizing transistor T2 is turned on, thereby writing the high-level data signal DA of the first node N1 into the gate of the driving transistor T1, that is, the driving circuit 110 of the control terminal G. Since the data writing transistor T5, the driving transistor T1, the compensation transistor T6 and the voltage stabilizing transistor T2 are all turned on, the data signal DA passes through the data writing transistor T5, the driving transistor T1, the compensation transistor T6 and the voltage stabilizing transistor T2 to the storage capacitor C Charging is performed again, that is, the gate of the driving transistor T1 is charged, that is, the control terminal G is charged, so the voltage of the gate of the driving transistor T1 gradually increases.
- Vda represents the voltage of the data signal DA
- Vth represents the threshold voltage of the driving transistor T1. Since the driving transistor T1 is described by taking a P-type transistor as an example in this embodiment, the threshold voltage Vth here may be a negative value.
- the voltage of the gate of the driving transistor T1 is Vda+Vth, that is to say, the voltage information of the data signal DA and the threshold voltage Vth are stored in the storage capacitor C for subsequent use in the third stage P3 When , the threshold voltage of the driving transistor T1 is compensated.
- the gate of the drive reset transistor T3 receives a high level drive reset control signal RST, and the drive reset transistor T3 is turned off.
- the gate of the light-emitting reset transistor T4 receives the high-level light-emitting reset control signal EMS, and the light-emitting reset transistor T4 is turned off.
- the gate of the first light-emitting control transistor T7 receives a high-level light-emitting control signal EMS, and the first light-emitting control transistor T7 is turned off; the gate of the second light-emitting control transistor T8 receives a high-level light-emitting control signal EMS, and the second The light emission control transistor T8 is turned off.
- the high-level drive reset control signal RST, the high-level scan signal GA, the low-level light emission control signal EMS, the low-level voltage stabilization control signal STV and the low-level data signal are input. da.
- the low-level light emission control signal EMS may be an active-low pulse width modulation signal.
- the falling edge of the light emission control signal EMS is later than the end point of the second phase P1, that is, later than the falling edge of the voltage stabilization control signal STV.
- the gate of the first light emission control transistor T7 receives the light emission control signal EMS.
- the light emission control signal EMS may be pulse width modulated.
- the first light emission control transistor T7 is turned on, so as to apply the first power supply voltage Vdd to the first terminal F.
- the gate of the second light emission control transistor T8 receives the light emission control signal EMS.
- the emission control signal EMS is at a low level
- the second emission control transistor T8 is turned on, so as to apply the driving current generated by the driving transistor T1 to the anode of the OLED.
- the gate of the voltage stabilizing transistor T2 receives the low level voltage stabilizing control signal Stv, and the voltage stabilizing transistor T2 is turned off.
- the active layer of the voltage stabilizing transistor T2 includes an oxide semiconductor material, and its leakage current is 10-16 to 10-19A. Compared with single-gate low-temperature polysilicon transistors and double-gate low-temperature polysilicon transistors, the leakage current is smaller, so that the electric leakage of the storage circuit can be further reduced to improve the uniformity of brightness.
- the gate of the light emission reset transistor T4 receives the light emission control signal EMS.
- the light emission control signal EMS is at a high level, the light emission reset transistor T4 is turned on.
- the light emitting reset voltage is supplied to the anode of the OLED to reset the anode of the OLED.
- the emission control signal EMS is a pulse width modulation signal, this can enable the anode of the OLED to be reset before each emission of the OLED under the control of the emission control signal EMS, thereby further improving the uniformity of brightness .
- the gate of the drive reset transistor T3 receives the high level drive reset control signal RST, and the drive reset transistor T3 is turned off.
- the gate of the data writing transistor T5 receives the high-level scan signal GA, and the data writing transistor T5 is turned off.
- the gate of the compensation transistor T6 receives the high-level scan signal GA, and the compensation transistor T6 is turned off.
- the anode and the cathode of the OLED are respectively connected to the first power supply voltage Vdd (high voltage) and the second power supply voltage Vss (low voltage), so as to emit light under the driving current generated by the driving transistor T1.
- the driving current ID for driving the OLED to emit light can be obtained according to the following formula:
- Vth represents the threshold voltage of the driving transistor T1
- VGS represents the voltage between the gate and the source of the driving transistor T1
- K is a constant.
- K in the above formula can be expressed as:
- n is the electron mobility of the driving transistor T1
- Cox is the gate unit capacitance of the driving transistor T1
- W is the channel width of the driving transistor T1
- L is the channel length of the driving transistor T1.
- the light emission reset control signal RST, the compensation control signal COM and the scan signal GA may be the same signal.
- the voltage stabilizing transistor T2 can be an N-type transistor, and the driving transistor T1, driving reset transistor T3, light emitting reset transistor T4, data writing transistor T5, compensation transistor T6, first light emitting control transistor T7 and second light emitting control transistor T8 are P type transistor.
- the difference from the working process of the pixel circuit in the above-mentioned embodiments is that in the first phase P1, the light-emitting reset transistor T4 receives a high-level scan signal GA, and the light-emitting reset transistor T4 is turned off.
- the light emission reset voltage VINT2 is not supplied to the anode of the light emitting device OLED, and thus the anode of the light emitting device OLED is not reset.
- the light-emitting reset transistor T4 receives the low-level scan signal GA, and the light-emitting reset transistor T4 is turned on.
- the light emission reset voltage VINT2 is supplied to the anode of the light emitting device OLED to reset the anode of the light emitting device OLED.
- the rest of the working process of the pixel circuit in the first period P1, the second period P2 and the third period P3 is similar to the above-mentioned embodiment, and will not be repeated here.
- the relationship between the drive reset control signal RST, the scan signal GA, the light emission control signal EMS, the voltage stabilization control signal STV, and the data signal DA and each stage is only schematic.
- the duration of the high level or low level of the drive reset control signal RST, the scan signal GA, the light emission control signal EMS, the voltage stabilization control signal STV, and the data signal DA is only exemplary.
- each high level duration of the light emitting control signal EMS may be the same.
- FIG. 3 shows schematic plan views of various layers in an array substrate according to an embodiment of the present disclosure.
- a pixel circuit as shown in FIG. 3 is taken as an example for illustration.
- the emission reset control signal RST and the emission control signal EMS are the same signal
- the voltage stabilization control signal COM and the scanning signal GA are the same signal
- the voltage stabilization transistor T2 and the emission reset transistor T4 are metal oxide transistors.
- each circuit in the pixel circuit on the substrate will be described below with reference to FIGS. 5 to 11 .
- the scales in the accompanying drawings 5 to 11 are drawn scales, so as to more clearly show the position of each part, which cannot be regarded as the true scale of the parts.
- Those skilled in the art can select the size of each component based on actual requirements, which is not specifically limited in the present disclosure.
- the array substrate includes a first active semiconductor layer 310 on a substrate 300 .
- FIG. 5 shows a schematic plan view of the first active semiconductor layer 310 in the array substrate according to an embodiment of the present disclosure.
- the driving transistor T1, driving reset transistor T3, light emission reset transistor T4, data writing transistor T5, compensation transistor T6, first light emission control transistor T7, and second light emission control transistor in the pixel circuit T8 is a silicon transistor, such as a low temperature polysilicon transistor.
- the first active semiconductor layer 310 may be used to form the above-mentioned drive transistor T1, drive reset transistor T3, light emission reset transistor T4, data write transistor T5, compensation transistor T6, first light emission control transistor T7 and the active area of the second light emitting control transistor T8.
- the first active semiconductor layer 310 includes a channel region pattern and a doped region pattern of a transistor (ie, a first source/drain region and a second source/drain region of the transistor).
- the channel region pattern and the doped region pattern of each transistor are integrally arranged.
- dotted-line boxes are used to indicate regions in the first active semiconductor layer 310 used for source/drain regions and channel regions of respective transistors.
- the first active semiconductor layer 310 sequentially includes a channel region T3-c for driving the reset transistor T3 and a channel region for the data writing transistor T5 along the Y direction (column direction) and the X direction (row direction).
- the first active semiconductor layer used for the above transistor may include an integrally formed low temperature polysilicon layer.
- the source region and the drain region of each transistor can be conductorized by doping or the like to realize the electrical connection of each structure. That is, the first active semiconductor layer of the transistor is an overall pattern formed of p-silicon or n-silicon, and each transistor in the same pixel circuit includes a doped region pattern (ie, source region s and drain region d ) and channel region pattern.
- the active layers of different transistors are separated by doping structures.
- the first active semiconductor layer 310 further includes along the Y direction and the X direction: the drain region T3-d of the drive reset transistor T3, the drain region T5-d of the data writing transistor T5, the drive reset transistor The source region of T3 and the source region T3-s/T6-s of the compensation transistor T6, the source region T5-s of the data writing transistor T5, the source region of the driving transistor T1 and the source of the first light emission control transistor T7 Region T1-s/T7-s, the drain region of the compensation transistor T6 and the drain region of the drive transistor T1 and the drain region T6-d/T1-d/T8-d of the second light emission control transistor T8, the first light emission The drain region T7-d of the control transistor T7, and the source region T8-s of the second light emission control transistor T8.
- the first active semiconductor layer 310 may be formed of a silicon semiconductor material such as amorphous silicon, polycrystalline silicon, or the like.
- the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
- the source region and the drain region of the first light emission control transistor T7, the data writing transistor T5, the driving transistor T1, the compensation transistor T6, and the second light emission control transistor T8 are regions doped with P-type impurities.
- the array substrate further includes a first conductive layer 320 located on a side of the first active semiconductor layer away from the substrate.
- FIG. 6 is a schematic plan view of the first conductive layer 320 in the array substrate according to an embodiment of the present disclosure.
- the first conductive layer 320 includes a drive reset control signal line RSTL1 , a scan signal line GAL, a first electrode C1 of a capacitor C, and an emission control signal line EML arranged in sequence along the Y direction.
- the first conductive layer 320 further includes a drive reset control signal line RSTL1' for adjacent pixel circuits along the Y direction.
- the driving and reset control signal line RSTL1' of the adjacent pixel circuit has the same effect on the adjacent pixel circuit as the driving and reset control signal line RSTL1 has on the pixel circuit, and will not be described again hereafter.
- the light emission control signal line EML and the light emission control signal input terminal EM are configured to provide the light emission control signal EMS to the light emission control signal input terminal EM.
- the scanning signal line GAL is coupled to the scanning signal input terminal Gate and the compensation control signal input terminal Com, and is configured to provide the scanning signal GA to the scanning signal input terminal Gate, and is configured to provide the compensation control signal
- the signal input terminal Com provides a compensation control signal COM.
- the first electrode C1 of the capacitor C and the gate T1-g of the driving transistor T1 are integrally structured.
- the drive reset control signal line RSTL1 is coupled to the drive reset control signal input terminal Rst1 to provide the drive reset control signal input terminal Rst1 with the drive reset control signal RST.
- the portion where the orthographic projection of the drive reset control signal line RSTL1 on the substrate overlaps with the orthographic projection of the portion 311 of the first active semiconductor layer 310 on the substrate is the gate T3-g of the driving reset transistor T3 of the pixel circuit.
- the parts where the orthographic projection of the scanning signal line GAL on the substrate overlaps with the orthographic projection of the portion 311 of the first active semiconductor layer 310 on the substrate are the gate T6-g and the data write gate T6-g of the compensation transistor T6 in the pixel circuit respectively. into the gate T5-g of transistor T5.
- the portion where the orthographic projection of the first pole C1 of the capacitor C in the pixel circuit on the substrate overlaps with the orthographic projection of the portion 311 of the first active semiconductor layer 310 on the substrate is the gate of the driving transistor T1 in the pixel circuit.
- the parts where the orthographic projection of the emission control signal line EML on the substrate overlaps with the orthographic projection of the portion 311 of the first active semiconductor layer 310 on the substrate are the gates T7- of the first emission control transistor T7 in the pixel circuit respectively.
- the gate T3-g of the reset transistor T3, the gate T6-g of the compensation transistor T6, and the gate T5-g of the data write transistor T5 are driven.
- g is located on the first side of the gate T1-g of the driving transistor T1.
- the gate T7-g of the first light emission control transistor T7 and the gate T8-g of the first light emission control transistor T8 are located on the second side of the gate T1-g of the driving transistor T1.
- the first side and the second side of the gate T1-g of the driving transistor T1 are opposite sides of the gate T1-g of the driving transistor T1 in the Y direction.
- the first side of the gate T1 - g of the driving transistor T1 may be the upper side of the gate T1 - g of the driving transistor T1 .
- the second side of the gate T1-g of the driving transistor T1 may be a lower side of the gate T1-g of the driving transistor T1.
- the "lower side” is, for example, the side of the array substrate for bonding ICs.
- the lower side of the gate T1-g of the driving transistor T1 is the side of the gate T1-g of the driving transistor T1 close to the IC (not shown in the figure).
- the upper side is the opposite side to the lower side, for example, the side away from the IC of the gate T1-g of the drive transistor T1.
- the gate T3-g of the driving reset transistor T3 is located on the upper side of the gate T6-g of the compensation transistor T6 and the gate T5-g of the data writing transistor T5.
- the gate T3-g of the drive reset transistor T3 is aligned with the gate T1-g of the drive transistor T1 in the Y direction.
- the gate T5-g of the data writing transistor T5 and the gate T7-g of the first light emission control transistor T7 are located at the gate of the driving transistor T1
- the gate T6-g of the compensation transistor T6 and the gate T8-g of the second light emission control transistor T8 are located on the fourth side of the gate T1-g of the driving transistor T1.
- the third side and the fourth side of the gate T1-g of the driving transistor T1 are opposite sides of the gate T1-g of the driving transistor T1 in the X direction.
- the third side of the gate T1 - g of the driving transistor T1 may be the left side of the gate T1 - g of the driving transistor T1 .
- the fourth side of the gate T1-g of the driving transistor T1 may be the right side of the gate T1-g of the driving transistor T1.
- the gate T7-g of the first light emission control transistor T7 is on the left side of the gate T5-g of the data writing transistor T5.
- the gate T8-g of the second light emission control transistor T8 is located on the right side of the gate T6-g of the compensation transistor T6.
- the active regions of the transistors shown in FIG. 6 correspond to respective regions where the first conductive layer 320 overlaps the first active semiconductor layer 310 .
- the array substrate further includes a second conductive layer located on a side of the first conductive layer away from the substrate and insulated from the first conductive layer.
- FIG. 7 shows a schematic plan view of the second conductive layer 330 in the array substrate according to an embodiment of the present disclosure.
- the second conductive layer 330 includes a voltage stabilization control signal line STVL arranged along the Y direction, a second electrode C2 of the capacitor, a first power supply voltage line VDL and a light emission reset control signal line RSTL2 .
- the second conductive layer 330 further includes light emission reset control signal lines RSTL2' of adjacent pixel circuits along the Y direction. The effect of the emission reset control signal line RSTL2' of the adjacent pixel circuit on the adjacent pixel circuit is the same as that of the emission reset control signal line RSTL2 on the pixel circuit, and will not be repeated below.
- projections of the second pole C2 of the capacitor C and the first pole C1 of the capacitor C on the substrate at least partially overlap.
- the first power supply voltage line VDL extends in the X direction and is integrally formed with the second pole C2 of the capacitor C.
- the first supply voltage line is coupled to the first supply voltage terminal VDD and configured to provide the first supply voltage Vdd thereto.
- the voltage regulation control signal line STVL is coupled to the voltage regulation control signal input terminal Stv and configured to provide the voltage regulation control signal STV thereto.
- the light-emitting reset control signal line RSTL2 is coupled to the light-emitting reset control signal input terminal Rst2 and configured to provide the light-emitting reset control signal thereto.
- the light emission reset control signal and the scan signal EMS are the same signal.
- the voltage regulation control signal line STVL is located at the first side of the second pole C2 of the capacitor.
- the first power signal line VDL and the lighting reset control signal line RSTL2 are located at the second side of the second pole C2 of the capacitor. Similar to the above description about the first side and the second side of the gate T1-g of the driving transistor T1, the first side and the second side of the second pole C2 of the capacitor are in the Y direction opposite sides of the .
- the first side of the second pole C2 of the capacitor is the upper side of the second pole C2 of the capacitor in the Y direction
- the second side of the second pole C2 of the capacitor is the lower side of the second pole C2 of the capacitor in the Y direction.
- the voltage stabilization control signal line STVL is located on the upper side of the second pole C2 of the capacitor.
- the first power signal line VDL and the light emission reset control signal line RSTL2 are located on the lower side of the second pole C2 of the capacitor.
- a first gate T2 - g1 of the voltage stabilizing transistor T2 is disposed on the voltage stabilizing control signal line STVL.
- the first gate T4-g1 of the light-emitting reset transistor T4 is provided on the light-emitting reset control signal line RSTL2.
- the specific positions of the first gate T2-g1 of the voltage stabilizing transistor T2 and the first gate T4-g1 of the light-emitting reset transistor T4 will be described in detail below with reference to FIG. 8 .
- the first gate T2-g1 of the voltage stabilizing transistor T2 is on the first side of the first gate T4-g1 of the light-emitting reset transistor T4 in the Y direction. Similar to the above description of the first side of the gate T1-g of the driving transistor T1, the first side of the first gate T4-g1 of the light-emitting reset transistor T4 is the first side of the first gate T4-g1 of the light-emitting reset transistor T4. upper side. That is, the first gate T2-g1 of the voltage stabilizing transistor T2 is on the upper side of the first gate T4-g1 of the light emission reset transistor T4. In the X direction, the first gate T2-g1 of the voltage stabilizing transistor T2 is at the same position as the first gate T4-g1 of the light-emitting reset transistor T4.
- the array substrate further includes a second active semiconductor layer located on a side of the second conductive layer away from the substrate and insulated from the second conductive layer.
- FIG. 8 shows a schematic plan view of the second active semiconductor layer 340 in the array substrate according to an embodiment of the present disclosure.
- the second active semiconductor layer 340 sequentially includes a first portion 341 and a second portion 342 in the Y direction, and the first portion 341 of the second active semiconductor layer 340 and the second portion of the second active semiconductor layer 340 Two parts 342 are aligned.
- the second active semiconductor layer 340 may be used to form the active layers of the voltage stabilizing transistor T2 and the light emitting reset transistor T4 described above.
- the first portion 341 of the second active semiconductor layer 340 may be used to form the active layer of the voltage stabilizing transistor T2.
- the second portion 342 of the second semiconductor layer 340 may be used to form the active layer of the voltage stabilizing transistor T7.
- the second active semiconductor layer 340 includes a channel pattern and a doped region pattern of a transistor (ie, the first source/drain region and second source/drain region).
- dotted-line boxes are used to show regions for source/drain regions and channel regions of respective transistors in the second active semiconductor layer 340 .
- the first part 341 of the second active semiconductor layer 340 sequentially includes the source region T2-s of the voltage stabilizing transistor T2, the channel region T2-c of the stabilizing transistor T2, and the stabilizing transistor T2 along the Y direction.
- the second portion 342 of the second active semiconductor layer 340 sequentially includes the source region T4-s of the light-emitting reset transistor T4, the channel region T4-c of the light-emitting reset transistor T4, and the drain region T4 of the light-emitting reset transistor T4 along the Y direction. -d.
- the overlapping portion of the orthographic projection of the voltage stabilization control signal line STVL on the substrate and the orthographic projection of the second active semiconductor layer 340 on the substrate is the voltage stabilization A first gate T2-g1 of the transistor T2.
- the channel region T8-c of the voltage stabilizing transistor T2 completely overlaps with the projection of the first gate T2-g1 of the voltage stabilizing transistor T2 on the substrate.
- the overlapping portion of the orthographic projection of the light emission control signal line RSTL2 on the substrate and the orthographic projection of the second active semiconductor layer 340 on the substrate is the first gate T4-g1 of the light emission reset transistor T4.
- the channel region T4-c of the light-emitting reset transistor T4 completely overlaps the projection of the first gate T4-g1 of the light-emitting reset transistor T4 on the substrate.
- the second active semiconductor layer 340 may be formed of an oxide semiconductor material, for example, indium gallium zinc oxide IGZO.
- the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
- the source regions and drain regions of the voltage stabilizing transistor T2 and the light emitting reset transistor T4 are regions doped with N-type impurities.
- the array substrate further includes a third conductive layer located on a side of the second active semiconductor layer away from the substrate and insulated from the second active semiconductor layer.
- FIG. 9 shows a schematic plan view of the third conductive layer 350 in the array substrate according to an embodiment of the present disclosure.
- the third conductive layer 350 includes a voltage stabilization control signal line STVL, a light emission reset control signal line RSTL2 , and a light emission reset voltage line VINL2 .
- the third conductive layer 350 further includes a light emission reset control signal line RSTL2' and a light emission reset voltage line VINL2' of adjacent pixel circuits along the Y direction.
- the light emission reset control signal line RSTL2' and the light emission reset voltage line VINL2' of the adjacent pixel circuit have the same effect on the adjacent pixel circuit as the light emission reset control signal line RSTL2 and the light emission reset voltage line VINL2 have the same effect on the pixel circuit. Repeat for it.
- the voltage stabilization control signal line STVL, the light emission reset control signal line RSTL2 , and the light emission reset voltage line VINL2 are sequentially arranged in the Y direction.
- the second gate T2 - g2 of the voltage stabilizing transistor T2 is disposed on the voltage stabilizing control signal line STVL.
- the second gate T4-g2 of the light emission reset transistor T4 is provided on the light emission reset control signal line RSTL2.
- the overlapping portion of the orthographic projection of the voltage stabilizing control signal line STVL on the substrate and the orthographic projection of the second active semiconductor layer 340 on the substrate is the second gate T2 - g2 of the voltage stabilizing transistor T2 .
- the overlapping portion of the orthographic projection of the light-emitting reset control signal line RSTL2 on the substrate and the orthographic projection of the second active semiconductor layer 340 on the substrate is the second gate T4-g2 of the light-emitting reset transistor T4.
- the second gate of the voltage stabilizing transistor T2 in the Y direction
- the gate T2-g2 is on the first side of the second gate T4-g2 of the light emitting reset transistor T4.
- the first side of the second gate T4-g2 of the light-emitting reset transistor T4 is the upper side of the second gate T4-g2 of the light-emitting reset transistor T4. That is, the second gate T2-g2 of the constant voltage transistor T2 is on the upper side of the second gate T4-g2 of the light emission reset transistor T4.
- the second gate T2-g2 of the voltage stabilizing transistor T2 is at the same position as the second gate T4-g2 of the light-emitting reset transistor T4.
- the second gate T2-g2 of the voltage stabilizing transistor T2, the channel region T2-c of the stabilizing transistor T2 and the first gate of the stabilizing transistor T2 The projections of the gate T2-g1 on the substrate completely overlap. Projections on the substrate of the second gate T4-g2 of the light-emitting reset transistor T4, the channel region T4-c of the light-emitting reset transistor T4 and the first gate T4-g1 of the light-emitting reset transistor T4 overlap completely.
- an insulating layer or a dielectric layer is respectively provided between adjacent active semiconductor layers and conductive layers or between adjacent conductive layers. Specifically, between the first active semiconductor layer 310 and the first conductive layer 320, between the first conductive layer 320 and the second conductive layer 330, and between the second conductive layer 330 and the second active semiconductor layer 340 between the second active semiconductor layer 340 and the third conductive layer 350, between the third conductive layer 350 and the fourth conductive layer 360 (which will be described in detail below with reference to FIG. Between the layer 360 and the fifth conductive layer 370 (which will be described in detail below with reference to FIG. 11 ) are respectively disposed an insulating layer or a dielectric layer (which will be described in detail below with reference to a cross-sectional view).
- the via hole described below is a via hole that simultaneously penetrates an insulating layer or a dielectric layer disposed between adjacent active semiconductor layers and conductive layers or between adjacent conductive layers. Specifically, the via hole penetrates between the first active semiconductor layer 310 and the first conductive layer 320, between the first conductive layer 320 and the second conductive layer 330, and between the second conductive layer 330 and the second active layer. Between the source semiconductor layer 340, between the second active semiconductor layer 340 and the third conductive layer 350, between the third conductive layer 350 and the fourth conductive layer 360, and between the fourth conductive layer 360 and the fifth conductive layer Vias for each insulating layer or dielectric layer between layers 370 .
- the light emission reset voltage line VINL2 is coupled to the second active semiconductor layer 340 through the via hole 3501 to form the first pole T4 - 1 of the light emission reset transistor T4 .
- the emission reset voltage line VINL2 in FIG. 9 overlaps with the projection on the substrate of the drain region T7 - d of the emission reset transistor T4 of the second part 342 in FIG. 8 .
- the light emission reset voltage line VINL2 is coupled to the drain region T4 - d of the light emission reset transistor T4 through the via hole 3501 .
- the array substrate further includes a fourth conductive layer located on a side of the third conductive layer away from the substrate and insulated from the third conductive layer.
- FIG. 10 shows a schematic plan view of the fourth conductive layer 360 in the array substrate according to an embodiment of the present disclosure.
- the fourth conductive layer 360 includes a first connection portion 361, a second connection portion 362, a third connection portion 363, a fourth connection portion 364, a fifth connection portion 365, a sixth connection portion 366, a seventh connection portion The connection part 367 and the eighth connection part 368 .
- the fourth conductive layer 360 further includes a ninth connection portion 369 for adjacent pixel circuits along the Y direction.
- the ninth connecting portion 369 and the via hole 3691 thereon may serve as the first connecting portion 361 and the via hole 3611 thereon of an adjacent pixel circuit.
- connection method and function are similar to the first connection portion 361 and the via hole 3611 thereon in the pixel circuit, and will not be repeated below.
- first connecting portion 361 of the adjacent pixel circuit and the via hole 3611 thereon are set as above.
- the second connection part 362 , the third connection part 363 , the fourth connection part 364 , the fifth connection part 365 , the sixth connection part 366 , the seventh connection part 367 , and the eighth connection part 368 is disposed on the second side of the first connecting portion 361 .
- the second side of the first connection part 361 is the lower side of the first connection part 361 . That is, the second connecting portion 362, the third connecting portion 363, the fourth connecting portion 364, the fifth connecting portion 365, the sixth connecting portion 366, the seventh connecting portion 367, and the eighth connecting portion 368 are arranged on the first connecting portion.
- the third connecting portion 363 and the sixth connecting portion 366 are arranged in sequence along the Y direction.
- the second connection portion 362 , the fourth connection portion 364 , the fifth connection portion 365 , the seventh connection portion 367 , and the eighth connection portion 368 are arranged in sequence along the Y direction.
- the second connection portion 362 , the fourth connection portion 364 , the fifth connection portion 365 , the seventh connection portion 367 , and the eighth connection portion 368 are on the third side of the third connection portion 363 and the sixth connection portion 366 .
- the third side of the third connection part 363 and the sixth connection part 366 are the distance between the third connection part 363 and the sixth connection part 366.
- the second connection portion 362 , the fourth connection portion 364 , the fifth connection portion 365 , the seventh connection portion 367 , and the eighth connection portion 368 are on the right side of the third connection portion 363 and the sixth connection portion 366 .
- the first connection part 361 is coupled with the first active semiconductor layer 310 through the via hole 3611 . Specifically, the first connection portion 361 is coupled to the drain region T3 - d of the drive reset transistor T3 through the via hole 3611 to form a first pole T3 - 1 of the drive reset transistor T3 .
- the first connection part 361 functions as a driving reset voltage line VINL1.
- the second connection portion 362 is coupled to the third conductive layer 350 through the via hole 3621 . Specifically, the second connection portion 362 is coupled to the light emission reset voltage line VINL2 through the via hole 3621 .
- the third connection part 363 is coupled to the first active semiconductor layer 310 through the via hole 3631 . Specifically, the third connection portion 363 is coupled to the drain region T5-d of the data writing transistor T5 through the via hole 3631 to form the first electrode T5-1 of the data writing transistor T5.
- the fourth connection part 364 is coupled to the first active semiconductor layer 310 through the via hole 3641 . Specifically, the fourth connection portion 364 is coupled to the source region of the drive reset transistor T3 and the source region T3-s/T6-s of the compensation transistor T6 through the via hole 3641 to form the second pole of the drive reset transistor T3 and the compensation The second pole T3-2/T6-2 of the transistor T6.
- the fourth connection part 364 is coupled to the second active semiconductor layer 340 through the via hole 3642 . Specifically, the fourth connection portion 364 is coupled to the source region T2 - s of the voltage stabilizing transistor T2 through the via hole 3642 to form the second pole T2 - 2 of the voltage stabilizing transistor T2 .
- the fifth connection portion 365 is coupled to the third conductive layer 330 through the via hole 3651 .
- the fifth connection portion 365 is coupled to the second conductive layer 320 through the via hole 3652 .
- the fifth connection portion 365 is coupled to the gate T1 - g of the driving transistor T1 and the first pole C1 of the capacitor C through the via hole 3652 .
- the fifth connection part 365 is coupled to the second active semiconductor layer 340 through the via hole 3653 .
- the fifth connection portion 365 is coupled to the drain region T2 - d of the voltage stabilizing transistor T2 through the via hole 3653 to form the first pole T2 - 1 of the voltage stabilizing transistor T2 .
- the sixth connection part 366 is coupled to the first active semiconductor layer 310 through the via hole 3662 . Specifically, the sixth connection portion 366 is coupled to the drain region T7 - d of the first light emission control transistor T7 via the via hole 3662 to form the first electrode T7 - 1 of the first light emission control transistor T7 .
- the seventh connection part 367 is coupled to the first active semiconductor layer 310 through the via hole 3671 . Specifically, the seventh connection portion 367 is coupled to the source region T8-s of the second light emission control transistor T8 through the via hole 3671 to form the second pole T8-2 of the second light emission control transistor T8.
- the seventh connection part 367 is coupled to the second active semiconductor layer 340 through the via hole 3672 . Specifically, the seventh connection portion 367 is coupled to the source region T4-s of the light-emitting reset transistor T4 through the via hole 3672 to form the second pole T4-2 of the light-emitting reset transistor T4.
- the eighth connection part 368 is coupled to the second active semiconductor layer 340 through the via hole 3681 .
- the eighth connection portion 368 is coupled to the source region T4-d of the light-emitting reset transistor T4 through the via hole 3681 to form the first pole T4-1 of the light-emitting reset transistor T4.
- the eighth connecting portion 368 and the via hole 3682 thereon may serve as the second connecting portion 362 and the via hole 3621 thereon of adjacent pixel circuits along the Y direction. Its specific connection method and function are similar to the second connection portion 362 and the via hole 3621 in the pixel circuit, and will not be repeated here.
- the second connection portion 362 of the adjacent pixel circuit and the via hole 3621 thereon are set as above.
- the array substrate further includes a fifth conductive layer located on a side of the fourth conductive layer away from the substrate and insulated from the fourth conductive layer.
- FIG. 11 shows a schematic plan view of the fifth conductive layer 370 in the array substrate according to an embodiment of the present disclosure.
- the fifth conductive layer includes a data signal line DAL, a first power voltage line VDL, and a second power voltage line VSL disposed along the row direction X.
- the data signal line DAL extends along the column direction Y, and is coupled to the third connection portion 363 of the fourth conductive layer 360 through the via hole 3711 .
- the first power supply voltage line VDL extends along the column direction Y, and is coupled to the third connection portion 363 of the fourth conductive layer 360 through the via hole 3721 .
- the second power supply voltage line VSL extends along the column direction Y, and is coupled to the seventh connection portion 367 of the fourth conductive layer 360 through the via hole 3731 .
- the distance the second power voltage line VSL extends in the column direction Y is smaller than the data signal line DAL and the first power voltage line VDL.
- the second supply voltage line VSL may serve as a cathode of a light emitting device, such as an OLED.
- the first power voltage line VDL has a closed rectangular part 371 . 8 and 11, the orthographic projection of the second side extending along the Y direction of the rectangular member 371 arranged along the row direction X on the substrate is the same as the orthographic projection of the first portion 341 of the second active semiconductor layer 340 on the substrate.
- the projections overlap.
- This arrangement can isolate the second active semiconductor layer 340 from the encapsulation layer on the side of the fifth conductive layer 370 away from the substrate and adjacent to the fifth conductive layer 370, thereby preventing the hydrogen element in the encapsulation layer from making the first
- the performance of the oxide material in the second active semiconductor layer 340 such as metal oxide material, is not stable.
- the orthographic projection of the second power supply voltage line VSL on the substrate overlaps with the orthographic projection of the second portion 342 of the second active semiconductor layer 340 on the substrate.
- the arrangement of the second power supply voltage line VSL is similar to the arrangement of the above-mentioned first power supply voltage line VDL.
- the conductive layer 370 is isolated adjacent to the encapsulation layer, so as to prevent the hydrogen element in the encapsulation layer from destabilizing the performance of the oxide material in the second active semiconductor layer 340 .
- the plan layout 380 includes a first active semiconductor layer 310 , a first conductive layer 320 , a second conductive layer 330 , a second active semiconductor layer 340 , a third conductive layer 350 , and a fourth conductive layer 360 and the fifth conductive layer 370 .
- FIG. 12 shows a pixel circuit including a stacked first active semiconductor layer, a first conductive layer, a second conductive layer, a second active semiconductor layer, a third conductive layer, and a fourth conductive layer (thereby the array substrate ) schematic diagram of the floor plan.
- the plan layout 380 includes a first active semiconductor layer 310 , a first conductive layer 320 , a second conductive layer 330 , a second active semiconductor layer 340 , a third conductive layer 350 , and a fourth conductive layer 360 and the fifth conductive layer 370 .
- FIG. 12 shows a pixel circuit including a stacked first active semiconductor layer, a first conductive layer, a second conductive layer,
- FIG. 12 shows the gate T1-g of the drive transistor T1, the gate T2-g of the voltage stabilizing transistor T2, the gate T3-g of the drive reset transistor T3, and the gate T4-g of the light-emitting reset transistor T4. g.
- the gate T5-g of the data writing transistor T5, the gate T6-g of the compensation transistor T6, the first plate C1 of the storage capacitor C, the gate T7-g of the first light emission control transistor T7 and the second light emission Gate T8-g of transistor T8 is controlled.
- FIG. 12 also shows a section line A1A2 passing through the array substrate where the via hole 3651 , the gate T6 - g of the compensation transistor T6 and the gate T2 - g of the voltage stabilizing transistor T2 are located. A cross-sectional view taken along a section line A1A2 will be described below with reference to FIG. 13 .
- FIG. 13 shows a schematic cross-sectional structure diagram of the array substrate taken along line A1A2 in FIG. 12 according to an embodiment of the present disclosure.
- the array substrate 10 includes: a substrate 300 ; a first buffer layer 101 on the substrate 300 ; and a first active semiconductor layer 310 on the first buffer layer 101 .
- the cross-sectional view shows the channel region T6 - c of the compensation transistor T6 included in the first active semiconductor layer 310 .
- the array substrate 10 further includes: a first gate insulating layer 102 covering the first buffer layer 101 and the first active semiconductor layer 310; The layer 102 is away from the first conductive layer 320 on the side of the substrate 300 .
- This section shows the scan signal line GAL included in the first conductive layer 320 .
- the overlapping portion of the orthographic projection of the scanning signal line GAL on the substrate 300 and the orthographic projection of the channel region T6-c of the compensation transistor T6 included in the first active semiconductor layer 310 on the substrate 300 is the gate T6-g of the compensation transistor T6.
- the array substrate 10 further includes: a first interlayer insulating layer 103 located on the side of the first conductive layer 320 away from the substrate 300 ;
- the second conductive layer 330 on the side away from the substrate 300 .
- the cross-sectional view shows the voltage stabilization control signal line STVL and a connection portion 331 included in the second conductive layer.
- the voltage stabilization control signal line STVL includes a first gate T2-g1 of the voltage stabilization transistor T2.
- the array substrate 10 further includes: a second interlayer insulating layer 104 located on a side of the second conductive layer 330 away from the substrate 300 ; the second buffer layer 105; and the second active semiconductor layer 340 located on the side of the second buffer layer 105 away from the substrate 300 .
- This cross-sectional view shows the orthographic projection of the voltage stabilizing transistor T2 on the substrate 300 overlapping with the orthographic projection of the first gate T2-g1 of the voltage stabilizing transistor T2 on the voltage stabilizing control signal line STVL on the substrate 300.
- Channel region T2-c is shown in FIG. 13 , the array substrate 10 further includes: a second interlayer insulating layer 104 located on a side of the second conductive layer 330 away from the substrate 300 ; the second buffer layer 105; and the second active semiconductor layer 340 located on the side of the second buffer layer 105 away from the substrate 300 .
- the array substrate 10 further includes: a second gate insulating layer 106 covering the second active semiconductor layer 340 and the second buffer layer 105; 106 on the side away from the substrate 300 of the third conductive layer 350 .
- the cross-sectional view shows that the third conductive layer 350 includes the voltage regulation control signal line STVL.
- the orthographic projection of the voltage stabilization control signal line STVL on the substrate 300 is the same as the orthographic projection of the channel region T2-c of the voltage stabilization transistor T2 included in the second active semiconductor layer 320 on the substrate 300.
- the overlapping part is the second gate T2-g2 of the voltage stabilizing transistor T2.
- the array substrate 10 further includes: a third interlayer insulating layer 107 covering the third conductive layer 350 and the second gate insulating layer 106 ;
- the layer 107 is away from the fourth conductive layer 360 on the side of the substrate 300 .
- the cross-sectional view shows the fifth connection portion 365 .
- the fifth connection portion 365 is coupled to the connection portion 331 on the second conductive layer 330 through the via hole 3651 .
- the array substrate 10 further includes: a first flat layer 108 covering the fourth conductive layer 360 and the third interlayer insulating layer 107; The fifth conductive layer 370 on the bottom 300 side.
- the sectional view shows the first power supply voltage line VDL.
- the array substrate 10 further includes a second planar layer 109 covering the fifth conductive layer 370 and the first planar layer 108 .
- FIG. 14 shows a schematic cross-sectional structure diagram of the array substrate taken along line A1A2 in FIG. 12 according to an embodiment of the present disclosure.
- the array substrate 10 further includes a shielding layer 400 between the substrate 100 and the first buffer layer 101.
- the shielding layer 400 is configured to at least partially shield the active semiconductor layer of the transistor of the pixel circuit from the light incident on the side of the substrate 300 not provided with the pixel circuit, In order to prevent photodegradation of the transistor.
- the blocking layer 400 is configured to block particles released from the substrate from entering the pixel circuit.
- the released particles also degrade the performance of the transistor if they enter the active semiconductor layer.
- the particles when they are charged particles, once they are embedded in the pixel circuit structure (for example, embedded in the dielectric layer of the circuit structure), they will also interfere with various signal voltages input to the pixel circuit, thus affecting the display performance.
- the substrate 300 is a polyimide substrate, since the polyimide material always undesirably contains various impurity ions, in the thermal exposure process (for example, the growth of the active semiconductor layer and the During the sputtering and evaporation of the conductive layer such as metal), these impurity ions will be released from the substrate 300 and enter into the pixel circuit.
- the obscuring layer 400 may not be biased (ie, suspended).
- a voltage bias can also be applied to the shielding layer 400 to further improve the shielding effect.
- the voltage applied to the blocking layer may be a constant voltage.
- the voltage applied to the blocking layer may be selected from one of the following voltages: first power supply voltage Vdd (anode voltage of the light emitting device), second power supply voltage Vss (cathode voltage of the light emitting device), driving reset voltage VINT1 or other voltages.
- the range of the voltage applied to the shielding layer includes one selected from the following ranges: -10V ⁇ +10V, -5V ⁇ +5V, -3V ⁇ +3V, -1V ⁇ +1V, or -0.5V ⁇ +0.5V.
- the voltage applied to the shielding layer may be selected from one of the following voltages: -0.3V, -0.2V, 0V, 0.1V, 0.2V, 0.3V or 10.1V.
- the voltage applied to the shielding layer may be greater than the second power supply voltage Vss and less than the first power supply voltage Vdd; or, the voltage applied to the shielding layer may be greater than the driving reset voltage VINT1 and less than the first power supply voltage Vdd.
- FIG. 15 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure.
- FIG. 15 shows a configuration of an obscuring layer 400a.
- the shielding layer 400a completely covers the substrate 300 on the region of the array substrate 10 having pixel units (ie, the display region).
- the cross-sectional structure of Fig. 14 corresponds to this configuration. By fully arraying the display area of the substrate, the shielding layer can achieve the best protection effect.
- FIG. 16 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure.
- FIG. 16 shows another configuration of the shielding layer 400b, where the shielding layer 400b does not completely cover the substrate 300 on the region of the array substrate 10 having pixel units (ie, the display region).
- the blocking layer 400b includes first strips 401 extending along the row direction X and spaced apart from each other along the column direction Y and second strips 402 extending along the column direction Y and spaced apart from each other along the row direction X.
- the first strip 401 and the second strip 402 have the same width (ie, a dimension perpendicular to the direction in which the strips extend).
- the orthographic projection of the intersecting portion of the first strip 401 and the second strip 402 on the substrate 300 and the active region 3101 of the driving transistor T1 (that is, the trench of the first active semiconductor layer 310 constituting the driving transistor T1
- the orthographic projections of the channel region T1-c, the source region T1-s and the drain region T1-d) on the substrate 300 at least partially overlap.
- FIG. 17 shows a schematic block diagram of an array substrate according to an embodiment of the present disclosure.
- FIG. 17 shows another configuration of the shielding layer 400c, which is similar to the configuration of the shielding layer 400b in FIG. Substrate 300.
- the blocking layer 400b has a main body 410 in each sub-pixel, a first connecting portion 420 for connecting the main body 410 along the row direction X, and a second connecting portion 430 for connecting the main body 410 along the column direction Y.
- the dimension Sc1 of the first connecting portion 420 along the column direction is smaller than the dimension Sb1 of the main body 410 along the column direction
- the dimension Sc2 of the second connecting portion 430 along the row direction is smaller than the dimension Sb2 of the main body 410 along the row direction.
- size is intended to mean the largest dimension of a component.
- the dimension Sc1 of the first connection part 420 along the column direction may be the same as the dimension Sc2 of the second connection part 430 along the row direction.
- the size Sc1 of the first connection part 420 along the column direction may be different from the size Sc2 of the second connection part 430 along the row direction.
- a dimension Sc1 of the first connection part 420 along the column direction may be smaller than a dimension Sc2 of the second connection part 430 along the row direction.
- FIG. 18 shows a schematic plan layout of a pixel circuit including a stacked shielding layer, an active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer.
- the blocking layer 401c has the configuration shown in FIG. 17 .
- the shielding layer 401c has a main body 411 located in each sub-pixel, a first connecting portion 421 for connecting the main body 411 along the row direction, and a second connecting portion 431 for connecting the main body 410 along the column direction.
- the dimension Sc1 of the first connecting portion 421 along the column direction is smaller than the dimension Sb1 of the main body 410 along the column direction
- the dimension Sc2 of the second connecting portion 430 along the row direction is smaller than the dimension Sb2 of the main body 410 along the column direction.
- the shape and size of the main body 411 are configured to not only at least partially overlap with the active region 3101 of the driving transistor T1 in the direction perpendicular to the substrate, but also at least partially overlap with the fifth connection portion 365 of the fourth conductive layer 360 .
- at least 10% of the area of the fifth connecting portion overlaps with the main body 411 in a direction perpendicular to the substrate. For example, FIG.
- the size (width) Sc2 of the second connection portions 430 and 431 along the row direction may vary along the column direction.
- the width of a portion where the second connection portion overlaps with the wiring extending in the row direction of the signal having a relatively high frequency may be larger than that in the row direction of the signal having a relatively low frequency.
- the wiring extending in the row direction for the signal having a relatively high frequency includes, for example, an emission control signal line EML, a scanning signal line GAL, and the like. The higher the signal frequency, the more significant the parasitic effect.
- the width of the portion where the first connection portion overlaps the wiring extending in the column direction of the signal having a relatively high frequency may be greater than the width of the portion where the first connection portion overlaps the wiring extending in the column direction of the signal having a relatively low frequency. The width of the section.
- the width of the portion where the second connection portion overlaps the wiring extending in the row direction with a constant signal may be larger than the width of the portion where the second connection portion overlaps the wiring extending in the row direction without a constant signal.
- the wiring extending in the row direction with a constant signal may include, for example, a light emission reset voltage line VINL, a first power supply voltage line VDL, and the like.
- the width of the portion where the first connection portion overlaps the wiring extending in the column direction with a constant signal may be greater than the width of the portion where the first connection portion overlaps the wiring extending in the column direction without a constant signal.
- a display panel 700 may include the array substrate 20 according to any embodiment of the present disclosure or an array substrate including the pixel circuit 100 according to any embodiment of the present disclosure.
- the display panel 700 may also include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc., and these components may be existing conventional components, which will not be described in detail here.
- the display panel 700 may be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel.
- the display panel 700 can be not only a flat panel, but also a curved panel, or even a spherical panel.
- the display panel 700 may also have a touch function, that is, the display panel 700 may be a touch display panel.
- Embodiments of the present disclosure further provide a display device, which includes the display panel according to any one of the embodiments of the present disclosure.
- FIG. 20 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure.
- a display device 800 may include the display panel 700 according to any embodiment of the present disclosure.
- the display device 800 may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
- FIG. 21 shows a pixel circuit, which is a 7T1C structure including 7 transistors and 1 capacitor.
- active layers of transistors T1 and T2 include oxide semiconductor material, and transistors T1 and T2 may be N-type oxide transistors.
- the active layers of transistors T3-T7 include silicon semiconductor material, such as low temperature polysilicon.
- FIG. 22 shows a masking layer for the circuit shown in FIG. 21 .
- FIG. 26 shows the position of the shielding layer 0.
- the shielding layer is located between the semiconductor layer of the active layer and the substrate and is at least insulated from the active semiconductor layer.
- FIG. 23 shows the planar layout of each functional layer (semiconductor layer and conductive layer) of the pixel circuit including the light-shielding layer.
- the oxide semiconductors of T1 and T2 are designed as mirror images; the shielding layer shields the silicon semiconductor material.
- the overall plane layout of the pixel circuit including the light-shielding layer is also a mirror image design; in the embodiments of the present disclosure, the mirror image design can also be, for example, the plane layout of the pixel circuit including the light-shielding layer shown in FIG. 24 and FIG. 29 .
- Da is the access point of the data signal terminal Data[m] in FIG.
- Vinit_OLED is the access point of the initial signal terminal Vinit_OLED in FIG. 21, and N1 is the potential point of node N1 in FIG. 21, wherein, N1 is located in the first source-drain layer.
- N4 is the potential point of the node N4 in FIG. 21
- ELVDD is the potential point of the power supply terminal ELVDD in FIG. 21
- ELVDD is located in the first source-drain layer.
- the occlusion layer meets at least one of the following conditions:
- the main part of the shielding layer is covered with silicon semiconductor material, and the coverage area between the N1 node and the shielding layer is greater than 10%; to stabilize the N1 node;
- the shielding layer does not overlap with the oxide channel, or the overlapping area is less than 90%, so as to alleviate the parasitic capacitance on the oxide layer;
- the overlapping area of the shielding layer and the initialization signal line should be reduced as much as possible to reduce the load on the initialization signal line.
- the layout design here is to avoid the arc-shaped trace at the T7 position, and only overlap with the horizontal trace.
- the conductive part 47 is bent and extended in the orthographic projection of the base substrate to reduce the overlapping of the light shielding layer and the second initial signal line Vinit2;
- the initialization signal line can be narrowed where it overlaps with the shielding layer, and the shielding layer can also be narrowed.
- FIG. 24 shows a plan layout of a pixel circuit of an embodiment of the present disclosure.
- the connection lines of the shielding layer along the row and column directions should avoid scanning lines and the like as much as possible to avoid parasitic effects.
- N1 in FIG. 24 is the potential point of node N1 in FIG. 21 , wherein N1 is located in the first source-drain layer.
- the biasing of the shielding layer can be achieved in the following manner.
- Embodiment 3 If a VDD or Vint signal is used, a punching connection can be made at the overlapping position of the VDD line and the Vint line.
- the SD1 and SD2 layers are the source-drain electrode film layers, and the materials may include metal materials, such as molybdenum, aluminum, copper, titanium, niobium, one of them or alloys, or molybdenum/titanium alloys or laminated layers, etc. , or it could be a titanium/aluminum/titanium stack.
- the gate1 and gate2 layers are the gate electrode film layers, which can be made of the same material as the gate of the oxide transistor, and/or made in the same layer.
- the material can be molybdenum, aluminum, copper, titanium, niobium, one of them Or alloy, or molybdenum/titanium alloy or lamination, etc.
- the potential loaded on the shielding layer can be the same potential loaded on the power line VDD (voltage source potential); it can also be the same potential loaded on the initialization signal line; it can also be the same potential loaded on the cathode (cathode potential VSS); it can also be other fixed Potential, for example, the range of fixed potential is -10V ⁇ +10V, and for example, the range of fixed potential is -5V ⁇ +5V, and for example, the range of fixed potential is -3V ⁇ +3V, and for example, the range of fixed potential It is -1V ⁇ +1V, and for example, the range of fixed potential is -0.5V ⁇ +0.5V, and for example, the range of fixed potential is 0V, and for example, the range of fixed potential is 0.1V, and for example, the range of fixed potential The range is 10.1V, and for example, the range of the fixed potential is 0.2V, and for example, the range of the fixed potential is -0.2V, and for example, the range of the fixed potential is 0.3V, and for
- the potential applied to the light-shielding layer may be greater than the potential applied to the cathode (cathode potential VSS), and lower than the potential applied to the power line VDD; or, the potential applied to the light-shielding layer may be greater than the potential applied to the initialization signal line, and lower than the power line VDD Loaded potential.
- the shielding layer may be made of amorphous silicon material, or metal material, or an oxide semiconductor material such as IGZO, or polysilicon material, or a conductorized semiconductor material.
- FIG. 27 it is a schematic circuit structure diagram of a pixel driving circuit in an exemplary embodiment of an array substrate of the present disclosure.
- the pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
- the first pole of the fourth transistor T4 is connected to the data signal terminal Da
- the second pole is connected to the first pole of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2
- the first pole of the fifth transistor T5 is connected to the A power supply terminal VDD
- the second pole is connected to the first pole of the driving transistor DT
- the gate is connected to the enable signal terminal EM
- the gate of the driving transistor T3 is connected to the node N
- the first pole of the second transistor T2 is connected to the node N
- the second pole is connected to the node N.
- the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T3, and the second pole is connected to the first pole of the seventh transistor T7.
- the pixel driving circuit may be connected to a light emitting unit OLED for driving the light emitting unit OLED to emit light, and the light emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power supply terminal VSS.
- the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, and the N-type metal oxide transistors have a small leakage current, so that the light-emitting phase can be avoided, and the node N passes through the first transistor T1 and the second transistor T2 leakage.
- the driving transistor T3, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be low-temperature polysilicon transistors, and low-temperature polysilicon transistors have higher carrier mobility , so as to facilitate the realization of a display panel with high resolution, high response speed, high pixel density, and high aperture ratio.
- the first initial signal terminal and the second initial signal terminal may output the same or different voltage signals according to actual conditions.
- FIG. 28 it is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 27 .
- G1 represents the timing of the first gate driving signal terminal G1
- G2 represents the timing of the second gate driving signal terminal G2
- Re1 represents the timing of the first reset signal terminal Re1
- Re2 represents the timing of the second reset signal terminal Re2
- EM represents the timing of the enable signal terminal EM
- Da represents the timing of the data signal terminal Da.
- the driving method of the pixel driving circuit may include a first reset phase t1, a compensation phase t2, a second reset phase T3, and a light emitting phase t4.
- the first reset phase t1 the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N.
- the compensation stage t2 the first gate drive signal terminal G1 outputs a high-level signal, the second gate drive signal terminal G2 outputs a low-level signal, the fourth transistor T4, the second transistor T2, and the data signal terminal Da outputs a drive The signal is to write the voltage Vdata+Vth to the node N, wherein Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3.
- the second reset signal terminal Re2 outputs a low level signal
- the seventh The transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6.
- the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
- the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
- the array substrate may include a base substrate, a light shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source and drain Floor.
- FIGS. 29-41 FIGS. 29-41 , FIG. 29 is a structural layout of an exemplary embodiment of an array substrate of the present disclosure, FIG. 30 is a structural layout of the light-shielding layer in FIG. 29 , and FIG. 31 is a structure of the first active layer in FIG.
- Figure 32 is the structural layout of the first gate layer in Figure 29
- Figure 33 is the structural layout of the second gate layer in Figure 29
- Figure 34 is the structural layout of the second active layer in Figure 29
- Figure 35 is The structural layout of the third gate layer in Figure 29
- Figure 36 is the structural layout of the first source-drain layer in Figure 29
- Figure 37 is the structural layout of the light-shielding layer and the first active layer in Figure 29
- Figure 38 is the structural layout of Figure 29
- FIG. 39 is the structural layout of the light-shielding layer, the first active layer, the first grid layer, and the second grid layer in FIG. 29.
- FIG. 40 is the structural layout of the light shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG. 29, and FIG. 41 is the light shielding layer, the first active layer, and the second active layer in FIG. The structural layout of the first gate layer, the second gate layer, the second active layer, and the third gate layer.
- the light-shielding layer may include a plurality of repeating units 0 and connecting portions 02 connected between the repeating units 0 .
- the repeating unit 0 may include two light-shielding parts 01 arranged symmetrically along the dotted line A, wherein the dotted line A extends along the second direction Y.
- the light shielding portion 01 may include a first light shielding portion 011 , a second light shielding portion 012 , a third light shielding portion 013 , and a fourth light shielding portion 014 .
- the orthographic projection of the second shading portion 012 and the third shading portion 013 on the substrate may extend along the second direction Y
- the orthographic projection of the fourth shading portion 014 on the substrate may extend along the first direction X
- the second light-shielding part 012 and the third light-shielding part 013 can be respectively connected to both sides of the first light-shielding part 011 in the second direction Y, and the second light-shielding part 012 is projected vertically on the substrate and the third light-shielding part 013 is projected on the substrate.
- the orthographic projections of the base substrates may be separated by a preset distance in the first direction X.
- the fourth light shielding portion 014 may be located on one side of the first light shielding portion in the first direction X.
- two adjacent first light shielding portions 011 in the first direction X are connected.
- two adjacent light shielding portions 01 are connected by respective fourth light shielding portions 014 .
- two adjacent light-shielding parts 01 can be connected by a connecting part 02, wherein the connecting part 02 can respectively connect the second light-shielding part 012 and the third light-shielding part 013 in the two light-shielding parts 01, and the connecting part 02
- the base substrate orthographic projection extends along the first direction X.
- the first direction X and the second direction Y may intersect, for example, the first direction X may be a row direction, and the second direction may be a column direction.
- the first active layer may include an active portion 54 , an active portion 53 , an active portion 55 , and an active portion 57 .
- the active part 54 can be used to form the channel region of the fourth transistor T4
- the active part 53 can be used to form the channel region of the driving transistor T3
- the active part 55 can be used to form the channel of the fifth transistor T5 region
- the active portion 57 may be used to form a channel region of the seventh transistor T7.
- the first active layer may be formed of polycrystalline silicon semiconductor material.
- the first gate layer may include a second gate drive signal line G2 , an enable signal line EM , a second reset signal line Re2 , and a conductive portion 11 .
- Orthographic projections of the second gate driving signal line G2, the enable signal line EM, and the second reset signal line Re2 on the base substrate may all extend along the first direction X.
- the second gate drive signal line G2 can be used to provide the second gate drive signal terminal in FIG. 27, the enable signal line EM can be used to provide the enable signal terminal in FIG. 27, and the second reset signal line Re2 Can be used to provide the second reset signal terminal in Figure 27.
- the orthographic projection of the second gate driving signal line G2 on the substrate can cover the orthographic projection of the active portion 54 on the substrate, and part of the structure of the second gate driving signal line G2 can be used to form the gate of the fourth transistor T4. .
- the orthographic projection of the enabling signal line EM on the substrate can cover the orthographic projection of the active portion 55 on the substrate, and a part of the structure of the enabling signal line EM can be used to form the gate of the fifth transistor T5.
- the orthographic projection of the second reset signal line Re2 on the base substrate covers the orthographic projection of the active portion 57 on the base substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7.
- the orthographic projection of the conductive portion 11 on the substrate can cover the orthographic projection of the active portion 53 on the substrate, the conductive portion 11 can be used to form the gate of the driving transistor T3, and at the same time, the conductive portion 11 can also form a portion of the capacitor C. electrode.
- the first active layer can be doped by using the first gate layer as a mask, so that the first active layer covered by the first gate layer forms a semiconductor structure, and the first active layer not covered by the first gate layer Partially forms a conductor structure.
- the second gate layer may include a first initial signal line Vinit1, a first reset signal line Re1, a first gate driving signal line G1, a conductive portion 21, and a connecting portion. twenty two. Orthographic projections of the first initial signal line Vinit1 , the first reset signal line Re1 , and the first gate driving signal line G1 on the base substrate may all extend along the first direction. Among them, the first initial signal line Vinit1 can be used to provide the first initial signal terminal in FIG. 27, the first reset signal line Re1 can be used to provide the first reset signal terminal in FIG. 27, and the first gate drive signal line G1 It can be used to provide the first gate drive signal terminal in FIG. 27 .
- the conductive part 21 is used for another electrode of the capacitor C. Wherein, the conductive parts 21 adjacent in the first direction X may be connected to each other through the connection part 22 , and a through hole 211 may be formed on the conductive parts 21 .
- the second active layer may include an active portion 6, and the active portion 6 may include an active portion 61 and an active portion 62, wherein the active portion 61 may form a first The channel region of the transistor T1, the active portion 62 may form the channel region of the second transistor T2.
- the active part 6 is located on the side of the active part 61 away from the active part 62 and can be connected to the first initial signal line Vinit1 through the via hole 71 to connect the second pole of the first transistor T1 and the first transistor T1.
- the second active layer may be formed of a metal oxide semiconductor material, for example, InGaZnO.
- the third gate layer may include a gate line 3Re1 , a gate line 3G1 , and a gate line 3Re1 .
- the orthographic projection of the gate line 3Re1 on the substrate may extend along the first direction, and the orthographic projection of the gate line 3Re1 on the substrate at least partially overlaps with the orthographic projection of the first reset signal line Re1 on the substrate.
- the gate line 3Re1 may be connected to the first reset signal line Re1 through at least one via hole, and the via hole may be located in a non-display area or a display area of the display panel.
- the orthographic projection of the gate line 3G1 on the substrate may extend along the first direction, and the orthographic projection of the gate line 3G1 on the substrate may at least partially overlap with the orthographic projection of the first gate driving signal line G1 on the substrate.
- the gate line 3G1 may be connected to the first gate driving signal line G1 through at least one via hole, and the via hole may be located in a non-display area or a non-display area of the display panel.
- the second active layer can be conductively formed by using the third gate layer as a mask, that is, the second active layer covered by the third gate layer forms a semiconductor structure, and the part not covered by the third gate layer form a conductor structure.
- the first source-drain layer may include a conductive portion 41, a conductive portion 42, a conductive portion 43, a conductive portion 44, a conductive portion 45, a conductive portion 46, a conductive portion 47, and a second initial signal line Vinit2,
- the second initial signal line Vinit2 is connected to the conductive part 47 for providing the second initial signal terminal in FIG. 27 .
- the orthographic projection of the second initial signal line Vinit2 on the substrate may at least partially overlap with the orthographic projection of the first reset signal line Re1 on the substrate.
- the conductive part 41 can be connected to the active part 6 through the via hole 72, and connected to the first initial signal line Vinit1 through the via hole 73, so as to connect the second pole of the first transistor T1 and the first initial signal line Vinit1, and the conductive part 41 can be further The contact efficiency of the active part 6 and the first initial signal line Vinit1 is increased.
- the conductive part 42 can connect the position of the active part 6 between the active part 61 and the active part 62 through the via hole 74, and connect the conductive part 11 through the via hole 75, so as to connect the first pole of the first transistor T1 and the driver Gate of transistor T3.
- the via hole 75 may pass through the through hole 211 on the conductive portion 21 , and the conductor filled in the via hole 75 is not electrically connected to the conductive portion 21 .
- the conductive part 43 can be connected to the connection part 22 through the via hole 76 , and at the same time be connected to the first active layer on the side of the active part 55 through the via hole 77 , so as to connect the capacitor C and the first electrode of the fifth transistor T5 .
- the conductive part 44 can be connected to the first active layer between the active part 57 and the active part 56 through the via hole 78 to connect the second pole of the sixth transistor T6, wherein the conductive part 44 can be used to connect the light emitting unit the anode.
- the conductive part 45 can be connected to the active part 6 through the via hole 710, which is located on the side of the active part 62 away from the active part 61, and connected to the first active layer on the side of the active part 53 through the via hole 711 to connect to the second transistor.
- the conductive part 46 can be connected to the connection part 22 through the via hole 712 , and the conductive part 46 can also be connected to a power line for providing the first power signal terminal VDD in FIG. 27 .
- the conductive part 47 can be connected to the first active layer on one side of the active part 57 through the via hole 79, so as to connect the second initial signal line Vinit2 and the second electrode of the seventh transistor T7.
- the orthographic projection of the fourth light shielding portion 014 on the base substrate and the orthographic projection of the connecting portion 22 on the base substrate are at least partially overlapped. This arrangement can minimize the shielding effect of the fourth light shielding portion 014 on light, and increase the light transmittance of the array substrate.
- the orthographic projection of the connecting portion 02 on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate are at least partially overlapped. Similarly, this setting can be minimized.
- the light shielding function of the small connecting portion 02 increases the light transmittance of the array substrate.
- the first reset signal line Re1 is located on the second gate layer, the distance between the first reset signal line Re1 and the light-shielding layer is relatively large, and the capacitive coupling effect of the connecting portion 02 on the first reset signal line Re1 is relatively small. Compared with disposing the connecting portion 02 directly below the gate line in the first gate layer, this arrangement can reduce the capacitive coupling effect of the connecting portion 02 on the gate line.
- the second gate layer may further include a raised portion 23, the raised portion 23 is connected to the first initial signal line Vinit1, the raised portion 23 includes a side edge 231, and the first initial signal line Vinit1 includes a side 232 connected to the side 231 , and the included angle between the side 231 in the orthographic projection of the base substrate and the side 232 in the base substrate is less than 180°.
- the orthographic projection of the protruding portion 23 on the base substrate and the second light-shielding portion 012 are at least partially overlapped on the orthographic projection of the base substrate.
- the protruding part 23 can reduce the resistance of the first initial signal line Vinit1.
- the orthographic projection of the substrate of the protruding part 23 and the second light-shielding part 012 overlap at least partially in the orthographic projection of the substrate, so that the protruding part can be minimized 23
- the light-shielding effect on the array substrate It should be understood that, in other exemplary embodiments, a raised portion of a similar structure may also be provided on other gates extending in the row direction, and the raised portion can be used without affecting the light transmittance of the array substrate. Reduce the resistance of the grid lines.
- the light-shielding layer can be a conductive structure, for example, the light-shielding layer can be located on the metal light-shielding layer, and the light-shielding layer can be connected to a stable voltage source, and the stable voltage source can be the first power signal terminal VDD in FIG. Any one of the two power signal terminals VSS, the first initial signal terminal Vinit1 and the second initial signal terminal Vinti2.
- the light-shielding layer can be connected to the above-mentioned stable power supply in the non-display area or display area of the array substrate.
- the above-mentioned stable voltage source can also be provided by other power sources.
- the orthographic projection of the conductive part 42 on the base substrate and the orthographic projection of the third light shielding part 013 on the base substrate are at least partially overlapped. 42 has a voltage stabilizing effect.
- the conductive part 42 is connected to the gate of the drive transistor T3 (conductive part 11), that is, the third light shielding part 013 has a voltage stabilizing effect on the gate of the drive transistor T3, this setting can reduce the voltage of the gate of the drive transistor T3 in the light-emitting stage. Voltage fluctuations.
- the positive projection of the first light shielding part 011 on the base substrate can cover the positive projection of the active part 53 on the base substrate, and the first light shielding part 011 can play a light shielding effect on the active part 53, thereby reducing the active Section 53 changes in the output characteristics of the drive transistor T3 due to illumination.
- the orthographic projection of the first light-shielding part 011 on the base substrate can also cover the gate of the driving transistor T3 (conductive part 11) on the orthographic projection of the base substrate, so that the first light-shielding part 011 can stabilize the gate of the driving transistor T3. function, thereby reducing the voltage fluctuation of the gate of the driving transistor T3 in the light-emitting phase. As shown in FIG.
- the orthographic projection of the first light-shielding portion 011 on the base substrate can at least partially overlap with the orthographic projection of the conductive portion 42 on the base substrate, so that the first light-shielding portion 011 can further stabilize the gate of the driving transistor T3. pressure effect.
- the area covered by the light-shielding layer of the gate of the driving transistor (conducting part 11) and the conducting part 42 can be greater than 50% of the total area of the conducting part 11 and the conducting part 42, such as 60%-70%; 80%-90%, or between range of values, or cover all, etc.
- the array substrate may further include a second source and drain layer and an anode layer.
- the second source and drain layer may be located on the side of the first source and drain layer away from the base substrate, and the anode layer may be located on the side of the second source and drain layer away from the base substrate. side.
- the second source-drain layer may include a data signal line for providing a data signal terminal in FIG. 27 and a power supply line for providing a first power signal terminal.
- the orthographic projections of the data signal lines and the power lines on the base substrate can both extend along the second direction Y.
- the anode layer may form the anode of the light emitting unit.
- the array can basically include a second source and drain layer, as shown in Figures 42 and 43, Figure 42 is a structural layout of an exemplary embodiment of the array substrate of the present disclosure, and Figure 43 is the structure layout in Figure 42 The structural layout of the second source and drain layer.
- the second source-drain layer may include a data line Da and a power line VDD, and the orthographic projections of the data line Da and the power line VDD on the base substrate may extend along the second direction Y.
- the data line Da can be used to provide the data signal terminal in FIG. 27
- the power supply line VDD can be used to provide the first power signal terminal in FIG. 27 .
- the power line VDD can be connected to the connection part 22 through the via hole 713 to connect the first power signal terminal and the capacitor C.
- the data line can be connected to the first active layer on one side of the active portion 54 through the via hole 714 to connect the first electrode of the fourth transistor T4 and the data signal terminal.
- the power line VDD may include an extension 91 and an extension 92 distributed along its extension direction, wherein the dimension of the extension 91 in the first direction X in the normal projection of the base substrate may be larger than that of the extension 92 in the normal projection of the base substrate.
- the orthographic projection of the extension part 91 on the base substrate can cover the channel regions of the first transistor and the second transistor.
- this setting can shield and light-shield the transistor through the power line VDD; on the other hand, this setting can reduce the resistance of the power line VDD.
- FIG. 44 is a structural layout of an exemplary embodiment of an array substrate of the present disclosure
- FIG. 45 is a structural layout of a second source and drain layer in FIG. 44 .
- the difference between the second source-drain layer shown in FIG. 45 and the second source-drain layer shown in FIG. 43 is that the extension part 91 not only covers the channel regions of the first transistor and the second transistor, but also covers the sixth transistor T6 and the channel region of drive transistor T3.
- both are schematic structural diagrams of the second initial signal line in another exemplary embodiment of the array substrate of the present disclosure.
- the second initial signal line Vinit2 may be a parallel grid line or a broken line, and may be designed according to the consideration of the voltage drop of the initialization signal line.
- the array substrate may also include a first insulating layer 82, a second insulating layer 83, a third insulating layer 84, a fourth insulating layer 85, a sixth insulating layer 86, a dielectric layer 87, a passivation layer 88, a first flat layer 89.
- the base substrate 81, light shielding layer, first insulating layer 82, first active layer, second insulating layer 83, first gate layer, third insulating layer 84, second gate layer, fourth insulating layer 85 are examples of the base substrate 81, light shielding layer, first insulating layer 82, first active layer, second insulating layer 83, first gate layer, third insulating layer 84, second gate layer, fourth insulating layer 85.
- the second active layer, the fifth insulating layer 86, the third gate layer, the dielectric layer 87, the first source-drain layer, the passivation layer 88, the first flat layer 89, and the second source-drain layer are sequentially stacked .
- the first insulating layer 82 includes at least one of a silicon oxide layer and a silicon nitride layer, and the thickness of the first insulating layer 82 may be 2500-3500 angstroms.
- the second insulating layer 83 may be a silicon oxide layer, and the thickness of the second insulating layer 83 may be 1000-2000 angstroms.
- the third insulating layer 84 may be an interlayer insulating layer or an interlayer dielectric layer, the third insulating layer 84 may be a silicon nitride layer, and the thickness may be 1000-2000 angstroms.
- the fourth insulating layer 85 may include a silicon oxide layer and a silicon nitride layer, wherein the thickness of the silicon oxide layer may be 3000-4000 angstroms, and the thickness of the silicon nitride may be 500-1000 angstroms.
- the fifth insulating layer 86 may be a silicon oxide layer with a thickness of 1000-1700 angstroms.
- the dielectric layer 87 may include a silicon oxide layer and a silicon nitride layer, the thickness of the silicon oxide layer may be 1500-2500 ⁇ , and the thickness of the silicon nitride layer may be 2500-3500 ⁇ .
- the side of the second source and drain layer away from the base substrate can also be provided with a second flat layer, the anode layer is located on the side of the second flat layer away from the base substrate, and the side of the anode layer away from the base substrate can also be provided with a light emitting layer.
- the unit layer, the light-emitting unit layer may include an electron injection layer, an organic light-emitting layer, a hole injection layer, and the like.
- the display panel and the display device provided by the embodiments of the present disclosure have the same or similar beneficial effects as the array substrate provided by the foregoing embodiments of the present disclosure. Since the array substrate has been described in detail in the foregoing embodiments, details will not be repeated here.
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Abstract
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Claims (21)
- 一种阵列基板,包括:衬底;设置在所述衬底上的排布为多行多列的多个子像素,所述多个子像素中的至少一个包括像素电路,每个所述像素电路包括:驱动电路、稳压电路、驱动复位电路和发光复位电路,其中,所述驱动电路包括控制端、第一端和第二端,并被配置为向发光器件提供驱动电流,所述稳压电路与所述驱动电路的所述控制端、第一节点和稳压控制信号输入端耦接,并被配置为在来自所述稳压控制信号输入端的稳压控制信号的控制下使所述驱动电路的所述控制端与所述第一节点导通,所述驱动复位电路耦接驱动复位控制信号输入端、所述第一节点和驱动复位电压端,并被配置为在来自所述驱动复位控制信号输入端的驱动复位控制信号的控制下将来自驱动复位电压端的所述驱动复位电压提供给所述稳压电路,以对所述驱动电路的所述控制端进行复位,以及所述发光复位电路耦接发光复位控制信号输入端、发光器件和发光复位电压端,并被配置为在来自所述发光复位控制信号输入端的发光复位控制信号的控制下将来自所述发光复位电压端的发光复位电压提供给所述发光器件,以对所述发光器件进行复位;驱动复位电压线,其耦接所述驱动复位电压端,并被配置为向其提供所述驱动复位电压;以及发光复位电压线,其耦接所述发光复位电压端,并被配置为向其提供所述发光复位电压。
- 根据权利要求1所述的阵列基板,所述驱动电路包括驱动晶体管,所述稳压电路包括稳压晶体管,所述驱动复位电路包括驱动复位晶体管,所述发光复位电路包括发光复位晶体管,其中,所述驱动晶体管的第一极与所述驱动电路的所述第一端耦接,所述驱动晶体管的栅极与所述驱动电路的所述控制端耦接,所述驱动晶体管的第二极与所述驱动电路的所述第一端耦接;其中,所述稳压晶体管的第一极与所述驱动电路的所述控制端耦接,所述稳压晶体管的第二极与所述第一节点耦接,所述稳压晶体管的栅极与所述稳压控制信号输入端耦接;其中,所述驱动复位晶体管的第一极与所述驱动复位电压端耦接,所述驱动复位晶体管的栅极与所述驱动复位控制信号输入端耦接,所述驱动复位晶体管的第二极与所述第一节点耦接;其中,所述发光复位晶体管的第一极与所述发光复位电压端耦接,所述发光复位晶体管的栅极与所述发光复位控制信号输入端耦接,所述发光复位晶体管的第二极与所述发光器件的第一端耦接;其中,所述稳压晶体管的有源层包括氧化物半导体材料,所述驱动晶体管和所述驱动复位晶体管的有源层包括硅半导体材料。
- 根据权利要求2所述的阵列基板,其中,所述发光复位晶体管的有源层包括所述氧化物半导体材料。
- 根据权利要求3所述的阵列基板,进一步包括:位于所述衬底上的第一有源半导体层,包括所述硅半导体材料;以及位于所述第一有源半导体层背离所述衬底一侧的并与所述第一有源半导体层绝缘隔离的第二有源半导体层,包括所述氧化物半导体材料。
- 根据权利要求4所述的阵列基板,其中,所述第一有源半导体层包括所述驱动晶体管的有源层和所述驱动复位晶体管的有源层,其中,所述第二有源半导体层包括沿列方向设置的第一部分和第二部分,所述第二有源半导体的所述第一部分包括所述稳压晶体管的有源层,所述第二有源半导体的所述第二部分包括所述发光复位晶体管的有源层。
- 根据权利要求5所述的阵列基板,其中,所述第二有源半导体的所述第一部分与所述第二有源半导体的所述第二部分沿列方向对准。
- 根据权利要求6所述的阵列基板,所述像素电路进一步包括数据写入电路、补偿电路、存储电路和发光控制电路,其中,所述数据写入电路耦接数据信号输入端、扫描信号输入端和所述驱动电路的所述第一端,并被配置为在来自所述扫描信号输入端的扫描信号的控制下将来自所述数据信号输入端的数据信号提供给所述驱动电路的所述第一端;所述补偿电路耦接所述驱动电路的所述第二端、所述第一节点和补偿控制信号输入端,并被配置为根据来自所述补偿控制信号输入端的补偿控制信号,对所述驱动电路进行阈值补偿;所述存储电路耦接第一电源电压端和所述驱动电路的所述控制端,并被配置为存储所述第一电源电压端与所述驱动电路的所述控制端之间的电压差;以及所述发光控制电路耦接发光控制信号输入端、所述第一电源电压端、所述驱动电路的所述第一端及所述第二端、发光复位电路、以及所述发光器件,并被配置为在来自所述发光控制信号输入端的发光控制信号的控制下将来自所述第一电源电压端的第一电源电压施加至所述驱动电路,并将所述驱动电路产生的驱动电流施加至所述发光器件。
- 根据权利要求7所述的阵列基板,其中,所述数据写入电路包括数据写入晶体管,所述补偿电路包括补偿晶体管,所述存储电路包括存储电容,所述发光控制电路包括第一发光控制晶体管和第二发光控制晶体管,其中,所述数据写入晶体管的第一极与所述数据信号输入端耦接,所述数据写入晶体管的栅极与所述扫描信号输入端耦接,所述数据写入晶体管的第二极与所述驱动电路的所述第一端耦接;其中,所述补偿晶体管的第一极与所述驱动电路的所述第二端耦接,所述补偿晶体管的栅极与所述补偿控制信号输入端耦接,所述补偿晶体管的第二极与所述第一节点耦接;其中,所述存储电容的第一极耦接所述第一电源电压端,所述存储电容的第二极耦接所述驱动电路的所述控制端,并被配置为存储所述第一电源电压端与所述驱动电路的所述控制端之间的电压差;其中,所述第一发光控制晶体管的第一极与所述第一电源电压端耦接,所述第一发光控制晶体管的栅极与所述发光控制信号输入端耦接,所述第一发光控制晶体管的第二极与所述驱动电路的所述第一端耦接;以及其中,所述第二发光控制晶体管的第一极与所述驱动电路的所述第二端耦接,所述第二发光控制晶体管的栅极与所述发光控制信号输入端耦接,所述第二发光控制晶体管的第二极与所述发光器件的第一极耦接。
- 根据权利要求8所述的阵列基板,其中,所述第一有源半导体层包括所述数据写入晶体管、所述补偿晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管的有源层。
- 根据权利要求9所述的阵列基板,其中,所述发光复位控制信号与所述发光控制信号是同一信号。
- 根据权利要求9所述的阵列基板,其中,所述扫描信号与所述补偿控制信号是同一信号。
- 根据权利要求11所述的阵列基板,进一步包括位于所述第一有源半导体层与所述第二有源半导体层之间的并与所述第一有源半导体层和所述第二有源半导体层绝缘隔离的第一导电层,所述第一导电层包括沿列方向依次设置的驱动复位控制信号线、扫描信号线、所述 驱动晶体管的栅极、所述存储电容的第一极、以及发光控制信号线,其中,所述驱动复位控制信号线与所述驱动复位控制信号输入端耦接,并被配置为向其提供所述驱动复位控制信号;其中,所述扫描信号线与所述扫描信号输入端及所述补偿控制信号输入端耦接,被配置为向所述扫描信号输入端提供所述扫描信号,并被配置为向所述补偿控制信号输入端提供所述补偿控制信号;其中,所述存储电容的第一极与所述驱动晶体管的栅极为一体结构;以及其中,所述发光控制信号线与所述发光控制信号输入端,并被配置为向所述发光控制信号输入端提供所述发光控制信号。
- 根据权利要求12所述的阵列基板,其中,所述驱动复位控制信号线在所述衬底上的正投影与所述第一有源半导体层在所述衬底上的正投影的重叠的部分为所述驱动复位晶体管的栅极;其中,所述扫描信号线在所述衬底上的正投影与所述第一有源半导体层在所述衬底上的正投影的重叠的部分为所述补偿晶体管的栅极和所述数据写入晶体管的栅极;以及其中,所述发光控制信号线在所述衬底上的正投影与所述第一有源半导体层在所述衬底上的正投影的重叠的部分为所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的栅极。
- 根据权利要求13所述的阵列基板,进一步包括位于所述第一导电层与所述第二有源半导体层之间的并与所述第一导电层和所述第二有源半导体层绝缘隔离的第二导电层,所述第二导电层包括沿列方向设置的稳压控制信号线、所述存储电容的第二极、第一电源电压线和发光复位控制信号线,其中,所述稳压控制信号线与所述稳压控制信号输入端耦接,并被配置为向其提供所述稳压控制信号;其中,所述第一电源电压线与所述第一电源电压端耦接,并被配置为向其提供所述第一电源电压;其中,所述存储电容的第二极与所述存储电容的第一极在所述衬底上的正投影至少部分重叠;其中,所述存储电容的第二极与所述第一电源电压线一体形成;以及其中,所述发光复位控制信号线与所述发光复位控制信号输入端耦接,并被配置为向其提供所述发光复位控制信号。
- 根据权利要求14所述的阵列基板,其中,所述稳压控制信号线在所述衬底上的正投影与所述第二有源半导体层在所述衬底上的正投影的重叠的部分为所述稳压晶体管的第一栅极;以及其中,所述发光控制信号线在所述衬底上的正投影与所述第二有源半导体层在所述衬底上的正投影的重叠的部分为所述发光复位晶体管的第一栅极。
- 根据权利要求15所述的阵列基板,进一步包括位于所述第二有源半导体层背离所述衬底一侧的并与所述第二有源半导体层绝缘隔离的第三导电层,所述第三导电层包括沿列方向设置的所述稳压控制信号线、所述发光复位控制信号线、以及发光复位电压线。
- 根据权利要求16所述的阵列基板,其中,所述稳压控制信号线在所述衬底上的正投影与所述第二有源半导体层在所述衬底上的正投影的重叠的部分为所述稳压晶体管的第二栅极;其中,所述发光复位控制信号线在所述衬底上的正投影与所述第二有源半导体层在所述衬底上的正投影的重叠的部分为所述发光复位晶体管的第二栅极;以及其中,所述发光复位电压线经由过孔与所述第二有源半导体层耦接,以形成所述发光复位晶体管的第一极。
- 根据权利要求17所述的阵列基板,进一步包括位于所述第三导电层背离所述衬底一侧的并与所述第三导电层绝缘隔离的第四导电层,所述第四导电层包括第一连接部、第二连接部、第三连接部、第四连接部、第五连接部、第六连接部、第七连接部、以及第八连接部,其中,所述第一连接部用作所述驱动复位电压线;其中,所述第一连接部经由过孔与所述驱动复位晶体管的漏极区域耦接,形成所述驱动复位晶体管的第一极;其中,所述第二连接部经由过孔与所述发光复位电压线耦接;其中,所述第三连接部经由过孔与所述数据写入晶体管的漏极区域耦接,形成所述数据写入晶体管的第一极;其中,所述第四连接部经由过孔与所述驱动复位晶体管的源极区域及所述补偿晶体管的源极区域耦接,分别形成所述驱动复位晶体管的第二极及所述补偿晶体管的第二极,所述第四连接部经由过孔与所述稳压晶体管的源极区域耦接,形成所述稳压晶体管的第二极;其中,所述第五连接部经由过孔与所述驱动晶体管的栅极及所述存储电容的第一极耦接,所述第五连接部经由过孔与所述稳压晶体管的漏极区域耦接,形成所述稳压晶体管的第一极;其中,所述第六连接部经由过孔与所述第一发光控制晶体管的漏极区域耦接,形成所述第一发光控制晶体管的第一极;其中,所述第七连接部经由过孔与所述第二发光控制晶体管的源极区域耦接,形成所述第二发光控制晶体管的第二极,所述第七连接部经由过孔与所述发光复位晶体管的源极区域耦接,形成所述发光复位晶体管的第二极;以及其中,所述第八连接部经由过孔与所述发光复位晶体管的源极区域耦接,形成所述发光复位晶体管的第一极。
- 根据权利要求18所述的阵列基板,进一步包括位于所述第四导电层背离所述衬底一侧的并与所述第四导电层绝缘隔离的第五导电层,所述第五导电层包括沿行方向设置的数据信号线、所述第一电源电压线、以及第二电源电压线,其中,所述数据信号线沿列方向延伸,并经由过孔与所述第四导电层的所述第三连接部耦接;其中,所述第一电源电压线沿列方向延伸,并经由过孔与所述第四导电层的所述第三连接部耦接;以及其中,所述第二电源电压线沿列方向延伸,并经由过孔与所述第四导电层的所述第七连接部耦接。
- 一种显示面板,其包括根据权利要求1至19中任一项所述的阵列基板。
- 一种显示装置,其包括根据权利要求20所述的显示面板。
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