WO2022110179A1 - 像素驱动电路及其驱动方法、显示面板 - Google Patents

像素驱动电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2022110179A1
WO2022110179A1 PCT/CN2020/132866 CN2020132866W WO2022110179A1 WO 2022110179 A1 WO2022110179 A1 WO 2022110179A1 CN 2020132866 W CN2020132866 W CN 2020132866W WO 2022110179 A1 WO2022110179 A1 WO 2022110179A1
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WIPO (PCT)
Prior art keywords
base substrate
transistor
orthographic projection
gate
active
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Application number
PCT/CN2020/132866
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English (en)
French (fr)
Inventor
王铸
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/438,448 priority Critical patent/US20230110045A1/en
Priority to DE112020007192.8T priority patent/DE112020007192T5/de
Priority to CN202080003103.7A priority patent/CN115176304A/zh
Priority to PCT/CN2020/132866 priority patent/WO2022110179A1/zh
Publication of WO2022110179A1 publication Critical patent/WO2022110179A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel driving circuit and a driving method thereof, and a display panel.
  • the pixel driving circuit is used to drive the light-emitting unit in the pixel unit to emit light.
  • the pixel driving circuit includes a driving transistor and a capacitor.
  • the driving transistor is used for outputting driving current to the light emitting unit according to its gate voltage output; the capacitor is connected to the gate of the driving transistor for storing electric charge, so as to continuously provide voltage to the driving transistor during the lighting phase of the pixel driving circuit.
  • the gate of the driving transistor is likely to leak electricity through the transistor connected thereto, thereby affecting the stability of the pixel driving circuit to emit light during the light-emitting stage.
  • a pixel driving circuit including: a driving transistor, a data writing circuit, a compensation circuit, a light emission control circuit, a storage circuit, and a reset circuit.
  • the first pole of the driving transistor is connected to the first node, the second pole is connected to the second node, and the gate is connected to the third node;
  • the data writing circuit is connected to the first node and the data signal terminal, and is used for responding to a control signal to write the The signal of the data signal terminal is transmitted to the first node;
  • the compensation circuit is connected to the second node and the third node for responding to a control signal to connect the second node and the third node;
  • the lighting control circuit is connected to the second node and the third node;
  • the first and second poles of the driving transistor, the first power supply terminal, the first electrode of the light-emitting unit, and the enable signal terminal are used to connect the first power supply terminal and the driver in response to the signal of the enable signal terminal An electrode of the transistor, and another electrode connecting the first
  • the first electrode of the first transistor is connected to the third node, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the reset signal terminal; the first electrode of the second transistor is connected to the second electrode of the first transistor
  • the first and second transistors are N-type oxide transistors, and the driving transistor is P-type low-temperature polysilicon transistors.
  • the light-emitting control circuit is configured to connect the first power supply terminal and the second electrode of the driving transistor, and connect the first power terminal of the light-emitting unit in response to a signal of the enable signal terminal. an electrode and the first electrode of the drive transistor.
  • the data writing circuit includes a third transistor, a first terminal of the third transistor is connected to the data signal terminal, a second terminal is connected to the first node, and a gate is connected to the first gate drive signal terminal.
  • the compensation circuit includes a fourth transistor, a first electrode of the fourth transistor is connected to a second node, a second electrode is connected to the third node, and a gate of the fourth transistor is connected to a second gate driving signal terminal; wherein, the third transistor is a P-type low temperature polysilicon transistor, and the fourth transistor is an N-type oxide transistor.
  • the compensation circuit includes a fourth transistor, a first electrode of the fourth transistor is connected to the second node, a second electrode is connected to the third node, and a gate of the fourth transistor is connected to the first gate driving signal terminal; wherein, the third transistor and the fourth transistor are both P-type low-temperature polysilicon transistors.
  • the compensation circuit includes a fourth transistor, a first electrode of the fourth transistor is connected to the second node, a second electrode is connected to the third node, and a gate of the fourth transistor is connected to the first gate driving signal terminal; wherein, the third transistor and the fourth transistor are both N-type oxide transistors.
  • the light-emitting control circuit includes a fifth transistor and a sixth transistor.
  • a first electrode of the fifth transistor is connected to the first power supply terminal, a second electrode is connected to the second node, and a gate electrode is connected to the second node.
  • the pole is connected to the enable signal terminal; the first pole of the sixth transistor is connected to the first node, the second pole is connected to the first electrode of the light-emitting unit, and the gate is connected to the enable signal terminal.
  • the fifth transistor and the sixth transistor are P-type low temperature polysilicon transistors.
  • the storage circuit includes a capacitor, and the capacitor is connected between the first power supply terminal and the third node.
  • a display panel including the above pixel driving circuit, the display panel including: a base substrate, a first active layer, a first conductive layer, a second active layer, a second conductive layer layer, the third conductive layer.
  • the first active layer is located on one side of the base substrate, the first active layer includes a first active part, and the first active part is used to form a channel region of the driving transistor;
  • a conductive layer is located on a side of the first active layer away from the base substrate, the first conductive layer includes a first conductive portion, and the first conductive portion covers the base substrate in an orthographic projection of the base substrate.
  • the first active part is an orthographic projection of the base substrate, and the first conductive part is used to form the gate of the driving transistor.
  • the second active layer is located on the side of the first conductive layer away from the base substrate, and the second active layer includes: a second active part, a third active part, a fourth active part, The fifth active part and the sixth active part.
  • the second active part is located on the side of the first conductive part in the first direction in the orthographic projection of the base substrate; in the first direction, the third active part is The source portion is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the second active portion on the base substrate, and the third active portion has an orthographic projection of the base substrate.
  • the orthographic projection of the source portion on the base substrate is located on one side of the orthographic projection of the second active portion on the base substrate in a second direction, and the first direction intersects the second direction;
  • the fourth active part is connected between the second active part and the third active part, and the orthographic projection of the fourth active part on the base substrate is located at the position of the third active part
  • the base substrate is orthographically projected on one side of a third direction, the second direction is opposite to the third direction, and in the first direction, the fourth active part is on the base substrate
  • the orthographic projection of the first conductive part is located between the orthographic projection of the first conductive part on the base substrate and the orthographic projection of the second active part on the base substrate;
  • the fifth active part is connected to the second active part , the fifth active part is located on the side of the orthographic projection of the base substrate in the first direction of the second active part;
  • the sixth active part is connected to the The third active part is located on the side of the third active part which is orthographically projected on the base
  • the second conductive layer is disposed on the side of the second active layer away from the base substrate, and the second conductive layer includes: a first gate line and a first protrusion.
  • the orthographic projection of the first grid line on the base substrate extends along the second direction, the first grid line includes a second conductive portion, and the orthographic projection of the second conductive portion on the base substrate is the same as the second direction.
  • the third conductive layer is disposed on the side of the second conductive layer away from the base substrate, and the third conductive layer includes: a first connection part and an initial signal line.
  • the first connection part connects the sixth active part and the first conductive part through a via hole; the orthographic projection of the initial signal line on the base substrate extends along the second direction, and the initial signal line is in the
  • the orthographic projection of the base substrate is located on one side of the first gate line on the base substrate which is orthographically projected in the first direction, and the initial signal line is connected to the fifth active part through a via hole.
  • the display panel further includes a fourth conductive layer disposed between the first conductive layer and the second active layer.
  • the fourth conductive layer includes: a second grid line and a second raised portion, the second grid line extends along the second direction on the orthographic projection of the base substrate, and the second grid line includes a fourth conductive portion , the orthographic projection of the second active part on the base substrate is located on the orthographic projection of the fourth conductive part on the base substrate, and the fourth conductive part is used to form the second part of the second transistor a gate; a second raised portion is connected to the second gate line, and in the first direction, the orthographic projection of the second raised portion on the base substrate is located on the second gate line on the
  • the orthographic projection of the base substrate and the first conductive portion are between the orthographic projection of the base substrate, the second raised portion includes a fifth conductive portion, and the third active portion is on the front of the base substrate.
  • the projection is located on the orthographic projection of the fifth conductive portion on the base substrate, and the fifth
  • the light-emitting control circuit includes: a fifth transistor and a sixth transistor.
  • the first pole of the fifth transistor is connected to the first power supply terminal, the second pole is connected to the second node, and the gate is connected to the enable signal terminal; the first pole of the sixth transistor is connected to the first node, and the first pole of the sixth transistor is connected to the first node.
  • the diode is connected to the first electrode of the light-emitting unit, and the gate is connected to the enable signal terminal.
  • the first active layer further includes: a seventh active part and an eighth active part.
  • the seventh active part is used for forming the channel region of the fifth transistor, and in the first direction, the orthographic projection of the seventh active part on the base substrate is located on the first conductive part on the The orthographic projection of the base substrate and the fourth active part are between the orthographic projection of the base substrate; the eighth active part is used to form the channel region of the sixth transistor, and in the first direction, the The orthographic projection of the eighth active portion on the base substrate is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the fourth active portion on the base substrate.
  • the first conductive layer further includes a third grid line, the third grid line extends along the second direction in the orthographic projection of the base substrate, and the third grid line covers the orthographic projection of the base substrate.
  • the orthographic projection of the seventh active part and the eighth active part on the base substrate, part of the third gate line is used to form the gate of the fifth transistor, and part of the third gate line is used to form the gate of the fifth transistor forming the gate of the sixth transistor.
  • the data writing circuit includes a third transistor, a first pole of the third transistor is connected to the data signal terminal, a second terminal is connected to the first node, and a gate of the third transistor is connected to the first node Gate drive signal terminal.
  • the compensation circuit includes a fourth transistor, the first electrode of the fourth transistor is connected to the second node, the second electrode is connected to the third node, and the gate is connected to the second gate driving signal terminal.
  • the third transistor and the fourth transistor are both P-type low temperature polysilicon transistors.
  • the first active layer further includes: a ninth active part and a tenth active part, the ninth active part is used to form a channel region of the third transistor, and the ninth active part is located in the
  • the orthographic projection of the base substrate is located on one side of the first conductive portion on the base substrate which is orthographically projected in a fourth direction, and the fourth direction is opposite to the first direction; the tenth active portion is used to form In the channel region of the fourth transistor, the orthographic projection of the tenth active portion on the base substrate is located on one side of the first conductive portion on the base substrate which is orthographically projected in the fourth direction.
  • the first conductive layer further includes a fourth grid line, the fourth grid line extends along the second direction in the orthographic projection of the base substrate, and the fourth grid line covers the entire surface in the orthographic projection of the base substrate.
  • the orthographic projection of the ninth active part and the tenth active part on the base substrate, part of the fourth gate line is used to form the gate of the third transistor, and part of the fourth gate line is used to form the gate of the third transistor A gate of the fourth transistor is formed.
  • the display panel further includes a fifth conductive layer, and the fifth conductive layer is disposed on a side of the third conductive layer away from the base substrate.
  • the fifth conductive layer includes: a first power line, a first shielding part, a first data line, and a second shielding part.
  • the first power line extends along the first direction on the orthographic projection of the base substrate, and includes a first edge; the first shielding portion is connected to the power line, and the first shielding portion includes and is connected to the first power line
  • the second edge connected by the first edge, the included angle between the orthographic projection of the first edge on the base substrate and the orthographic projection of the second edge on the base substrate is less than 180°, and the first shielding portion is located on the base substrate.
  • the orthographic projection of the base substrate covers the orthographic projection of the third active portion on the base substrate; the orthographic projection of the first data line on the base substrate extends along the first direction and includes a third edge; the second shields The second shielding part includes a fourth edge connected to the third edge of the first data line, the third edge is orthographically projected on the base substrate and the fourth edge is on the
  • the included angle of the orthographic projection of the base substrate is less than 108°, and the orthographic projection of the second shielding portion on the base substrate covers the orthographic projection of the second active portion on the base substrate.
  • the data writing circuit includes a third transistor, a first pole of the third transistor is connected to the data signal terminal, a second terminal is connected to the first node, and a gate of the third transistor is connected to the first node Gate drive signal terminal.
  • the compensation circuit includes a fourth transistor, the first electrode of the fourth transistor is connected to the second node, the second electrode is connected to the third node, and the gate is connected to the second gate driving signal terminal.
  • the third transistor is a P-type low temperature polysilicon transistor
  • the fourth transistor is an N-type oxide transistor.
  • the first active layer further includes an eleventh active part, where the eleventh active part is used to form a channel region of the third transistor, and the eleventh active part is located on the base of the base substrate.
  • the orthographic projection is located on one side of the first conductive portion on the base substrate which is orthographically projected in a fourth direction, and the fourth direction is opposite to the first direction; the first conductive layer further includes a fifth grid line, and the fourth direction is opposite to the first direction.
  • the five grid lines extend along the second direction on the orthographic projection of the base substrate.
  • the fifth gate line is orthographically projected on the base substrate to cover the eleventh active portion, and a part of the fifth gate line is used to form the gate of the third transistor.
  • the fourth conductive layer further includes a sixth grid line, the sixth grid line extends along the second direction in the orthographic projection of the base substrate, and the sixth grid line is located in the second direction in the orthographic projection of the base substrate
  • the fifth gate line is orthographically projected on one side of the base substrate in the fourth direction.
  • the second active layer further includes: a twelfth active part, a thirteenth active part, and a fourteenth active part, where the twelfth active part is used to form the first channel region of the fourth transistor, The twelfth active part is located on the orthographic projection of the base substrate and the sixth gate line is located on the orthographic projection of the base substrate; the thirteenth active part is used to form the second channel of the fourth transistor area, the thirteenth active part is located on the orthographic projection of the base substrate and the sixth gate line is located on the orthographic projection of the base substrate; the fourteenth active part is connected to the twelfth active part and the Between the thirteenth active parts, the fourteenth active part is located on a side of the sixth gate line on the orthographic projection of the base substrate in the fourth direction.
  • the second conductive layer further includes: a seventh grid line, the seventh grid line extends along the second direction in the orthographic projection of the base substrate, and the seventh grid line covers the entire surface in the orthographic projection of the base substrate.
  • the twelfth active part and the thirteenth active part are orthographically projected on the base substrate.
  • the fifth conductive layer further includes a second power line, the second power line extends along the first direction on the orthographic projection of the base substrate, and the second power line is on the substrate
  • the orthographic projection of the substrate covers the orthographic projection of the fourteenth active part on the base substrate.
  • the second power line includes a fifth edge
  • the fifth conductive layer further includes a third shielding portion
  • the third shielding portion is connected to the second power line
  • the third shielding portion comprising a sixth edge connected to the fifth edge of the second power line
  • the included angle between the orthographic projection of the sixth edge on the base substrate and the orthographic projection of the fifth edge on the base substrate is less than 180°
  • the third shielding portion covers the second active portion and the third active portion by orthographic projection on the base substrate.
  • a display panel including the above-mentioned pixel driving circuit.
  • a method for driving a pixel driving circuit for driving the above-mentioned pixel driving circuit comprising:
  • the first transistor and the second transistor are turned on, so as to input an initial signal to the third node and the first electrode of the light-emitting unit through the initial signal terminal;
  • the compensation circuit it is beneficial for the compensation circuit to turn on the first node and the third node, and at the same time use the data writing circuit to write a data signal to the first node;
  • a light-emitting control circuit is used to connect the first power supply terminal and one electrode of the driving transistor, and connect the first electrode of the light-emitting unit and the other electrode of the driving transistor.
  • FIG. 1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit of the present disclosure
  • FIG. 2 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure
  • FIG. 3 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 2;
  • FIG. 4 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • FIG. 6 is a structural layout of a first active layer in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 7 is a structural layout of a first conductive layer in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 8 is a structural layout of a fourth conductive layer in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 9 is a structural layout of a second active layer in an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 10 is a structural layout of a second conductive layer in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 11 is a layout of a stacked structure of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, and a second conductive layer in an exemplary embodiment of the disclosed display panel;
  • FIG. 12 is a structural layout of a third conductive layer in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 13 is a layout of a stacked structure of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, and a third conductive layer in an exemplary embodiment of the disclosed display panel;
  • FIG. 14 is a structural layout of a fifth conductive layer in an exemplary embodiment of a display panel of the present disclosure
  • 15 is a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, a third conductive layer, and a fifth conductive layer in an exemplary embodiment of a display panel of the present disclosure Layout of the cascading structure;
  • Figure 16 is a partial cross-sectional view along the dashed line AA in Figure 15;
  • 17 is a structural layout of a first active layer in another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 18 is a structural layout of a first conductive layer in another exemplary embodiment of a display panel of the present disclosure.
  • 19 is a structural layout of a fourth conductive layer in another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 20 is a structural layout of a second active layer in another exemplary embodiment of a display panel of the present disclosure.
  • 21 is a structural layout of a second conductive layer in another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 22 is a layout of a stacked structure of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, and a second conductive layer in another exemplary embodiment of the disclosed display panel;
  • FIG. 23 is a structural layout of a third conductive layer in another exemplary embodiment of a display panel of the present disclosure.
  • FIG. 24 is a layout of a stacked structure of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, and a third conductive layer in another exemplary embodiment of the display panel of the present disclosure ;
  • 25 is a structural layout of a fifth conductive layer in another exemplary embodiment of a display panel of the present disclosure.
  • 26 is a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, a third conductive layer, and a fifth conductive layer in another exemplary embodiment of the display panel of the present disclosure
  • Layer stack structure layout
  • FIG. 27 is a partial cross-sectional view taken along the dotted line AA in FIG. 26 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure.
  • the pixel driving circuit may include: a driving transistor DT, a data writing circuit 1 , a compensation circuit 2 , a lighting control circuit 3 , a storage circuit 4 , and a reset circuit 5 .
  • the first pole of the driving transistor DT is connected to the first node N1, the second pole is connected to the second node N2, and the gate is connected to the third node N3;
  • the data writing circuit 1 is connected to the first node N1 and the data signal terminal Da, for The signal of the data signal terminal Da is transmitted to the first node N1 in response to a control signal;
  • the compensation circuit 2 is connected to the second node N2 and the third node N3 for responding to a control signal to connect the The second node N2 and the third node N3;
  • the light-emitting control circuit is connected to the first and second electrodes of the driving transistor DT, the first power supply terminal VDD, the first electrode of the light-emitting unit OLED, and the enable signal terminal EM, the The light-emitting control circuit 3 is used for connecting the first power supply terminal VDD and the first electrode of the driving transistor DT (ie, the first node N1 ) in response to the signal of the enable signal terminal EM, and connecting the light
  • the first electrode of the first transistor T1 is connected to the third node N3, the second electrode is connected to the first electrode of the light-emitting unit OLED, and the gate is connected to the reset signal terminal Re; the first electrode of the second transistor T2 is connected to the first electrode of the first transistor T2.
  • the second pole of a transistor T1 is connected to the initial signal terminal Vinit, and the gate is connected to the reset signal terminal Re; wherein, the first transistor T1 and the second transistor T2 are N-type oxide transistors, and the driving transistor DT It is a P-type low temperature polysilicon transistor.
  • the first electrode of the light-emitting unit OLED may be the anode of the light-emitting unit, and the cathode of the light-emitting unit OLED may be connected to the second power supply terminal VSS.
  • the first transistor T1 and the second transistor T2 can be turned on, so as to connect the third node N3 and the first transistor of the light-emitting unit OLED to the third node N3 through the initial signal terminal Vinit.
  • the electrode inputs an initial signal; in the compensation stage, the compensation circuit 2 can turn on the first node N1 and the third node N3, and at the same time use the data writing circuit 1 to write a data signal to the first node N1, thereby Write the voltage Vdata+Vth to the third node and store it in the storage circuit, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor; in the light-emitting stage, the light-emitting control circuit 3 is used to connect the first power supply The terminal VDD and the first electrode of the driving transistor DT (ie the second node N1), and the first electrode of the light emitting unit OLED and the second electrode of the driving transistor DT (ie the second node N2) are connected to drive the The transistor DT outputs a driving current to the light emitting unit OLED under the action of the charges of the third node N3.
  • the driving transistor DT in the pixel driving circuit may be a P-type low-temperature polysilicon transistor, and the low-temperature polysilicon transistor has high carrier mobility, so that the pixel driving circuit is conducive to realizing high resolution , a display panel with high response speed, high pixel density, and high aperture ratio;
  • the first transistor T1 and the second transistor T2 are N-type oxide transistors, and the oxide transistors have a small leakage current, which can reduce the number of pixels
  • the third node N3 passes the leakage current of the first transistor T1 and the second transistor T2.
  • the first transistor T1 and the second transistor T2 are connected in series between the third node N3 and the initial signal terminal Vinit, so that the leakage current from the third node N3 to the initial signal terminal Vinit can be reduced;
  • the voltage written to the third node N3 by the initial signal terminal Vinit needs to be able to turn on the driving transistor DT, so as to write the voltage Vdata+Vth to the third node N3 in the compensation stage.
  • the voltage of the initial signal terminal Vinit is relatively small, generally is a negative value, in the light-emitting stage, the voltage of the second node N2 is less than the voltage of the third node N3 and greater than the voltage of the initial signal terminal Vinit, that is, the voltage of the first electrode of the light-emitting unit OLED is less than the voltage of the third node N3 and greater than the initial signal
  • the voltage of the first electrode of the light-emitting unit OLED can effectively isolate the third node N3 and the initial signal terminal Vinit. A larger voltage across, thereby reducing the leakage current from the third node to the initial signal terminal Vinit.
  • the voltage of the second node N2 changes with the voltage of the third node N3.
  • the voltage of the third node N3 is lower, and the voltage of the second node The voltage is higher.
  • the voltage of the third node N3 is higher, and the voltage of the second node is lower. Therefore, under different display gray levels, there are different voltage differences between the third node N3 and the second node N2, so that under different display gray levels, the third node N3 has different leakage currents to the second node N.
  • the leakage current from the third node N3 to the second node N2 is relatively large, and at the same time, due to the high sensitivity of the human eye to changes in brightness at low brightness, the third node N3 to the second node N2 The leakage current will seriously affect the display effect of the display panel.
  • FIG. 2 it is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • the light-emitting control circuit 3 may be configured to connect the first power supply terminal VDD and the second pole (ie, the second node N2 ) of the driving transistor DT in response to the signal of the enable signal terminal EM, and connect the The first electrode of the light emitting unit OLED and the first electrode of the driving transistor DT (ie, the first node N1).
  • Other structures of the pixel driving circuit can be the same as the pixel driving circuit shown in FIG. 1 .
  • the first power supply terminal VDD is connected to the second node N2, and the first electrode of the light emitting unit OLED is connected to the first node.
  • the voltage of the second node N2 is stable to the voltage of the first power supply terminal VDD, and the voltage of the second node N2 will not change with the change of the driving gray scale. Therefore, the pixel driving circuit has a relatively stable voltage. drive effect.
  • the voltage of the third node N3 is higher, and the voltage of the second node N2 is also higher, and the third node N3 has a smaller leakage current to the second node N2.
  • the data writing circuit 1 may include a third transistor T3 , the first pole of the third transistor T3 is connected to the data signal terminal Da, and the second terminal is connected to the first A node N1, the gate of which is connected to the first gate driving signal terminal Gate1.
  • the compensation circuit 2 may include a fourth transistor T4 , the first pole of the fourth transistor T4 is connected to the second node N2 , and the second pole is connected to the third node N3, the gate is connected to the first gate driving signal terminal Gate1; wherein, the third transistor T3 and the fourth transistor T4 can both be P-type low temperature polysilicon transistors.
  • the light-emitting control circuit 3 may include a fifth transistor T5 and a sixth transistor T6.
  • the first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, and the second The pole is connected to the first node N1, the gate is connected to the enable signal terminal EM; the first pole of the sixth transistor T6 is connected to the second node N2, and the second pole is connected to the first electrode of the light-emitting unit OLED, The gate is connected to the enable signal terminal EM.
  • the fifth transistor T5 and the sixth transistor T6 may be P-type low temperature polysilicon transistors.
  • the light-emitting control circuit 3 may include a fifth transistor T5 and a sixth transistor T6.
  • the first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, and the second The pole is connected to the second node N2, the gate is connected to the enable signal terminal EM; the first pole of the sixth transistor T6 is connected to the first node N1, and the second pole is connected to the first electrode of the light-emitting unit OLED, The gate is connected to the enable signal terminal EM.
  • the fifth transistor T5 and the sixth transistor T6 may be P-type low temperature polysilicon transistors.
  • the storage circuit 4 may include a capacitor C, and the capacitor C may be connected between the first power supply terminal VDD and the third node N3 . It should be understood that the capacitor C may also be connected between the third node N3 and other stable signal terminals.
  • FIG. 3 it is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 2 .
  • EM represents the signal timing of the enable signal terminal
  • Re represents the signal timing of the reset signal terminal
  • Gate1 represents the signal timing of the first gate driving signal terminal.
  • the driving method of the pixel driving circuit includes three stages: a reset stage T1, a compensation stage T2, and a light-emitting stage T3.
  • the reset signal terminal In the reset stage T1, the reset signal terminal outputs a high-level signal to turn on the first transistor T1, the second transistor T1, and the second In the transistor T2, the signal of the initial signal terminal Vinit is transmitted to the third node and the first electrode of the light-emitting unit OLED, wherein the driving transistor DT is turned on under the action of the initial signal terminal signal; in the compensation stage T2, the first gate driving signal The terminal Gate1 outputs a low-level signal, the third transistor T3 and the fourth transistor T4 are turned on, and the data signal terminal writes a voltage Vdata+Vth to the third node, where Vdata is the voltage of the data signal terminal, and Vth is the threshold voltage of the driving transistor In the light-emitting stage T3, the enable signal terminal outputs a low-level signal to turn on the sixth transistor T6 and the fifth transistor T5, and the drive transistor DT emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the output current formula of the driving transistor I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, and L is the driving transistor The length of the channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the output current I ( ⁇ WCox/2L)(Vdata+Vth ⁇ Vdd ⁇ Vth) 2 of the driving transistor in the pixel driving circuit of the present disclosure.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • FIG. 4 it is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure.
  • the third transistor T3 may be a P-type low temperature polysilicon transistor
  • the fourth transistor T4 may be an N-type oxide transistor.
  • the fourth transistor T4 may be connected to the second gate driving signal terminal Gate2, so as to turn on the fourth transistor T4 through the second gate driving signal terminal Gate2 in the compensation stage.
  • the oxide transistor has a small leakage current, which can reduce the leakage of electricity from the third node N3 to the second node through the fourth transistor during the light-emitting stage of the pixel driving circuit.
  • FIG. 5 it is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure.
  • the difference between the pixel driving circuit and the pixel driving circuit is that the third transistor T3 and the fourth transistor T4 can both be N-type oxide transistors. Both the third transistor T3 and the fourth transistor T4 can be turned on under the action of the high level of the first gate driving signal terminal Gate1 in the compensation stage, so as to write the compensation voltage to the third node.
  • This arrangement reduces the leakage of electricity from the third node N3 to the second node through the fourth transistor, and can realize the driving of the third transistor T3 and the fourth transistor T4 only through the first gate driving signal terminal Gate1, that is, the pixel driving circuit is applied.
  • the display panel can simultaneously drive the third transistor T3 and the fourth transistor T4 through a gate driving circuit.
  • the third transistor T3 and the fourth transistor T4 in FIGS. 1 , 2 , 4 , and 5 may all be of a double-gate structure, that is, the third transistor T3 and the fourth transistor T4 may include two active regions , this setting can reduce the leakage current of the third transistor T3 and the fourth transistor T4.
  • the present exemplary embodiment also provides a display panel, which may include a pixel driving circuit as shown in FIG. 2 , as shown in FIGS. 6-15 , and FIG. 6 is the first display panel in an exemplary embodiment of the present disclosure.
  • a structural layout of an active layer FIG. 7 is a structural layout of a first conductive layer in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 8 is a structure of a fourth conductive layer in an exemplary embodiment of a display panel of the present disclosure Layout
  • FIG. 9 is the structural layout of the second active layer in an exemplary embodiment of the display panel of the present disclosure
  • FIG. 10 is the structural layout of the second conductive layer in an exemplary embodiment of the display panel of the present disclosure;
  • FIG. 12 is the first display panel of the present disclosure.
  • 13 is the first active layer, the first conductive layer, the fourth conductive layer, the second active layer, the The stacked structure layout of the second conductive layer and the third conductive layer;
  • FIG. 14 is the structural layout of the fifth conductive layer in an exemplary embodiment of the display panel of the present disclosure;
  • FIG. 15 is the layout of the display panel in an exemplary embodiment of the present disclosure.
  • the display panel may include: a base substrate 1 , a first active layer, a first conductive layer, a second active layer, a second conductive layer, and a third conductive layer.
  • the first active layer is located on one side of the base substrate 1, the first active layer includes a first active part 21, and the first active part 21 is used to form the channel of the driving transistor DT
  • the first conductive layer may be located on the side of the first active layer away from the base substrate 1, and the first conductive layer may include a first conductive portion 31, and the first conductive portion 31 may be located on the side of the first active layer.
  • the orthographic projection of the base substrate covers the orthographic projection of the first active portion 21 on the base substrate, and the first conductive portion 31 is used to form the gate of the driving transistor DT.
  • the second active layer may be located on the side of the first conductive layer away from the base substrate 1 , and the second active layer may include: a second active part 42 , a third active part 43 , a fourth The active part 44 , the fifth active part 45 , and the sixth active part 46 .
  • the second active part 42 is located on the side of the first conductive part 31 on the orthographic projection of the base substrate in the first direction Y1; the third active part 43 is located on the side of the base substrate.
  • the orthographic projection of the base substrate is located on the side of the orthographic projection of the first conductive portion 31 on the base substrate in the first direction Y1, and the orthographic projection of the third active portion 43 on the base substrate Located on the side of the second active part 42 on the second direction X1 of the orthographic projection of the base substrate, the first direction Y1 intersects the second direction X1, for example, the first direction Y1 is perpendicular to the second direction X1.
  • the fourth active part 44 is connected between the second active part 42 and the third active part 43 , and the orthographic projection of the fourth active part 44 on the base substrate is located in the third active part
  • the active portion 43 is projected on the base substrate on one side of the third direction X2, the second direction X1 is opposite to the third direction X2, and on the first direction Y1, the fourth direction X1 is opposite to the third direction X2.
  • the orthographic projection of the active portion 44 on the base substrate is located between the orthographic projection of the first conductive portion 31 on the base substrate and the orthographic projection of the second active portion 42 on the base substrate.
  • the fifth active part 45 may be connected to the second active part 42 , and the orthographic projection of the fifth active part 45 on the base substrate may be located on the front side of the base substrate of the second active part 42 .
  • the sixth active part 46 can be connected to the third active part 43 , and the sixth active part 46 is located in the orthographic projection of the base substrate and the third active part 43 is in the orthographic projection of the base substrate one side in the second direction X1.
  • the second conductive layer may be disposed on the side of the second active layer away from the base substrate, and the second conductive layer may include: a first gate line 51 and a first protrusion 52 , wherein the first gate Line 51 may be used to provide the reset signal terminal in FIG. 2 .
  • the first grid line 51 extends along the second direction X1 on the orthographic projection of the base substrate, and the first grid line 51 may include a second conductive portion 512, and the second conductive portion 512 is on the base substrate
  • the orthographic projection of the second active portion 42 on the base substrate may be coincident, and the second conductive portion 512 may be used to form the first gate of the second transistor T2;
  • the first raised portion 52 may be connected to the first grid line 51, and in the first direction, the orthographic projection of the first raised portion 52 on the base substrate may be located on the substrate of the first grid line 51
  • the first protruding portion 52 may include a third conductive portion 523, and the third conductive portion 523 is on the substrate
  • the orthographic projection of the substrate may coincide with the orthographic projection of the third active portion 43 on the base substrate, and the third conductive portion 523 may be used to form the first gate of the first transistor T1.
  • the first active layer may be
  • the display panel may further include a fourth conductive layer disposed between the first conductive layer and the second active layer.
  • the fourth conductive layer may include: a second gate line 81 and a second raised portion 82, wherein the second gate line 81 may provide the reset signal terminal in FIG. 2, and the second gate line 81 may run along the periphery of the display panel.
  • the line area is connected to the first gate line 51 through a via hole.
  • the second gate line 81 extends along the second direction X1 in the orthographic projection of the base substrate, the second gate line 81 may include a fourth conductive portion 814, and the second active portion 42 is located on the substrate
  • the orthographic projection of the substrate may be located on the orthographic projection of the fourth conductive portion 814 on the base substrate, and the fourth conductive portion 814 may be used to form the second gate of the second transistor T2;
  • the second raised portion 82 can be connected to the second grid line 81, and in the first direction Y1, the orthographic projection of the second raised portion 82 on the base substrate can be located on the second grid line 81 on the substrate.
  • the second protruding portion 82 may include a fifth conductive portion 825 , and the third active portion 43 is located between the orthographic projection of the base substrate.
  • the orthographic projection of the base substrate may be located on the orthographic projection of the fifth conductive portion 825 on the base substrate, and the fifth conductive portion 825 may be used to form the second gate of the first transistor T1.
  • the fourth conductive layer may further include a sixth conductive portion 86 , and the sixth conductive portion 86 covers the orthographic projection of the base substrate on the first conductive portion on the base substrate. Projection, the sixth conductive portion 86 can be used to form an electrode of the capacitor C. As shown in FIG.
  • the sixth conductive portion 86 may be provided with an opening 861 .
  • a third conductive layer may be disposed on the side of the second conductive layer away from the base substrate, and the third conductive layer may include: a first connection portion 61 , an initial signal Line 62.
  • the initial signal line 62 may be used to provide the initial signal terminal in FIG. 2 .
  • the first connection part 61 can be connected to the sixth active part 46 through the via hole 71, and the first connection part 61 can also be connected to the first conductive part 31 through the via hole 78, so that the gate of the driving transistor DT and the first conductive part 31 can be realized.
  • the first pole of a transistor T1 is connected.
  • the orthographic projection of the via hole 78 on the base substrate and the opening 861 on the sixth conductive portion 86 are within the orthographic projection of the base substrate, that is, the orthographic projection of the via hole 78 on the base substrate There is a certain distance between the edge of the opening 861 and the edge of the orthographic projection of the opening 861 , so that the conductive material filled in the via hole 78 can be insulated from the sixth conductive portion 86 .
  • the orthographic projection of the initial signal line 62 on the base substrate may extend along the second direction X1 , and the orthographic projection of the initial signal line 62 on the base substrate may be located at any
  • the first gate line 51 is projected on one side of the base substrate in the first direction Y1, wherein the initial signal line 62 can provide the initial signal terminal in FIG. 2, and the initial signal line 62 can pass through the via hole 72 It is connected to the fifth active part 45, so that the second pole of the second transistor T2 can be connected to the initial signal terminal.
  • the orthographic projections of the fourth active part 44 and the sixth active part 46 on the base substrate may be located in the first direction Y1.
  • the fourth active portion 44 may pass through between the first conductive portion 31 and the first grid line 51
  • the conductive structure between them is connected to the driving transistor, and the sixth active part 46 can be electrically connected to the first conductive part 31 through the conductive structure located between the first gate line 51 and the first conductive part 31, so that the pixels of the display panel are driven
  • the circuit has a high degree of integration.
  • both the first transistor T1 and the second transistor T2 adopt a double-gate structure, and the first gate line 51 and the second gate line 81 can provide gate voltages to the first transistor T1 and the second transistor T2 at the same time.
  • the response speed of the first transistor T1 and the second transistor T2, and the gates of the first transistor T1 and the second transistor T2 located in the fourth conductive layer can block the channel region thereof, so as to avoid the light on the first transistor T1 and the second transistor T1 and the second transistor T2.
  • the influence of the characteristics of the channel region of the two transistors T2 to improve the electrical stability of the first transistor T1 and the second transistor T2.
  • the display panel may also not be provided with the second grid line 81 .
  • the first active layer may further include: a seventh active part 27 and an eighth active part 28 .
  • the seventh active part 27 can be used to form the channel region of the fifth transistor T5, and in the first direction Y1, the orthographic projection of the seventh active part 27 on the base substrate can be located in the first direction Y1. Between the orthographic projection of a conductive portion 31 on the base substrate and the orthographic projection of the fourth active portion 44 on the base substrate.
  • the eighth active part 28 may be used to form the channel region of the sixth transistor T6, and in the first direction Y1, the orthographic projection of the eighth active part 28 on the base substrate may be located in the first direction Y1.
  • the first conductive layer may further include a third grid line 33, the orthographic projection of the third grid line 33 on the base substrate may extend along the second direction X1, and the third grid line 33 may be used to provide FIG. 2 . in the enable signal terminal.
  • the third gate line 33 may include a first gate part 331 and a second gate part 332.
  • the orthographic projection of the first gate part 331 on the base substrate may cover the seventh active part 27.
  • the orthographic projection of the second gate portion 332 on the base substrate may cover the orthographic projection of the eighth active portion 28 on the base substrate.
  • the first gate part 331 may be used to form the gate of the fifth transistor T5, and the second gate part 332 may be used to form the gate of the sixth transistor.
  • the first active layer may further include: a ninth active part 29 and a tenth active part 210 , and the ninth active part 29 is used for The channel region of the third transistor T3 is formed, and the orthographic projection of the ninth active portion 29 on the base substrate is located on the orthographic projection of the first conductive portion 31 on the base substrate in the fourth direction Y2
  • the fourth direction X2 is opposite to the first direction Y1
  • the tenth active part 210 is used to form the channel region of the fourth transistor T4, and the tenth active part 210 is in the
  • the orthographic projection of the base substrate is located on the side of the first conductive portion 31 in the fourth direction Y2 on the orthographic projection of the base substrate.
  • the first conductive layer may further include a fourth gate line 34, the fourth gate line 34 may extend along the second direction X1 on the orthographic projection of the base substrate, and the fourth gate line 34 may include a third gate portion 343 and the fourth gate part 344, the orthographic projection of the third gate part 343 on the base substrate can cover the orthographic projection of the ninth active part 29 on the base substrate, and the fourth gate part 344
  • the orthographic projection on the base substrate may cover the orthographic projection of the tenth active part 210 on the base substrate.
  • the third gate part 343 may be used to form the gate of the third transistor T3, and the fourth gate part 344 may be used to form the gate of the fourth transistor T4.
  • the third conductive layer further includes: a third connection part 63 , a fourth connection part 64 , and a fifth connection part 65 .
  • the third connection portion 63 is connected to the fourth active portion 44 through the via hole 73 , and is connected to the active portion 219 on the side of the eighth active portion through the via hole 74 to connect the second active portion of the first transistor T1 pole and the second pole of the sixth transistor T6.
  • the third connection portion 63 may also be connected to the fourth active portion 44 through a plurality of via holes.
  • the third connection portion 63 may be connected to the fourth active portion 44 through two via holes.
  • the fourth connection part 64 can be connected to one side of the seventh active part 27 through the via hole 75 , and the fourth connection part 64 is also connected to the sixth conductive part 86 through the via hole 77 , thereby connecting the first electrode of the fifth transistor T5 and the capacitor one electrode of C.
  • the fifth connection part 65 is connected to one side of the ninth active part through the via hole 76 to connect to the first electrode of the third transistor T3. It should be understood that, the first connection portion 61 , the third connection portion 63 , the fourth connection portion 64 , and the fifth connection portion 65 may also be located on other conductive layers as the transfer layer.
  • the first connection part 61 can also be located in any layer of the second conductive layer and the fifth conductive layer; the third connection part 63 can also be located in the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer In any layer of the conductive layers, the fourth connection part 64 may also be located in the second conductive layer; the fifth connection part 65 may also be located in any layer of the second conductive layer and the fourth conductive layer.
  • the display panel may further include a fifth conductive layer, and the fifth conductive layer may be disposed on a side of the third conductive layer away from the base substrate.
  • the fifth conductive layer may include: a first power line 91 , a first shielding portion 92 , a first data line 93 , and a second shielding portion 94 .
  • the first power line 91 can extend along the first direction Y1 on the orthographic projection of the base substrate, and includes a first edge 911; the first shielding portion 92 is connected to the power line 91, and the first shielding portion 92 includes The second edge 922 connected to the first edge 911 of the first power line 91, the angle between the orthographic projection of the first edge 911 on the base substrate and the orthographic projection of the second edge 922 on the base substrate is less than 180°. That is, the first shielding portion 92 is located on the side of the orthographic projection of the first power line 91 on the base substrate on the base substrate. As shown in FIGS. 14 and 15 , the first shielding portion 92 is located on the substrate.
  • the orthographic projection of the substrate may be located on the side of the first power line 91 on the third direction X2 of the orthographic projection of the base substrate.
  • the orthographic projection of the first shielding portion 92 on the base substrate may cover the orthographic projection of the third active portion 43 on the base substrate.
  • the first shielding portion 92 can avoid the influence of light on the characteristics of the channel region of the first transistor T1, so as to improve the electrical stability of the first transistor T1.
  • the first data line 93 can extend along the first direction Y1 in the orthographic projection of the base substrate, and includes a third edge 933; the second shielding portion 94 can be connected to the data line 93, and the second shielding portion 94 It may include a fourth edge 944 connected to the third edge 933 of the first data line, a clip between the orthographic projection of the third edge 933 on the base substrate and the orthographic projection of the fourth edge 944 on the base substrate The angle is less than 108°. That is, the second shielding portion 94 is located on the side of the orthographic projection of the data line 93 on the base substrate on the base substrate. As shown in FIGS. 14 and 15 , the second shielding portion 94 is located on the front side of the base substrate.
  • the projection may be located on the side of the data line 93 on the second direction X1 which is orthographically projected on the base substrate.
  • the orthographic projection of the second shielding portion 944 on the base substrate covers the orthographic projection of the second active portion 42 on the base substrate.
  • the second shielding portion 944 can avoid the influence of light on the characteristics of the channel region of the second transistor T2, so as to improve the electrical stability of the second transistor T2.
  • the first power line 91 may provide the first power terminal in FIG. 2
  • the data line 93 may provide the data signal terminal in FIG. 2 .
  • the first power line 91 may be connected to the fourth connection part 64 through the via hole 79 to connect the first pole of the fifth transistor T5.
  • the data line 93 may be connected to the fifth connection part 65 through the via hole 710 to connect the first electrode of the third transistor.
  • the fifth conductive layer may further include a connection portion 99 , the connection portion 99 may be connected to the third connection portion 63 through the via hole 716 , and the connection portion 99 may also be connected to the anode of the light-emitting unit through the via hole, so as to The second electrode of the sixth transistor T6 is connected to the anode of the light emitting unit.
  • the fifth conductive layer may further include a shielding layer connected to the first power line 91, and the orthographic projection of the shielding layer on the base substrate may cover the first conductive portion 31 on the backing Orthographic projection of the bottom substrate, the shielding layer can shield the influence of other signals on the gate voltage of the drive transistor.
  • the display panel further includes: a blocking layer 101, a first gate insulating layer 102, a second gate insulating layer 103, a third gate insulating layer 104, a buffer layer 105, a fourth gate insulating layer 106, a first dielectric layer layer 107 , second dielectric layer 108 , passivation layer 109 , first planarization layer 110 .
  • the flat layer 110 and the fifth conductive layer are stacked in sequence.
  • the third connection part 63 can be connected to the fourth active part 44 through the via hole 73
  • the active part 219 can be connected to the active part 219 through the via hole 74 .
  • connection part 99 in the fifth conductive layer can be connected to the third connection part 63 through the via hole 716, and the connection part 99 can also be connected to the anode layer located on the side of the fifth conductive layer away from the base substrate through the via hole, so as to connect the light emitting unit the anode.
  • a second flat layer may also be disposed between the fifth conductive layer and the anode layer.
  • the materials of the dielectric layer and passivation layer can be inorganic materials, such as at least one of silicon nitride, silicon oxide, silicon oxynitride or a combination thereof; or organic materials, such as transparent polyimide (CPI) ), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) and other materials.
  • inorganic materials such as at least one of silicon nitride, silicon oxide, silicon oxynitride or a combination thereof
  • organic materials such as transparent polyimide (CPI) ), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) and other materials.
  • the material of the conductive layer can also be at least one of copper, molybdenum, titanium, aluminum, nickel, silver, indium tin oxide (ITO), or a combination thereof, or an alloy material of the above materials, or a laminate, such as titanium/aluminum /Titanium tri-laminate.
  • ITO indium tin oxide
  • the barrier layer and the buffer layer can be made of inorganic materials, for example, including at least one of silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.
  • the material of the flat layer can be an organic material, such as transparent polyimide (CPI), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate Alcohol ester (PEN) and other materials.
  • CPI transparent polyimide
  • PI polyimide
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate Alcohol ester
  • the material of the gate insulating layer may be an inorganic material, for example, including at least one of silicon nitride, silicon oxide, and silicon oxynitride, or a combination thereof.
  • FIG. 16 only shows the relative positions of the various levels of the display panel, and does not represent the specific structure of the display panel.
  • the inorganic layer (including other insulating layers other than the flat layer) formed on the protruding structure will follow the shape to cover the protruding structure.
  • the first gate insulating layer 102 may conformally cover the first active portion 21
  • the third gate insulating layer 104 may conformally cover the fourth conductive portion 814 .
  • the via holes 71 , 72 , and 73 may penetrate through the fourth gate insulating layer 106 , the first dielectric layer 107 , and the second dielectric layer 108 ; the via holes 74 , 75 , and 76 may Through the first gate insulating layer 102 , the second gate insulating layer 103 , the third gate insulating layer 104 , the buffer layer 105 , the fourth gate insulating layer 106 , the first dielectric layer 107 , and the second dielectric layer 108 ;
  • the vias 77 may penetrate the third gate insulating layer 104, the buffer layer 105, the fourth gate insulating layer 106, the first dielectric layer 107, the second dielectric layer 108; the vias 79, 710, 716 may penetrate the passivation
  • the sintering layer 109 and the first planarization layer 110 are formed.
  • the passivation layer 109 may be omitted according to actual design requirements, that is to say, the passivation layer 109 may not be provided above the third conductive layer (including the pattern of the first connection portion 61 , etc.)
  • the first flat layer 110 may be provided above the third conductive layer (including the pattern of the first connection portion 61 , etc.).
  • This exemplary embodiment also provides another display panel, which may include a pixel driving circuit as shown in FIG. 4 , as shown in FIGS. 17-26 , and FIG. 17 is another exemplary embodiment of the display panel of the present disclosure.
  • the structural layout of the first active layer in FIG. 18 is the structural layout of the first conductive layer in another exemplary embodiment of the display panel of the present disclosure;
  • FIG. 19 is the fourth exemplary embodiment of the display panel of the present disclosure.
  • FIG. 20 is the structural layout of the second active layer in another exemplary embodiment of the display panel of the present disclosure;
  • FIG. 21 is the structural layout of the second conductive layer in another exemplary embodiment of the display panel of the present disclosure. Structural layout; FIG.
  • FIG. 22 is a laminated structure layout of the first active layer, the first conductive layer, the fourth conductive layer, the second active layer, and the second conductive layer in another exemplary embodiment of the display panel of the present disclosure
  • FIG. 23 is the structural layout of the third conductive layer in another exemplary embodiment of the display panel of the present disclosure
  • FIG. 24 is the first active layer, the first conductive layer, the fourth conductive layer in another exemplary embodiment of the display panel of the present disclosure The layout of the stacked structure of the conductive layer, the second active layer, the second conductive layer, and the third conductive layer
  • FIG. 25 is the structural layout of the fifth conductive layer in another exemplary embodiment of the display panel of the present disclosure
  • 26 is the layout A stacked structure of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, a third conductive layer, and a fifth conductive layer in another exemplary embodiment of a display panel is disclosed territory.
  • the display panel may include: a base substrate 1 , a first active layer, a first conductive layer, a second active layer, a second conductive layer, and a third conductive layer.
  • the first active layer is located on one side of the base substrate 1 , and the first active layer may include a first active part 21 , and the first active part 21 is used to form a trench of the driving transistor DT
  • the first conductive layer may be located on the side of the first active layer away from the base substrate 1, and the first conductive layer may include a first conductive portion 31, where the first conductive portion 31 is located.
  • the orthographic projection of the base substrate covers the orthographic projection of the first active portion 21 on the base substrate, and the first conductive portion 31 is used to form the gate of the driving transistor DT.
  • the second active layer may be located on the side of the first conductive layer away from the base substrate 1 , and the second active layer may include: a second active part 42 , a third active part 43 , a fourth The active part 44 , the fifth active part 45 , and the sixth active part 46 .
  • the second active part 42 is located on the side of the first conductive part 31 on the first direction Y1 in the orthographic projection of the base substrate; in the first direction Y1, all the
  • the third active portion 43 is located between the orthographic projection of the first conductive portion 31 on the base substrate and the orthographic projection of the second active portion 42 on the base substrate.
  • the orthographic projection of the third active part 43 on the base substrate is located on the side of the orthographic projection of the second active part 42 on the base substrate in the second direction X1, the first A direction Y1 intersects the second direction X1, for example, the first direction Y1 is perpendicular to the second direction X1.
  • the fourth active part 44 is connected between the second active part 42 and the third active part 43 , and the orthographic projection of the fourth active part 44 on the base substrate is located in the third active part
  • the active portion 43 is projected on the base substrate on one side of the third direction X2, the second direction X1 is opposite to the third direction X2, and on the first direction Y1, the fourth direction X1 is opposite to the third direction X2.
  • the orthographic projection of the active portion 44 on the base substrate is located between the orthographic projection of the first conductive portion 31 on the base substrate and the orthographic projection of the second active portion 42 on the base substrate.
  • the fifth active part 45 may be connected to the second active part 42 , and the orthographic projection of the fifth active part 45 on the base substrate may be located on the front side of the base substrate of the second active part 42 . One side projected on the first direction Y1.
  • the sixth active part 46 is connected to the third active part 43 , and the sixth active part 46 is located in the orthographic projection of the base substrate; the third active part 43 is in the orthographic projection of the base substrate; One side in the second direction X1.
  • the second conductive layer may be disposed on the side of the second active layer away from the base substrate, and the second conductive layer may include: a first gate line 51 and a first protrusion 52 , wherein the first gate Line 51 may be used to provide the reset signal terminal in FIG. 4 .
  • the first grid line 51 extends along the second direction X1 on the orthographic projection of the base substrate, and the first grid line 51 may include a second conductive portion 512, and the second conductive portion 512 is on the base substrate
  • the orthographic projection of the second active portion 42 on the base substrate may be coincident, and the second conductive portion 512 may be used to form the first gate of the second transistor T2; the first raised portion 52 can be connected to the first grid line 51, and in the first direction Y1, the orthographic projection of the first protrusion 52 on the base substrate can be located on the first grid line 51 on the substrate.
  • the first protruding portion 52 may include a third conductive portion 523, and the third conductive portion 523 is on the substrate
  • the orthographic projection of the base substrate may coincide with the orthographic projection of the third active portion 43 on the base substrate, and the third conductive portion 523 may be used to form the first gate of the first transistor T1 .
  • the first active layer may be formed of low temperature polysilicon material
  • the second active layer may be formed of indium gallium zinc oxide material.
  • the display panel may further include a fourth conductive layer disposed between the first conductive layer and the second active layer.
  • the fourth conductive layer may include: a second gate line 81 and a second raised portion 82, wherein the second gate line 81 may provide the reset signal terminal in FIG. 2, and the second gate line 81 may run along the periphery of the display panel.
  • the line area is connected to the first gate line 51 through a via hole.
  • the second gate line 81 may extend along the second direction X1 on the orthographic projection of the base substrate, the second gate line 81 may include a fourth conductive portion 814, and the second active portion 42 may be located on the substrate
  • the orthographic projection of the base substrate may be located on the orthographic projection of the fourth conductive portion 814 on the base substrate, and the fourth conductive portion 814 may be used to form the second gate of the second transistor T2; the second protrusion
  • the portion 82 may be connected to the second grid line 81. In the first direction Y1, the orthographic projection of the second raised portion 82 on the base substrate is located on the second grid line 81 on the substrate.
  • the second protruding portion 82 may include a fifth conductive portion 825 , and the third active portion 43 is located between the orthographic projection of the base substrate.
  • the orthographic projection of the base substrate may be located on the orthographic projection of the fifth conductive portion 825 on the base substrate, and the fifth conductive portion 825 may be used to form the second gate of the first transistor T1.
  • the fourth conductive layer may further include a sixth conductive portion 86 , and the orthographic projection of the sixth conductive portion 86 on the base substrate may cover the first conductive portion 31 on the base substrate
  • the orthographic projection of the sixth conductive portion 86 can be used to form an electrode of the capacitor C.
  • the sixth conductive portion 86 may be provided with an opening 861 .
  • a third conductive layer may be disposed on the side of the second conductive layer away from the base substrate, and the third conductive layer may include: a first connection part 61 and an initial signal line 62 .
  • the initial signal line 62 may be used to provide the initial signal terminal in FIG. 4 .
  • the first connection part 61 can be connected to the sixth active part 46 through the via hole 71 , and the first connection part 61 can be connected to the first conductive part 31 through the via hole 78 , so that the gate of the driving transistor DT and the first conductive part 31 can be realized.
  • the first pole of the transistor T1 is connected.
  • the orthographic projection of the via hole 78 on the base substrate and the opening 861 on the sixth conductive portion 86 are within the orthographic projection of the base substrate, that is, the orthographic projection of the via hole 78 on the base substrate There is a certain distance between the edge of the opening 861 and the edge of the orthographic projection of the base substrate, so that the conductive material filled in the via hole 78 can be insulated from the sixth conductive portion 86 .
  • the orthographic projection of the initial signal line 62 on the base substrate may extend along the second direction X1, and the orthographic projection of the initial signal line 62 on the base substrate may be located on the substrate of the first gate line 51 .
  • the bottom substrate is orthographically projected on one side of the first direction Y1, wherein the initial signal line 62 can provide the initial signal terminal in FIG. 4, and the initial signal line 62 can be connected to the fifth active part 45 through the via hole 72 , so that the first pole of the second transistor T2 can be connected to the initial signal terminal.
  • the orthographic projections of the fourth active portion 44 and the sixth active portion 46 on the base substrate are located on the substrate of the first conductive portion 31
  • the fourth active part 44 can communicate with the conductive structure located between the first conductive part 31 and the first gate line 51 and the driving transistor connection
  • the sixth active part 46 can be electrically connected to the first conductive part 31 through the conductive structure between the first gate line 51 and the first conductive part 31, so that the pixel driving circuit of the display panel has a high degree of integration .
  • both the first transistor T1 and the second transistor T2 adopt a double-gate structure, and the gate voltages can be supplied to the two gates of the first transistor T1 and the second transistor T2 at the same time, so that the first transistor T1 and the second transistor T2 can be increased.
  • the gates of the first transistor T1 and the second transistor T2 located in the fourth conductive layer can block their channel regions, so as to avoid the effect of light on the characteristics of the channel regions of the first transistor T1 and the second transistor T2. influence, so as to improve the electrical stability of the first transistor T1 and the second transistor T2.
  • the display panel may also not be provided with the second grid line 81 .
  • the first active layer may further include: a seventh active part 27 and an eighth active part 28 .
  • the seventh active part 27 can be used to form the channel region of the fifth transistor T5, and in the first direction Y1, the orthographic projection of the seventh active part 27 on the base substrate can be located in the first direction Y1.
  • a conductive part 31 is between the orthographic projection of the base substrate and the fourth active part 44 is between the orthographic projection of the base substrate; the eighth active part 28 can be used to form the groove of the sixth transistor T6 In the channel region, in the first direction Y1, the orthographic projection of the eighth active portion 28 on the base substrate is located at the orthographic projection of the first conductive portion 31 on the base substrate and the fourth active portion The portion 44 is between the orthographic projections of the base substrates.
  • the first conductive layer may further include a third grid line 33, the orthographic projection of the third grid line 33 on the base substrate may extend along the second direction X1, and the third grid line 33 may be used to provide FIG. 4 . in the enable signal terminal.
  • the third gate line 33 may include a gate part 331 and a gate part 332, the orthographic projection of the gate part 331 on the base substrate may cover the seventh active part 27, and the gate part 332 is in the
  • the orthographic projection of the base substrate may be the orthographic projection of the eighth active portion 28 on the base substrate.
  • the gate part 331 may be used to form the gate of the fifth transistor T5, and the gate part 332 may be used to form the gate of the sixth transistor.
  • the first active layer further includes an eleventh active part 211, the eleventh active part 211 is used to form the channel region of the third transistor T3, and the eleventh active part 211 is in the
  • the orthographic projection of the base substrate is located on the side of the first conductive portion 31 on the base substrate which is orthographically projected in the fourth direction Y2, and the fourth direction Y2 is opposite to the first direction Y1; the first conductive layer
  • a fifth grid line 35 may also be included, and the fifth grid line 35 extends along the second direction X1 on the orthographic projection of the base substrate.
  • the fifth gate line 35 may include a gate portion 351 , the orthographic projection of the base substrate covering the eleventh active portion 211 , and the gate portion 351 may be used to form the gate of the third transistor T3 .
  • the fourth conductive layer may further include a sixth grid line 87 , and the sixth grid line 87 may extend along the second direction X1 on the orthographic projection of the base substrate, The sixth grid line 87 may be located on the side of the fourth direction Y2 in the orthographic projection of the fifth grid line 35 on the base substrate.
  • the second active layer may further include: a twelfth active part 412 , a thirteenth active part 413 , and a fourteenth active part 414 , and the twelfth active part 412 may be used to form the fourth transistor T4
  • the twelfth active part 412 can be located on the orthographic projection of the base substrate on the sixth gate line 87;
  • the thirteenth active part 413 is used for The second channel region of the fourth transistor T4 is formed, and the orthographic projection of the thirteenth active portion 413 on the base substrate may be located on the orthographic projection of the sixth gate line 87 on the base substrate;
  • the four active parts 414 may be connected between the twelfth active part 412 and the thirteenth active part 413 , and the fourteenth active part 414 may be located in the orthographic projection of the base substrate.
  • the six grid lines 87 are on one side of the base substrate which is orthographically projected in the fourth direction Y2.
  • the second conductive layer may further include a seventh gate line 57, the seventh gate line 57 extends along the second direction X1 in the orthographic projection of the base substrate, and the seventh gate line 57 is on the base substrate.
  • the orthographic projection covers the orthographic projection of the twelfth active portion 412 and the thirteenth active portion 414 on the base substrate.
  • the fourth transistor T4 has two channel regions, so that the leakage current of the third node through the fourth transistor can be further reduced.
  • the seventh gate line 57 and the sixth gate line 87 can be connected by via holes in the peripheral wiring area of the display panel, and the seventh gate line 57 and the sixth gate line 87 can simultaneously provide gate driving signals to the fourth transistor, so that the The response speed of the fourth transistor T4 is increased.
  • the seventh gate line 57 and the sixth gate line 87 may be used to provide the second gate driving signal terminal in FIG. 4 .
  • the first connection part 61 is also connected to the side of the thirteenth active part 413 away from the fourteenth active part 414 through the via hole 75 to connect the fourth The second pole of the transistor T4 and the gate of the drive transistor DT.
  • the third conductive layer further includes: a connecting portion 63 , a connecting portion 64 , a connecting portion 65 , a connecting portion 66 , and a connecting portion 67 .
  • the connecting portion 63 can be connected to the side of the twelfth active portion 412 away from the fourteenth active portion 414 through the via hole 73 , and can be connected to the side of the seventh active portion 27 through the via hole 74 to connect the fourth active portion 412 .
  • the connection part 64 may be connected to the sixth conductive part 86 through the via hole 76 .
  • the connection part 65 may be connected to a side of the seventh active part 27 away from the connection part 62 through the via hole 77 to connect the first pole of the fifth transistor.
  • the connection part 66 can connect the active part 219 on the side of the eighth active part 28 through the via hole 715 , and at the same time connect the fourth active part through the via hole 79 to connect the second electrode of the sixth transistor and the first electrode of the first transistor. Diode.
  • the connection part 67 may connect one side of the eleventh active part 211 through the via hole 714 to connect the first pole of the third transistor T3.
  • the fourteenth active part 414 is a conductor, and parasitic capacitance is formed between the fourteenth active part 414 and the seventh gate line 57 and the sixth gate line 87 .
  • the voltage on the six gate line 87 changes, based on the bootstrap effect of the capacitance, the voltage of the fourteenth active part 414 will also change correspondingly, so that the fourteenth active part 414 is connected to the source of the fourth transistor T4.
  • the drain leaks, which eventually leads to abnormal driving of the pixel driving circuit.
  • the display panel may further include a fifth conductive layer, and the fifth conductive layer may be disposed on a side of the third conductive layer away from the base substrate.
  • the fifth conductive layer further includes a second power supply line 95, which may be used to provide the first power supply terminal in FIG. 4 .
  • the second power line 95 may extend along the first direction Y1 in the orthographic projection of the base substrate, and the second power line 95 may cover the fourteenth active part 414 in the orthographic projection of the base substrate. Orthographic projection of the base substrate.
  • the second power supply line 95 has a stable voltage, and the second power supply line 95 can suppress the potential variation of the fourteenth active part 414, thereby reducing the leakage current of the fourteenth active part 414 to the source and drain of the fourth transistor T4.
  • the second power line 95 may include a fifth edge 955
  • the fifth conductive layer may further include a third shielding portion 98
  • the third shielding portion 98 is connected to the The second power line 95
  • the third shielding portion 98 includes a sixth edge 986 connected to the fifth edge 955 of the second power line 95
  • the sixth edge 986 is orthographically projected on the base substrate to the first edge 986
  • the included angle of the orthographic projection of the fifth edge 955 on the base substrate is less than 180°. That is, the third shielding portion 98 is located on the side of the orthographic projection of the base substrate of the second power line 95 on the base substrate.
  • the third shielding portion 98 covers the second active portion and the third active portion by orthographic projection on the base substrate.
  • the third shielding portion 98 can avoid the influence of light on the characteristics of the channel regions of the first transistor T1 and the second transistor T2, so as to improve the electrical stability of the first transistor T1 and the second transistor T2.
  • the second power line 95 may also be connected to the connection part 64 through the via hole 710 .
  • the orthographic projection of the second power line 95 on the base substrate covers the orthographic projection of the first connection portion 61 on the base substrate. It should be understood that, in other exemplary embodiments, the orthographic projection of the second power line 95 on the base substrate may also not intersect or only partially intersect with the orthographic projection of the first connection portion 61 on the base substrate.
  • the fifth conductive layer may further include a data line 96 and a connection part 97 , and the data 96 is connected to the connection part 67 through the via hole 713 to connect to the first pole of the third transistor T3 .
  • the connection part 97 is connected to the connection part 66 through the via hole 712 to connect the second pole of the sixth transistor T6, and the connection part 97 can be connected to the anode of the light emitting unit through the via hole.
  • the display panel further includes: a blocking layer 101, a first gate insulating layer 102, a second gate insulating layer 103, a third gate insulating layer 104, a buffer layer 105, a fourth gate insulating layer 106, a first dielectric layer layer 107 , second dielectric layer 108 , passivation layer 109 , first planarization layer 110 .
  • the flat layer 110 and the fifth conductive layer are stacked in sequence.
  • the connection part 66 can be connected to the active part 219 through the via hole 715 and the fourth active part 44 can be connected through the via hole 79 to connect the second electrode of the sixth transistor and the first electrode of the second transistor.
  • connection part 97 in the fifth conductive layer can be connected to the connection part 66 through the via hole 712, and the connection part 97 can also be connected to the anode layer located on the side of the fifth conductive layer away from the base substrate through the via hole, so as to connect the anode of the light emitting unit .
  • a second flat layer may also be disposed between the fifth conductive layer and the anode layer.
  • the materials of the dielectric layer and passivation layer can be silicon nitride or transparent organic resin, etc., and the material of the flat layer can also be polyimide (PI), transparent polyimide (CPI), polyimide Ethylene phthalate (PET), polyethylene naphthalate (PEN) and other materials.
  • the material of the conductive layer can also be metal materials such as copper and molybdenum.
  • An inorganic material can be used for the barrier layer.
  • FIG. 27 only shows the relative positions of the various levels of the display panel, and does not represent the specific structure of the display panel.
  • the inorganic layer (including other insulating layers other than the flat layer) formed on the protruding structure will follow the shape to cover the protruding structure.
  • the first gate insulating layer 102 may conformally cover the first active portion 21
  • the third gate insulating layer 104 may conformally cover the fourth conductive portion 814 .
  • This exemplary embodiment also provides a method for driving a pixel driving circuit for driving the above-mentioned pixel driving circuit, and the driving method includes:
  • the first transistor and the second transistor are turned on, so as to input an initial signal to the third node and the first electrode of the light-emitting unit through the initial signal terminal;
  • the compensation circuit it is beneficial for the compensation circuit to turn on the first node and the third node, and at the same time use the data writing circuit to write a data signal to the first node;
  • a light-emitting control circuit is used to connect the first power supply terminal and one electrode of the driving transistor, and connect the first electrode of the light-emitting unit and the other electrode of the driving transistor.
  • the driving method has been analyzed in detail in the above content, and will not be repeated here.

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Abstract

一种像素驱动电路及其驱动方法、显示面板。像素驱动电路包括驱动晶体管(DT)、数据写入电路(1)、补偿电路(2)、发光控制电路(3)、存储电路(4)、第一晶体管(T1)、第二晶体管(T2)。驱动晶体管(DT)的第一极连接第一节点(N1)、第二极连接第二节点(N2)、栅极连接第三节点(N3)；数据写入电路(1)连接第一节点(N1)、数据信号端(Da)；补偿电路(2)连接第二节点(N2)和第三节点(N3)；发光控制电路(3)连接驱动晶体管(DT)、第一电源端(VDD)、发光单元(OLED)、使能信号端(EM)；存储电路(4)连接于第一电源端(VDD)和第三节点(N3)之间。第一晶体管(T1)、第二晶体管(T2)串联于第三节点(N3)和初始信号端(Vinit)之间；第一晶体管(T1)为N型氧化物晶体管，驱动晶体管(DT)为P型低温多晶硅晶体管。

Description

像素驱动电路及其驱动方法、显示面板 技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示面板。
背景技术
像素驱动电路用于驱动像素单元中的发光单元发光，相关技术中，像素驱动电路包括有驱动晶体管和电容。驱动晶体管用于根据其栅极电压输出向发光单元输出驱动电流；电容连接驱动晶体管的栅极，用于存储电荷，以在像素驱动电路发光阶段持续向驱动晶体管提供电压。
然而，驱动晶体管的栅极容易通过与其连接的晶体管漏电，从而影响像素驱动电路在发光阶段发光的稳定性。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种像素驱动电路，该像素驱动电路包括：驱动晶体管、数据写入电路、补偿电路、发光控制电路、存储电路、复位电路。驱动晶体管的第一极连接第一节点，第二极连接第二节点，栅极连接第三节点；数据写入电路连接所述第一节点、数据信号端，用于响应一控制信号将所述数据信号端的信号传输到所述第一节点；补偿电路连接所述第二节点和所述第三节点，用于响应一控制信号以连接所述第二节点和第三节点；发光控制电路连接所述驱动晶体管的第一极和第二极、第一电源端、发光单元的第一电极、使能信号端，用于响应所述使能信号端的信号连接所述第一电源端和所述驱动晶体管的一电极，以及连接所述发光单元的第一电极和所述驱动晶体管的另一电极；存储电路连接于所述第三节点之间；复位电路包括：第一晶体管、第二晶体管。第一晶体管的第一极连接所述第三节点，第二极连接所述发光单元的第一电极，栅极连接复位信号端；第二晶体管的第一极连接所述第一晶体管的第二极，第二极连接初始信号端，栅极连接所述复位信号端；其中，所述第一晶体管、第二晶体管为N型氧化物晶体管，驱动晶体管为P型低温多晶硅晶体管。
本公开一种示例性实施例中，所述发光控制电路用于响应所述使能信号端的信号连接所述第一电源端和所述驱动晶体管的第二极，以及连接所述发光单元的第一电极和所述驱动晶体管的第一极。
本公开一种示例性实施例中，数据写入电路包括第三晶体管，第三晶体管的第一极连接所述数据信号端，第二端连接所述第一节点，栅极连接第一栅极驱动信号端。
本公开一种示例性实施例中，所述补偿电路包括第四晶体管，第四晶体管的第一极连接第二节点，第二极连接所述第三节点，栅极连接第二栅极驱动信号端；其中，所述第三晶体管为P型低温多晶硅晶体管，第四晶体管为N型氧化物晶体管。
本公开一种示例性实施例中，所述补偿电路包括第四晶体管，第四晶体管的第一极连接第二节点，第二极连接所述第三节点，栅极连接第一栅极驱动信号端；其中，所述第三晶体管、第四晶体管均为P型低温多晶硅晶体管。
本公开一种示例性实施例中，所述补偿电路包括第四晶体管，第四晶体管的第一极连 接第二节点，第二极连接所述第三节点，栅极连接第一栅极驱动信号端；其中，所述第三晶体管、第四晶体管均为N型氧化物晶体管。
本公开一种示例性实施例中，所述发光控制电路包括第五晶体管、第六晶体管，第五晶体管的第一极连接所述第一电源端，第二极连接所述第二节点，栅极连接所述使能信号端；第六晶体管的第一极连接所述第一节点，第二极连接所述发光单元的第一电极，栅极连接所述使能信号端。
本公开一种示例性实施例中，所述第五晶体管和所述第六晶体管为P型低温多晶硅晶体管。
本公开一种示例性实施例中，存储电路包括电容，电容连接于所述第一电源端和所述第三节点之间。
根据本公开的一个方面，提供一种显示面板，包括上述的像素驱动电路，所述显示面板包括：衬底基板、第一有源层、第一导电层、第二有源层、第二导电层、第三导电层。第一有源层位于所述衬底基板的一侧，所述第一有源层包括第一有源部，所述第一有源部用于形成所述驱动晶体管的沟道区；第一导电层位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板的正投影覆盖所述第一有源部在所述衬底基板的正投影，所述第一导电部用于形成所述驱动晶体管的栅极。第二有源层，位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括：第二有源部、第三有源部、第四有源部、第五有源部、第六有源部。第二有源部在所述衬底基板正投影位于所述第一导电部在所述衬底基板正投影在第一方向上的一侧；在所述第一方向上，所述第三有源部在所述衬底基板正投影位于所述第一导电部在所述衬底基板正投影和所述第二有源部在所述衬底基板正投影之间，且所述第三有源部在所述衬底基板的正投影位于所述第二有源部在所述衬底基板的正投影在第二方向上的一侧，所述第一方向与所述第二方向相交；第四有源部连接于所述第二有源部和所述第三有源部之间，所述第四有源部在所述衬底基板的正投影位于所述第三有源部在所述衬底基板正投影在第三方向的一侧，所述第二方向与所述第三方向相反，且在所述第一方向上，所述第四有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影和所述第二有源部在所述衬底基板正投影之间；第五有源部连接所述第二有源部，所述第五有源部在所述衬底基板正投影位于所述第二有源部在所述衬底基板正投影在所述第一方向上的一侧；第六有源部连接所述第三有源部，所述第六有源部在所述衬底基板正投影位于所述第三有源部在所述衬底基板正投影在所述第二方向上的一侧。第二导电层设置于所述第二有源层背离所述衬底基板的一侧，所述第二导电层包括：第一栅线、第一凸起部。第一栅线在所述衬底基板正投影沿所述第二方向延伸，所述第一栅线包括第二导电部，所述第二导电部在所述衬底基板的正投影与所述第二有源部在所述衬底基板的正投影重合，所述第二导电部用于形成第二晶体管的第一栅极；第一凸起部连接所述第一栅线，在所述第一方向上，所述第一凸起部在所述衬底基板的正投影位于所述第一栅线在所述衬底基板正投影和所述第一导电部在所述衬底基板正投影之间，所述第一凸起部包括第三导电部，所述第三导电部在所述衬底基板的正投影与所述第三有源部在所述衬底基板正投影重合，用于形成所述第一晶体管的第一栅极。第三导电层设置于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：第一连接部、初始信号线。第一连接部通过过孔连接所述第六有源部和所述第一导电部；初始信号线在所述衬底基板的正投影沿所述第二方向延伸，所述初始信号线在所述衬底基板正投影位于所述第一栅线在所述衬底基板正投影在第一方向的一侧，所述初始信号线通过过孔与所述第五有源部连接。
本公开一种示例性实施例中，所述显示面板还包括第四导电层，第四导电层设置于所述第一导电层和所述第二有源层之间。所述第四导电层包括：第二栅线、第二凸起部，第二栅线在所述衬底基板正投影沿所述第二方向延伸，所述第二栅线包括第四导电部，所述 第二有源部在所述衬底基板的正投影位于所述第四导电部在所述衬底基板的正投影上，所述第四导电部用于形成第二晶体管的第二栅极；第二凸起部连接所述第二栅线，在所述第一方向上，所述第二凸起部在所述衬底基板的正投影位于所述第二栅线在所述衬底基板正投影和所述第一导电部在所述衬底基板正投影之间，所述第二凸起部包括第五导电部，所述第三有源部在所述衬底基板正投影位于所述第五导电部在所述衬底基板的正投影上，第五导电部用于形成所述第一晶体管的第二栅极。
本公开一种示例性实施例中，所述发光控制电路包括：第五晶体管、第六晶体管。第五晶体管的第一极连接所述第一电源端，第二极连接所述第二节点，栅极连接所述使能信号端；第六晶体管的第一极连接所述第一节点，第二极连接所述发光单元的第一电极，栅极连接所述使能信号端。所述第一有源层还包括：第七有源部、第八有源部。第七有源部用于形成所述第五晶体管的沟道区，在第一方向上，所述第七有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影和所述第四有源部在所述衬底基板正投影之间；第八有源部用于形成所述第六晶体管的沟道区，在第一方向上，所述第八有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影和所述第四有源部在所述衬底基板正投影之间。所述第一导电层还包括第三栅线，第三栅线在所述衬底基板的正投影沿所述第二方向延伸，所述第三栅线在所述衬底基板的正投影覆盖所述第七有源部、第八有源部在所述衬底基板的正投影，部分所述第三栅线用于形成所述第五晶体管的栅极，部分所述第三栅线用于形成所述第六晶体管的栅极。
本公开一种示例性实施例中，所述数据写入电路包括第三晶体管，第三晶体管的第一极连接所述数据信号端，第二端连接所述第一节点，栅极连接第一栅极驱动信号端。所述补偿电路包括第四晶体管，第四晶体管的第一极连接第二节点，第二极连接所述第三节点，栅极连接第二栅极驱动信号端。其中，所述第三晶体管、第四晶体管均为P型低温多晶硅晶体管。所述第一有源层还包括：第九有源部、第十有源部，第九有源部用于形成所述第三晶体管的沟道区，所述第九有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影在第四方向的一侧，所述第四方向与所述第一方向相反；第十有源部用于形成所述第四晶体管的沟道区，所述第十有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影在第四方向的一侧。所述第一导电层还包括第四栅线，第四栅线在所述衬底基板正投影沿所述第二方向延伸，所述第四栅线在所述衬底基板的正投影覆盖所述第九有源部、第十有源部在所述衬底基板的正投影，部分所述第四栅线用于形成所述第三晶体管的栅极，部分所述第四栅线用于形成所述第四晶体管的栅极。
本公开一种示例性实施例中，显示面板还包括第五导电层，第五导电层设置于所述第三导电层背离所述衬底基板的一侧。所述第五导电层包括：第一电源线、第一遮挡部、第一数据线、第二遮挡部。第一电源线在所述衬底基板正投影沿所述第一方向延伸，且包括第一边沿；第一遮挡部连接所述电源线，所述第一遮挡部包括与所述第一电源线第一边沿连接的第二边沿，第一边沿在所述衬底基板正投影与所述第二边沿在所述衬底基板正投影的夹角小于180°，所述第一遮挡部在所述衬底基板正投影覆盖所述第三有源部在所述衬底基板正投影；第一数据线所述衬底基板正投影沿所述第一方向延伸，且包括第三边沿；第二遮挡部连接所述数据线，所述第二遮挡部包括与所述第一数据线第三边沿连接的第四边沿，第三边沿在所述衬底基板正投影与所述第四边沿在所述衬底基板正投影的夹角小于108°，所述第二遮挡部在所述衬底基板正投影覆盖所述第二有源部在所述衬底基板正投影。
本公开一种示例性实施例中，所述数据写入电路包括第三晶体管，第三晶体管的第一极连接所述数据信号端，第二端连接所述第一节点，栅极连接第一栅极驱动信号端。所述补偿电路包括第四晶体管，第四晶体管的第一极连接第二节点，第二极连接所述第三节点，栅极连接第二栅极驱动信号端。其中，所述第三晶体管为P型低温多晶硅晶体管，第四晶 体管为N型氧化物晶体管。所述第一有源层还包括第十一有源部，第十一有源部用于形成所述第三晶体管的沟道区，所述第十一有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影在第四方向的一侧，所述第四方向与所述第一方向相反；第一导电层还包括第五栅线，第五栅线在所述衬底基板正投影沿所述第二方向延伸。所述第五栅线在所述衬底基板正投影覆盖所述第十一有源部，部分所述第五栅线用于形成所述第三晶体管的栅极。所述第四导电层还包括第六栅线，第六栅线在所述衬底基板正投影沿所述第二方向延伸，所述第六栅线在所述衬底基板正投影位于所述第五栅线在所述衬底基板正投影在所述第四方向的一侧。第二有源层还包括：第十二有源部、第十三有源部、第十四有源部，第十二有源部用于形成所述第四晶体管的第一沟道区，第十二有源部在所述衬底基板正投影位于所述第六栅线在所述衬底基板正投影上；第十三有源部用于形成所述第四晶体管的第二沟道区，第十三有源部在所述衬底基板正投影位于所述第六栅线在所述衬底基板正投影上；第十四有源部连接于所述第十二有源部和所述第十三有源部之间，第十四有源部在所述衬底基板正投影位于所述第六栅线在所述衬底基板正投影在第四方向上的一侧。所述第二导电层还包括：第七栅线，第七栅线在所述衬底基板正投影沿所述第二方向延伸，所述第七栅线在所述衬底基板正投影覆盖所述第十二有源部、第十三有源部在所述衬底基板正投影。
本公开一种示例性实施例中，第五导电层还包括第二电源线，第二电源线在所述衬底基板正投影沿所述第一方向延伸，第二电源线在所述衬底基板正投影覆盖所述第十四有源部在所述衬底基板的正投影。
本公开一种示例性实施例中，所述第二电源线包括第五边沿，第五导电层还包括第三遮挡部，第三遮挡部连接所述第二电源线，所述第三遮挡部包括与所述第二电源线的第五边沿连接的第六边沿，第六边沿在所述衬底基板正投影与所述第五边沿在所述衬底基板正投影的夹角小于180°，所述第三遮挡部在所述衬底基板正投影覆盖所述第二有源部和所述第三有源部。
根据本公开的一个方面，提供一种显示面板，其包括上述的像素驱动电路。
根据本公开的一个方面，提供一种像素驱动电路驱动方法，用于驱动上述的像素驱动电路，该驱动方法包括：
在重置阶段，导通所述第一晶体管和所述第二晶体管，以通过所述初始信号端向所述第三节点和所述发光单元第一电极输入初始信号；
在补偿阶段，利于补偿电路导通所述第一节点和第三节点，同时利用所述数据写入电路向所述第一节点写入数据信号；
在发光阶段，利用发光控制电路连接所述第一电源端和所述驱动晶体管的一电极，以及连接所述发光单元的第一电极和所述驱动晶体管的另一电极。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开像素驱动电路一种示例性实施例的结构示意图；
图2为本公开像素驱动电路另一种示例性实施例的结构示意图；
图3为图2中像素驱动电路一种驱动方法中各节点的时序图；
图4为本公开像素驱动电路另一种示例性实施例中的结构示意图；
图5为本公开像素驱动电路另一种示例性实施例中的结构示意图；
图6为本公开显示面板一种示例性实施例中第一有源层的结构版图；
图7为本公开显示面板一种示例性实施例中第一导电层的结构版图；
图8为本公开显示面板一种示例性实施例中第四导电层的结构版图；
图9为本公开显示面板一种示例性实施例中第二有源层的结构版图；
图10为本公开显示面板一种示例性实施例中第二导电层的结构版图；
图11为本公开显示面板一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层的层叠结构版图；
图12为本公开显示面板一种示例性实施例中第三导电层的结构版图；
图13为本公开显示面板一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层、第三导电层的层叠结构版图；
图14为本公开显示面板一种示例性实施例中第五导电层的结构版图；
图15为本公开显示面板一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层、第三导电层、第五导电层的层叠结构版图；
图16为沿图15中虚线AA的部分剖视图；
图17为本公开显示面板另一种示例性实施例中第一有源层的结构版图；
图18为本公开显示面板另一种示例性实施例中第一导电层的结构版图；
图19为本公开显示面板另一种示例性实施例中第四导电层的结构版图；
图20为本公开显示面板另一种示例性实施例中第二有源层的结构版图；
图21为本公开显示面板另一种示例性实施例中第二导电层的结构版图；
图22为本公开显示面板另一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层的层叠结构版图；
图23为本公开显示面板另一种示例性实施例中第三导电层的结构版图；
图24为本公开显示面板另一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层、第三导电层的层叠结构版图；
图25为本公开显示面板另一种示例性实施例中第五导电层的结构版图；
图26为本公开显示面板另一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层、第三导电层、第五导电层的层叠结构版图；
图27为沿图26中虚线AA的部分剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可 存在另外的要素/组成部分/等。
本示例性实施例提供一种像素驱动电路，如图1所示，为本公开像素驱动电路一种示例性实施例的结构示意图。该像素驱动电路可以包括：驱动晶体管DT、数据写入电路1、补偿电路2、发光控制电路3、存储电路4、复位电路5。驱动晶体管DT的第一极连接第一节点N1，第二极连接第二节点N2，栅极连接第三节点N3；数据写入电路1连接所述第一节点N1、数据信号端Da，用于响应一控制信号将所述数据信号端Da的信号传输到所述第一节点N1；补偿电路2连接所述第二节点N2和所述第三节点N3，用于响应一控制信号以连接所述第二节点N2和第三节点N3；发光控制电路连接所述驱动晶体管DT的第一极和第二极、第一电源端VDD、发光单元OLED的第一电极、使能信号端EM，所述发光控制电路3用于响应所述使能信号端EM的信号连接所述第一电源端VDD和所述驱动晶体管DT的第一极(即第一节点N1)，以及连接所述发光单元OLED的第一电极和所述驱动晶体管DT的第二极(即第二节点N2)；复位电路包括：第一晶体管T1、第二晶体管T2。第一晶体管T1的第一极连接所述第三节点N3，第二极连接所述发光单元OLED的第一电极，栅极连接复位信号端Re；第二晶体管T2的第一极连接所述第一晶体管T1的第二极，第二极连接初始信号端Vinit，栅极连接所述复位信号端Re；其中，所述第一晶体管T1、第二晶体管T2为N型氧化物晶体管，驱动晶体管DT为P型低温多晶硅晶体管。其中，发光单元OLED的第一电极可以为发光单元的阳极，发光单元OLED的阴极可以连接第二电源端VSS。
该像素驱动电路在重置阶段，可以导通所述第一晶体管T1和所述第二晶体管T2，以通过所述初始信号端Vinit向所述第三节点N3和所述发光单元OLED的第一电极输入初始信号；在补偿阶段，可以利于补偿电路2导通所述第一节点N1和第三节点N3，同时利用所述数据写入电路1向所述第一节点N1写入数据信号，从而向第三节点写入电压Vdata+Vth，并存储于存储电路中，其中，Vdata为数据信号的电压，Vth为驱动晶体管的阈值电压；在发光阶段，利用发光控制电路3连接所述第一电源端VDD和所述驱动晶体管DT的第一极(即第二节点N1)，以及连接所述发光单元OLED的第一电极和所述驱动晶体管DT的第二极(即第二节点N2)，驱动晶体管DT在第三节点N3的电荷作用下向发光单元OLED输出驱动电流。
本示例性实施例中，一方面，像素驱动电路中的驱动晶体管DT可以为P型低温多晶硅晶体管，低温多晶硅晶体管具有较高的载流子迁移率，从而该像素驱动电路有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板；另一方面，第一晶体管T1和第二晶体管T2为N型氧化物晶体管，氧化物晶体管具有较小的漏电流，从而可以降低像素驱动电路在发光阶段，第三节点N3通过第一晶体管T1和第二晶体管T2的漏电流。再一方面，第一晶体管T1和第二晶体管T2串联于第三节点N3和初始信号端Vinit之间，从而可以降低第三节点N3向初始信号端Vinit的漏电流；再一方面，在重置阶段，初始信号端Vinit写入第三节点N3的电压需要能够导通驱动晶体管DT，以便在补偿阶段向第三节点N3写入电压Vdata+Vth，因此，初始信号端Vinit的电压较小，一般为负值，在发光阶段，第二节点N2的电压小于第三节点N3的电压且大于初始信号端Vinit的电压，即发光单元OLED第一电极的电压小于第三节点N3的电压且大于初始信号端Vinit的电压，同时由于第一晶体管T1的第二极连接所述发光单元OLED的第一电极，因此，发光单元OLED的第一电极电压可以有效隔绝第三节点N3和初始信号端Vinit之间较大的跨压，从而降低第三节点向初始信号端Vinit的漏电流。
在图1所示的像素驱动电路中，第二节点N2的电压随第三节点N3的电压变化而变化，例如，在高灰阶状态下，第三节点N3的电压较低，第二节点的电压较高，在低灰阶状态下，第三节点N3的电压较高，第二节点的电压较低。因此，在不同显示灰阶下，第三节点N3与第二节点N2之间具有不同的电压差，从而在不同显示灰阶下，第三节点N3 向第二节点N具有不同的漏电流。尤其，在低灰阶状态下，第三节点N3向第二节点N2的漏电流较大，同时由于人眼对低亮度下亮度变化的敏感度较高，从而第三节点N3向第二节点N2的漏电流会严重影响显示面板的显示效果。
如图2所示，为本公开像素驱动电路另一种示例性实施例的结构示意图。其中，所述发光控制电路3可以用于响应所述使能信号端EM的信号连接所述第一电源端VDD和所述驱动晶体管DT的第二极(即第二节点N2)，以及连接所述发光单元OLED的第一电极和所述驱动晶体管DT的第一极(即第一节点N1)。该像素驱动电路的其他结构可以与图1所示的像素驱动电路相同。
本示例性实施例中，第一电源端VDD连接于第二节点N2，发光单元OLED的第一电极连接于第一节点。像素驱动电路在发光阶段，第二节点N2的电压稳定为第一电源端VDD的电压，第二节点N2的电压不会随驱动灰阶的变化而变化，因此，该像素驱动电路具有较为稳定的驱动效果。尤其在低灰阶驱动状态下，第三节点N3的电压较高，同时第二节点N2的电压也较高，第三节点N3向第二节点N2具有较小的漏电流。
本示例性实施例中，如图1、2所示，数据写入电路1可以包括第三晶体管T3，第三晶体管T3的第一极连接所述数据信号端Da，第二端连接所述第一节点N1，栅极连接第一栅极驱动信号端Gate1。
本示例性实施例中，如图1、2所示，所述补偿电路2可以包括第四晶体管T4，第四晶体管T4的第一极连接第二节点N2，第二极连接所述第三节点N3，栅极连接第一栅极驱动信号端Gate1；其中，所述第三晶体管T3、第四晶体管T4均可以为P型低温多晶硅晶体管。
本示例性实施例中，如图1所示，所述发光控制电路3可以包括第五晶体管T5、第六晶体管T6，第五晶体管T5的第一极连接所述第一电源端VDD，第二极连接所述第一节点N1，栅极连接所述使能信号端EM；第六晶体管T6的第一极连接所述第二节点N2，第二极连接所述发光单元OLED的第一电极，栅极连接所述使能信号端EM。其中，所述第五晶体管T5和所述第六晶体管T6可以为P型低温多晶硅晶体管。
本示例性实施例中，如图2所示，所述发光控制电路3可以包括第五晶体管T5、第六晶体管T6，第五晶体管T5的第一极连接所述第一电源端VDD，第二极连接所述第二节点N2，栅极连接所述使能信号端EM；第六晶体管T6的第一极连接所述第一节点N1，第二极连接所述发光单元OLED的第一电极，栅极连接所述使能信号端EM。其中，所述第五晶体管T5和所述第六晶体管T6可以为P型低温多晶硅晶体管。
本示例性实施例中，如图1、2所示，存储电路4可以包括电容C，电容C可以连接于所述第一电源端VDD和所述第三节点N3之间。应该理解的是，电容C还可以连接于所述第三节点N3和其他稳定信号端之间。
如图3所示，为图2中像素驱动电路一种驱动方法中各节点的时序图。其中，EM表示使能信号端的信号时序，Re表示复位信号端的信号时序，Gate1表示第一栅极驱动信号端的信号时序。该像素驱动电路的驱动方法包括三个阶段：重置阶段T1、补偿阶段T2、发光阶段T3，在重置阶段T1，复位信号端输出高电平信号，以导通第一晶体管T1、第二晶体管T2，初始信号端Vinit的信号传输到第三节点和发光单元OLED的第一电极，其中，驱动晶体管DT在初始信号端信号的作用下导通；在补偿阶段T2，第一栅极驱动信号端Gate1输出低电平信号，第三晶体管T3、第四晶体管T4导通，数据信号端向第三节点写入电压Vdata+Vth，其中，Vdata为数据信号端的电压，Vth为驱动晶体管的阈值电压；在发光阶段T3，使能信号端输出低电平信号，以导通第六晶体管T6、第五晶体管T5导通，驱动晶体管DT在电容C存储的电压Vdata+Vth作用下发光。驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为 驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
本示例性实施例中，如图4所示，为本公开像素驱动电路另一种示例性实施例中的结构示意图。该像素驱动电路与图2所示的像素驱动电路相比，区别在于所述第三晶体管T3可以为P型低温多晶硅晶体管，第四晶体管T4可以为N型氧化物晶体管。相应的，第四晶体管T4可以连接第二栅极驱动信号端Gate2，以在补偿阶段通过第二栅极驱动信号端Gate2导通第四晶体管T4。其中，氧化物晶体管具有较小的漏电流，从而可以降低像素驱动电路在发光阶段，第三节点N3通过第四晶体管向第二节点漏电。
本示例性实施例中，如图5所示，为本公开像素驱动电路另一种示例性实施例中的结构示意图。该像素驱动电路与图2所示的像素驱动电路相比，区别在于所述第三晶体管T3、第四晶体管T4均可以为N型氧化物晶体管。第三晶体管T3、第四晶体管T4在补偿阶段均可以在第一栅极驱动信号端Gate1的高电平作用下导通，以向第三节点写入补偿电压。该设置在降低第三节点N3通过第四晶体管向第二节点漏电的同时，可以仅通过第一栅极驱动信号端Gate1实现第三晶体管T3、第四晶体管T4的驱动，即应用该像素驱动电路的显示面板可以通过一个栅极驱动电路同时驱动第三晶体管T3、第四晶体管T4。
本示例性实施例中，图1、2、4、5中的第三晶体管T3、第四晶体管T4均可以为双栅结构，即第三晶体管T3、第四晶体管T4可以包括两个有源区，该设置可以降低第三晶体管T3、第四晶体管T4的漏电流。
本示例性实施例还提供一种显示面板，该显示面板可以包括如图2所示的像素驱动电路，如图6-15所示，图6为本公开显示面板一种示例性实施例中第一有源层的结构版图；图7为本公开显示面板一种示例性实施例中第一导电层的结构版图；图8为本公开显示面板一种示例性实施例中第四导电层的结构版图；图9为本公开显示面板一种示例性实施例中第二有源层的结构版图；图10为本公开显示面板一种示例性实施例中第二导电层的结构版图；图11为本公开显示面板一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层的层叠结构版图；图12为本公开显示面板一种示例性实施例中第三导电层的结构版图；图13为本公开显示面板一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层、第三导电层的层叠结构版图；图14为本公开显示面板一种示例性实施例中第五导电层的结构版图；图15为本公开显示面板一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层、第三导电层、第五导电层的层叠结构版图。
如图6-13所示，所述显示面板可以包括：衬底基板1、第一有源层、第一导电层、第二有源层、第二导电层、第三导电层。第一有源层位于所述衬底基板1的一侧，所述第一有源层包括第一有源部21，所述第一有源部21用于形成所述驱动晶体管DT的沟道区；第一导电层可以位于所述第一有源层背离所述衬底基板1的一侧，所述第一导电层可以包括第一导电部31，所述第一导电部31在所述衬底基板的正投影覆盖所述第一有源部21在所述衬底基板的正投影，所述第一导电部31用于形成所述驱动晶体管DT的栅极。第二有源层可以位于所述第一导电层背离所述衬底基板1的一侧，所述第二有源层可以包括：第二有源部42、第三有源部43、第四有源部44、第五有源部45、第六有源部46。第二有源部42在所述衬底基板正投影位于所述第一导电部31在所述衬底基板正投影在第一方向Y1上的一侧；第三有源部43在所述衬底基板正投影位于所述第一导电部31在所述衬底基板正投影在所述第一方向Y1上的一侧，且所述第三有源部43在所述衬底基板的正投影位于所述第二有源部42在所述衬底基板的正投影在第二方向X1上的一侧，所述第一方向Y1与所述第二方向X1相交，例如，所述第一方向Y1与所述第二方向X1垂直。第四有源部44连接于所述第二有源部42和所述第三有源部43之间，所述第四有源部44在所述 衬底基板的正投影位于所述第三有源部43在所述衬底基板正投影在第三方向X2的一侧，所述第二方向X1与所述第三方向X2相反，且在所述第一方向Y1上，所述第四有源部44在所述衬底基板的正投影位于所述第一导电部31在所述衬底基板正投影和所述第二有源部42在所述衬底基板正投影之间。第五有源部45可以连接所述第二有源部42，所述第五有源部45在所述衬底基板正投影可以位于所述第二有源部42在所述衬底基板正投影在所述第一方向Y1上的一侧。第六有源部46可以连接所述第三有源部43，所述第六有源部46在所述衬底基板正投影位于所述第三有源部43在所述衬底基板正投影在所述第二方向X1上的一侧。第二导电层可以设置于所述第二有源层背离所述衬底基板的一侧，所述第二导电层可以包括：第一栅线51、第一凸起部52，其中第一栅线51可以用于提供图2中的复位信号端。第一栅线51在所述衬底基板正投影沿所述第二方向X1延伸，所述第一栅线51可以包括第二导电部512，所述第二导电部512在所述衬底基板的正投影可以与所述第二有源部42在所述衬底基板的正投影重合，所述第二导电部512可以用于形成第二晶体管T2的第一栅极；第一凸起部52可以连接所述第一栅线51，在所述第一方向上，所述第一凸起部52在所述衬底基板的正投影可以位于所述第一栅线51在所述衬底基板正投影和所述第一导电部31在所述衬底基板正投影之间，所述第一凸起部52可以包括第三导电部523，所述第三导电部523在所述衬底基板的正投影可以与所述第三有源部43在所述衬底基板正投影重合，所述第三导电部523可以用于形成所述第一晶体管T1的第一栅极。其中，第一有源层可以由低温多晶硅材料形成，第二有源层可以由铟镓锌氧化物材料形成。
如图8、11所示，所述显示面板还可以包括第四导电层，第四导电层设置于所述第一导电层和所述第二有源层之间。所述第四导电层可以包括：第二栅线81、第二凸起部82，其中第二栅线81可以提供图2中的复位信号端，第二栅线81可以在显示面板的周边走线区与第一栅线51通过过孔连接。第二栅线81在所述衬底基板正投影沿所述第二方向X1延伸，所述第二栅线81可以包括第四导电部814，所述第二有源部42在所述衬底基板的正投影可以位于所述第四导电部814在所述衬底基板的正投影上，所述第四导电部814可以用于形成第二晶体管T2的第二栅极；第二凸起部82可以连接所述第二栅线81，在所述第一方向Y1上，所述第二凸起部82在所述衬底基板的正投影可以位于所述第二栅线81在所述衬底基板正投影和所述第一导电部31在所述衬底基板正投影之间，所述第二凸起部82可以包括第五导电部825，所述第三有源部43在所述衬底基板正投影可以位于所述第五导电部825在所述衬底基板的正投影上，第五导电部825可以用于形成所述第一晶体管T1的第二栅极。
如图8、11所示，第四导电层还可以包括第六导电部86，第六导电部86在所述衬底基板的正投影覆盖所述第一导电部在所述衬底基板的正投影，第六导电部86可以用于形成电容C的一电极。第六导电部86上可以设置有开口861。
如图7、12、13所示，第三导电层可以设置于所述第二导电层背离所述衬底基板的一侧，所述第三导电层可以包括：第一连接部61、初始信号线62。初始信号线62可以用于提供图2中的初始信号端。第一连接部61可以通过过孔71连接所述第六有源部46，第一连接部61还可以通过过孔78连接所述第一导电部31，从而可以实现驱动晶体管DT栅极和第一晶体管T1的第一极连接。其中，过孔78在所述衬底基板的正投影位于所述第六导电部86上的开口861在所述衬底基板的正投影内，即过孔78在所述衬底基板的正投影的边沿与开口861在所述衬底基板的正投影的边沿具有一定的距离，从而过孔78内填充的导电物可以与第六导电部86绝缘。
如图7、12、13所示，初始信号线62在所述衬底基板的正投影可以沿所述第二方向X1延伸，所述初始信号线62在所述衬底基板正投影可以位于所述第一栅线51在所述衬底基板正投影在第一方向Y1的一侧，其中，初始信号线62可以提供图2中的初始信号端，所述初始信号线62可以通过过孔72与所述第五有源部45连接，从而可以实现第二 晶体管T2第二极和初始信号端连接。
在本示例性实施例中，如图9、11所示，在第一方向Y1上，第四有源部44、第六有源部46在所述衬底基板的正投影可以位于所述第一导电部31在所述衬底基板正投影和第一栅线51在所述衬底基板正投影之间，第四有源部44可以通位于第一导电部31和第一栅线51之间的导电结构与驱动晶体管连接，第六有源部46可以通过位于第一栅线51和第一导电部31之间的导电结构与第一导电部31电连接，从而该显示面板的像素驱动电路具有较高的集成度。此外，第一晶体管T1和第二晶体管T2均采用双栅结构，第一栅线51、第二栅线81可以同时向第一晶体管T1和第二晶体管T2提供栅极电压，该设置可以增加第一晶体管T1和第二晶体管T2的响应速度，同时第一晶体管T1和第二晶体管T2位于第四导电层的栅极可以对其沟道区产生遮挡作用，从而避免光照对第一晶体管T1和第二晶体管T2沟道区特性的影响，以提高第一晶体管T1和第二晶体管T2的电学稳定性。应该理解的是，在其他示例性实施例中，该显示面板还可以不设置第二栅线81。
本示例性实施例中，如图6、7、11所示，所述第一有源层还可以包括：第七有源部27、第八有源部28。第七有源部27可以用于形成所述第五晶体管T5的沟道区，在第一方向上Y1，所述第七有源部27在所述衬底基板的正投影可以位于所述第一导电部31在所述衬底基板正投影和所述第四有源部44在所述衬底基板正投影之间。第八有源部28可以用于形成所述第六晶体管T6的沟道区，在第一方向上Y1，所述第八有源部28在所述衬底基板的正投影可以位于所述第一导电部31在所述衬底基板正投影和所述第四有源部44在所述衬底基板正投影之间。所述第一导电层还可以包括第三栅线33，第三栅线33在所述衬底基板的正投影可以沿所述第二方向X1延伸，第三栅线33可以用于提供图2中的使能信号端。所述第三栅线33可以包括第一栅极部331和第二栅极部332，第一栅极部331在所述衬底基板的正投影可以覆盖所述第七有源部27，第二栅极部332在所述衬底基板的正投影可以覆盖第八有源部28在所述衬底基板的正投影。第一栅极部331可以用于形成所述第五晶体管T5的栅极，第二栅极部332可以用于形成所述第六晶体管的栅极。
本示例性实施例中，如图6、7、11所示，所述第一有源层还可以包括：第九有源部29、第十有源部210，第九有源部29用于形成所述第三晶体管T3的沟道区，所述第九有源部29在所述衬底基板的正投影位于所述第一导电部31在所述衬底基板正投影在第四方向Y2的一侧，所述第四方向X2与所述第一方向相反Y1；第十有源部210用于形成所述第四晶体管T4的沟道区，所述第十有源部210在所述衬底基板的正投影位于所述第一导电部31在所述衬底基板正投影在第四方向Y2的一侧。所述第一导电层还可以包括第四栅线34，第四栅线34在所述衬底基板正投影可以沿所述第二方向X1延伸，第四栅线34可以包括第三栅极部343和第四栅极部344，第三栅极部343在所述衬底基板的正投影可以覆盖所述第九有源部29在所述衬底基板的正投影，第四栅极部344在所述衬底基板的正投影可以覆盖所述第十有源部210在所述衬底基板的正投影。第三栅极部343可以用于形成第三晶体管T3的栅极，第四栅极部344可以用于形成第四晶体管T4的栅极。
本示例性实施例中，如图12、13所示，所述第三导电层还包括包括：第三连接部63、第四连接部64、第五连接部65。其中，第三连接部63通过过孔73与第四有源部44连接，且通过过孔74与连接于第八有源部一侧的有源部219，以连接第一晶体管T1的第二极和第六晶体管T6的第二极。其中，第三连接部63还可以通过多个过孔与第四有源部44连接，例如，第三连接部63可以通过两个过孔与第四有源部44连接。第四连接部64可以通过过孔75连接第七有源部27的一侧，第四连接部64还通过过孔77连接第六导电部86，从而连接第五晶体管T5的第一极和电容C的一电极。第五连接部65通过过孔76连接第九有源部的一侧，以连接第三晶体管T3的第一极。应该理解的是，第一连接部61、第三连接部63、第四连接部64、第五连接部65作为转接层还可以位于其他导电层。例如，第一连接部61还可以位于第二导电层、第五导电层中的任意一层；第三连接部63还可以位 于第一导电层、第二导电层、第四导电层、第五导电层中的任意一层，第四连接部64还可以位于第二导电层；第五连接部65还可以位于第二导电层、第四导电层中的任意一层。
如图14、15所示，显示面板还可以包括第五导电层，第五导电层可以设置于所述第三导电层背离所述衬底基板的一侧。所述第五导电层可以包括：第一电源线91、第一遮挡部92、第一数据线93、第二遮挡部94。第一电源线91在所述衬底基板正投影可以沿所述第一方向Y1延伸，且包括第一边沿911；第一遮挡部92连接所述电源线91，所述第一遮挡部92包括与所述第一电源线91第一边沿911连接的第二边沿922，第一边沿911在所述衬底基板正投影与所述第二边沿922在所述衬底基板正投影的夹角小于180°。即第一遮挡部92在所述衬底基板正投影位于第一电源线91在所述衬底基板正投影的一侧，如图14、15所述，第一遮挡部92在所述衬底基板正投影可以位于第一电源线91在所述衬底基板正投影在第三方向X2上的一侧。本示例性实施例中，所述第一遮挡部92在所述衬底基板正投影可以覆盖所述第三有源部43在所述衬底基板正投影。第一遮挡部92可以避免光照对第一晶体管T1沟道区特性的影响，以提高第一晶体管T1的电学稳定性。第一数据线93在所述衬底基板正投影可以沿所述第一方向Y1延伸，且包括第三边沿933；第二遮挡部94可以连接所述数据线93，所述第二遮挡部94可以包括与所述第一数据线第三边933沿连接的第四边沿944，第三边沿933在所述衬底基板正投影与所述第四边沿944在所述衬底基板正投影的夹角小于108°。即第二遮挡部94在所述衬底基板正投影位于数据线93在所述衬底基板正投影的一侧，如图14、15所示，第二遮挡部94在所述衬底基板正投影可以位于数据线93在所述衬底基板正投影在第二方向X1上的一侧。所述第二遮挡部944在所述衬底基板正投影覆盖所述第二有源部42在所述衬底基板正投影。第二遮挡部944可以避免光照对第二晶体管T2沟道区特性的影响，以提高第二晶体管T2的电学稳定性。其中，第一电源线91可以提供图2中的第一电源端，数据线93可以提供图2中的数据信号端。第一电源线91可以通过过孔79连接第四连接部64以连接第五晶体管T5的第一极。数据线93可以通过过孔710连接第五连接部65以连接第三晶体管的第一极。如图14、15所示，第五导电层还可以包括连接部99，连接部99可以通过过孔716连接第三连接部63，连接部99还可以通过过孔以连接发光单元的阳极，以使第六晶体管T6的第二极连接发光单元的阳极。
应该理解的是，在其他示例性实施例中，第五导电层还可以包括与第一电源线91连接的屏蔽层，该屏蔽层在衬底基板的正投影可以覆盖第一导电部31在衬底基板的正投影，该屏蔽层能够屏蔽其他信号对驱动晶体管栅极电压的影响。
如图16所示，为沿图15中虚线AA的部分剖视图。该显示面板还包括：阻挡层101、第一栅极绝缘层102、第二栅极绝缘层103、第三栅极绝缘层104、缓冲层105、第四栅极绝缘层106、第一介电层107、第二介电层108、钝化层109、第一平坦层110。其中，衬底基板1、阻挡层101、第一有源层、第一栅极绝缘层102、第一导电层、第二栅极绝缘层103、第四导电层、第三栅极绝缘层104、缓冲层105、第二有源层、第四栅极绝缘层106、第二导电层、第一介电层107、第二介电层108、第三导电层、钝化层109、第一平坦层110、第五导电层依次层叠设置。其中，第三连接部63可以通过过孔73与第四有源部44连接，且通过过孔74连接有源部219。第五导电层中的连接部99可以通过过孔716连接第三连接部63，连接部99还可以通过过孔与位于第五导电层背离衬底基板一侧的阳极层连接，以连接发光单元的阳极。第五导电层和阳极层之间还可以设置第二平坦层。
其中，介电层、钝化层的材料可以为无机材料，例如包括氮化硅、氧化硅、氮氧化硅中的至少一种或者其组合；或有机材料，例如：透明聚酰亚胺(CPI)、聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)等材料。
导电层的材料还可以为铜、钼、钛、铝、镍、银、氧化铟锡(ITO)等至少一种或者其组合，或者上述材料的合金材料，或者叠层，例如可以是钛/铝/钛三叠层。
阻挡层、缓冲层可以采用无机材料，例如包括氮化硅、氧化硅、氮氧化硅中的至少一种或者其组合。
其中，平坦层的材料可以为有机材料，例如可以为透明聚酰亚胺(CPI)、聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)等材料。
其中，栅极绝缘层的材料可以为无机材料，例如包括氮化硅、氧化硅、氮氧化硅中的至少一种或者其组合。
应该理解的是，图16仅体现该显示面板各个层级相对位置，并不表示显示面板的具体结构。该显示面板的实际结构中，在凸起结构上形成的无机层(包括平坦层以外的其他绝缘层)会随形覆盖与凸起结构上。例如，第一栅极绝缘层102会随形覆盖于第一有源部21上，第三栅极绝缘层104会随形覆盖于第四导电部814上。
本示例性实施例中，结合图16，过孔71、72、73可以贯穿第四栅极绝缘层106、第一介电层107、第二介电层108；过孔74，75，76可以贯穿第一栅极绝缘层102、第二栅极绝缘层103、第三栅极绝缘层104、缓冲层105、第四栅极绝缘层106、第一介电层107、第二介电层108；过孔77可以贯穿第三栅极绝缘层104、缓冲层105、第四栅极绝缘层106、第一介电层107、第二介电层108；过孔79、710、716可以贯穿钝化层109和第一平坦层110。需要说明的是，本公开实施例中钝化层109可以根据实际设计需要省略，也即是说第三导电层(包括第一连接部61图形等)上方可以不设置钝化层109，直接设置第一平坦层110。
本示例性实施例还提供另一种显示面板，该显示面板可以包括如图4所示的像素驱动电路，如图17-26所示，图17为本公开显示面板另一种示例性实施例中第一有源层的结构版图；图18为本公开显示面板另一种示例性实施例中第一导电层的结构版图；图19为本公开显示面板另一种示例性实施例中第四导电层的结构版图；图20为本公开显示面板另一种示例性实施例中第二有源层的结构版图；图21为本公开显示面板另一种示例性实施例中第二导电层的结构版图；图22为本公开显示面板另一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层的层叠结构版图；图23为本公开显示面板另一种示例性实施例中第三导电层的结构版图；图24为本公开显示面板另一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层、第三导电层的层叠结构版图；图25为本公开显示面板另一种示例性实施例中第五导电层的结构版图；图26为本公开显示面板另一种示例性实施例中第一有源层、第一导电层、第四导电层、第二有源层、第二导电层、第三导电层、第五导电层的层叠结构版图。
如图17-24所示，所述显示面板可以包括：衬底基板1、第一有源层、第一导电层、第二有源层、第二导电层、第三导电层。第一有源层位于所述衬底基板1的一侧，所述第一有源层可以包括第一有源部21，所述第一有源部21用于形成所述驱动晶体管DT的沟道区；第一导电层可以位于所述第一有源层背离所述衬底基板1的一侧，所述第一导电层可以包括第一导电部31，所述第一导电部31在所述衬底基板的正投影覆盖所述第一有源部21在所述衬底基板的正投影，所述第一导电部31用于形成所述驱动晶体管DT的栅极。第二有源层可以位于所述第一导电层背离所述衬底基板1的一侧，所述第二有源层可以包括：第二有源部42、第三有源部43、第四有源部44、第五有源部45、第六有源部46。第二有源部42在所述衬底基板正投影位于所述第一导电部31在所述衬底基板正投影在第一方向Y1上的一侧；在所述第一方向Y1上，所述第三有源部43在所述衬底基板正投影位于所述第一导电部31在所述衬底基板正投影和所述第二有源部42在所述衬底基板正投影之间，且所述第三有源部43在所述衬底基板的正投影位于所述第二有源部42在所述衬底基板的正投影在第二方向X1上的一侧，所述第一方向Y1与所述第二方向X1相交，例如，所述第一方向Y1与所述第二方向X1垂直。第四有源部44连接于所述第二有源部42和所述第三有源部43之间，所述第四有源部44在所述衬底基板的正投影位于所述第三有 源部43在所述衬底基板正投影在第三方向X2的一侧，所述第二方向X1与所述第三方向X2相反，且在所述第一方向Y1上，所述第四有源部44在所述衬底基板的正投影位于所述第一导电部31在所述衬底基板正投影和所述第二有源部42在所述衬底基板正投影之间。第五有源部45可以连接所述第二有源部42，所述第五有源部45在所述衬底基板正投影可以位于所述第二有源部42在所述衬底基板正投影在所述第一方向Y1上的一侧。第六有源部46连接所述第三有源部43，所述第六有源部46在所述衬底基板正投影位于所述第三有源部43在所述衬底基板正投影在所述第二方向X1上的一侧。第二导电层可以设置于所述第二有源层背离所述衬底基板的一侧，所述第二导电层可以包括：第一栅线51、第一凸起部52，其中第一栅线51可以用于提供图4中的复位信号端。第一栅线51在所述衬底基板正投影沿所述第二方向X1延伸，所述第一栅线51可以包括第二导电部512，所述第二导电部512在所述衬底基板的正投影可以与所述第二有源部42在所述衬底基板的正投影重合，所述第二导电部512可以用于形成第二晶体管T2的第一栅极；第一凸起部52可以连接所述第一栅线51，在所述第一方向Y1上，所述第一凸起部52在所述衬底基板的正投影可以位于所述第一栅线51在所述衬底基板正投影和所述第一导电部31在所述衬底基板正投影之间，所述第一凸起部52可以包括第三导电部523，所述第三导电部523在所述衬底基板的正投影可以与所述第三有源部43在所述衬底基板正投影重合，所述第三导电部523可以用于形成所述第一晶体管T1的第一栅极。其中，第一有源层可以由低温多晶硅材料形成，第二有源层可以由铟镓锌氧化物材料形成。
如图19、22所示，所述显示面板还可以包括第四导电层，第四导电层设置于所述第一导电层和所述第二有源层之间。所述第四导电层可以包括：第二栅线81、第二凸起部82，其中第二栅线81可以提供图2中的复位信号端，第二栅线81可以在显示面板的周边走线区与第一栅线51通过过孔连接。第二栅线81在所述衬底基板正投影可以沿所述第二方向X1延伸，所述第二栅线81可以包括第四导电部814，所述第二有源部42在所述衬底基板的正投影可以位于所述第四导电部814在所述衬底基板的正投影上，所述第四导电部814可以用于形成第二晶体管T2的第二栅极；第二凸起部82可以连接所述第二栅线81，在所述第一方向Y1上，所述第二凸起部82在所述衬底基板的正投影位于所述第二栅线81在所述衬底基板正投影和所述第一导电部31在所述衬底基板正投影之间，所述第二凸起部82可以包括第五导电部825，所述第三有源部43在所述衬底基板正投影可以位于所述第五导电部825在所述衬底基板的正投影上，第五导电部825可以用于形成所述第一晶体管T1的第二栅极。
如图19、22所示，第四导电层还可以包括第六导电部86，第六导电部86在所述衬底基板的正投影可以覆盖所述第一导电部31在所述衬底基板的正投影，第六导电部86可以用于形成电容C的一电极。第六导电部86上可以设置有开口861。
如图23、24所示，第三导电层可以设置于所述第二导电层背离所述衬底基板的一侧，所述第三导电层可以包括：第一连接部61、初始信号线62。初始信号线62可以用于提供图4中的初始信号端。第一连接部61可以通过过孔71连接所述第六有源部46，第一连接部61可以通过过孔78连接所述第一导电部31，从而可以实现驱动晶体管DT栅极和第一晶体管T1的第一极连接。其中，过孔78在所述衬底基板的正投影位于所述第六导电部86上的开口861在所述衬底基板的正投影内，即过孔78在所述衬底基板的正投影的边沿与开口861在所述衬底基板的正投影的边沿具有一定的距离，从而过孔78内填充的导电物可以与第六导电部86绝缘。
初始信号线62在所述衬底基板的正投影可以沿所述第二方向X1延伸，所述初始信号线62在所述衬底基板正投影可以位于所述第一栅线51在所述衬底基板正投影在第一方向Y1的一侧，其中，初始信号线62可以提供图4中的初始信号端，所述初始信号线62可以通过过孔72与所述第五有源部45连接，从而可以实现第二晶体管T2第一极和初始信号 端连接。
在本示例性实施例中，在第一方向Y1上，第四有源部44、第六有源部46在所述衬底基板的正投影位于所述第一导电部31在所述衬底基板正投影和所述第一栅线51在所述衬底基板正投影之间，第四有源部44可以通位于第一导电部31和第一栅线51之间的导电结构与驱动晶体管连接，第六有源部46可以通过位于第一栅线51和第一导电部31之间的导电结构与第一导电部31电连接，从而该显示面板的像素驱动电路具有较高的集成度。此外，第一晶体管T1和第二晶体管T2均采用双栅结构，第一晶体管T1和第二晶体管T2的两个栅极可以同时提供栅极电压，从而可以增加第一晶体管T1和第二晶体管T2的响应速度，同时第一晶体管T1和第二晶体管T2位于第四导电层的栅极可以对其沟道区产生遮挡作用，从而避免光照对第一晶体管T1和第二晶体管T2沟道区特性的影响，以提高第一晶体管T1和第二晶体管T2的电学稳定性。应该理解的是，在其他示例性实施例中，该显示面板还可以不设置第二栅线81。
本示例性实施例中，如图17、18、22所示，所述第一有源层还可以包括：第七有源部27、第八有源部28。第七有源部27可以用于形成所述第五晶体管T5的沟道区，在第一方向上Y1，所述第七有源部27在所述衬底基板的正投影可以位于所述第一导电部31在所述衬底基板正投影和所述第四有源部44在所述衬底基板正投影之间；第八有源部28可以用于形成所述第六晶体管T6的沟道区，在第一方向上Y1，所述第八有源部28在所述衬底基板的正投影位于所述第一导电部31在所述衬底基板正投影和所述第四有源部44在所述衬底基板正投影之间。所述第一导电层还可以包括第三栅线33，第三栅线33在所述衬底基板的正投影可以沿所述第二方向X1延伸，第三栅线33可以用于提供图4中的使能信号端。所述第三栅线33可以包括栅极部331和栅极部332，栅极部331在所述衬底基板的正投影可以覆盖所述第七有源部27，栅极部332在所述衬底基板的正投影可以第八有源部28在所述衬底基板的正投影。栅极部331可以用于形成所述第五晶体管T5的栅极，栅极部332可以用于形成所述第六晶体管的栅极。
所述第一有源层还包括第十一有源部211，第十一有源211部用于形成所述第三晶体管T3的沟道区，所述第十一有源部211在所述衬底基板的正投影位于所述第一导电部31在所述衬底基板正投影在第四方向Y2的一侧，所述第四方向Y2与所述第一方向Y1相反；第一导电层还可以包括第五栅线35，第五栅线35在所述衬底基板正投影沿所述第二方向X1延伸。第五栅线35可以包括栅极部351，栅极部351所述衬底基板正投影覆盖所述第十一有源部211，栅极部351可以用于形成第三晶体管T3的栅极。
如图19、20、21、22所示，所述第四导电层还可以包括第六栅线87，第六栅线87在所述衬底基板正投影可以沿所述第二方向X1延伸，所述第六栅线87在所述衬底基板正投影可以位于所述第五栅线35在所述衬底基板正投影在所述第四方向Y2的一侧。第二有源层还可以包括：第十二有源部412、第十三有源部413、第十四有源部414，第十二有源部412可以用于形成所述第四晶体管T4的第一沟道区，第十二有源部412在所述衬底基板正投影可以位于所述第六栅线87在所述衬底基板正投影上；第十三有源部413用于形成所述第四晶体管T4的第二沟道区，第十三有源部413在所述衬底基板正投影可以位于所述第六栅线87在所述衬底基板正投影上；第十四有源部414可以连接于所述第十二有源部412和所述第十三有源部413之间，第十四有源部414在所述衬底基板正投影可以位于所述第六栅线87在所述衬底基板正投影在第四方向Y2上的一侧。所述第二导电层还可以包括第七栅线57，第七栅线57在所述衬底基板正投影沿所述第二方向X1延伸，所述第七栅线57在所述衬底基板正投影覆盖所述第十二有源部412、第十三有源部414在所述衬底基板正投影。第四晶体管T4具有两个沟道区，从而可以进一步降低第三节点通过第四晶体管的漏电流。第七栅线57和第六栅线87可以在显示面板端周边走线区通过过孔连接，第七栅线57和第六栅线87可以同时向第四晶体管提供栅极驱动信号，从而可以增加第四 晶体管T4的响应速度。第七栅线57和第六栅线87可以用于提供图4中的第二栅极驱动信号端。
本示例性实施例中，如图23、24所示，第一连接部61还通过过孔75与第十三有源部413远离第十四有源部414的一侧连接，以连接第四晶体管T4的第二极和驱动晶体管DT的栅极。所述第三导电层还包括包括：连接部63、连接部64、连接部65、连接部66、连接部67。连接部63可以通过过孔73与第十二有源部412远离第十四有源部414的一侧连接，同时通过过孔74与第七有源部27的一侧连接，以连接第四晶体管T4的第一极和第五晶体管T5的第二极。连接部64可以通过过孔76连接第六导电部86。连接部65可以通过过孔77连接第七有源部27远离连接部62的一侧，以连接第五晶体管的第一极。连接部66可以通过过孔715连接第八有源部28一侧的有源部219，同时通过过孔79连接第四有源部，以连接第六晶体管的第二极和第一晶体管的第二极。连接部67可以通过过孔714连接第十一有源部211的一侧，以连接第三晶体管T3的第一极。
本示例性实施例中，第十四有源部414为导体，第十四有源部414与第七栅线57和第六栅线87之间形成寄生电容，当第七栅线57和第六栅线87上的电压发生变化时，基于电容的自举效应，第十四有源部414的电压也会发生相应的变化，从而导致第十四有源部414向第四晶体管T4的源漏极漏电，最终导致像素驱动电路驱动异常。如图25、26所示，显示面板还可以包括第五导电层，第五导电层可以设置于所述第三导电层背离所述衬底基板的一侧。第五导电层还包括第二电源线95，第二电源线95可以用于提供图4中的第一电源端。第二电源线95在所述衬底基板正投影可以沿所述第一方向Y1延伸，第二电源线95在所述衬底基板正投影可以覆盖所述第十四有源部414在所述衬底基板的正投影。第二电源线95具有稳定的电压，第二电源线95可以抑制第十四有源部414的电位变化，从而降低第十四有源部414向第四晶体管T4源漏极漏电的漏电流。
本示例性实施例中，如图25、26所示，所述第二电源线95可以包括第五边沿955，第五导电层还可以包括第三遮挡部98，第三遮挡部98连接所述第二电源线95，所述第三遮挡部98包括与所述第二电源线95的第五边沿955连接的第六边沿986，第六边沿986在所述衬底基板正投影与所述第五边沿955在所述衬底基板正投影的夹角小于180°。即第三遮挡部98在所述衬底基板正投影位于第二电源线95在所述衬底基板正投影的一侧。所述第三遮挡部98在所述衬底基板正投影覆盖所述第二有源部和所述第三有源部。第三遮挡部98可以避免光照对第一晶体管T1、第二晶体管T2沟道区特性的影响，以提高第一晶体管T1、第二晶体管T2的电学稳定性。第二电源线95还可以通过过孔710连接连接部64。如图26所示，本示例性实施例中，第二电源线95在衬底基板的正投影覆盖第一连接部61在衬底基板的正投影。应该理解的是，在其他示例性实施例中，第二电源线95在衬底基板的正投影还可以与第一连接部61在衬底基板的正投影不相交或仅部分相交。
所述第五导电层还可以包括数据线96、连接部97，数据96通过过孔713连接连接部67，以连接第三晶体管T3的第一极。连接部97通过过孔712连接连接部66，以连接第六晶体管T6的第二极，连接部97可以通过过孔连接发光单元的阳极。
如图27所示，为沿图26中虚线AA的部分剖视图。该显示面板还包括：阻挡层101、第一栅极绝缘层102、第二栅极绝缘层103、第三栅极绝缘层104、缓冲层105、第四栅极绝缘层106、第一介电层107、第二介电层108、钝化层109、第一平坦层110。其中，衬底基板1、阻挡层101、第一有源层、第一栅极绝缘层102、第一导电层、第二栅极绝缘层103、第四导电层、第三栅极绝缘层104、缓冲层105、第二有源层、第四栅极绝缘层106、第二导电层、第一介电层107、第二介电层108、第三导电层、钝化层109、第一平坦层110、第五导电层依次层叠设置。其中，连接部66可以通过过孔715连接有源部219，同时通过过孔79连接第四有源部44，以连接第六晶体管的第二极和第二晶体管的第一极。第五导电层中的连接部97可以通过过孔712连接连接部66，连接部97还可以通过过孔与位于第 五导电层背离衬底基板一侧的阳极层连接，以连接发光单元的阳极。第五导电层和阳极层之间还可以设置第二平坦层。
其中，介电层、钝化层的材料可以为氮化硅或透明的有机树脂等材料，平坦层的材料还可以为聚酰亚胺(PI)、透明聚酰亚胺(CPI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)等材料。导电层的材料还可以为铜、钼等金属材料。阻挡层可以采用无机材料。
应该理解的是，图27仅体现该显示面板各个层级相对位置，并不表示显示面板的具体结构。该显示面板的实际结构中，在凸起结构上形成的无机层(包括平坦层以外的其他绝缘层)会随形覆盖与凸起结构上。例如，第一栅极绝缘层102会随形覆盖于第一有源部21上，第三栅极绝缘层104会随形覆盖于第四导电部814上。
本示例性实施例还提供一种像素驱动电路驱动方法，用于驱动上述的像素驱动电路，该驱动方法包括：
在重置阶段，导通所述第一晶体管和所述第二晶体管，以通过所述初始信号端向所述第三节点和所述发光单元第一电极输入初始信号；
在补偿阶段，利于补偿电路导通所述第一节点和第三节点，同时利用所述数据写入电路向所述第一节点写入数据信号；
在发光阶段，利用发光控制电路连接所述第一电源端和所述驱动晶体管的一电极，以及连接所述发光单元的第一电极和所述驱动晶体管的另一电极。
该驱动方法已在上述内容做出详细分析，此处不再赘述。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (19)

  1. 一种像素驱动电路，其中，包括：
    驱动晶体管，第一极连接第一节点，第二极连接第二节点，栅极连接第三节点；
    数据写入电路，连接所述第一节点、数据信号端，用于响应一控制信号将所述数据信号端的信号传输到所述第一节点；
    补偿电路，连接所述第二节点和所述第三节点，用于响应一控制信号以连接所述第二节点和第三节点；
    发光控制电路，连接所述驱动晶体管的第一极和第二极、第一电源端、发光单元的第一电极、使能信号端，用于响应所述使能信号端的信号连接所述第一电源端和所述驱动晶体管的一电极，以及连接所述发光单元的第一电极和所述驱动晶体管的另一电极；
    存储电路，连接于所述第三节点之间；
    复位电路，包括：
    第一晶体管，第一极连接所述第三节点，第二极连接所述发光单元的第一电极，栅极连接复位信号端；
    第二晶体管，第一极连接所述第一晶体管的第二极，第二极连接初始信号端，栅极连接所述复位信号端；
    其中，所述第一晶体管、第二晶体管为N型氧化物晶体管，驱动晶体管为P型低温多晶硅晶体管。
  2. 根据权利要求1所述的像素驱动电路，其中，所述发光控制电路用于响应所述使能信号端的信号连接所述第一电源端和所述驱动晶体管的第二极，以及连接所述发光单元的第一电极和所述驱动晶体管的第一极。
  3. 根据权利要求1所述的像素驱动电路，其中，数据写入电路包括：
    第三晶体管，第一极连接所述数据信号端，第二端连接所述第一节点，栅极连接第一栅极驱动信号端。
  4. 根据权利要求3所述的像素驱动电路，其中，所述补偿电路包括：
    第四晶体管，第一极连接第二节点，第二极连接所述第三节点，栅极连接第二栅极驱动信号端；
    其中，所述第三晶体管为P型低温多晶硅晶体管，第四晶体管为N型氧化物晶体管。
  5. 根据权利要求3所述的像素驱动电路，其中，所述补偿电路包括：
    第四晶体管，第一极连接第二节点，第二极连接所述第三节点，栅极连接第一栅极驱动信号端；
    其中，所述第三晶体管、第四晶体管均为P型低温多晶硅晶体管。
  6. 根据权利要求3所述的像素驱动电路，其中，所述补偿电路包括：
    第四晶体管，第一极连接第二节点，第二极连接所述第三节点，栅极连接第一栅极驱动信号端；
    其中，所述第三晶体管、第四晶体管均为N型氧化物晶体管。
  7. 根据权利要求2所述的像素驱动电路，其中，所述发光控制电路包括：
    第五晶体管，第一极连接所述第一电源端，第二极连接所述第二节点，栅极连接所述使能信号端；
    第六晶体管，第一极连接所述第一节点，第二极连接所述发光单元的第一电极，栅极连接所述使能信号端。
  8. 根据权利要求7所述的像素驱动电路，其中，所述第五晶体管和所述第六晶体管为P型低温多晶硅晶体管。
  9. 根据权利要求1所述的像素驱动电路，其中，存储电路包括：
    电容，连接于所述第一电源端和所述第三节点之间。
  10. 一种显示面板，其中，包括权利要求1所述的像素驱动电路，所述显示面板包括：
    衬底基板；
    第一有源层，位于所述衬底基板的一侧，所述第一有源层包括第一有源部，所述第一有源部用于形成所述驱动晶体管的沟道区；
    第一导电层，位于所述第一有源层背离所述衬底基板的一侧，所述第一导电层包括：
    第一导电部，所述第一导电部在所述衬底基板的正投影覆盖所述第一有源部在所述衬底基板的正投影，所述第一导电部用于形成所述驱动晶体管的栅极；
    第二有源层，位于所述第一导电层背离所述衬底基板的一侧，所述第二有源层包括：
    第二有源部，在所述衬底基板正投影位于所述第一导电部在所述衬底基板正投影在第一方向上的一侧；
    第三有源部，在所述第一方向上，所述第三有源部在所述衬底基板正投影位于所述第一导电部在所述衬底基板正投影和所述第二有源部在所述衬底基板正投影之间，且所述第三有源部在所述衬底基板的正投影位于所述第二有源部在所述衬底基板的正投影在第二方向上的一侧，所述第一方向与所述第二方向相交；
    第四有源部，连接于所述第二有源部和所述第三有源部之间，所述第四有源部在所述衬底基板的正投影位于所述第三有源部在所述衬底基板正投影在第三方向的一侧，所述第二方向与所述第三方向相反，且在所述第一方向上，所述第四有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影和所述第二有源部在所述衬底基板正投影之间；
    第五有源部，连接所述第二有源部，所述第五有源部在所述衬底基板正投影位于所述第二有源部在所述衬底基板正投影在所述第一方向上的一侧；
    第六有源部，连接所述第三有源部，所述第六有源部在所述衬底基板正投影位于所述第三有源部在所述衬底基板正投影在所述第二方向上的一侧；
    第二导电层，设置于所述第二有源层背离所述衬底基板的一侧，所述第二导电层包括：
    第一栅线，在所述衬底基板正投影沿所述第二方向延伸，所述第一栅线包括第二导电部，所述第二导电部在所述衬底基板的正投影与所述第二有源部在所述衬底基板的正投影重合，所述第二导电部用于形成第二晶体管的第一栅极；
    第一凸起部，连接所述第一栅线，在所述第一方向上，所述第一凸起部在所述衬底基板的正投影位于所述第一栅线在所述衬底基板正投影和所述第一导电部在所述衬底基板正投影之间，所述第一凸起部包括第三导电部，所述第三导电部在所述衬底基板的正投影与所述第三有源部在所述衬底基板正投影重合，用于形成所述第一晶体管的第一栅极；
    第三导电层，设置于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：
    第一连接部，通过过孔连接所述第六有源部和所述第一导电部；
    初始信号线，在所述衬底基板的正投影沿所述第二方向延伸，所述初始信号线在所述衬底基板正投影位于所述第一栅线在所述衬底基板正投影在第一方向的 一侧，所述初始信号线通过过孔与所述第五有源部连接。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板还包括：
    第四导电层，设置于所述第一导电层和所述第二有源层之间，所述第四导电层包括：
    第二栅线，在所述衬底基板正投影沿所述第二方向延伸，所述第二栅线包括第四导电部，所述第二有源部在所述衬底基板的正投影位于所述第四导电部在所述衬底基板的正投影上，所述第四导电部用于形成第二晶体管的第二栅极；
    第二凸起部，连接所述第二栅线，在所述第一方向上，所述第二凸起部在所述衬底基板的正投影位于所述第二栅线在所述衬底基板正投影和所述第一导电部在所述衬底基板正投影之间，所述第二凸起部包括第五导电部，所述第三有源部在所述衬底基板正投影位于所述第五导电部在所述衬底基板的正投影上，所述第五导电部用于形成所述第一晶体管的第二栅极。
  12. 根据权利要求10所述的显示面板，其中，所述发光控制电路包括：
    第五晶体管，第一极连接所述第一电源端，第二极连接所述第二节点，栅极连接所述使能信号端；
    第六晶体管，第一极连接所述第一节点，第二极连接所述发光单元的第一电极，栅极连接所述使能信号端；
    所述第一有源层还包括：
    第七有源部，用于形成所述第五晶体管的沟道区，在第一方向上，所述第七有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影和所述第四有源部在所述衬底基板正投影之间；
    第八有源部，用于形成所述第六晶体管的沟道区，在第一方向上，所述第八有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影和所述第四有源部在所述衬底基板正投影之间；
    所述第一导电层还包括：
    第三栅线，用于提供所述使能信号端，在所述衬底基板的正投影沿所述第二方向延伸，所述第三栅线在所述衬底基板的正投影覆盖所述第七有源部、第八有源部在所述衬底基板的正投影，部分所述第三栅线用于形成所述第五晶体管的栅极，部分所述第三栅线用于形成所述第六晶体管的栅极。
  13. 根据权利要求10所述的显示面板，其中，所述数据写入电路包括：
    第三晶体管，第一极连接所述数据信号端，第二端连接所述第一节点，栅极连接第一栅极驱动信号端；
    所述补偿电路包括：
    第四晶体管，第一极连接第二节点，第二极连接所述第三节点，栅极连接第一栅极驱动信号端；
    其中，所述第三晶体管、第四晶体管均为P型低温多晶硅晶体管；
    所述第一有源层还包括：
    第九有源部，用于形成所述第三晶体管的沟道区，所述第九有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影在第四方向的一侧，所述第四方向与所述第一方向相反；
    第十有源部，用于形成所述第四晶体管的沟道区，所述第十有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影在第四方向的一侧；
    所述第一导电层还包括：
    第四栅线，用于提供所述第一栅极驱动信号端，在所述衬底基板正投影沿所述第二方向延伸，所述第四栅线在所述衬底基板的正投影覆盖所述第九有源部、 第十有源部在所述衬底基板的正投影，部分所述第四栅线用于形成所述第三晶体管的栅极，部分所述第四栅线用于形成所述第四晶体管的栅极。
  14. 根据权利要求13所述的显示面板，其中，还包括：
    第五导电层，设置于所述第三导电层背离所述衬底基板的一侧，所述第五导电层包括：
    第一电源线，用于提供所述第一电源端，在所述衬底基板正投影沿所述第一方向延伸，包括第一边沿；
    第一遮挡部，连接所述电源线，所述第一遮挡部包括与所述第一电源线第一边沿连接的第二边沿，第一边沿在所述衬底基板正投影与所述第二边沿在所述衬底基板正投影的夹角小于180°，所述第一遮挡部在所述衬底基板正投影覆盖所述第三有源部在所述衬底基板正投影；
    第一数据线，用于提供所述数据信号端，在所述衬底基板正投影沿所述第一方向延伸，包括第三边沿；
    第二遮挡部，连接所述数据线，所述第二遮挡部包括与所述第一数据线第三边沿连接的第四边沿，第三边沿在所述衬底基板正投影与所述第四边沿在所述衬底基板正投影的夹角小于108°，所述第二遮挡部在所述衬底基板正投影覆盖所述第二有源部在所述衬底基板正投影。
  15. 根据权利要求11所述的显示面板，其中，所述数据写入电路包括：
    第三晶体管，第一极连接所述数据信号端，第二端连接所述第一节点，栅极连接第一栅极驱动信号端；
    所述补偿电路包括：
    第四晶体管，第一极连接第二节点，第二极连接所述第三节点，栅极连接第二栅极驱动信号端；
    其中，所述第三晶体管为P型低温多晶硅晶体管，第四晶体管为N型氧化物晶体管；
    所述第一有源层还包括：
    第十一有源部，用于形成所述第三晶体管的沟道区，所述第十一有源部在所述衬底基板的正投影位于所述第一导电部在所述衬底基板正投影在第四方向的一侧，所述第四方向与所述第一方向相反；
    第一导电层还包括：
    第五栅线，用于提供所述第一栅极驱动信号端，在所述衬底基板正投影沿所述第二方向延伸，所述第五栅线在所述衬底基板正投影覆盖所述第十一有源部，部分所述第五栅线用于形成所述第三晶体管的栅极；
    所述第四导电层还包括：
    第六栅线，用于提供所述第二栅极驱动信号端，在所述衬底基板正投影沿所述第二方向延伸，所述第六栅线在所述衬底基板正投影位于所述第五栅线在所述衬底基板正投影在所述第四方向的一侧；
    第二有源层还包括：
    第十二有源部，用于形成所述第四晶体管的第一沟道区，第十二有源部在所述衬底基板正投影位于所述第六栅线在所述衬底基板正投影上；
    第十三有源部，用于形成所述第四晶体管的第二沟道区，第十三有源部在所述衬底基板正投影位于所述第六栅线在所述衬底基板正投影上；
    第十四有源部，连接于所述第十二有源部和所述第十三有源部之间，第十四有源部在所述衬底基板正投影位于所述第六栅线在所述衬底基板正投影在第四方向上的一侧；
    所述第二导电层还包括：
    第七栅线，用于提供所述第二栅极驱动信号端，在所述衬底基板正投影沿所述第二方向延伸，所述第七栅线在所述衬底基板正投影覆盖所述第十二有源部、第十三有源部在所述衬底基板正投影。
  16. 根据权利要求15所述的显示面板，其中，第五导电层还包括：
    第二电源线，用于提供所述数据信号端，在所述衬底基板正投影沿所述第一方向延伸，第二电源线在所述衬底基板正投影覆盖所述第十四有源部在所述衬底基板的正投影。
  17. 根据权利要求16所述的显示面板，其中，所述第二电源线包括第五边沿，第五导电层还包括：
    第三遮挡部，连接所述第二电源线，所述第三遮挡部包括与所述第二电源线的第五边沿连接的第六边沿，第六边沿在所述衬底基板正投影与所述第五边沿在所述衬底基板正投影的夹角小于180°，所述第三遮挡部在所述衬底基板正投影覆盖所述第二有源部和所述第三有源部。
  18. 一种显示面板，其中，包括权利要求1-9任一项所述的像素驱动电路。
  19. 一种像素驱动电路驱动方法，用于驱动权利要求1-9任一项所述的像素驱动电路，其中，包括：
    在重置阶段，导通所述第一晶体管和所述第二晶体管，以通过所述初始信号端向所述第三节点和所述发光单元第一电极输入初始信号；
    在补偿阶段，利于补偿电路导通所述第一节点和第三节点，同时利用所述数据写入电路向所述第一节点写入数据信号；
    在发光阶段，利用发光控制电路连接所述第一电源端和所述驱动晶体管的一电极，以及连接所述发光单元的第一电极和所述驱动晶体管的另一电极。
PCT/CN2020/132866 2020-11-30 2020-11-30 像素驱动电路及其驱动方法、显示面板 WO2022110179A1 (zh)

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