WO2022087851A1 - 阵列基板、显示装置 - Google Patents

阵列基板、显示装置 Download PDF

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Publication number
WO2022087851A1
WO2022087851A1 PCT/CN2020/124163 CN2020124163W WO2022087851A1 WO 2022087851 A1 WO2022087851 A1 WO 2022087851A1 CN 2020124163 W CN2020124163 W CN 2020124163W WO 2022087851 A1 WO2022087851 A1 WO 2022087851A1
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WIPO (PCT)
Prior art keywords
base substrate
conductive
transistor
orthographic projection
gate
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Application number
PCT/CN2020/124163
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English (en)
French (fr)
Inventor
陈义鹏
石领
李文强
谢帅
于洋
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/437,936 priority Critical patent/US11950456B2/en
Priority to PCT/CN2020/124163 priority patent/WO2022087851A1/zh
Priority to DE112020007100.6T priority patent/DE112020007100T5/de
Priority to CN202080002492.1A priority patent/CN114930543A/zh
Publication of WO2022087851A1 publication Critical patent/WO2022087851A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a display device.
  • the pixel driving circuit can be formed by using a low temperature polycrystalline oxide (LTPO) technology.
  • LTPO low temperature polycrystalline oxide
  • a pixel driving circuit is formed in a combined manner.
  • the gate of the driving transistor will be pulled down, thereby affecting the charging of the gate of the driving transistor.
  • an array substrate includes a pixel driving circuit and a data line
  • the pixel driving circuit includes a driving transistor, and is connected between a first electrode of the driving transistor and the data line and a second transistor connected between the gate of the driving transistor and the second electrode
  • the driving transistor and the first transistor are P-type transistors
  • the second transistor is an N-type transistor
  • the array substrate further includes: a base substrate and a first conductive layer, the first conductive layer is disposed on one side of the base substrate, and the first conductive layer includes: a first conductive portion, a first gate line, a first conductive layer, and a first conductive layer.
  • the first conductive part is used to form the gate of the driving transistor; the first gate line is located on one side of the first conductive part, and part of the first gate line is used to form the gate of the first transistor a gate; a second gate line is located on a side of the first gate line away from the first conductive part, and a part of the second gate line is used to form a first gate of the second transistor.
  • the first gate line is located on one side of the first conductive portion in a first direction, and extends along a second direction, the first direction and the second direction intersecting, the first grid line includes: a first extension part and a second extension part, the orthographic projection of the first extension part on the base substrate and at least part of the first conductive part on the base substrate The orthographic projection of the second extending portion on the base substrate is opposite to the orthographic projection of the first conductive portion on the base substrate in the first direction wrong.
  • the distance between the orthographic projection of the first extension portion on the base substrate and the orthographic projection of the first conductive portion on the base substrate in the first direction is smaller than the distance between the orthographic projection of the second extension portion on the base substrate and the orthographic projection of the first conductive portion on the base substrate in the first direction.
  • the first extension portion includes a third edge facing a side of the first conductive portion, and the first conductive portion includes a fourth edge facing a side of the first extension portion
  • the size of the orthographic projection of the third edge on the base substrate in the second direction is equal to the size of the orthographic projection of the fourth edge on the base substrate in the second direction.
  • At least part of the second extension is used to form the gate of the first transistor.
  • the array substrate includes a plurality of the pixel driving circuits
  • the first conductive layer includes a plurality of the first conductive parts spaced along the second direction, a plurality of The first conductive parts are used to respectively form gates of driving transistors in different pixel driving circuits
  • the first gate lines include: a plurality of the first extension parts, a plurality of the second extension parts, the first gate line
  • An extension portion is provided in a one-to-one correspondence with the first conductive portion, the orthographic projection of the first extension portion on the base substrate and at least part of the corresponding first conductive portion on the base substrate The orthographic projections are opposite in the first direction; a plurality of the second extension parts are connected between adjacent first extension parts.
  • the array substrate further includes a second conductive layer, the second conductive layer is disposed on a side of the first conductive layer away from the base substrate, and the second conductive layer includes : a second conductive portion, a third conductive portion, and a first conductive wire, the orthographic projection of the second conductive portion on the base substrate at least partially coincides with the orthographic projection of the first conductive portion on the base substrate , and is electrically connected to the first conductive part through a via hole; the third conductive part is used to form the first electrode of the second transistor, and the orthographic projection of the first gate line on the base substrate is located in the The second conductive part is between the orthographic projection of the base substrate and the orthographic projection of the third conductive part; the first conductive wire is connected between the second conductive part and the third conductive part and extending along the first direction, the orthographic projection of the first conductive line on the base substrate intersects with the orthographic projection of the first grid line on the base substrate.
  • the second conductive layer further includes: a fourth conductive portion, the fourth conductive portion is connected to the first conductive wire, and the fourth conductive portion is located on the base plate.
  • the orthographic projection is at least partially coincident with the orthographic projection of the first grid line on the base substrate; wherein, the fourth conductive portion includes a first edge, and the first conductive line includes a second conductive portion and the fourth conductive portion.
  • One edge is connected to the second edge, and the included angle between the orthographic projection of the first edge on the base substrate and the orthographic projection of the second edge on the base substrate is less than 180 degrees.
  • an orthographic projection of the fourth conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first extension portion on the base substrate.
  • the orthographic projection of the second grid line on the base substrate is located at the orthographic projection of the first grid line on the base substrate, and the third conductive portion is located on the substrate between the orthographic projections of the base substrate;
  • the second grid line includes a third extension portion and a fourth extension portion that are alternately connected in sequence along the second direction, wherein the third extension portion is on the front side of the base substrate
  • the size projected on the first direction is smaller than the size of the fourth extension portion projected on the base substrate on the first direction; the first conductive line is on the normal side of the base substrate.
  • the projection intersects the orthographic projection of the third extension on the base substrate.
  • a portion of the fourth extension is used to form the first gate of the second transistor.
  • the second conductive layer further includes a power line extending along the first direction; the array substrate further includes a third conductive layer, and the third conductive layer is disposed on the A side of the second conductive layer facing away from the base substrate.
  • the power cord includes a fifth extension portion, and an orthographic projection of the fifth extension portion on the base substrate and at least part of the first conductive portion on the base substrate
  • the orthographic projections are opposite in the second direction
  • the third conductive layer includes the data lines, the data lines extend along the first direction, and some of the data lines are on the positive side of the base substrate
  • the projection is on the orthographic projection of the fifth extension on the base substrate.
  • the third conductive layer includes: a fifth conductive part, the fifth conductive part is connected to the power line through a via hole, and the fifth conductive part is located on the positive side of the base substrate.
  • the projection covers the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the fifth conductive portion on the base substrate covers the orthographic projection of the second conductive portion on the base substrate .
  • the array substrate further includes a third transistor, a first electrode of the third transistor is connected to a gate of the driving transistor, and both the second transistor and the third transistor are N-type metal oxide transistor, the first conductive layer further includes: a third gate line, the third gate line is located on a side of the second gate line away from the first conductive portion and along the second direction extending, and part of the third gate line is used to form the gate of the third transistor; the third conductive layer includes a fifth conductive part, the fifth conductive part is connected to the power line through a via hole, and the fifth conductive layer
  • the orthographic projection of the conductive portion on the base substrate covers the orthographic projection of the second transistor and the third transistor on the base substrate.
  • the array substrate includes: an R pixel driving circuit, a G pixel driving circuit, and a B pixel driving circuit; wherein, in the R pixel driving circuit, the width to length ratio of the channel region of the driving transistor, the G pixel The width to length ratio of the channel region of the driving transistor in the driving circuit and the width to length ratio of the channel region of the driving transistor in the G pixel driving circuit are not all the same.
  • the width to length ratio of the channel region of the driving transistor in the R pixel driving circuit is equal to the width to length ratio of the channel region of the driving transistor in the G pixel driving circuit, and the channel region of the driving transistor in the R pixel driving circuit The width to length ratio of the region is smaller than the width to length ratio of the channel region of the driving transistor in the R pixel driving circuit.
  • the width to length ratio of the channel region of the driving transistor in the R pixel driving circuit is 3.5/40
  • the width to length ratio of the channel region of the driving transistor in the B pixel driving circuit is 3.5/25.
  • the array substrate further includes: a fourth conductive layer, the fourth conductive layer is stacked between the first conductive layer and the second conductive layer, and the fourth conductive layer includes: The fourth grid line, the fourth grid line extends along the second direction, the orthographic projection of the first grid line on the base substrate is located at the orthographic projection of the first conductive portion on the base substrate and the The fourth gate line is between the orthographic projections of the base substrate, and a part of the fourth gate line is used to form the second gate of the second transistor.
  • the fourth gate line includes a sixth extension portion and a seventh extension portion that are alternately connected in sequence along the second direction;
  • the size of the sixth extension portion in the first direction in the orthographic projection of the base substrate is smaller than the size of the seventh extension portion in the first direction in the orthographic projection of the base substrate size; the orthographic projection of the first conductive line on the base substrate intersects with the orthographic projection of the sixth extension portion on the base substrate.
  • a part of the seventh extension is used to form the second gate of the second transistor.
  • the array substrate further includes: a first active layer and a second active layer, where the first active layer is stacked between the base substrate and the first conductive layer , part of the first active layer is used to form the channel region of the driving transistor; the second active layer is stacked between the fourth conductive layer and the first conductive layer, and part of the second active layer is The source layer is used to form channel regions of the second and third transistors.
  • the array substrate further includes: an enable signal line, an initial signal line, an anode layer, a first reset signal line, a second reset signal line, and a power supply line
  • the pixel driving circuit further includes: Including: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a capacitor.
  • the first pole of the third transistor is connected to the gate of the driving transistor, the second pole is connected to the initial signal line, and the gate is connected to the second reset signal line;
  • the first pole of the fourth transistor is connected to the power supply line, The second pole is connected to the first pole of the driving transistor, the gate is connected to the enable signal line;
  • the first pole of the fifth transistor is connected to the second pole of the driving transistor, the second pole is connected to the anode layer, and the gate
  • the pole is connected to the enable signal line;
  • the first pole of the sixth transistor is connected to the second pole of the fifth transistor, the second pole is connected to the initial signal line, the gate is connected to the first reset signal line;
  • the capacitor is connected between the gate of the driving transistor and the power line.
  • the driving transistor, the fourth transistor, the fifth transistor, and the sixth transistor are P-type low-temperature polysilicon transistors.
  • a display device wherein the display device includes the above-mentioned array substrate.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit of the present disclosure
  • FIG. 2 is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 1;
  • FIG. 3 is a structural layout of an exemplary embodiment of the disclosed array substrate
  • FIG. 4 is a structural layout of another exemplary embodiment of the disclosed array substrate
  • Fig. 5 is the structural layout of the second conductive layer in Fig. 4;
  • FIG. 6 is a structural layout of another exemplary embodiment of the disclosed array substrate.
  • FIG. 7 is a schematic structural diagram of the third conductive layer in FIG. 6;
  • Fig. 8 is the structural layout of the first active layer
  • 11 is a combined layout of the first active layer, the first conductive layer, and the second active layer;
  • 13 is a combined layout of the first active layer, the first conductive layer, the second active layer, and the fourth conductive layer;
  • 15 is a combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, and the second conductive layer;
  • 17 is a combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, the second conductive layer, and the third conductive layer;
  • Fig. 18 is the structural layout of the anode layer
  • 19 is a combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, the second conductive layer, the third conductive layer, and the anode layer;
  • Figure 20 is a partial cross-sectional view taken along dotted line A in Figure 17;
  • 21 is a structural layout of a second conductive layer in another exemplary embodiment of the disclosed array substrate.
  • 22 is a combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, the second conductive layer, and the third conductive layer in another exemplary embodiment of the disclosed array substrate;
  • FIG. 23 is a cross-sectional view taken along the dotted line A in FIG. 22 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the pixel driving circuit may include: a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a capacitor C.
  • the first pole of the first transistor T1 is connected to the data signal terminal Da
  • the second pole is connected to the first pole of the driving transistor DT
  • the gate is connected to the first gate driving signal terminal G1
  • the first pole of the fourth transistor T4 is connected to the first pole of the driving transistor DT.
  • a power supply terminal VDD the second pole is connected to the first pole of the driving transistor DT, and the gate is connected to the enable signal terminal EM;
  • the gate of the driving transistor DT is connected to the node N, and the second pole is connected to the first pole of the fifth transistor T5;
  • the first pole of the two transistors T2 is connected to the node N, the second pole is connected to the second pole of the driving transistor DT, and the gate is connected to the second gate driving signal terminal G2;
  • the second pole of the fifth transistor T5 is connected to the second pole of the sixth transistor T6
  • One pole, the gate is connected to the enable signal terminal EM, the second pole of the sixth transistor T6 is connected to the initial signal terminal Vinit, the gate is connected to the first reset signal terminal Re1;
  • the first pole of the third transistor T3 is connected to the node N, the second The pole is connected to the initial signal terminal Vinit, the gate is connected to the second reset signal terminal Re2, and the capacitor C is connected between the first power terminal VDD and the no
  • the pixel driving circuit can be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light, and the light-emitting unit OLED is connected between the second pole of the fifth transistor T5 and the second power terminal VSS.
  • the second transistor T2 and the third transistor T3 can be N-type metal oxide transistors, and the N-type metal oxide transistor has a smaller leakage current, so that the light-emitting stage can be avoided, and the node N passes through the second transistor T2 and the third transistor. T3 leakage.
  • the driving transistor DT, the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be low-temperature polysilicon transistors, and the low-temperature polysilicon transistors have higher carrier mobility, which is beneficial to the realization of Display panel with high resolution, high response speed, high pixel density and high aperture ratio.
  • FIG. 2 it is a timing diagram of each node in a driving method of the pixel driving circuit of FIG. 1 .
  • G1 represents the timing of the first gate driving signal terminal G1
  • G2 represents the timing of the second gate driving signal terminal G2
  • Re1 represents the timing of the first reset signal terminal Re1
  • Re2 represents the timing of the second reset signal terminal Re2
  • N represents the timing of the node N
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3.
  • the first reset signal terminal Re1 outputs a low-level signal
  • the second reset signal terminal Re2 outputs a high-level signal
  • the third transistor T3 and the sixth transistor T6 are turned on
  • the initial signal terminal Vinit goes to the node N
  • the first The second pole of the five transistors T5 is input with an initialization signal.
  • the first gate driving signal terminal G1 outputs a low-level signal
  • the second gate driving signal terminal G2 outputs a high-level signal
  • the first transistor T1 and the second transistor T2 are turned on
  • the data signal terminal Da The driving signal is output to write the voltage Vdata+Vth to the node N, where Vdata is the voltage of the driving signal and Vth is the threshold voltage of the driving transistor DT.
  • Light-emitting stage t3 the enable signal terminal EM outputs a low-level signal, the fourth transistor T4 and the fifth transistor T5 are turned on, and the driving transistor DT emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the drive transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth)2, where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the drive transistor channel, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the output current I ( ⁇ WCox/2L)(Vdata+Vth ⁇ Vdd ⁇ Vth)2 of the drive transistor in the pixel drive circuit of the present disclosure.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • the second gate driving signal terminal G2 is lowered from a high level to a low level , that is, the gate of the second transistor T2 is lowered from a high level to a low level, the voltage of the first electrode of the second transistor T2 will decrease under the capacitive coupling effect, and the voltage of the node N connected to the first electrode of the second transistor T2 will also decrease. will be reduced accordingly.
  • the voltage drop of the node N ie, the gate of the driving transistor
  • the source driving circuit In order to ensure that the driving transistor outputs a normally required driving current, the source driving circuit needs to provide a data signal with a higher voltage value to the data signal terminal through the data line.
  • the voltage provided by the source driving circuit to the data line needs to be greater than 6.3V, but the maximum voltage provided by the existing source driving circuit to the data line is 6V, which cannot meet the Display requirements normally.
  • this exemplary embodiment provides an array substrate, the array substrate may include a pixel driving circuit and a data line, the circuit structure of the pixel driving circuit may be as shown in FIG. 1 , and the driving method may be as shown in FIG. 2 . .
  • FIG. 3 it is a structural layout of an exemplary embodiment of an array substrate of the present disclosure.
  • the array substrate may further include: a base substrate 0 and a first conductive layer, the first conductive layer is disposed on one side of the base substrate 0, and the first conductive layer may include: a first conductive portion 13, a first conductive layer A gate line 11, a second gate line 12, and a first conductive portion 13 may be used to form the gate of the driving transistor; the first gate line 11 may be located on one side of the first conductive portion 13, and part of the first conductive portion 13 A gate line 11 may be used to form the gate of the first transistor; a second gate line 12 may be located on the side of the first gate line 11 away from the first conductive part 13 , and part of the second gate line 12 may be used to form the first gate of the second transistor.
  • the array substrate disposes the second gate line 12 on the side of the first gate line 11 away from the first conductive portion 13 .
  • this arrangement increases the distance between the second gate line 12 and the first conductive part 13, reduces the lateral capacitance between the second gate line 12 and the first conductive part 13, and thus reduces the gate of the second transistor
  • the first gate line 11 and the first conductive part 13 can form a side capacitance, as shown in FIG. 2 , the first transistor ends at the compensation stage t2 Then, jump from low level to high level, so that the gate of the first transistor can pull up the gate of the driving transistor.
  • the array substrate provided by this exemplary embodiment reduces the size of the first gate line 11 and the The distance between the first conductive parts 13 increases the lateral capacitance between the first gate line 11 and the first conductive part 13, so that the pull-up effect of the gate of the first transistor on the gate of the driving transistor can be enhanced; , the first gate line 11 is located between the first conductive part 13 and the second gate line 12, the first gate line 11 can play a certain shielding effect on the second gate line 12, thereby further reducing the second transistor gate to drive Pull-down effect of transistor gate.
  • the pull-up effect of the first gate line 11 on the first conductive portion 13 is stronger than the pull-down effect of the second gate line 12 on the first conductive portion 13 , so that the array substrate can offset the above to a certain extent.
  • the pixel driving circuit in the array substrate may also be other circuit structures.
  • the N-type first transistor connected between the gate electrode and the second electrode of the driving transistor will pull down the gate of the driving transistor after the compensation stage is completed.
  • other exemplary embodiments can also use the above-mentioned array substrate structure design, by reducing the pull-down effect of the gate of the N-type first transistor on the gate of the driving transistor, and increasing the pull-down effect of the gate of the P-type second transistor on the gate of the driving transistor. pull-down action to weaken the pull-down action of the second transistor on the gate of the driving transistor.
  • the first gate line 11 may be located on one side of the first conductive portion 13 in the first direction Y1 and extend along the second direction X, and the first gate line 11 may be located on one side of the first conductive portion 13 in the first direction Y1
  • a direction Y1 and the second direction X intersect, for example, the first direction Y1 and the second direction X may be perpendicular.
  • the first gate line 11 may include: a first extension part 111 and a second extension part 112 .
  • the orthographic projection of the first extension part 111 on the base substrate is located where at least part of the first conductive part 13 is located.
  • the orthographic projection of the base substrate is opposite to the first direction Y1; the orthographic projection of the second extension portion 112 on the base substrate and the orthographic projection of the first conductive portion 13 on the base substrate Misalignment in the first direction Y1.
  • Both the first direction and the second direction may be directions parallel to the plane of the base substrate.
  • “the orthographic projection of the first extension portion 111 on the base substrate is opposite to the orthographic projection of at least part of the first conductive portion 13 on the base substrate in the first direction Y1” can be understood Therefore, the area covered by the orthographic projection of the first extending portion 111 on the base substrate moves infinitely along the first direction Y1 and the third direction Y2 and at least part of the first conductive portion 13 is on the base substrate.
  • the orthographic projection of the second extension portion 112 on the base substrate is staggered from the orthographic projection of the first conductive portion 13 on the base substrate in the first direction Y1 can be understood to mean that the The area covered by the infinite movement of the second extension portion 112 on the base substrate along the first direction Y1 and the third direction Y2 is the same as the orthographic projection of the first conductive portion 13 on the base substrate along the first direction Y1 and the third direction Y2.
  • the areas covered by infinite movement in the direction Y1 and the third direction Y2 do not intersect, and similarly, the first direction Y1 and the third direction Y2 are opposite.
  • the distance between the orthographic projection of the first extension portion 111 on the base substrate and the orthographic projection of the first conductive portion 13 on the base substrate on the first direction Y1 S1 may be smaller than the distance S2 between the orthographic projection of the second extension portion 112 on the base substrate and the orthographic projection of the first conductive portion 13 on the base substrate in the first direction Y1. As shown in FIG.
  • the distance S1 between the orthographic projection of the first extension portion 111 on the base substrate and the orthographic projection of the first conductive portion 13 on the base substrate on the first direction Y1 It may refer to the edge of the first extension portion 111 facing the first conductive portion 13 in the orthographic projection of the base substrate and the side of the first conductive portion 13 facing the first extension portion 111 in the orthographic projection of the base substrate The distance of the edge in the first direction Y1.
  • the distance S2 between the orthographic projection of the second extension portion 112 on the base substrate and the orthographic projection of the first conductive portion 13 on the base substrate in the first direction Y1 may refer to the second extension
  • the edge of the portion 112 on the side of the orthographic projection of the base substrate facing the first conductive portion 13 and the edge of the first conductive portion 13 on the side of the orthographic projection of the base substrate facing the second extension portion 112 are on the first line.
  • the first extension portion 111 includes a third edge 1111 facing the side of the first conductive portion 13
  • the first conductive portion 13 includes a third edge 1111 facing the first conductive portion 13
  • the fourth edge 131 on one side of the extension part 111, the dimension of the third edge 1111 on the base substrate in the second direction X may be equal to the size of the fourth edge 131 on the base substrate
  • both the third edge 1111 and the fourth edge 131 may extend along the second direction. It should be understood that, in other exemplary embodiments, the third edge 1111 and the fourth edge 131 may also extend in a direction intersecting the second direction.
  • the third edge 1111 is on the base substrate
  • the size of the orthographic projection on the second direction X can be understood as the size of the right-angled side extending along the second direction in the right-angled triangle with the third edge 1111 in the orthographic projection of the base substrate as the hypotenuse
  • the dimension of the orthographic projection of the fourth edge 131 on the base substrate in the second direction X can be understood as a right-angled triangle whose orthographic projection of the fourth edge 131 on the base substrate is a hypotenuse The dimension of the right-angled side extending in the second direction.
  • the size of the orthographic projection of the third edge 1111 on the base substrate in the second direction X may also be smaller than the size of the orthographic projection of the fourth edge 131 on the base substrate on
  • At least part of the second extension portion 112 may be used to form the gate of the first transistor. Since the distance between the orthographic projection of the second extension portion 112 on the base substrate in the first direction and the orthographic projection of the first conductive portion 13 on the base substrate is relatively large, this design can fully reserve the setting of the first transistor. Space.
  • the array substrate may include a plurality of the pixel driving circuits
  • the first conductive layer may include a plurality of the first conductive layers spaced along the second direction X.
  • a conductive part 13, a plurality of the first conductive parts 13 are used to respectively form gates of the driving transistors in different pixel driving circuits;
  • the first gate line 11 may include: a plurality of the first extension parts 111, a plurality of Each of the second extension portions 112 , the first extension portions 111 may be provided in a one-to-one correspondence with the first conductive portions 13 , the orthographic projection of the first extension portion 111 on the base substrate and the corresponding At least a part of the first conductive portion 13 is opposite in the first direction Y1 in the orthographic projection of the base substrate.
  • FIG. 4 is a structural layout of another exemplary embodiment of the disclosed array substrate
  • FIG. 5 is a structural layout of the second conductive layer in FIG. 4
  • the array substrate may further include a second conductive layer
  • the second conductive layer may be disposed on the side of the first conductive layer away from the base substrate
  • the second conductive layer may include: a second conductive portion 22 , the third conductive portion 23 , the first conductive wire 21 , the orthographic projection of the second conductive portion 22 on the base substrate 0 and the orthographic projection of the first conductive portion 13 on the base substrate 0 are at least partially overlap, and are electrically connected to the first conductive part 13 through the via hole 25;
  • the third conductive part 23 can be used to form the first electrode of the second transistor, and the first gate line 11 is on the base substrate
  • the orthographic projection of 0 is located between the orthographic projection of the second conductive portion 22 on the base substrate and the orthographic projection of the third conductive portion 23 on
  • the orthographic projection of the line 21 on the base substrate intersects the orthographic projection of the first grid line 11 on the base substrate.
  • part of the first conductive line 21 may be connected to part of the first grid line 11 .
  • a gate line 11 forms a parallel plate capacitor structure. Using the coupling effect of the parallel plate capacitance structure, the first gate line 11 can pull up the first conductive line 21 after the compensation phase of the pixel driving circuit is completed, because the first conductive line 21 is electrically connected to the first conductive portion 13 , that is, this arrangement can further enhance the pull-up effect of the first gate line 11 on the first conductive portion 13 .
  • the second conductive layer may further include: a fourth conductive part 24 , the fourth conductive part 24 may be connected to the first conductive wire 21 , and the fourth conductive part 24
  • the orthographic projection of the conductive portion 24 on the base substrate may at least partially coincide with the orthographic projection of the first grid line 11 on the base substrate, wherein the fourth conductive portion 24 may include a first edge 241 ,
  • the first conductive line 21 may include a second edge 211 connected to the first edge 241 of the fourth conductive portion, and the orthographic projection of the first edge 241 on the base substrate is in line with the second edge 211 .
  • the included angle ⁇ of the orthographic projection of the base substrate is less than 180 degrees.
  • Part of the fourth conductive portion 24 may form a parallel plate capacitor structure with part of the first gate line 11 .
  • the first gate line 11 can pull up the fourth conductive portion 24 after the compensation stage of the pixel driving circuit is completed.
  • a conductive portion 13 is electrically connected, that is, this arrangement can further enhance the pull-up effect of the first gate line 11 on the first conductive portion 13 .
  • the fourth conductive portion 24 can be connected to the side of the first conductive wire 21 in the opposite direction of the second direction X.
  • the fourth conductive portion 24 is on the positive side of the base substrate.
  • the projection may at least partially coincide with the orthographic projection of the first extension portion 111 on the base substrate.
  • C in Table 1 represents the parasitic capacitance formed by the first gate line and the first conductive part (ie node N)
  • Vn represents the voltage of node N in FIG. 1 in the light-emitting stage
  • Table 1 shows the data When the signal voltage is 6V, Vn corresponding to different parasitic capacitances C. It can be seen from Table 1 that the larger the parasitic capacitance C is, the stronger the pull-up effect of the first gate line on the first conductive portion is.
  • the orthographic projection of the second grid line 12 on the base substrate may be located on the front side of the first grid line 11 on the base substrate.
  • the projection and the orthographic projection of the third conductive portion 23 are between the orthographic projections of the base substrate;
  • the second grid line 12 may include a third extension portion 123 and a fourth extension portion 124 alternately connected in sequence along the second direction X , wherein the size of the orthographic projection of the third extension portion 123 on the base substrate in the first direction Y1 may be smaller than the size of the orthographic projection of the fourth extension portion 124 on the base substrate in the first direction Y1 The dimension in the first direction Y1.
  • the orthographic projection of the first conductive line 21 on the base substrate may intersect with the orthographic projection of the third extension portion 123 on the base substrate.
  • Part of the third extension part 123 and part of the first conductive line 21 may form a parallel plate capacitor structure. Based on the coupling effect of the parallel plate capacitor structure, the third extension portion 123 can pull down the first conductive line 21 after the compensation stage of the pixel driving circuit is completed. Since the first conductive line 21 is electrically connected to the first conductive portion 13, the The three extending portions 123 can pull down the first conductive portion 13 .
  • the size of the orthographic projection of the third extension portion 123 on the base substrate in the first direction Y1 is smaller than the size of the orthographic projection of the fourth extension portion 124 on the base substrate
  • the size in the first direction Y1 that is, the present exemplary embodiment reduces the size of the third extension part 123 in the first direction Y1, thereby reducing the third extension part 123 and the first conductive wire 21
  • the electrode area of the formed parallel plate capacitor structure according to the capacitance calculation of the parallel plate capacitor, it can be known that the capacitance of the parallel plate capacitor structure is proportional to its electrode area, that is, the setting reduces the amount of space between the third extension 123 and the first conductive line 21.
  • the capacitance of the parallel plate capacitor structure is formed, thereby reducing the pull-down effect of the third extension portion 123 on the first conductive portion 13 .
  • a part of the fourth extension portion 124 may be used to form the first gate of the second transistor.
  • the channel region of the second transistor may extend along the first direction Y1, so that the channel region of the second transistor may have a larger length to reduce leakage current of the second transistor.
  • the second conductive layer may further include a power supply line 26 , the power supply line 26 may extend along the first direction Y1 , and the power supply line 26 may be used to provide the power supply line 26 in FIG. 1 . in the first power supply terminal.
  • the orthographic projection of the power line 26 on the base substrate may intersect with the orthographic projection of the third extension 123 on the base substrate, and this arrangement can reduce the overlapping area of the power line 26 and the second grid line, thereby reducing the power supply The capacitive coupling effect caused by the line 26 to the second gate line 12 when the voltage fluctuates.
  • FIG. 6 is a structural layout of another exemplary embodiment of an array substrate of the disclosure
  • FIG. 7 is a schematic structural diagram of the third conductive layer in FIG. 6
  • the array substrate may further include a third conductive layer, and the third conductive layer may be disposed on a side of the second conductive layer away from the base substrate.
  • the power cord 26 may include a fifth extension portion 265 , and the orthographic projection of the fifth extension portion 265 on the base substrate and at least part of the first conductive portion 13 on the The orthographic projections of the base substrate are opposite in the second direction X.
  • the orthographic projection of the fifth extension portion 265 on the base substrate is opposite to the orthographic projection of at least part of the first conductive portion 13 on the base substrate in the second direction X” can be understood as, The area covered by the infinite movement of the fifth extension portion 265 on the orthographic projection of the base substrate along the second direction and the opposite direction of the second direction is at least partially covered by the first conductive portion 13 on the positive side of the base substrate. The area covered by the infinite movement of the projection in the second direction and the opposite direction of the second direction is completely coincident.
  • the third conductive layer may include the data lines 31, the data lines 31 extend along the first direction Y1, and a part of the orthographic projections of the data lines 31 on the base substrate may be located in the fifth
  • the extension 265 is on the orthographic projection of the base substrate.
  • the fifth extension portion 265 is disposed between the data line 31 and the first conductive portion 13, and the fifth extension portion 265 receives a stable voltage, so that the fifth extension portion 265 can serve as a shielding layer to reduce the data line 31 and the first conductive portion 13.
  • the coupling capacitance between the parts 13 is reduced, thereby reducing the coupling effect of the data line 31 to the first conductive part 13 .
  • the third conductive layer may further include: a fifth conductive part 35 , and the fifth conductive part 35 may be connected to the power line 26 through a via hole 34 , and the The orthographic projection of the fifth conductive portion 35 on the base substrate 0 may cover the orthographic projection of the first conductive portion 13 on the base substrate 0 , and the fifth conductive portion 35 is on the base substrate 0 .
  • the orthographic projection of can cover the orthographic projection of the second conductive portion 22 on the base substrate 0 .
  • the fifth conductive portion 35 covers the first conductive portion 13 and the second conductive portion 22 , and the fifth conductive portion 35 receives a stable voltage, so that the fifth conductive portion 35 can act as a shielding layer to reduce the impact of other signals on the first conductive portion 13 and the capacitive coupling effect of the second conductive part 22 , for example, the fifth conductive part 35 can reduce the capacitive coupling effect of the data line and the anode layer to the first conductive part 13 and the second conductive part 22 .
  • the first conductive layer may further include: a third gate line 14 , and the third gate line 14 is located on the second gate line 12 and away from the first conductive portion 13 . and extending along the second direction X, part of the third gate line 14 may be used to form the gate of the third transistor T3.
  • the array substrate may further include a second active layer, the second active layer may be disposed between the first conductive layer and the second conductive layer, and the second active layer may include a fourth active portion 6.
  • the fourth active part 6 may extend along the first direction Y1.
  • the orthographic projection of the fourth active portion 6 on the base substrate 0 intersects with the orthographic projection of the fourth extension portion 124 on the base substrate 0 to form the second transistor T2 in FIG. 1 ; the fourth active portion 6 is on the base substrate 0 .
  • the orthographic projection of 0 intersects with the orthographic projection of the third gate line 14 on the base substrate 0 to form the third transistor T3 in FIG. 1 .
  • the orthographic projection of the fifth conductive portion 35 on the base substrate 0 may also cover the orthographic projection of the second transistor T2 and the third transistor T3 on the base substrate 0 .
  • the material of the fourth active part 6 can be metal oxide, such as indium gallium zinc oxide.
  • the second transistor and the third transistor can be metal oxide transistors, and the characteristics of metal oxide transistors will change under the illumination environment.
  • the second transistor T2 and the third transistor T3 By covering the second transistor T2 and the third transistor T3 with the fifth conductive portion 35, the influence of light on the output characteristics of the second transistor T2 and the third transistor T3 can be avoided.
  • Figure 8 is the structural layout of the first active layer;
  • Figure 9 is the structural layout of the first conductive layer;
  • Figure 10 is the structural layout of the second active layer;
  • Figure 11 is the first active layer Layer, the first conductive layer, the combined layout of the second active layer;
  • Figure 12 is the structural layout of the fourth conductive layer;
  • Figure 13 is the first active layer, the first conductive layer, the second active layer, the fourth conductive layer The combined layout of the layers;
  • Figure 14 is the structural layout of the second conductive layer;
  • Figure 15 is the combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, and the second conductive layer;
  • Figure 16 is the structural layout of the third conductive layer;
  • FIG. 17 is the combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, the second conductive layer, and the third conductive layer;
  • FIG. 18 19 shows the combined layout of the first active layer, the first conductive layer, the second active layer, the fourth conductive layer, the second conductive layer, the third conductive layer and the anode layer.
  • the first active layer may include a first active part 51 and a second active part 52 extending along the first direction Y1, and the first active part 51 and the second active part 52 Distributed at intervals along the second direction X.
  • a third active portion 53 is connected between the first active portion 51 and the second active portion 52 .
  • the first active portion 51 may include a first sub-active portion 511 and a second sub-active portion 514, and the second active portion 52 may include a third sub-active portion 525 and a fourth sub-active portion 526.
  • the third active part 53 can be used to form the channel region of the driving transistor; the first sub-active part 511 can be used to form the channel region of the first transistor; the second sub-active part 514 can be used to form the first sub-active part 514
  • the first active layer may be a polysilicon material, and correspondingly, the driving transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be P-type low temperature polysilicon transistors.
  • the first conductive layer includes the above-mentioned first conductive portion 13 , the first grid line 11 , the second grid line 12 , and the third grid line 14 .
  • the first conductive layer may also include a fifth The gate line 15 and the sixth gate line 16 .
  • the fifth grid line 15 is located on the side of the first conductive portion 1 away from the first grid line
  • the sixth grid line 16 is located on the side of the fifth grid line 15 away from the first conductive portion 13 .
  • the first gate line 11 , the second gate line 12 , the third gate line 14 , the fifth gate line 15 , and the sixth gate line 16 may all extend along the second direction X.
  • the first gate line 11 may be used to provide the first gate driving signal terminal in FIG. 1 , the first gate line 11 may include a first gate part 113 ; the second gate line 12 may be used to provide the first gate line 11 in FIG. 1 .
  • Two gate driving signal terminals the second gate line 12 may include a second gate portion 125; the third gate line 14 may be used as a second reset signal line for providing the second reset signal terminal in FIG. 1, the third gate line 14 may include a third gate part 143; the fifth gate line 15 may be used as an enable signal line for providing the enable signal terminal in FIG.
  • the fifth gate line 15 may include a fourth gate part 154 and a fifth gate The pole part 155 ; the sixth gate line 16 can be used as the first reset signal line to provide the first reset signal terminal in FIG. 1 , and the sixth gate line 16 includes the sixth gate part 166 .
  • the first gate portion 113 may be used to form the gate of the first transistor T1
  • the second gate portion 125 may be used to form the first gate of the second transistor
  • the third gate portion 143 may be used to form the first gate of the second transistor T1.
  • the first gate of the three transistors; the fourth gate part 154 can be used to form the gate of the fourth transistor; the fifth gate part 155 can be used to form the gate of the fifth transistor; the sixth gate part 166 can be used to form the gate of the fifth transistor to form the gate of the sixth transistor.
  • the first gate part 113 may be located on the above-mentioned second extension part 112
  • the second gate part 125 may be located on the above-mentioned fourth extension part 124 .
  • the second active layer may include a plurality of the above-mentioned fourth active parts 6 extending along the first direction Y1 , and the plurality of fourth active parts 6 may be distributed along the second direction X at intervals.
  • the fourth active parts 6 are provided in a one-to-one correspondence with the plurality of pixel driving circuits.
  • the fourth active part 6 may include a fifth sub-active part 62 and a sixth sub-active part 63 , wherein the fifth sub-active part 62 may form a channel region of the second transistor, the first The six sub-active parts 63 may form the channel region of the third transistor.
  • the second gate line 12 can shield the fifth sub-active part 62 from light, so as to prevent the output characteristics of the second transistor from being affected by light; the third grid line 14 can shield the sixth sub-active part 63 from light, In order to prevent the output characteristic of the third transistor from being affected by light.
  • the fourth conductive layer may include a fourth gate line 74 , a fifth gate line 75 , a sixth gate line 76 , and a sixth conductive portion 72 .
  • the fourth gate line 74 , the fifth gate line 75 , and the sixth gate line 76 can all extend along the second direction X.
  • the fourth gate line 74 may be connected to the second gate line 12 in the routing area around the display area through vias; the fifth gate line 75 may be connected to the third gate line 14 through vias in the routing area around the display area.
  • the orthographic projection of the first grid line 11 on the base substrate is located at the orthographic projection of the first conductive portion 13 on the base substrate and the fourth grid line 74 is located on the base substrate.
  • the fourth gate line 74 includes a sixth extension portion 746 and a seventh extension portion 747 which are alternately connected in sequence along the second direction X; wherein, the sixth extension portion 746 is on the orthographic projection of the base substrate on the base plate.
  • the size in the first direction Y1 is smaller than the size of the orthographic projection of the seventh extension portion 747 on the base substrate in the first direction Y1.
  • a portion of the seventh extension 747 may form the second gate of the second transistor.
  • the fifth gate line 75 may include a seventh gate part 753, and the seventh gate part 753 may form the second gate of the third transistor.
  • the parallel connection of the fourth gate line 74 and the second gate line 12 can improve the transmission speed of the gate driving signal transmitted thereon, thereby improving the response speed of the second transistor.
  • the parallel connection of the fifth gate line 75 and the third gate line 14 can increase the transmission speed of the gate driving signal transmitted thereon, thereby increasing the response speed of the third transistor.
  • the sixth gate line 76 can be used as an initial signal line for providing the initial signal terminal in FIG. 1 .
  • the sixth conductive portion 72 may include a plurality of first sub-conductive portions 721 and a plurality of second sub-conductive portions 722, and the plurality of first sub-conductive portions 721 and the plurality of second sub-conductive portions 722 are alternately distributed along the second direction X in sequence.
  • the second sub-conducting portions 722 are connected between adjacent first sub-conducting portions 721 .
  • the orthographic projection of the first sub-conductive portion 721 on the base substrate may cover the orthographic projection of the first conductive portion 13 on the base substrate.
  • the second sub-conducting portion 722 can be connected to the power line in the second conductive layer through a via hole, so that the first sub-conducting portion 721 can act as a shielding layer to reduce the impact of other signals (eg, data lines, anode signals) on the first conductive layer. Capacitive coupling effect of the conductive portion 13 .
  • the second conductive layer includes the above-mentioned power line 26 , the first conductive line 21 , the third conductive portion 23 , the fourth conductive portion 24 , and the second conductive portion 22 .
  • the second conductive layer also It may include a first connection part 27 , a second connection part 28 , a third connection part 29 , and a fourth connection part 201 .
  • the first connection part 27 can be connected to the second active part 52 through the via hole 202 to connect the second pole of the sixth transistor, and the first connection part 27 is also connected to the sixth gate line 76 through the via hole 203, so that the The sixth gate line 76 provides the initial signal terminal to the second electrode of the sixth transistor.
  • connection part 27 can also be connected to the fourth active part 6 in the pixel driving circuit of the next row through the via hole and 204, so as to provide the third transistor in the pixel driving circuit of the next row through the sixth gate line 76 Initial signal terminal.
  • the second connection part 28 may be connected to the second active part 52 through the via hole 205 to connect the second electrode of the fifth transistor.
  • the third connection part 29 is connected to the fourth active part 6 through the via hole 206 to connect to the second electrode of the second transistor, and the third connection part 29 can be connected to the second active part 52 through the via hole 207 to connect to the driving transistor the second pole, so that the second pole of the second transistor is connected to the second pole of the driving transistor.
  • the fourth connection part 201 may be connected to the first active part 51 through the via hole 208 to connect the first electrode of the first transistor.
  • the orthographic projection of the first conductive line 21 on the base substrate may intersect with the orthographic projection of the sixth extension portion 746 on the base substrate, thereby reducing the size of the sixth extension portion 746 and the first
  • the capacitance of the parallel-plate capacitor structure formed by the conductive lines 21 further reduces the pull-down effect of the sixth extension portion 746 on the first conductive portion 13 after the compensation stage t2 ends.
  • the second conductive portion 22 is connected to the first conductive portion 13 through the via hole 25 , wherein the via hole 25 can penetrate through the first sub-conductive portion 721 in FIG.
  • a specific method for forming the structure may be: forming a fourth dielectric layer on the side of the fourth conductive layer away from the base substrate, and forming a first pass through the fourth conductive layer and extending to the first conductive portion 13 on the fourth dielectric layer.
  • a fifth dielectric layer is formed on the fourth dielectric layer, and the via hole 25 is formed on the fifth dielectric layer.
  • a second conductive portion is then formed on the fifth dielectric layer and filled with vias 25 .
  • the third conductive layer may include the above-mentioned data lines 31 and the fifth conductive portion 35 , and in addition, the third conductive layer may further include the fifth connection portion 32 .
  • the data line 31 can be connected to the fourth connection part 201 through the via hole 33 to connect the first electrode of the first transistor.
  • the fifth conductive portion 35 may be connected to the power line 26 through the via hole 34 .
  • the fifth connection part 32 may be connected with the second connection part 28 through the via hole 36 to be connected with the second pole of the fifth transistor.
  • the distance between the first conductive portion 13 and the first sub-conductive portion 721 may be greater than the distance between the second conductive portion 22 and the fifth conductive portion 35, and the two electrodes of the capacitor C in FIG. 1 may be mainly composed of the second conductive portion 22 and a fifth conductive portion 35 are formed.
  • the anode layer may include a first anode part 81 , a second anode part 82 , and a third anode part 83
  • the first anode part 81 may be connected to the fifth connection part 32 through a via hole 84 to connect with the fifth connection part 32 .
  • the second pole of the fifth transistor is connected; the second anode part 82 can be connected to the fifth connection part 32 in another pixel driving circuit through the via hole 85 ; the third anode part 83 can be connected to another pixel driving circuit through the via hole 86 the fifth connecting part 32 .
  • G light-emitting units may be formed on the first anode portion 81 ; R light-emitting units may be formed on the second anode portion 82 ; and B light-emitting units may be formed on the third anode portion 83 .
  • the array substrate may include a base substrate 0, a barrier layer 02 on the side of the base substrate 0, a second buffer layer 03 on the side of the barrier layer away from the base substrate 0, and the second buffer layer 03 on the side away from the base substrate 0
  • the first active layer on one side including the third active part 53), the second gate insulating layer 05 on the side of the first active layer away from the base substrate, the second gate insulating layer on the side away from the base substrate
  • the first conductive layer on one side including the first conductive portion 13 and the second gate portion 125), the first dielectric layer 07 on the side of the first conductive layer away from the base substrate, and the first dielectric layer 07 on the side away from the substrate
  • the second conductive layer (including the second conductive portion 22 and the power supply line 26) on the side, the passivation layer 014 located on the side of the second conductive layer away from the base substrate, the first passivation layer 014 located on the side of the passivation layer 014 away from the base substrate
  • the third active portion 53 is used to form the channel region of the driving transistor DT
  • the fifth sub-active portion 62 is used to form the channel region of the second transistor T2.
  • the base substrate may include a first polyimide (PI) layer, a first silicon oxide (SiO) layer, an amorphous silicon layer, and a second polyimide (PI) layer which are arranged in sequence , the second silicon dioxide layer.
  • the barrier layer 02 may be located on the side of the second silicon dioxide layer facing away from the first polyimide (PI) layer.
  • the thicknesses of the first polyimide (PI) layer and the second polyimide (PI) layer can both be 90000-110000 ⁇ 5% angstroms, such as 90000 angstroms, 95000 angstroms, 110000 angstroms; the thickness of the first silicon oxide layer
  • the thickness can be 5000-7000 angstroms, such as 5000 angstroms, 5500 angstroms, 7000 angstroms;
  • the thickness of the amorphous silicon layer can be 40-60 angstroms, for example, 40 angstroms, 45 angstroms, 60 angstroms;
  • the thickness of the second silicon dioxide layer can be It is 4500-6500 angstroms, such as 4500 angstroms, 5000 angstroms, 6500 angstroms.
  • the second buffer layer 03 may include a first silicon nitride (SiN) layer and a third silicon oxide layer arranged in sequence, and the first silicon nitride layer may be located on the third silicon oxide layer and the base substrate between.
  • the thickness of the first silicon nitride layer may be 900-1100 angstroms, for example, 900 angstroms, 950 angstroms, and 1100 angstroms; the thickness of the third silicon oxide layer may be 2000-4000 angstroms, for example, 2000 angstroms, 2500 angstroms, and 4000 angstroms. .
  • the first active layer may be a polysilicon layer, and the thickness of the first active layer may be 400-600 angstroms, for example, 400 angstroms, 500 angstroms, and 600 angstroms.
  • the second gate insulating layer 05 can be a silicon oxide layer, and the thickness of the second gate insulating layer 05 can be 500-2000 angstroms, for example, 500 angstroms, 1500 angstroms, 2000 angstroms.
  • Both the first conductive layer and the fourth conductive layer can be molybdenum layers, and the thicknesses of the first conductive layer and the fourth conductive layer can be 1500-2500 angstroms, for example, 1500 angstroms, 2000 angstroms, and 2500 angstroms.
  • the first dielectric layer 07 can be a silicon nitride layer, and the thickness of the first dielectric layer 07 can be 1200-1400 angstroms, for example, 1200 angstroms, 1300 angstroms, and 1400 angstroms.
  • the first buffer layer 08 may be a silicon oxide layer, and the thickness of the first buffer layer 08 may be 3000-5000 angstroms, for example, 3000 angstroms, 3500 angstroms, and 5000 angstroms.
  • the second active layer may be an indium gallium zinc oxide (IGZO) layer, and the thickness of the second active layer may be 300-500 angstroms, for example, 300 angstroms, 350 angstroms, 500 angstroms.
  • IGZO indium gallium zinc oxide
  • the second gate insulating layer 05 may be a silicon oxide layer, and the thickness of the second gate insulating layer 05 may be 1000-2000 angstroms, for example, 1000 angstroms, 1500 angstroms, and 2000 angstroms.
  • the second conductive layer may include a first titanium layer, an aluminum layer, and a second titanium layer stacked in sequence, and the thicknesses of the first titanium layer and the second titanium layer may both be 300-700 angstroms, such as 300 angstroms, 450 angstroms, and 700 angstroms.
  • the thickness of the aluminum layer can be 4500-6500 angstroms, for example, 4500 angstroms, 5000 angstroms, and 6500 angstroms.
  • the second flat layer 19 may be a polyimide (PI) layer, and the thickness of the second flat layer 19 may be 10,000-20,000 angstroms, for example, 10,000 angstroms, 16,000 angstroms, and 20,000 angstroms.
  • an anode layer may be provided on the side of the second flat layer 19 facing away from the base substrate, and a pixel defining layer may be provided on the side of the anode layer facing away from the base substrate.
  • the side can also be provided with support columns.
  • the pixel-defining layer may be a polyimide (PI) layer, and the thickness of the pixel-defining layer may be 10,000-20,000 angstroms, for example, 10,000 angstroms, 16,000 angstroms, and 20,000 angstroms.
  • the support column can be a polyimide (PI) layer, and the thickness of the support column can be 10,000-20,000 angstroms, for example, 10,000 angstroms, 16,000 angstroms, and 20,000 angstroms.
  • the anode layer may include a first indium tin oxide layer, a silver layer, and a second indium tin oxide layer arranged in sequence, and the thickness of the first indium tin oxide layer and the second indium tin oxide layer may be 50-100 angstroms, such as 50 angstroms, 80 angstroms, 100 angstroms, the thickness of the silver layer may be 500-1500 angstroms, for example, 500 angstroms, 800 angstroms, 1500 angstroms.
  • the above-mentioned structural film layer can also be of other materials and thicknesses, for example, the material of the dielectric layer and the passivation layer can also be silicon nitride or transparent organic resin and other materials, and the material of the flat layer can also be transparent Polyimide (CPI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) and other materials.
  • the material of the conductive layer can also be metal materials such as copper and molybdenum.
  • the second conductive portion 22 since the second conductive portion 22 needs to form the electrode of the capacitor, the second conductive portion 22 needs to be designed to have a larger area, so that in a limited plane space, the fifth conductive portion 35 is not easy to completely cover the second conductive portion 35.
  • the larger area of the second conductive portion 22 is also likely to form a larger parasitic capacitance with other structures. Under the coupling effect of the parasitic capacitance, the gate of the driving transistor is more susceptible to external noise interference.
  • FIG. 21 is a structural layout of the second conductive layer in another exemplary embodiment of the array substrate of the disclosure
  • FIG. 22 is the first active layer in another exemplary embodiment of the array substrate of the disclosure.
  • the bonding layout shown in FIG. 22 differs from the bonding layout shown in FIG. 17 only in that the structure of the second conductive layer is different.
  • FIG. 23 it is a partial cross-sectional view taken along the dotted line A in FIG. 22 .
  • the array substrate may include a base substrate 0, a barrier layer 02 on the side of the base substrate 0, a second buffer layer 03 on the side of the barrier layer away from the base substrate 0, and the second buffer layer 03 on the side away from the base substrate 0
  • the first active layer on one side including the third active part 53), the second gate insulating layer 05 on the side of the first active layer away from the base substrate, the second gate insulating layer on the side away from the base substrate
  • the first conductive layer on one side including the first conductive portion 13 and the second gate portion 125), the first dielectric layer 07 on the side of the first conductive layer away from the base substrate, and the first dielectric layer 07 on the side away from the substrate
  • the third active portion 53 is used to form the channel region of the driving transistor DT, and the fifth sub-active portion 62 is used to form the channel region of the second transistor T2.
  • the second conductive portion 22 is connected to the first conductive portion 13 through the via hole 87 .
  • the first buffer layer 08 may be provided with a slot 411, and the orthographic projection of the slot 411 on the base substrate and the orthographic projection of the first conductive portion 13 on the base substrate are at least partially coincide.
  • the first sub-conducting portion 721 is located at the bottom of the slot 411 , and the orthographic projection of the first sub-conducting portion 721 on the base substrate 0 and the first conducting portion 13 on the base substrate The orthographic projections of are at least partially coincident.
  • the second sub-conducting portion 722 may be located outside the slot 411 , that is, the orthographic projection of the second sub-conducting portion 722 on the base substrate does not intersect with the orthographic projection of the slot 411 on the base substrate.
  • a slot 411 is provided on the first buffer layer 08 , and a first sub-conducting portion 721 is provided at the bottom of the slot 411 .
  • the arrangement of the slot 411 reduces the distance between the first sub-conducting portion 721 and the first conducting portion 13 , so that the first sub-conducting portion 721 and the first conducting portion 13 can form two electrodes of the capacitor C.
  • the present exemplary embodiment does not need to design the second conductive portion 22 with a large area in the related art as a capacitor electrode, so that the noise influence of the external signal on the gate of the driving transistor can be reduced.
  • the ratio of the orthographic projection area of the second conductive portion 22 on the base substrate 0 to the orthographic projection area of the first conductive portion 13 on the base substrate may be 4%-25%.
  • the ratio of the orthographic projection area of the second conductive portion 22 on the base substrate 0 to the orthographic projection area of the first conductive portion 13 on the base substrate may be 4%, 8%, 10%, Any of 12%, 15%, 20%, 25%.
  • the ratio of the orthographic projection area of the second conductive portion 22 on the base substrate 0 to the orthographic projection area of the via hole 87 on the base substrate may be 1-2.5, for example , the ratio of the orthographic projection area of the second conductive portion 22 on the base substrate 0 to the orthographic projection area of the via hole 87 on the base substrate may be 1, 1.2, 1.5, 2.0, 2.5, etc. It should be understood that, in other exemplary embodiments, due to process errors and other reasons, the orthographic projection area of the second conductive portion 22 on the base substrate 0 may also be slightly smaller than that of the via hole 87 on the front side of the base substrate shadow area.
  • Table 2 shows the data signal voltages required by different sizes of driving transistors DT in the LTPO technology under different brightness, and the LPTS (transistors in the pixel driving circuit are all low temperature The data signal voltage required by different sizes of driving transistors DT under different brightness in crystalline silicon transistor) technology.
  • the data signal voltage required by the driving transistor DT in the LTPO technology is greater than the data signal voltage required by the driving transistor in the LTPS technology.
  • the table verifies that the second transistor in the LTPO technology will pull down the gate voltage of the drive transistor after the compensation phase, so that the pixel unit needs a higher data signal voltage to display the same brightness.
  • the limit value of the output voltage of the source drive circuit is 6V. It can be seen from Table 2 that in the LTPO technology, when the brightness is R0 (that is, no light is emitted), the data signal voltage required by the driving transistor is already greater than 6V, Therefore, the display panel formed by the LTPO technology cannot normally be at the R0 brightness.
  • the first gate line can pull up the first conductive part by 0.5V, so that in the TPO technology, when the brightness is R0 (that is, no light is emitted) , the required data signal voltage of the drive transistor is within 6V.
  • the R pixel unit, the G pixel unit, and the B pixel unit have different driving voltage intervals.
  • the source driver circuit needs to provide data signals of different driving voltage intervals to the R pixel unit, G pixel unit, and B pixel unit, and the source driver circuit needs to switch between different driving voltage intervals, so the source driver circuit needs to consume more power. .
  • the array substrate may include: an R pixel driving circuit, a G pixel driving circuit, and a B pixel driving circuit; the aspect ratio of the channel region of the driving transistor in the R pixel driving circuit, the driving circuit in the G pixel driving circuit
  • the width to length ratio of the channel region of the transistor and the width to length ratio of the channel region of the driving transistor in the G pixel driving circuit are not all the same. That is, in the R pixel driving circuit, the G pixel driving circuit, and the B pixel driving circuit, the width to length ratio of the channel region of the driving transistor in at least one of the pixel driving circuits is not equal to the width and length of the channel region of the driving transistor in the other pixel driving circuits. Compare.
  • the width to length ratio of the channel region of the driving transistor in the R pixel driving circuit may be 3.5/40
  • the width to length ratio of the channel region of the driving transistor in the B pixel driving circuit may be 3.5/25.
  • Table 2 it can be seen that compared with the channel region of the driving transistor in the R pixel driving circuit, the channel region of the driving transistor in the G pixel driving circuit, and the channel region of the driving transistor in the R pixel driving circuit have the same width and length. This setting can reduce the difference in driving voltage between the R pixel unit, the G pixel unit, and the B pixel unit, thereby reducing the power consumption of the source driving circuit.
  • the channel region of the driving transistor in the B pixel unit is "Z" type
  • the channel region of the driving transistor in the R pixel unit and the channel region of the driving transistor in the G pixel unit are "S” type.
  • the width to length ratio of the channel region of the driving transistor in the B pixel unit is smaller than the width to length ratio of the channel region of the driving transistor in the R pixel unit and the area width to length ratio of the channel region of the driving transistor in the G pixel unit.
  • the present exemplary embodiment also provides a display device, wherein the display device may include the above-mentioned array substrate.
  • the display device may be a display device such as a mobile phone, a tablet computer, and a TV.

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Abstract

涉及显示技术领域，提出一种阵列基板和显示装置，阵列基板包括像素驱动电路和数据线，像素驱动电路包括驱动晶体管（DT）、第一晶体管（T1）、以及第二晶体管（T2），驱动晶体管（DT）和第一晶体管（T1）为P型晶体管，第二晶体管（T2）为N型晶体管。阵列基板还包括：衬底基板（0）、第一导电层，第一导电层设置于衬底基板（0）的一侧，第一导电层包括：第一导电部（13）、第一栅线（11）、第二栅线（12），第一导电部（13）用于形成驱动晶体管（DT）的栅极；第一栅线（11）位于第一导电部（13）的一侧，部分第一栅线（11）用于形成第一晶体管（T1）的栅极；第二栅线（12）位于第一栅线（11）远离第一导电部（13）的一侧，部分第二栅线（12）用于形成第二晶体管（T2）的第一栅极。该阵列基板能够降低第二晶体管（T2）关断时对驱动晶体管（DT）栅极的下拉影响。

Description

阵列基板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示装置。
背景技术
相关技术中，像素驱动电路可以采用低温多晶氧化物(Low temperature polycrystalline oxide，LTPO)技术形成，低温多晶氧化物技术是通过将N型的金属氧化物晶体管和P型的低温多晶体硅晶体管相结合的方式形成像素驱动电路。然而，在低温多晶氧化物技术形成的像素驱动电路中，N型的金属氧化物晶体管关断时，会对驱动晶体管的栅极产生下拉作用，从而影响驱动晶体管栅极的充电。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种阵列基板，所述阵列基板包括像素驱动电路和数据线，所述像素驱动电路包括驱动晶体管、连接于所述驱动晶体管第一极和所述数据线之间的第一晶体管、以及连接于所述驱动晶体管栅极和第二电极之间的第二晶体管，所述驱动晶体管和所述第一晶体管为P型晶体管，所述第二晶体管为N型晶体管，所述阵列基板还包括：衬底基板、第一导电层，第一导电层设置于所述衬底基板的一侧，所述第一导电层包括：第一导电部、第一栅线、第二栅线，第一导电部用于形成所述驱动晶体管的栅极；第一栅线位于所述第一导电部的一侧，部分所述第一栅线用于形成所述第一晶体管的栅极；第二栅线位于所述第一栅线远离所述第一导电部的一侧，部分所述第二栅线用于形成所述第二晶体管的第一栅极。
本公开一种示例性实施例中，所述第一栅线位于所述第一导电部在第一方向上的一侧，且沿第二方向延伸，所述第一方向和所述第二方向相交，所述第一栅线包括：第一延伸部、第二延伸部，所述第一延伸部在所述衬底基板的正投影与至少部分所述第一导电部在所述衬底基板的正投影在所述第一方向上相对；所述第二延伸部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影在所述第一方向相错。
本公开一种示例性实施例中，所述第一延伸部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影在所述第一方向上的距离小于所述第二延伸部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影在所述第一方向上的距离。
本公开一种示例性实施例中，所述第一延伸部包括面向所述第一导电部一侧的第三边 沿，所述第一导电部包括面向所述第一延伸部一侧的第四边沿，所述第三边沿在所述衬底基板的正投影在所述第二方向上的尺寸等于所述第四边沿在所述衬底基板的正投影在所述第二方向的尺寸。
本公开一种示例性实施例中，至少部分所述第二延伸部用于形成所述第一晶体管的栅极。
本公开一种示例性实施例中，所述阵列基板包括多个所述像素驱动电路，所述第一导电层包括沿所述第二方向间隔分布的多个所述第一导电部，多个所述第一导电部用于分别形成不同像素驱动电路中驱动晶体管的栅极；所述第一栅线包括：多个所述第一延伸部、多个所述第二延伸部，所述第一延伸部与所述第一导电部一一对应设置，所述第一延伸部在所述衬底基板的正投影和与其对应的所述第一导电部的至少部分在所述衬底基板的正投影在所述第一方向上相对；多个所述第二延伸部，连接于相邻所述第一延伸部之间。
本公开一种示例性实施例中，所述阵列基板还包括第二导电层，第二导电层设置于所述第一导电层背离所述衬底基板的一侧，所述第二导电层包括：第二导电部、第三导电部、第一导电线，所述第二导电部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合，且通过过孔与所述第一导电部电连接；第三导电部用于形成所述第二晶体管的第一极，所述第一栅线在所述衬底基板的正投影位于所述第二导电部在所述衬底基板的正投影和第三导电部在所述衬底基板的正投影之间；第一导电线连接于所述第二导电部和所述第三导电部之间，且沿所述第一方向延伸，所述第一导电线在所述衬底基板的正投影与所述第一栅线在所述衬底基板的正投影相交。
本公开一种示例性实施例中，所述第二导电层还包括：第四导电部，第四导电部连接所述第一导电线，且所述第四导电部在所述衬底基板的正投影与所述第一栅线在所述衬底基板的正投影至少部分重合；其中，所述第四导电部包括第一边沿，所述第一导电线包括与所述第四导电部第一边沿连接的第二边沿，所述第一边沿在所述衬底基板的正投影与所述第二边沿在所述衬底基板的正投影的夹角小于180度。
本公开一种示例性实施例中，所述第四导电部在所述衬底基板的正投影与所述第一延伸部在所述衬底基板的正投影至少部分重合。
本公开一种示例性实施例中，所述第二栅线在所述衬底基板的正投影位于所述第一栅线在所述衬底基板的正投影和第三导电部在所述衬底基板的正投影之间；所述第二栅线包括沿所述第二方向依次交替连接的第三延伸部和第四延伸部，其中所述第三延伸部在所述衬底基板的正投影在所述第一方向上的尺寸小于所述第四延伸部在所述衬底基板的正投影在所述第一方向上的尺寸；所述第一导电线在所述衬底基板的正投影与所述第三延伸部在所述衬底基板的正投影相交。
本公开一种示例性实施例中，部分所述第四延伸部用于形成所述第二晶体管的第一栅极。
本公开一种示例性实施例中，所述第二导电层还包括电源线，电源线沿所述第一方向 延伸；所述阵列基板还包括第三导电层，第三导电层设置于所述第二导电层背离所述衬底基板的一侧。
本公开一种示例性实施例中，所述电源线包括第五延伸部，所述第五延伸部在所述衬底基板的正投影与至少部分所述第一导电部在所述衬底基板的正投影在所述第二方向上相对，所述第三导电层包括所述数据线，所述数据线沿所述第一方向延伸，且部分所述数据线在所述衬底基板的正投影位于所述第五延伸部在所述衬底基板的正投影上。
本公开一种示例性实施例中，所述第三导电层包括：第五导电部，第五导电部通过过孔连接所述电源线，所述第五导电部在所述衬底基板的正投影覆盖所述第一导电部在所述衬底基板的正投影，且所述第五导电部在所述衬底基板的正投影覆盖所述第二导电部在所述衬底基板的正投影。
本公开一种示例性实施例中，所述阵列基板还包括第三晶体管，所述第三晶体管第一极连接所述驱动晶体管的栅极，所述第二晶体管和所述第三晶体管均为N型金属氧化物晶体管，所述第一导电层还包括：第三栅线，第三栅线位于所述第二栅线远离所述第一导电部的一侧，且沿所述第二方向延伸，部分所述第三栅线用于形成所述第三晶体管的栅极；所述第三导电层包括第五导电部，第五导电部通过过孔连接所述电源线，所述第五导电部在所述衬底基板的正投影覆盖所述第二晶体管和所述第三晶体管在所述衬底基板的正投影。
本公开一种示例性实施例中，所述阵列基板包括：R像素驱动电路、G像素驱动电路、B像素驱动电路；其中，R像素驱动电路中驱动晶体管沟道区的宽长比、G像素驱动电路中驱动晶体管沟道区的宽长比以及G像素驱动电路中驱动晶体管沟道区的宽长比不全相同。
本公开一种示例性实施例中，R像素驱动电路中驱动晶体管沟道区的宽长比等于G像素驱动电路中驱动晶体管沟道区的宽长比，且R像素驱动电路中驱动晶体管沟道区的宽长比小于R像素驱动电路中驱动晶体管沟道区的宽长比。
本公开一种示例性实施例中，R像素驱动电路中驱动晶体管沟道区的宽长比为3.5/40，B像素驱动电路中驱动晶体管沟道区的宽长比为3.5/25。
本公开一种示例性实施例中，所述阵列基板还包括：第四导电层，第四导电层层叠于所述第一导电层和第二导电层之间，所述第四导电层包括：第四栅线，第四栅线沿所述第二方向延伸，所述第一栅线在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第四栅线在所述衬底基板的正投影之间，部分所述第四栅线用于形成所述第二晶体管的第二栅极。
本公开一种示例性实施例中，所述第四栅线包括沿所述第二方向依次交替连接的第六延伸部和第七延伸部；
其中，所述第六延伸部在所述衬底基板的正投影在所述第一方向上的尺寸小于所述第七延伸部在所述衬底基板的正投影在所述第一方向上的尺寸；所述第一导电线在所述衬底 基板的正投影与所述第六延伸部在所述衬底基板的正投影相交。
本公开一种示例性实施例中，部分所述第七延伸部用于形成所述第二晶体管的第二栅极。
本公开一种示例性实施例中，所述阵列基板还包括：第一有源层、第二有源层，第一有源层层叠于所述衬底基板和所述第一导电层之间，部分所述第一有源层用于形成所述驱动晶体管的沟道区；第二有源层层叠于所述第四导电层和所述第一导电层之间，部分所述第二有源层用于形成所述第二晶体管和第三晶体管的沟道区。
本公开一种示例性实施例中，所述阵列基板还包括：使能信号线、初始信号线、阳极层、第一复位信号线、第二复位信号线、电源线，所述像素驱动电路还包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管、电容。第三晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述初始信号线，栅极连接所述第二复位信号线；第四晶体管的第一极连接所述电源线，第二极连接所述驱动晶体管的第一极，栅极连接所述使能信号线；第五晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述阳极层，栅极连接所述使能信号线；第六晶体管的第一极连接所述第五晶体管的第二极，第二极连接所述初始信号线，栅极连接所述第一复位信号线；电容连接于所述驱动晶体管栅极和所述电源线之间。
本公开一种示例性实施例中，所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管为P型低温多晶硅晶体管。
根据本公开的一个方面，提供一种显示装置，其中，所述显示装置包括上述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种像素驱动电路的电路结构示意图；
图2为图1像素驱动电路一种驱动方法中各节点的时序图；
图3为本公开阵列基板一种示例性实施例的结构版图；
图4为本公开阵列基板另一种示例性实施例的结构版图；
图5为图4中第二导电层的结构版图；
图6为本公开阵列基板另一种示例性实施例的结构版图；
图7为图6中第三导电层的结构示意图；
图8为第一有源层的结构版图；
图9为第一导电层的结构版图；
图10为第二有源层的结构版图；
图11为第一有源层、第一导电层、第二有源层的结合版图；
图12为第四导电层的结构版图；
图13为第一有源层、第一导电层、第二有源层、第四导电层的结合版图；
图14为第二导电层的结构版图；
图15为第一有源层、第一导电层、第二有源层、第四导电层、第二导电层的结合版图；
图16为第三导电层的结构版图；
图17为第一有源层、第一导电层、第二有源层、第四导电层、第二导电层、第三导电层的结合版图；
图18为阳极层的结构版图；
图19为第一有源层、第一导电层、第二有源层、第四导电层、第二导电层、第三导电层、阳极层的结合版图；
图20为沿图17中虚线A的部分剖视图；
图21为本公开阵列基板另一种示例性实施例中第二导电层的结构版图；
图22为本公开阵列基板另一种示例性实施例中第一有源层、第一导电层、第二有源层、第四导电层、第二导电层、第三导电层的结合版图；
图23为图22中沿虚线A的剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成区分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成区分/等之外还可存在另外的要素/组成区分/等。
如图1所示，为本公开一种像素驱动电路的电路结构示意图。该像素驱动电路可以包括：驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、电容C。其中，第一晶体管T1的第一极连接数据信号端Da、第二极连接驱动晶体管DT的第一极，栅极连接第一栅极驱动信号端G1；第四晶体管T4的第一极连接第一电源端VDD，第二极连接驱动晶体管DT的第一极，栅极连接使能信号端EM；驱动晶体管DT的栅极连接节点N，第二极连接第五晶体管T5的第一极；第二晶体管T2的第一极连接节点N，第二极连接驱动晶体管DT的第二极，栅极连接第二栅极驱动信号端G2；第五晶体管T5的第二极连接第六晶体管T6的第一极，栅极连接使能信号端EM，第六晶体管T6的第二极连接初始信号端Vinit，栅极连接第一复位信号端Re1；第三晶体管T3的第一极连接节点N，第二极连接初始信号端Vinit，栅极连接第二复位信号端Re2，电容C连接于第一电源端VDD和节点N之间。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED连接于第五晶体管T5第二极和第二电源端VSS之间。其中，第二晶体管T2和第三晶体管T3可以为N型金属氧化物晶体管，N型金属氧化物晶体管具有较小的漏电流，从而可以避免发光阶段，节点N通过第二晶体管T2和第三晶体管T3漏电。同时，驱动晶体管DT、第一晶体管T1、第四晶体管T4、第五晶体管T5、第六晶体管T6可以为低温多晶体硅晶体管，低温多晶硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。
如图2所示，为图1像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示第一栅极驱动信号端G1的时序，G2表示第二栅极驱动信号端G2的时序，Re1表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，N表示节点N的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括复位阶段t1、补偿阶段t2，发光阶段t3。在复位阶段t1：第一复位信号端Re1输出低电平信号，第二复位信号端Re2输出高电平信号，第三晶体管T3、第六晶体管T6导通，初始信号端Vinit向节点N，第五晶体管T5的第二极输入初始化信号。在补偿阶段t2：第一栅极驱动信号端G1输出低电平信号，第二栅极驱动信号端G2输出高电平信号，第一晶体管T1、第二晶体管T2导通，同时数据信号端Da输出驱动信号以向节点N写入电压Vdata+Vth，其中Vdata为驱动信号的电压，Vth为驱动晶体管DT的阈值电压。发光阶段t3：使能信号端EM输出低电平信号，第四晶体管T4、第五晶体管T5导通，驱动晶体管DT在电容C存储的电压Vdata+Vth作用下发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth)2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压 差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth)2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
然而，由于第二晶体管T2的栅极和第一极之间存在寄生电容，如图2所示，在补偿阶段t2结束后，第二栅极驱动信号端G2由高电平降低为低电平，即第二晶体管T2的栅极由高电平降低为低电平，第二晶体管T2第一极的电压会在电容耦合效应下降低，与第二晶体管T2第一极连接的节点N电压也会相应降低。根据上述驱动晶体管输出电流公式可知，节点N(即驱动晶体管栅极)电压下降会影响驱动晶体管的输出电流。为了保证驱动晶体管输出正常所需的驱动电流，源极驱动电路需要通过数据线向数据信号端提供更高电压值的数据信号。通过仿真，上述像素驱动电路在显示灰阶0时，源极驱动电路向数据线提供的电压需要大于6.3V，但是现有的源极驱动电路向数据线提供的最大电压为6V，从而无法满足正常显示需求。
基于此，本示例性实施例提供一种阵列基板，所述阵列基板可以包括像素驱动电路和数据线，所述像素驱动电路的电路结构可以如图1所示，驱动方法可以如图2所示。如图3所示，为本公开阵列基板一种示例性实施例的结构版图。所述阵列基板还可以包括：衬底基板0、第一导电层，第一导电层设置于所述衬底基板0的一侧，所述第一导电层可以包括：第一导电部13、第一栅线11、第二栅线12，第一导电部13可以用于形成所述驱动晶体管的栅极；第一栅线11可以位于所述第一导电部13的一侧，部分所述第一栅线11可以用于形成所述第一晶体管的栅极；第二栅线12可以位于所述第一栅线11远离所述第一导电部13的一侧，部分所述第二栅线12可以用于形成所述第二晶体管的第一栅极。
本示例性实施例中，阵列基板将第二栅线12设置于第一栅线11远离第一导电部13的一侧。一方面，该设置增加了第二栅线12和第一导电部13之间距离，减小了第二栅线12和第一导电部13之间的侧向电容，从而降低了第二晶体管栅极在补偿阶段结束后对驱动晶体管栅极的下拉作用；另一方面，第一栅线11和第一导电部13可以形成侧向电容，如图2所示，第一晶体管在补偿阶段t2结束后，从低电平跳变到高电平，从而第一晶体管的栅极可以对驱动晶体管的栅极产生上拉作用，本示例性实施例提供的阵列基板减小了第一栅线11和第一导电部13之间距离，增加了第一栅线11和第一导电部13之间的侧向电容，从而可以增强第一晶体管栅极对驱动晶体管栅极的上拉作用；再一方面，第一栅线11位于第一导电部13和第二栅线12之间，第一栅线11可以对第二栅线12起到一定的屏蔽作用，从而进一步降低第二晶体管栅极对驱动晶体管栅极的下拉作用。本示例性实施例中，第一栅线11对第一导电部13的上拉作用强于第二栅线12对第一导电部13的下拉作用，从而该阵列基板可以在一定程度上抵消上述中第二晶体管对驱动晶体管栅极的下拉作用。
应该理解的是，在其他示例性实施例中，阵列基板中像素驱动电路还可以为其他电路结构。在通过LTPO技术形成像素驱动电路中，连接于驱动晶体管栅极和第二极之间的N 型第一晶体管均会在补偿阶段结束后对驱动晶体管的栅极产生下拉作用。相应的，其他示例性实施例也可以通过上述阵列基板结构设计，通过减小N型第一晶体管栅极对驱动晶体管栅极的下拉作用，增加P型第二晶体管栅极对驱动晶体管栅极的下拉作用，以减弱第二晶体管对驱动晶体管栅极的下拉作用。
本示例性实施例中，如图3所示，所述第一栅线11可以位于所述第一导电部13在第一方向Y1上的一侧，且沿第二方向X延伸，所述第一方向Y1和所述第二方向X相交，例如，所述第一方向Y1和所述第二方向X可以垂直。所述第一栅线11可以包括：第一延伸部111、第二延伸部112，所述第一延伸部111在所述衬底基板的正投影与至少部分所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1上相对；所述第二延伸部112在所述衬底基板的正投影与所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1相错。第一方向和第二方向均可以为与衬底基板所在平面平行的方向。其中，“所述第一延伸部111在所述衬底基板的正投影与至少部分所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1上相对”可以理解为，所述第一延伸部111在所述衬底基板的正投影沿第一方向Y1和第三方向Y2无限移动所覆盖的区域与至少部分所述第一导电部13在所述衬底基板的正投影沿第一方向Y1和第三方向Y2无限移动所覆盖的区域完全重合，其中，第一方向Y1和第三方向Y2相反。“所述第二延伸部112在所述衬底基板的正投影与所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1相错”可以理解为，所述第二延伸部112在所述衬底基板的正投影沿第一方向Y1和第三方向Y2无限移动所覆盖的区域与所述第一导电部13在所述衬底基板的正投影沿第一方向Y1和第三方向Y2无限移动所覆盖的区域不相交，同样的，第一方向Y1和第三方向Y2相反。
本示例性实施例中，所述第一延伸部111在所述衬底基板的正投影与所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1上的距离S1可以小于所述第二延伸部112在所述衬底基板的正投影与所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1上的距离S2。如图3所示，所述第一延伸部111在所述衬底基板的正投影与所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1上的距离S1可以指，第一延伸部111在所述衬底基板的正投影面向第一导电部13一侧的边沿与第一导电部13在所述衬底基板的正投影面向第一延伸部111一侧边沿在第一方向Y1上的距离。所述第二延伸部112在所述衬底基板的正投影与所述第一导电部13在所述衬底基板的正投影在所述第一方向Y1上的距离S2可以指，第二延伸部112在所述衬底基板的正投影面向第一导电部13一侧的边沿与第一导电部13在所述衬底基板的正投影面向第二延伸部112一侧边沿所在直线在第一方向Y1上的距离。该设置缩小了第一延伸部111与第一导电部13在第一方向上的距离，增加了第一延伸部111与第一导电部13的侧向电容，从而可以进一步增加了第一栅线对驱动晶体管栅极的上拉作用。
本示例性实施例中，如图3所示，所述第一延伸部111包括面向所述第一导电部13一侧的第三边沿1111，所述第一导电部13包括面向所述第一延伸部111一侧的第四边沿 131，所述第三边沿1111在所述衬底基板的正投影在所述第二方向X上的尺寸可以等于所述第四边沿131在所述衬底基板的正投影在所述第二方向X的尺寸。该设置可以极大的增加第一延伸部111和第一导电部13形成的侧向电容的电容值，以进一步增加了第一栅线对驱动晶体管栅极的上拉作用。其中，第三边沿1111和第四边沿131均可以沿第二方向延伸。应该理解的是，在其他示例性实施例中，第三边沿1111、第四边沿131还可以沿与第二方向相交的方向延伸，此时，“所述第三边沿1111在所述衬底基板的正投影在所述第二方向X上的尺寸”可以理解为，在以第三边沿1111在所述衬底基板的正投影为斜边的直角三角形中沿第二方向延伸的直角边的尺寸，“第四边沿131在所述衬底基板的正投影在所述第二方向X的尺寸”可以理解为，在以第四边沿131在所述衬底基板的正投影为斜边的直角三角形中沿第二方向延伸的直角边的尺寸。此外，所述第三边沿1111在所述衬底基板的正投影在所述第二方向X上的尺寸还可以小于所述第四边沿131在所述衬底基板的正投影在所述第二方向X的尺寸。
本示例性实施例中，至少部分所述第二延伸部112可以用于形成所述第一晶体管的栅极。由于第二延伸部112在所述衬底基板的正投影在第一方向上与第一导电部13在所述衬底基板的正投影距离较大，该设计可以充分预留出设置第一晶体管的空间。
本示例性实施例中，如图3所示，所述阵列基板可以包括多个所述像素驱动电路，所述第一导电层可以包括沿所述第二方向X间隔分布的多个所述第一导电部13，多个所述第一导电部13用于分别形成不同像素驱动电路中驱动晶体管的栅极；所述第一栅线11可以包括：多个所述第一延伸部111、多个所述第二延伸部112，所述第一延伸部111可以与所述第一导电部13一一对应设置，所述第一延伸部111在所述衬底基板的正投影和与其对应的所述第一导电部13的至少部分在所述衬底基板的正投影在所述第一方向Y1上相对。
本示例性实施例中，如图4、5所示，图4为本公开阵列基板另一种示例性实施例的结构版图，图5为图4中第二导电层的结构版图。所述阵列基板还可以包括第二导电层，第二导电层可以设置于所述第一导电层背离所述衬底基板0的一侧，所述第二导电层可以包括：第二导电部22、第三导电部23、第一导电线21，所述第二导电部22在所述衬底基板0的正投影与所述第一导电部13在所述衬底基板0的正投影至少部分重合，且通过过孔25与所述第一导电部13电连接；第三导电部23可以用于形成所述第二晶体管的第一极，所述第一栅线11在所述衬底基板0的正投影位于所述第二导电部22在所述衬底基板的正投影和第三导电部23在所述衬底基板的正投影之间；第一导电线21连接于所述第二导电部22和所述第三导电部23之间，以使第二晶体管的第一极连接驱动晶体管的栅极，第一导电线21可以沿所述第一方向Y1延伸，所述第一导电线21在所述衬底基板的正投影与所述第一栅线11在所述衬底基板的正投影相交。其中，由于所述第一导电线21在所述衬底基板的正投影与所述第一栅线11在所述衬底基板的正投影相交，因此，部分第一导电线21可以与部分第一栅线11形成平行板电容结构。利用该平行板电容结构的耦合效 应，第一栅线11可以在像素驱动电路补偿阶段结束后对第一导电线21起到上拉作用，由于第一导电线21与第一导电部13电连接，即该设置可以进一步增强第一栅线11对第一导电部13的上拉作用。
本示例性实施例中，如图4、5所示，所述第二导电层还可以包括：第四导电部24，第四导电部24可以连接所述第一导电线21，所述第四导电部24在所述衬底基板的正投影可以与所述第一栅线11在所述衬底基板的正投影至少部分重合，其中，所述第四导电部24可以包括第一边沿241，所述第一导电线21可以包括与所述第四导电部第一边沿241连接的第二边沿211，所述第一边沿241在所述衬底基板的正投影与所述第二边沿211在所述衬底基板的正投影的夹角α小于180度。部分第四导电部24可以与部分第一栅线11形成平行板电容结构。利用该平行板电容结构的耦合效应，第一栅线11可以在像素驱动电路补偿阶段结束后对第四导电部24起到上拉作用，由于第四导电部24通过第一导电线21与第一导电部13电连接，即该设置可以进一步增强第一栅线11对第一导电部13的上拉作用。如图4、5所示，第四导电部24可以连接于第一导电线21在第二方向X反方向的一侧，具体的，所述第四导电部24在所述衬底基板的正投影可以与所述第一延伸部111在所述衬底基板的正投影至少部分重合。
如下表1所示，表1中C表示第一栅线与第一导电部(即节点N)形成的寄生电容，Vn表示在发光阶段图1中节点N的电压，表1示出了在数据信号电压为6V状态下，不同寄生电容C对应的Vn。从表1可以看出，寄生电容C越大，第一栅线对第一导电部的上拉作用越强。
表1
Figure PCTCN2020124163-appb-000001
本示例性实施例中，如图3、4、5所示，所述第二栅线12在所述衬底基板的正投影可以位于所述第一栅线11在所述衬底基板的正投影和第三导电部23在所述衬底基板的正投影之间；所述第二栅线12可以包括沿所述第二方向X依次交替连接的第三延伸部123和第四延伸部124，其中，所述第三延伸部123在所述衬底基板的正投影在所述第一方向Y1上的尺寸可以小于所述第四延伸部124在所述衬底基板的正投影在所述第一方向Y1上的尺寸。所述第一导电线21在所述衬底基板的正投影可以与所述第三延伸部123在所述衬底基板的正投影相交。部分第三延伸部123可以与部分第一导电线21形成平行板电容结构。基于该平行板电容结构的耦合效应，第三延伸部123可以在像素驱动电路补偿阶段结束后对第一导电线21产生下拉作用，由于第一导电线21与第一导电部13电连接， 第三延伸部123会对第一导电部13产生下拉作用。本示例性实施例中，所述第三延伸部123在所述衬底基板的正投影在所述第一方向Y1上的尺寸小于所述第四延伸部124在所述衬底基板的正投影在所述第一方向Y1上的尺寸，即本示例性实施例缩小了第三延伸部123在所述第一方向Y1上的尺寸，从而减小了第三延伸部123和第一导电线21所形成平行板电容结构的电极面积，根据平行板电容器的电容计算公可知，平行板电容结构的电容与其电极面积成正比，即该设置减小了第三延伸部123和第一导电线21所形成平行板电容结构的电容，从而降低了第三延伸部123对第一导电部13的下拉作用。其中，部分所述第四延伸部124可以用于形成所述第二晶体管的第一栅极。第二晶体管的沟道区可以沿第一方向Y1延伸，从而第二晶体管的沟道区可以具有较大的长度，以降低第二晶体管的漏电流。
本示例性实施例中，如图4、5所示，所述第二导电层还可以包括电源线26，电源线26可以沿所述第一方向Y1延伸，电源线26可以用于提供图1中的第一电源端。其中，电源线26在衬底基板的正投影可以与第三延伸部123在衬底基板的正投影相交，该设置可以减小电源线26与第二栅线的交叠面积，从而减小电源线26在电压波动时对第二栅线12造成的电容耦合效应。
如图6、7所示，图6为本公开阵列基板另一种示例性实施例的结构版图，图7为图6中第三导电层的结构示意图。所述阵列基板还可以包括第三导电层，第三导电层可以设置于所述第二导电层背离所述衬底基板的一侧。如图5、6所示，所述电源线26可以包括第五延伸部265，所述第五延伸部265在所述衬底基板的正投影与至少部分所述第一导电部13在所述衬底基板的正投影在所述第二方向X上相对。“所述第五延伸部265在所述衬底基板的正投影与至少部分所述第一导电部13在所述衬底基板的正投影在所述第二方向X上相对”可以理解为，所述第五延伸部265在所述衬底基板的正投影沿第二方向和第二方向反方向无限移动所覆盖的区域与至少部分所述第一导电部13在所述衬底基板的正投影沿第二方向和第二方向反方向无限移动所覆盖的区域完全重合。所述第三导电层可以包括所述数据线31，所述数据线31沿所述第一方向Y1延伸，且部分所述数据线31在所述衬底基板的正投影可以位于所述第五延伸部265在所述衬底基板的正投影上。其中，第五延伸部265设置于数据线31和第一导电部13之间，且第五延伸部265接收一稳定电压，从而第五延伸部265可以作为屏蔽层降低数据线31和第一导电部13之间的耦合电容，进而降低数据线31对第一导电部13的耦合效应。
本示例性实施例中，如图6、7所示，所述第三导电层还可以包括：第五导电部35，第五导电部35可以通过过孔34连接所述电源线26，所述第五导电部35在所述衬底基板0的正投影可以覆盖所述第一导电部13在所述衬底基板0的正投影，且所述第五导电部35在所述衬底基板0的正投影可以覆盖所述第二导电部22在所述衬底基板0的正投影。其中，第五导电部35覆盖第一导电部13和第二导电部22，且第五导电部35接收一稳定电压，从而第五导电部35可以作为屏蔽层降低其他信号对第一导电部13和第二导电部 22的电容耦合效应，例如，第五导电部35可以降低数据线、阳极层对第一导电部13和第二导电部22的电容耦合效应。
本示例性实施例中，如图6所示，所述第一导电层还可以包括：第三栅线14，第三栅线14位于所述第二栅线12远离所述第一导电部13的一侧，且沿所述第二方向X延伸，部分所述第三栅线14可以用于形成第三晶体管T3的栅极。如图6所示，该阵列基板还可以包括第二有源层，第二有源层可以设置于第一导电层和第二导电层之间，第二有源层可以包括第四有源部6，第四有源部6可以沿第一方向Y1延伸。第四有源部6在衬底基板0的正投影与第四延伸部124在衬底基板0的正投影相交，以形成图1中第二晶体管T2；第四有源部6在衬底基板0的正投影与第三栅线14在衬底基板0的正投影相交，以形成图1中第三晶体管T3。所述第五导电部35在所述衬底基板0的正投影还可以覆盖所述第二晶体管T2和所述第三晶体管T3在所述衬底基板0的正投影。第四有源部6的材料可以为金属氧化物，例如氧化铟镓锌，相应的，第二晶体管和第三晶体管可以为金属氧化物晶体管，金属氧化物晶体管在光照环境下会发生特征变化，通过第五导电部35覆盖第二晶体管T2和第三晶体管T3，可以避免光照对第二晶体管T2和第三晶体管T3输出特征的影响。
以下本示例性实施例对阵列基板的整体结构进行详细说明：
如图8-19所示，图8为第一有源层的结构版图；图9为第一导电层的结构版图；图10为第二有源层的结构版图；图11为第一有源层、第一导电层、第二有源层的结合版图；图12为第四导电层的结构版图；图13为第一有源层、第一导电层、第二有源层、第四导电层的结合版图；图14为第二导电层的结构版图；图15为第一有源层、第一导电层、第二有源层、第四导电层、第二导电层的结合版图；图16为第三导电层的结构版图；图17为第一有源层、第一导电层、第二有源层、第四导电层、第二导电层、第三导电层的结合版图；图18为阳极层的结构版图；图19为第一有源层、第一导电层、第二有源层、第四导电层、第二导电层、第三导电层、阳极层的结合版图。
如图11、8所示，第一有源层可以包括有沿第一方向Y1延伸的第一有源部51和第二有源部52，第一有源部51和第二有源部52沿第二方向X间隔分布。第一有源部51和第二有源部52之间连接有第三有源部53。其中，第一有源部51可以包括有第一子有源部511和第二子有源部514，第二有源部52可以包括有第三子有源部525和第四子有源部526。其中，第三有源部53可以用于形成驱动晶体管的沟道区；第一子有源部511可以用于形成第一晶体管的沟道区；第二子有源部514可以用于形成第四晶体管的沟道区；第三子有源部525可以用于形成第五晶体管的沟道区；第四子有源部526可以用于形成第六晶体管的沟道区。本示例性实施例中，第一有源层可以为多晶硅材料，相应的，所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管可以为P型低温多晶硅晶体管。
如图11、9所示，第一导电层包括上述的第一导电部13、第一栅线11、第二栅线12、第三栅线14，此外，第一导电层还可以包括第五栅线15、第六栅线16。第五栅线15位 于第一导电部1远离第一栅线的一侧，第六栅线16位于第五栅线15远离第一导电部13的一侧。第一栅线11、第二栅线12、第三栅线14、第五栅线15、第六栅线16均可以沿第二方向X延伸。第一栅线11可以用于提供图1中的第一栅极驱动信号端，第一栅线11可以包括有第一栅极部113；第二栅线12可以用于提供图1中的第二栅极驱动信号端，第二栅线12可以包括第二栅极部125；第三栅线14可以作为第二复位信号线用于提供图1中的第二复位信号端，第三栅线14可以包括第三栅极部143；第五栅线15可以作为使能信号线用于提供图1中的使能信号端，第五栅线15可以包括第四栅极部154和第五栅极部155；第六栅线16可以作为第一复位信号线用于提供图1中的第一复位信号端，第六栅线16包括第六栅极部166。其中，第一栅极部113可以用于形成第一晶体管T1的栅极，第二栅极部125可以用于形成第二晶体管的第一栅极；第三栅极部143可以用于形成第三晶体管的第一栅极；第四栅极部154可以用于形成第四晶体管的栅极；第五栅极部155可以用于形成第五晶体管的栅极；第六栅极部166可以用于形成第六晶体管的栅极。第一栅极部113可以位于上述的第二延伸部112上，第二栅极部125可以位于上述的第四延伸部124上。
如图11、10所示，第二有源层可以包括沿第一方向Y1延伸的多个上述第四有源部6，多个第四有源部6可以沿第二方向X间隔分布，多个第四有源部6与多个像素驱动电路一一对应设置。如图10所示，第四有源部6可以包括第五子有源部62和第六子有源部63，其中，第五子有源部62可以形成第二晶体管的沟道区，第六子有源部63可以形成第三晶体管的沟道区。其中，第二栅线12可以对第五子有源部62产生遮光作用，以避免第二晶体管的输出特性受光照影响；第三栅线14可以对第六子有源部63产生遮光作用，以避免第三晶体管的输出特性受光照影响。
如图12、13所示，第四导电层可以包括第四栅线74、第五栅线75、第六栅线76，第六导电部72。第四栅线74、第五栅线75、第六栅线76均可沿第二方向X延伸。第四栅线74可以在显示区周边的走线区与第二栅线12通过过孔连接；第五栅线75可以在显示区周边的走线区与第三栅线14通过过孔连接。其中，所述第一栅线11在所述衬底基板的正投影位于所述第一导电部13在所述衬底基板的正投影和所述第四栅线74在所述衬底基板的正投影之间。第四栅线74包括沿所述第二方向X依次交替连接的第六延伸部746和第七延伸部747；其中，所述第六延伸部746在所述衬底基板的正投影在所述第一方向Y1上的尺寸小于所述第七延伸部747在所述衬底基板的正投影在所述第一方向Y1上的尺寸。部分第七延伸部747可以形成第二晶体管的第二栅极。第五栅线75可以包括第七栅极部753，第七栅极部753可以形成第三晶体管的第二栅极。其中，并联的第四栅线74和第二栅线12可以提高传输于其上的栅极驱动信号的传输速度，从而提高第二晶体管的响应速度。并联的第五栅线75和第三栅线14可以提高传输于其上的栅极驱动信号的传输速度，从而提高第三晶体管的响应速度。第六栅线76可以作为初始信号线用于提供图1中的初始信号端。第六导电部72可以包括多个第一子导电部721和多个第二子导电部722， 多个第一子导电部721和多个第二子导电部722沿第二方向X依次交替分布，第二子导电部722连接于相邻第一子导电部721之间。第一子导电部721在衬底基板的正投影可以覆盖第一导电部13在衬底基板的正投影。其中，第二子导电部722可以通过过孔与第二导电层中的电源线连接，从而第一子导电部721可以作为屏蔽层降低其他信号(例如，数据线、阳极的信号)对第一导电部13的电容耦合效应。
如图14、15所示，第二导电层包括上述的电源线26、第一导电线21、第三导电部23、第四导电部24、第二导电部22，此外，第二导电层还可以包括第一连接部27、第二连接部28、第三连接部29、第四连接部201。第一连接部27可以通过过孔202与第二有源部52连接，以连接第六晶体管的第二极，第一连接部27还通过过孔203与第六栅线76连接，从而可以通过第六栅线76向第六晶体管的第二极提供初始信号端。此外，第一连接部27还可以通过过孔与204与下一行像素驱动电路中的第四有源部6连接，以通过该第六栅线76向下一行像素驱动电路中的第三晶体管提供初始信号端。第二连接部28可以通过过孔205与第二有源部52连接，以连接第五晶体管的第二极。第三连接部29通过过孔206连接第四有源部6，以连接第二晶体管的第二极，第三连接部29可以通过过孔207连接第二有源部52，以连接驱动晶体管的第二极，从而使得第二晶体管的第二极连接驱动晶体管的第二极。第四连接部201可以通过过孔208与第一有源部51连接，以连接第一晶体管的第一极。其中，所述第一导电线21在所述衬底基板的正投影可以与所述第六延伸部746在所述衬底基板的正投影相交，从而减小了第六延伸部746和第一导电线21所形成平行板电容结构的电容，进而降低了第六延伸部746在补偿阶段t2结束后对第一导电部13的下拉作用。图4中第二导电部22通过过孔25连接第一导电部13，其中，过孔25可以贯穿图13中的第一子导电部721，且位于过孔25内的导电材料与第一子导电部721绝缘设置。该结构具体形成方法可以为，在第四导电层背离衬底基板一侧形成第四介电层，在第四介电层上形成贯穿第四导电层延伸至第一导电部13的第一过孔，在第四介电层上形成第五介电层，在五介电层上形成所述过孔25，过孔25在衬底基板的正投影位于该第一过孔在衬底基板的正投影以内，然后在第五介电层上形成第二导电部并填充过孔25。
如图16、17所示，第三导电层可以包括上述的数据线31、第五导电部35，此外，第三导电层还可以包括第五连接部32。其中，数据线31可以通过过孔33与第四连接部201连接，以连接第一晶体管的第一极。第五导电部35可以通过过孔34与电源线26连接。第五连接部32可以通过过孔36与第二连接部28连接，以与第五晶体管的第二极连接。其中，第一导电部13和第一子导电部721之间距离可以大于第二导电部22和第五导电部35之间的距离，图1中电容C的两电极可以主要由第二导电部22和第五导电部35形成。
如图18、19所示，阳极层可以包括第一阳极部81、第二阳极部82、第三阳极部83，第一阳极部81可以通过过孔84连接第五连接部32，以以与第五晶体管的第二极连接；第二阳极部82可以通过过孔85连接另一像素驱动电路中的第五连接部32；第三阳极部 83可以通过过孔86连接另一像素驱动电路中的第五连接部32。第一阳极部81上可以形成G发光单元；第二阳极部82上可以形成R发光单元；第三阳极部83上可以形成B发光单元。
如图20所示，为沿图17中虚线A的部分剖视图。该阵列基板可以包括衬底基板0、位于衬底基板0一侧的阻挡层02、位于阻挡层背离衬底基板0一侧的第二缓冲层03、位于第二缓冲层03背离衬底基板0一侧的第一有源层(包括第三有源部53)、位于第一有源层背离衬底基板一侧的第二栅极绝缘层05、位于第二栅极绝缘层背离衬底基板一侧的第一导电层(包括第一导电部13、第二栅极部125)、位于第一导电层背离衬底基板一侧的第一介电层07、位于第一介电层07背离衬底基板0一侧的第一缓冲层08、位于第一缓冲层08背离衬底基板0一侧的第二有源层(包括第五子有源部62)、位于第二有源层背离衬底基板一侧的第一栅极绝缘层(包括第一绝缘部0101和第二绝缘部0102)、位于第一栅极绝缘层背离衬底基板一侧的第四导电层(包括第一子导电部721、第七延伸部747、第二子导电部722)、位于第四导电层背离衬底基板一侧的第二介电层012、位于第二介电层012背离衬底基板的一侧的第二导电层(包括第二导电部22、电源线26)、位于第二导电层背离衬底基板一侧的钝化层014、位于钝化层014背离衬底基板一侧的第一平坦层015、位于第一平坦层015背离衬底基板一侧的第三导电层(包括第五导电部35)、位于第三导电层背离衬底基板一侧的第二平坦层19。其中，第三有源部53用于形成驱动晶体管DT的沟道区，第五子有源部62用于形成第二晶体管T2的沟道区。
本示例性实施例中，衬底基板可以包括依次设置的第一聚酰亚胺(PI)层、第一氧化硅(SiO)层、非晶硅层、第二聚酰亚胺(PI)层、第二氧化硅层。阻挡层02可以位于第二氧化硅层背离第一聚酰亚胺(PI)层的一侧。第一聚酰亚胺(PI)层和第二聚酰亚胺(PI)层的厚度均可以为90000-110000±5％埃，例如90000埃、95000埃、110000埃；第一氧化硅层的厚度可以为5000-7000埃，例如5000埃、5500埃、7000埃；非晶硅层的厚度可以为40-60埃，例如，40埃、45埃、60埃；第二氧化硅层的厚度可以为4500-6500埃，例如4500埃、5000埃、6500埃。
本示例性实施例中，第二缓冲层03可以包括依次设置的第一氮化硅(SiN)层和第三氧化硅层，第一氮化硅层可以位于第三氧化硅层和衬底基板之间。第一氮化硅层的厚度可以为900-1100埃，例如900埃、950埃、1100埃，；第三氧化硅层的厚度可以为2000-4000埃，例如，2000埃、2500埃、4000埃。第一有源层可以为多晶硅层，第一有源层的厚度可以为400-600埃，例如，400埃、500埃、600埃。第二栅极绝缘层05可以为氧化硅层，第二栅极绝缘层05的厚度可以为500-2000埃，例如，500埃、1500埃、2000埃。第一导电层、第四导电层均可以为钼层，第一导电层、第四导电层均的厚度可以为1500-2500埃，例如1500埃、2000埃、2500埃。第一介电层07可以为氮化硅层，第一介电层07的厚度可以为1200-1400埃，例如1200埃、1300埃、1400埃。第一缓冲层08可以为氧化硅层，第一缓冲层08的厚度可以为3000-5000埃，例如，3000埃、3500埃、5000埃。第二有源 层可以为氧化铟镓锌(IGZO)层，第二有源层的厚度可以为300-500埃，例如，300埃、350埃、500埃。第二栅极绝缘层05可以为氧化硅层，第二栅极绝缘层05的厚度可以为1000-2000埃，例如，1000埃、1500埃、2000埃。第二导电层可以包括依次层叠的第一钛层、铝层、第二钛层，第一钛层、第二钛层的厚度均可以为300-700埃，例如300埃、450埃、700埃，铝层的厚度均可以为4500-6500埃，例如，4500埃、5000埃、6500埃。第二平坦层19可以为聚酰亚胺(PI)层，第二平坦层19的厚度可以为10000-20000埃，例如，10000埃、16000埃、20000埃。
本示例性实施例中，第二平坦层19背离衬底基板的一侧还可以设置阳极层，阳极层背离衬底基板的一侧还可以设置像素限定层，像素定义层背离衬底基板的一侧还可以设置支撑柱。像素限定层可以为聚酰亚胺(PI)层，像素限定层的厚度可以为10000-20000埃，例如，10000埃、16000埃、20000埃。支撑柱可以为聚酰亚胺(PI)层，支撑柱的厚度可以为10000-20000埃，例如，10000埃、16000埃、20000埃。阳极层可以包括依次设置的第一氧化铟锡层、银层、第二氧化铟锡层，第一氧化铟锡层、第二氧化铟锡层的厚度可以为50-100埃，例如50埃、80埃、100埃，银层的厚度可以为500-1500埃，例如，500埃、800埃、1500埃。
应该理解的是，上述结构膜层还可以为其他材料和厚度，例如，介电层、钝化层的材料还可以为氮化硅或透明的有机树脂等材料，平坦层的材料还可以为透明聚酰亚胺(CPI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)等材料。导电层的材料还可以为铜、钼等金属材料。
本示例性实施例中，由于第二导电部22需要形成电容的电极，第二导电部22需要设计成较大的面积，从而在有限的平面空间内，第五导电部35不易完全覆盖第二导电部22，进而造成第二导电部22容易受到外部噪音干扰。此外，较大面积的第二导电部22还容易与其他结构形成较大的寄生电容，在该寄生电容耦合效应下，驱动晶体管栅极更容易受到外部噪音干扰。
如图21、22所示，图21为本公开阵列基板另一种示例性实施例中第二导电层的结构版图，图22为本公开阵列基板另一种示例性实施例中第一有源层、第一导电层、第二有源层、第四导电层、第二导电层、第三导电层的结合版图。图22所示的结合版图与图17所示的结合版图仅区别在于第二导电层的结构不同。如图23所示，为图22中沿虚线A的部分剖视图。该阵列基板可以包括衬底基板0、位于衬底基板0一侧的阻挡层02、位于阻挡层背离衬底基板0一侧的第二缓冲层03、位于第二缓冲层03背离衬底基板0一侧的第一有源层(包括第三有源部53)、位于第一有源层背离衬底基板一侧的第二栅极绝缘层05、位于第二栅极绝缘层背离衬底基板一侧的第一导电层(包括第一导电部13、第二栅极部125)、位于第一导电层背离衬底基板一侧的第一介电层07、位于第一介电层07背离衬底基板0一侧的第一缓冲层08、位于第一缓冲层08背离衬底基板0一侧的第二有源层(包括第五子有源部62)、位于第二有源层背离衬底基板一侧的第一栅极绝缘层(包 括绝缘部0102)、位于第一栅极绝缘层背离衬底基板一侧的第四导电层(包括第一子导电部721、第七延伸部747、第二子导电部722)、位于第四导电层背离衬底基板一侧的第二介电层012、位于第二介电层012背离衬底基板的一侧的第二导电层(包括第二导电部22、电源线26)、位于第二导电层背离衬底基板一侧的钝化层014、位于钝化层014背离衬底基板一侧的第一平坦层015、位于第一平坦层015背离衬底基板一侧的第三导电层(包括第五导电部35)、位于第三导电层背离衬底基板一侧的第二平坦层19。其中，第三有源部53用于形成驱动晶体管DT的沟道区，第五子有源部62用于形成第二晶体管T2的沟道区。第二导电部22通过过孔87与第一导电部13连接。
其中，所述第一缓冲层08上可以设置有开槽411，所述开槽411在所述衬底基板的正投影与所述第一导电部13在所述衬底基板的正投影至少部分重合。所述第一子导电部721位于所述开槽411的底部，且所述第一子导电部721在所述衬底基板0的正投影与所述第一导电部13在所述衬底基板的正投影至少部分重合。其中，第二子导电部722可以位于开槽411的外部，即第二子导电部722在衬底基板的正投影与开槽411在衬底基板的正投影不相交。
本示例性实施例提供的阵列基板在第一缓冲层08上设置开槽411，同时在开槽411的槽底设置第一子导电部721。开槽411的设置减小了第一子导电部721和第一导电部13之间的距离，从而可以使得第一子导电部721和第一导电部13形成电容C的两电极。本示例性实施例不需要设计相关技术中极大面积的第二导电部22作为电容电极，从而可以降低外部信号对驱动晶体管栅极的噪声影响。
其中，所述第二导电部22在所述衬底基板0的正投影面积与所述第一导电部13在所述衬底基板正投影面积的比值可以为4％-25％。例如，所述第二导电部22在所述衬底基板0的正投影面积与所述第一导电部13在所述衬底基板正投影面积的比值可以为4％、8％、10％、12％、15％、20％、25％中的任意一种。
本示例性实施例中，所述第二导电部22在所述衬底基板0的正投影面积与所述过孔87在所述衬底基板的正投影面积的比值可以为1-2.5，例如，所述第二导电部22在所述衬底基板0的正投影面积与所述过孔87在所述衬底基板的正投影面积的比值可以为1、1.2、1.5、2.0、2.5等。应该理解的是，在其他示例性实施例中，由于工艺误差等原因，第二导电部22在所述衬底基板0的正投影面积还可以略小于过孔87在所述衬底基板的正投影面积。
本示例性实施例中，如下表2所示，表2示出了LTPO技术中不同尺寸驱动晶体管DT在不同亮度下所需的数据信号电压，以及LPTS(像素驱动电路中的晶体管均为低温多晶体硅晶体管)技术中不同尺寸驱动晶体管DT在不同亮度下所需的数据信号电压。其中，DT尺寸表示驱动晶体管DT沟道区的宽长比；I表示驱动晶体管的输出电流；Vdata表示数据信号电压；R255(超亮)、R255(户外)、R255(室内)、R0表示红色像素单元的不同亮度；G255(超亮)、G255(户外)、G255(室内)、G0表示绿色像素单元的不同 亮度；B255(超亮)、B255(户外)、B255(室内)、B0表示蓝色像素单元的不同亮度；DR表示驱动电压区间，即最大亮度下数据信号电压与最低亮度下数据信号电压之差。
表2
Figure PCTCN2020124163-appb-000002
Figure PCTCN2020124163-appb-000003
通过表2可以看出，在相同尺寸、相同亮度状态下，LTPO技术中驱动晶体管DT所需的数据信号电压大于LTPS技术中驱动晶体管所需的数据信号电压。该表验证了LTPO技术中第二晶体管会在补偿阶段结束后会拉低驱动晶体管栅极电压，从而使得像素单元在显示相同亮度下，需要更高的数据信号电压。现有技术中，源极驱动电路输出电压的极限值为6V，从表2可以看出在LTPO技术中，亮度为R0(即不发光)时，驱动晶体管所需的数据信号电压已经大于6V，从而LTPO技术形成显示面板无法正常处于R0亮度。
结合表1、表2可以看出，当寄生电容C为5fF时，第一栅线可以对第一导电部上拉0.5V，从而可以使得在TPO技术中，亮度为R0(即不发光)时，驱动晶体管所需数据信号电压在6V以内。
此外，通过该表2可以看出，R像素单元、G像素单元、B像素单元具有不同的驱动电压区间。源极驱动电路需要向R像素单元、G像素单元、B像素单元提供不同驱动电压区间的数据信号，源极驱动电路需要在不同驱动电压区间之间切换，因而源极驱动电路需要消耗更大功率。本示例性实施例中，所述阵列基板可以包括：R像素驱动电路、G像素驱动电路、B像素驱动电路；R像素驱动电路中驱动晶体管沟道区的宽长比、G像素驱动电路中驱动晶体管沟道区的宽长比以及G像素驱动电路中驱动晶体管沟道区的宽长比不全相同。即在R像素驱动电路、G像素驱动电路、B像素驱动电路中，至少有一种像素驱动电路中驱动晶体管沟道区的宽长比不等于其他种像素驱动电路中驱动晶体管沟道区的宽长比。例如，R像素驱动电路中驱动晶体管沟道区的宽长比可以为3.5/40，B像素驱动电路中驱动晶体管沟道区的宽长比可以为3.5/25。结合表2可以看出，相较于R像素驱动电路中驱动晶体管的沟道区、G像素驱动电路中驱动晶体管的沟道区、R像素驱动电路中驱动晶体管的沟道区具有相同的宽长比，该设置可以降低R像素单元、G像素单元、B像素单元之间驱动电压的差异，从而可以降低源极驱动电路的功率消耗。
如图8、19所示，B像素单元中驱动晶体管沟道区为“Z”型，R像素单元中驱动晶体管沟道区和G像素单元中驱动晶体管沟道区为“S”型。B像素单元中驱动晶体管沟道区的宽长比小于R像素单元中驱动晶体管沟道区的宽长比和G像素单元中驱动晶体管沟道的区宽长比。
本示例性实施例还提供一种显示装置，其中，所述显示装置可以包括上述的阵列基板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性远离并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (25)

  1. 一种阵列基板，其中，所述阵列基板包括像素驱动电路和数据线，所述像素驱动电路包括驱动晶体管、连接于所述驱动晶体管第一极和所述数据线之间的第一晶体管、以及连接于所述驱动晶体管栅极和第二电极之间的第二晶体管，所述驱动晶体管和所述第一晶体管为P型晶体管，所述第二晶体管为N型晶体管，所述阵列基板还包括：
    衬底基板；
    第一导电层，设置于所述衬底基板的一侧，所述第一导电层包括：
    第一导电部，用于形成所述驱动晶体管的栅极；
    第一栅线，位于所述第一导电部的一侧，部分所述第一栅线用于形成所述第一晶体管的栅极；
    第二栅线，位于所述第一栅线远离所述第一导电部的一侧，部分所述第二栅线用于形成所述第二晶体管的第一栅极。
  2. 根据权利要求1所述的阵列基板，其中，所述第一栅线位于所述第一导电部在第一方向上的一侧，且沿第二方向延伸，所述第一方向和所述第二方向相交，所述第一栅线包括：
    第一延伸部，所述第一延伸部在所述衬底基板的正投影与至少部分所述第一导电部在所述衬底基板的正投影在所述第一方向上相对；
    第二延伸部，所述第二延伸部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影在所述第一方向相错。
  3. 根据权利要求2所述的阵列基板，其中，所述第一延伸部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影在所述第一方向上的距离小于所述第二延伸部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影在所述第一方向上的距离。
  4. 根据权利要求3所述的阵列基板，其中，所述第一延伸部包括面向所述第一导电部一侧的第三边沿，所述第一导电部包括面向所述第一延伸部一侧的第四边沿，所述第三边沿在所述衬底基板的正投影在所述第二方向上的尺寸等于所述第四边沿在所述衬底基板的正投影在所述第二方向的尺寸。
  5. 根据权利要求3所述的阵列基板，其中，至少部分所述第二延伸部用于形成所述第一晶体管的栅极。
  6. 根据权利要求3所述的阵列基板，其中，
    所述阵列基板包括多个所述像素驱动电路，所述第一导电层包括沿所述第二 方向间隔分布的多个所述第一导电部，多个所述第一导电部用于分别形成不同像素驱动电路中驱动晶体管的栅极；
    所述第一栅线包括：
    多个所述第一延伸部，所述第一延伸部与所述第一导电部一一对应设置，所述第一延伸部在所述衬底基板的正投影和与其对应的所述第一导电部的至少部分在所述衬底基板的正投影在所述第一方向上相对；
    多个所述第二延伸部，连接于相邻所述第一延伸部之间。
  7. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括：
    第二导电层，设置于所述第一导电层背离所述衬底基板的一侧，所述第二导电层包括：
    第二导电部，所述第二导电部在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影至少部分重合，且通过过孔与所述第一导电部电连接；
    第三导电部，用于形成所述第二晶体管的第一极，所述第一栅线在所述衬底基板的正投影位于所述第二导电部在所述衬底基板的正投影和第三导电部在所述衬底基板的正投影之间；
    第一导电线，连接于所述第二导电部和所述第三导电部之间，所述第一导电线在所述衬底基板的正投影与所述第一栅线在所述衬底基板的正投影相交。
  8. 根据权利要求7所述的阵列基板，其中，所述第二导电层还包括：
    第四导电部，连接所述第一导电线，所述第四导电部在所述衬底基板的正投影与所述第一栅线在所述衬底基板的正投影至少部分重合；
    其中，所述第四导电部包括第一边沿，所述第一导电线包括与所述第四导电部第一边沿连接的第二边沿，所述第一边沿在所述衬底基板的正投影与所述第二边沿在所述衬底基板的正投影的夹角小于180度。
  9. 根据权利要求8所述的阵列基板，其中，所述第四导电部在所述衬底基板的正投影与所述第一延伸部在所述衬底基板的正投影至少部分重合。
  10. 根据权利要求7所述的阵列基板，其中，所述第二栅线在所述衬底基板的正投影位于所述第一栅线在所述衬底基板的正投影和第三导电部在所述衬底基板的正投影之间；
    所述第二栅线包括沿所述第二方向依次交替连接的第三延伸部和第四延伸部，其中所述第三延伸部在所述衬底基板的正投影在所述第一方向上的尺寸小于所述第四延伸部在所述衬底基板的正投影在所述第一方向上的尺寸；
    所述第一导电线在所述衬底基板的正投影与所述第三延伸部在所述衬底基板 的正投影相交。
  11. 根据权利要求10所述的阵列基板，其中，部分所述第四延伸部用于形成所述第二晶体管的第一栅极。
  12. 根据权利要求7所述的阵列基板，其中，所述第二导电层还包括：
    电源线，沿所述第一方向延伸；
    所述阵列基板还包括：
    第三导电层，设置于所述第二导电层背离所述衬底基板的一侧。
  13. 根据权利要求12所述的阵列基板，其中，所述电源线包括第五延伸部，所述第五延伸部在所述衬底基板的正投影与至少部分所述第一导电部在所述衬底基板的正投影在所述第二方向上相对，所述第三导电层包括：
    所述数据线，沿所述第一方向延伸，且部分所述数据线在所述衬底基板的正投影位于所述第五延伸部在所述衬底基板的正投影上。
  14. 根据权利要求12所述的阵列基板，其中，所述第三导电层包括：
    第五导电部，通过过孔连接所述电源线，所述第五导电部在所述衬底基板的正投影覆盖所述第一导电部在所述衬底基板的正投影，且所述第五导电部在所述衬底基板的正投影覆盖所述第二导电部在所述衬底基板的正投影。
  15. 根据权利要求12所述的阵列基板，其中，所述阵列基板还包括第三晶体管，所述第三晶体管第一极连接所述驱动晶体管的栅极，所述第二晶体管和所述第三晶体管均为N型金属氧化物晶体管，
    所述第一导电层还包括：
    第三栅线，位于所述第二栅线远离所述第一导电部的一侧，且沿所述第二方向延伸，部分所述第三栅线用于形成所述第三晶体管的栅极；
    所述第三导电层还包括：
    第五导电部，通过过孔连接所述电源线，所述第五导电部在所述衬底基板的正投影覆盖所述第二晶体管和所述第三晶体管在所述衬底基板的正投影。
  16. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括：R像素驱动电路、G像素驱动电路、B像素驱动电路；
    其中，R像素驱动电路中驱动晶体管沟道区的宽长比、G像素驱动电路中驱动晶体管沟道区的宽长比以及G像素驱动电路中驱动晶体管沟道区的宽长比不全相同。
  17. 根据权利要求16所述的阵列基板，其中，R像素驱动电路中驱动晶体管沟道区的宽长比等于G像素驱动电路中驱动晶体管沟道区的宽长比，且R像素驱 动电路中驱动晶体管沟道区的宽长比小于R像素驱动电路中驱动晶体管沟道区的宽长比。
  18. 根据权利要求17所述的阵列基板，其中，R像素驱动电路中驱动晶体管沟道区的宽长比为3.5/40，B像素驱动电路中驱动晶体管沟道区的宽长比为3.5/25。
  19. 根据权利要求7所述的阵列基板，其中，所述阵列基板还包括：
    第四导电层，层叠于所述第一导电层和第二导电层之间，所述第四导电层包括：
    第四栅线，沿所述第二方向延伸，所述第一栅线在所述衬底基板的正投影位于所述第一导电部在所述衬底基板的正投影和所述第四栅线在所述衬底基板的正投影之间，部分所述第四栅线用于形成所述第二晶体管的第二栅极。
  20. 根据权利要求19所述的阵列基板，其中，所述第四栅线包括沿所述第二方向依次交替连接的第六延伸部和第七延伸部；
    其中，所述第六延伸部在所述衬底基板的正投影在所述第一方向上的尺寸小于所述第七延伸部在所述衬底基板的正投影在所述第一方向上的尺寸；
    所述第一导电线在所述衬底基板的正投影与所述第六延伸部在所述衬底基板的正投影相交。
  21. 根据权利要求20所述的阵列基板，其中，部分所述第七延伸部用于形成所述第二晶体管的第二栅极。
  22. 根据权利要求19所述的阵列基板，其中，所述阵列基板还包括：
    第一有源层，层叠于所述衬底基板和所述第一导电层之间，部分所述第一有源层用于形成所述驱动晶体管的沟道区；
    第二有源层，层叠于所述第四导电层和所述第一导电层之间，部分所述第二有源层用于形成所述第二晶体管的沟道区。
  23. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：使能信号线、初始信号线、阳极层、第一复位信号线、第二复位信号线、电源线，所述像素驱动电路还包括：
    第三晶体管，第一极连接所述驱动晶体管的栅极，第二极连接所述初始信号线，栅极连接所述第二复位信号线；
    第四晶体管，第一极连接所述电源线，第二极连接所述驱动晶体管的第一极，栅极连接所述使能信号线；
    第五晶体管，第一极连接所述驱动晶体管的第二极，第二极连接所述阳极层，栅极连接所述使能信号线；
    第六晶体管，第一极连接所述第五晶体管的第二极，第二极连接所述初始信号线，栅极连接所述第一复位信号线；
    电容，连接于所述驱动晶体管栅极和所述电源线之间。
  24. 根据权利要求23所述的阵列基板，其中，所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管为P型低温多晶硅晶体管。
  25. 一种显示装置，其中，所述显示装置包括权利要求要求1-24任一项所述的阵列基板。
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