WO2021016946A1 - 显示基板及其制备方法、显示面板、显示装置 - Google Patents

显示基板及其制备方法、显示面板、显示装置 Download PDF

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Publication number
WO2021016946A1
WO2021016946A1 PCT/CN2019/098707 CN2019098707W WO2021016946A1 WO 2021016946 A1 WO2021016946 A1 WO 2021016946A1 CN 2019098707 W CN2019098707 W CN 2019098707W WO 2021016946 A1 WO2021016946 A1 WO 2021016946A1
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WIPO (PCT)
Prior art keywords
pixel
light
sub
circuit
electrode block
Prior art date
Application number
PCT/CN2019/098707
Other languages
English (en)
French (fr)
Inventor
刘利宾
李梅
王红丽
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to AU2019279968A priority Critical patent/AU2019279968C1/en
Priority to BR112020000234A priority patent/BR112020000234A2/pt
Priority to PCT/CN2019/098707 priority patent/WO2021016946A1/zh
Priority to RU2020100067A priority patent/RU2728834C1/ru
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to MX2020000329A priority patent/MX2020000329A/es
Priority to EP19933238.8A priority patent/EP4006983A4/en
Priority to JP2019569438A priority patent/JP7420560B2/ja
Priority to CN201980001215.6A priority patent/CN112673475A/zh
Priority to US16/958,480 priority patent/US11735108B2/en
Priority to US16/600,316 priority patent/US11264430B2/en
Priority to TW108145836A priority patent/TWI730543B/zh
Publication of WO2021016946A1 publication Critical patent/WO2021016946A1/zh
Priority to AU2021203983A priority patent/AU2021203983B2/en
Priority to US18/295,284 priority patent/US11908410B2/en
Priority to US18/581,023 priority patent/US20240194141A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape

Definitions

  • the embodiments of the present disclosure relate to a display substrate and a preparation method thereof, a display panel, and a display device.
  • AMOLED active-matrix organic light-emitting diode
  • At least some embodiments of the present disclosure provide a display substrate including a base substrate and a plurality of repeating units provided on the base substrate, each of the repeating units includes a plurality of sub-pixels, and each of the sub-pixels includes a light emitting An element and a pixel circuit for driving the light-emitting element to emit light
  • the pixel circuit includes a driving circuit
  • the light-emitting element includes a first light-emitting voltage application electrode, a second light-emitting voltage application electrode, and a pixel circuit provided on the first light-emitting voltage application electrode and
  • the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the color of light emitted by the light-emitting element of the first sub-pixel and the second sub-pixel
  • the colors of the light emitted by the light-emitting elements of the pixels are the same, and the shape of the first light-
  • the area of the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel on the base substrate and the area of the orthographic projection of the second sub-pixel are The area of the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element on the base substrate is different.
  • the orthographic projection of the control terminal of the driving circuit of the pixel circuit of the first sub-pixel on the base substrate and the light-emitting element of the first sub-pixel are
  • the area of the overlapping portion of the orthographic projection of the first light-emitting voltage application electrode on the base substrate is the first area
  • the control terminal of the driving circuit of the pixel circuit of the second sub-pixel is on the base substrate.
  • the area of the overlapped portion of the projection and the orthographic projection of the first light-emitting voltage applying electrode of the second sub-pixel light-emitting element on the base substrate is the second area
  • the first area and the second area are The ratio satisfies the following relationship:
  • A1 represents the first area
  • A2 represents the second area
  • Amin represents the minimum ratio threshold and is 90%
  • Amax represents the maximum ratio threshold and is 110%.
  • the orthographic projection of the control terminal of the driving circuit of the pixel circuit of the first sub-pixel on the base substrate is located on the light-emitting element of the first sub-pixel.
  • the first light-emitting voltage application electrode is in the orthographic projection on the base substrate;
  • the orthographic projection of the control terminal of the driving circuit of the pixel circuit of the second sub-pixel on the base substrate is located in the second sub-pixel.
  • the first light-emitting voltage application electrode of the light-emitting element is in an orthographic projection on the base substrate.
  • the orthographic projection of the light-emitting layer of the light-emitting element of the first sub-pixel on the base substrate is in line with the light-emitting layer of the light-emitting element of the second sub-pixel.
  • the orthographic projection on the base substrate is continuous.
  • the pixel circuit further includes a first light-emitting control circuit and a second light-emitting control circuit
  • the driving circuit includes a control terminal, a first terminal, and a second terminal.
  • the first light-emitting control circuit is connected to the first terminal and the first voltage terminal of the driving circuit, and is configured to implement the driving circuit
  • the connection with the first voltage terminal is turned on or off
  • the second light emitting control circuit is electrically connected to the second terminal of the driving circuit and the first light emitting voltage applying electrode of the light emitting element, and is It is configured to realize that the connection between the driving circuit and the light-emitting element is turned on or off.
  • the pixel circuit of the first sub-pixel further includes a first parasitic circuit
  • the pixel circuit of the second sub-pixel further includes a second parasitic circuit.
  • the parasitic circuit is electrically connected to the control terminal of the driving circuit of the pixel circuit of the first sub-pixel and the first light-emitting voltage applying electrode of the light-emitting element of the first sub-pixel, and is configured to be based on the The voltage of the first light-emitting voltage applying electrode of the light-emitting element controls the voltage of the control terminal of the driving circuit of the pixel circuit of the first sub-pixel, and the control of the second parasitic circuit and the driving circuit of the pixel circuit of the second sub-pixel
  • the terminal is electrically connected to the first light-emitting voltage applying electrode of the light-emitting element of the second sub-pixel, and is configured to control the second sub-pixel based on the voltage of the first light-emitting voltage applying electrode of the light-emitting element of the second
  • the first parasitic circuit includes a first capacitor
  • the first capacitor includes a first pole and a second pole
  • a light-emitting voltage applying electrode includes an auxiliary electrode block, the orthographic projection of the auxiliary electrode block on the base substrate and the control end of the driving circuit of the pixel circuit of the first sub-pixel are on the base substrate.
  • the projections overlap at least partially, the auxiliary electrode block serves as the first pole of the first capacitor, and the control terminal of the driving circuit of the first sub-pixel is multiplexed as the second pole of the first capacitor.
  • the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel further includes a first driving electrode block, the first driving electrode block and the auxiliary electrode Blocks are electrically connected, the orthographic projection of the first drive electrode block on the base substrate, the orthographic projection of the light-emitting layer of the first sub-pixel on the base substrate and the first sub-pixel
  • the orthographic projection of the second light-emitting voltage applying electrode of the light-emitting element of the pixel on the base substrate at least partially overlaps.
  • the second parasitic circuit includes a second capacitor
  • the second capacitor includes a first pole and a second pole
  • a light-emitting voltage application electrode includes a second drive electrode block
  • the orthographic projection of the second drive electrode block on the base substrate and the control end of the drive circuit of the second sub-pixel pixel circuit are on the substrate
  • the orthographic projection on the substrate at least partially overlaps, the orthographic projection of the second drive electrode block on the base substrate, the orthographic projection of the light-emitting layer of the second sub-pixel light-emitting element on the base substrate, and
  • the orthographic projection of the second light-emitting voltage applying electrode of the light-emitting element of the second sub-pixel on the base substrate at least partially overlaps
  • the second driving electrode block is multiplexed as the first electrode of the second capacitor
  • the control terminal of the driving circuit of the second sub-pixel is multiplexed as the second pole of the second capacitor.
  • the shape of the first driving electrode block is the same as the shape of the second driving electrode block, and the first driving electrode block is on the base substrate.
  • the area of the orthographic projection is the same as the area of the orthographic projection of the second driving electrode block on the base substrate.
  • the first sub-pixel and the second sub-pixel are arranged along a first direction, and the first direction is parallel to all
  • the auxiliary electrode block is located on a side of the first driving electrode block away from the light-emitting element of the second sub-pixel.
  • the orthographic projection of the auxiliary electrode block on the base substrate and the light-emitting layer of the light-emitting element of the first sub-pixel on the base substrate do not overlap.
  • the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel further includes a first connecting electrode block, and in the first direction, the first The connecting electrode block is located on a side of the first driving electrode block away from the light emitting element of the second sub-pixel, and the first connecting electrode block is located between the auxiliary electrode block and the first driving electrode block, And it is electrically connected with the auxiliary electrode block and the first driving electrode block.
  • the display substrate provided by some embodiments of the present disclosure further includes an intermediate layer.
  • the pixel circuit is located between the intermediate layer and the base substrate.
  • the light emitting element is located on the side of the intermediate layer away from the base substrate, the intermediate layer includes a first via hole, and the first connecting electrode block extends to the first via hole and passes through the first via hole.
  • the hole is electrically connected to the pixel circuit of the first sub-pixel.
  • the first light-emitting voltage applying electrode of the light-emitting element of the second sub-pixel further includes a second connecting electrode block, and the second connecting electrode block is connected to the second The driving electrode block is electrically connected, and in the first direction, the second connecting electrode block is located on a side of the second driving electrode block away from the light emitting element of the first sub-pixel.
  • the intermediate layer includes a second via hole
  • the second connection electrode block extends to the second via hole and passes through the second via hole and the The pixel circuit of the second sub-pixel is electrically connected.
  • the first connecting electrode block is electrically connected to the second light-emitting control circuit of the pixel circuit of the first sub-pixel through the first via hole, and the first The two connecting electrode blocks are electrically connected to the second light-emitting control circuit of the pixel circuit of the second sub-pixel through the second via hole.
  • the pixel circuit includes an active semiconductor layer, a gate metal layer, and a source and drain metal layer.
  • the pixel circuit includes The source semiconductor layer is located between the base substrate and the gate metal layer, the gate metal layer is located between the active semiconductor layer and the source and drain metal layers, and the first connecting electrode block It extends to the source and drain metal layer of the pixel circuit through the first via hole, and the second connection electrode block extends to the source and drain metal layer of the pixel circuit through the second via hole.
  • the plurality of sub-pixels further includes a third sub-pixel and a fourth sub-pixel, and in each repeating unit, the third sub-pixel and the second sub-pixel
  • the four sub-pixels are arranged along a second direction, and in the second direction, the first sub-pixel and the second sub-pixel are located between the third sub-pixel and the fourth sub-pixel, the The second direction is parallel to the surface of the base substrate, and the first direction and the second direction are perpendicular to each other.
  • the first light-emitting voltage applying electrode of the light-emitting element of the third sub-pixel includes a third driving electrode block and a third connecting electrode block that are electrically connected to each other.
  • the first light-emitting voltage application electrode of the light-emitting element of the four sub-pixels includes a fourth drive electrode block and a fourth connection electrode block that are electrically connected to each other, the intermediate layer includes a third via hole and a fourth via hole, and the third connection The electrode block extends to the third via hole and is electrically connected to the pixel circuit of the third sub-pixel through the third via hole, and the fourth connection electrode block extends to the fourth via hole and passes through the The fourth via hole is electrically connected to the pixel circuit of the fourth sub-pixel.
  • the third connection electrode in each repeating unit, in the first direction, is located at a distance from the auxiliary driving electrode block to the third driving electrode block.
  • the third connecting electrode On one side of the electrode block, in the second direction, is located on the side of the third drive electrode block close to the fourth drive electrode block, and in the first direction, The fourth connecting electrode is located on a side of the fourth driving electrode block away from the auxiliary electrode block. In the second direction, the fourth connecting electrode is located near the fourth driving electrode block.
  • the third connecting electrode block is electrically connected to the second light-emitting control circuit of the pixel circuit of the third sub-pixel through the third via hole
  • the first The four-connection electrode block is electrically connected to the second light-emitting control circuit of the pixel circuit of the fourth sub-pixel through the fourth via hole.
  • the plurality of repeating units are arranged in a second direction to form a plurality of repeating unit groups, and the plurality of repeating unit groups are arranged in the first direction.
  • the first connection electrode block, the second connection electrode block, the third connection electrode block, and the fourth connection electrode block are located between two adjacent repeating unit groups.
  • at least a part of the auxiliary electrode block is located on the side of the auxiliary electrode block away from the first driving electrode block and adjacent to the repeating unit group where the auxiliary electrode block is located Between two adjacent repeating units in.
  • the first subpixel and the second subpixel are both green subpixels
  • the third subpixel is a red subpixel
  • the fourth subpixel is It is a blue sub-pixel.
  • the pixel circuit further includes a data writing circuit, a storage circuit, a threshold compensation circuit, and a reset circuit.
  • the data writing circuit is connected to the first terminal of the driving circuit. Are electrically connected and configured to write data signals into the storage circuit under the control of the scan signal;
  • the storage circuit is electrically connected to the control terminal of the drive circuit and the first voltage terminal, and is configured to store The data signal;
  • the threshold compensation circuit is electrically connected to the control terminal and the second terminal of the drive circuit, and is configured to perform threshold compensation on the drive circuit;
  • the reset circuit and the control terminal of the drive circuit It is electrically connected to the first light-emitting voltage application electrode of the light-emitting element, and is configured to reset the control terminal of the drive circuit and the first light-emitting voltage application electrode of the light-emitting element under the control of a reset control signal.
  • the driving circuit includes a driving transistor, the control terminal of the driving circuit includes the gate of the driving transistor, and the first terminal of the driving circuit includes the driving transistor.
  • the reset circuit includes a first reset transistor and a second reset transistor, the first light emission control circuit includes a first light emission control transistor, the second light emission control circuit includes a second light emission control transistor, the The reset control signal includes a first sub-reset control signal and a second sub-reset control signal, the first pole of the data writing transistor is electrically connected to the first pole of the driving transistor, and the second pole of the data writing transistor Is configured to receive the data signal, the gate of the data writing transistor is configured to receive the scan signal; the first pole of the third capacitor is electrically connected to the first power terminal, and the third
  • the gate of the transistor is electrically connected, and the gate of the threshold compensation transistor is configured to receive a compensation control signal; the first electrode of the first reset transistor is configured to receive a first reset signal, and the first electrode of the first reset transistor is configured to receive a first reset signal.
  • the two poles are electrically connected to the gate of the driving transistor, the gate of the first reset transistor is configured to receive the first sub-reset control signal; the first pole of the second reset transistor is configured to receive the first Two reset signals, the second electrode of the second reset transistor is electrically connected to the first light-emitting voltage application electrode of the light-emitting element, and the gate of the second reset transistor is configured to receive the second sub-reset control signal
  • the first pole of the first light emission control transistor is electrically connected to the first power supply terminal, the second pole of the first light emission control transistor is electrically connected to the first electrode of the drive transistor, and the first light emission
  • the gate of the control transistor is configured to receive a first light emission control signal, the first electrode of the second light emission control transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second light emission control transistor is electrically connected to The first light-emitting voltage applying electrode of the light-emitting element is electrically connected, and the gate of the second light-emitting control transistor is configured
  • Some embodiments of the present disclosure also provide a display panel including the display substrate according to any one of the above.
  • Some embodiments of the present disclosure further provide a display device including the display panel according to any one of the above.
  • the display device provided by some embodiments of the present disclosure further includes: a driving chip that is electrically connected to the display panel, and the driving chip is located far from the first sub-pixel in each repeating unit. Two sub-pixels on one side.
  • the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel on the base substrate is The area is larger than the area of the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel on the base substrate.
  • Some embodiments of the present disclosure further provide a preparation method for preparing the display substrate according to any one of the above, including: providing the base substrate, and forming the multiple repeating units on the base substrate, wherein, each of the repeating units includes a plurality of sub-pixels, each of the sub-pixels includes a pixel circuit and a light-emitting element, and the light-emitting element includes a first light-emitting voltage applying electrode, a second light-emitting voltage applying electrode, and A light-emitting layer between a light-emitting voltage applying electrode and the second light-emitting voltage applying electrode, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, and the color of the light emitted by the light-emitting element of the first sub-pixel The same color as the light emitted by the light-emitting element of the second sub-pixel, the shape of the first light-emitting voltage applying electrode of the light-emitting element of the first sub-pixel and the first
  • the orthographic projection on the base substrate at least partially overlaps, and the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel on the base substrate is identical to that of the pixel circuit of the second sub-pixel.
  • the orthographic projection of the control terminal of the driving circuit on the base substrate at least partially overlaps.
  • Some embodiments of the present disclosure also provide a display substrate, including a base substrate and a plurality of repeating units arranged on the base substrate, each of the repeating units includes a plurality of sub-pixels, and each of the sub-pixels includes a light emitting An element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit includes a driving circuit, the light-emitting element includes a first light-emitting voltage application electrode, a second light-emitting voltage application electrode, and a pixel circuit provided on the first light-emitting voltage application electrode and The light-emitting layer between the second light-emitting voltage applying electrodes, the driving circuits of the plurality of sub-pixels are arranged in an array on the base substrate, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, so The color of the light emitted by the light-emitting element of the first sub-pixel is the same as the color of the light emitted by the light-
  • the shape of the first driving electrode block is different from the shape of the auxiliary electrode block, and the shape of the first driving electrode block is different from the shape of the second driving electrode block.
  • the shapes of the blocks are the same, and the area of the orthographic projection of the first driving electrode block on the base substrate is the same as the area of the orthographic projection of the second driving electrode block on the base substrate.
  • the shape of the first connection electrode block is the same as the shape of the second connection electrode block, and the first connection electrode block is on the base substrate.
  • the area of the orthographic projection is the same as the area of the orthographic projection of the second connection electrode block on the base substrate.
  • the control terminal of the driving circuit of the pixel circuit of the first sub-pixel and the control terminal of the driving circuit of the pixel circuit of the second sub-pixel are arranged along the first direction.
  • the first drive electrode block is located at one of the control ends of the drive circuit of the pixel circuit of the first sub-pixel close to the control end of the drive circuit of the second sub-pixel. side.
  • the first driving electrode block in the first direction, is located at the control end of the driving circuit of the pixel circuit of the first sub-pixel and the second Between the control terminals of the drive circuit of the pixel circuit of the sub-pixel.
  • the first connecting electrode block is located on the first driving electrode block away from the pixel circuit of the second sub-pixel.
  • One side of the control end of the circuit is located on the first driving electrode block away from the pixel circuit of the second sub-pixel.
  • the first connecting electrode block is located at the control end of the driving circuit of the pixel circuit of the first sub-pixel and the second Between the control terminals of the drive circuit of the pixel circuit of the sub-pixel.
  • the first connection electrode block is located between the first driving electrode block and the auxiliary electrode block.
  • the second connecting electrode block is located at a distance from the control end of the driving circuit of the second sub-pixel pixel circuit.
  • the second driving electrode block is located between the second connecting electrode block and the first driving electrode block.
  • the distance between the center of the control terminal of the driving circuit of the pixel circuit of the first sub-pixel and the center of the first driving electrode block is greater than that of the second sub-pixel.
  • the distance between the center of the control terminal of the driving circuit of the pixel circuit of the pixel and the center of the second driving electrode block is greater than that of the second sub-pixel.
  • Some embodiments of the present disclosure also provide a display substrate, including a base substrate and a plurality of repeating units arranged on the base substrate, each of the repeating units includes a plurality of sub-pixels, and each of the sub-pixels includes a light emitting An element and a pixel circuit for driving the light-emitting element to emit light, the light-emitting element including a first light-emitting voltage applying electrode, a second light-emitting voltage applying electrode, and a first light-emitting voltage applying electrode and a second light-emitting voltage applying electrode
  • the pixel circuit includes a driving circuit, a second light-emitting control circuit, and a reset circuit.
  • the second light-emitting control circuit is electrically connected to a second light-emitting control signal line, a second end of the driving circuit, and a reset circuit.
  • the first light-emitting voltage application electrode of the light-emitting element is configured to realize the connection between the driving circuit and the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control signal line Or disconnected
  • the reset circuit is electrically connected to the control terminal of the drive circuit and the first reset control signal line, and is configured to perform the operation under the control of the first sub-reset control signal provided by the first reset control signal line
  • the control terminal of the driving circuit is reset, the second light emission control signal line and the first reset control signal line are arranged along a first direction, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, The orthographic projection of the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel on the base substrate and the first reset control
  • the orthographic projection on the base substrate and the orthographic projection of the second light-emitting control signal line connected to the second light-emitting control circuit of the pixel circuit of the first sub-pixel on the base substrate at least partially overlap.
  • the orthographic projection of the first light-emitting voltage applying electrode of the light-emitting element of the second sub-pixel on the base substrate and the second light-emitting control signal line connected to the second light-emitting control circuit of the pixel circuit of the second sub-pixel are in The orthographic projections on the base substrate at least partially overlap.
  • the pixel circuit further includes a data writing circuit, and the data writing circuit is electrically connected to the first end of the driving circuit and the first scanning signal line, and Is configured to write a data signal into the control terminal of the driving circuit under the control of the scan signal provided by the first scan signal line, and in the first direction, the first scan signal line is located at the first Between the two light-emitting control signal lines and the first reset control signal line, the first light-emitting voltage applying electrode of the light-emitting element of the first sub-pixel and the first light-emitting voltage applying electrode of the light-emitting element of the second sub-pixel Arranged along the first direction, in the first direction, the first scan signal line connected to the data writing circuit of the pixel circuit of the second sub-pixel is located at the light-emitting element of the first sub-pixel Between the first light-emitting voltage applying electrode and the first light-emitting voltage applying electrode of the light-emitting element of the second sub-pixel
  • the reset circuit is also electrically connected to a first reset power supply signal line, and the reset circuit is configured as a first sub-reset provided by the first reset control signal line. Under the control of the control signal, the control terminal of the driving circuit is reset according to the first reset signal provided by the first reset power signal line.
  • the first reset power signal line is located at the On the side of the first reset control signal line far away from the second light-emitting control signal line, the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel on the base substrate is also consistent with the The orthographic projection of the first reset power signal line connected to the reset circuit of the pixel circuit of the second sub-pixel on the base substrate at least partially overlaps.
  • the second light emitting control signal line, the first reset control signal line, the first scan signal line, and the first reset power signal line are all along The second direction extends, and the second direction and the first direction are perpendicular to each other.
  • the second light emission control signal line, the first reset control signal line, the first scan signal line, and the first reset power signal line are parallel to each other .
  • the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel includes an auxiliary electrode block, a first driving electrode block, and a first connecting electrode block.
  • a driving electrode block, the auxiliary electrode block, and the first connecting electrode block are electrically connected to each other and arranged along the first direction.
  • the first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel includes a first Two driving electrode blocks and a second connecting electrode block.
  • the second driving electrode block and the second connecting electrode block are electrically connected and arranged along the first direction.
  • the first A connecting electrode block and the auxiliary electrode block are both located on a side of the first driving electrode block away from the second driving electrode block, and the first connecting electrode block is located between the auxiliary electrode block and the first driving electrode block.
  • the second connecting electrode block is located on a side of the second driving electrode block away from the first driving electrode block, and the first driving electrode block is on the positive side of the base substrate.
  • the auxiliary electrode block is located in the pixel circuit of the first sub-pixel.
  • a side of the second light-emitting control signal line connected to the second light-emitting control circuit of the second sub-pixel away from the first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel, and the second connection electrode block is on the base substrate
  • the orthographic projection of and the orthographic projection of the second light-emitting control signal line connected to the second light-emitting control circuit of the pixel circuit of the second sub-pixel on the base substrate at least partially overlap, in the first direction
  • the second driving electrode block is located on the second light-emitting control signal line connected to the second light-emitting control circuit of the pixel circuit of the second sub-pixel and connected to the data writing circuit of the pixel circuit of the second sub-pixel. Between the first scan signal lines.
  • the color of the light emitted by the light-emitting element of the first sub-pixel is the same as the color of the light emitted by the light-emitting element of the second sub-pixel, and the first sub-pixel
  • the shape of the first light-emitting voltage applying electrode of the light-emitting element of the pixel and the shape of the first light-emitting voltage applying electrode of the light-emitting element of the second sub-pixel are different.
  • FIG. 1 is a schematic diagram of a structure of a pixel repeating unit in a pixel arrangement structure
  • FIG. 2 is a schematic block diagram of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 3A is a schematic structural diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • 3B is a schematic structural diagram of a pixel circuit of a first sub-pixel provided by some embodiments of the present disclosure
  • 3C is a schematic structural diagram of a second sub-pixel pixel circuit provided by some embodiments of the present disclosure.
  • 4A-4E are schematic diagrams of various layers of a pixel circuit provided by some embodiments of the present disclosure.
  • 5A is a schematic plan view of a display substrate provided by some embodiments of the present disclosure.
  • 5B is a schematic plan view of a repeating unit provided by some embodiments of the present disclosure.
  • 6A is a schematic plan view of another repeating unit provided by some embodiments of the present disclosure.
  • 6B is a layout diagram of a display substrate provided by some embodiments of the present disclosure.
  • 6C is a schematic cross-sectional structure diagram of the line L1-L1' in FIG. 6B;
  • 6D is a schematic cross-sectional structure diagram of the line L2-L2' in FIG. 6B;
  • 6E is a schematic plan view of still another display substrate provided by some embodiments of the present disclosure.
  • FIG. 7 is a schematic diagram of a partial structure of a display panel provided by some embodiments of the present disclosure.
  • FIG. 8A is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • FIG. 8B is a schematic structural diagram of a display device provided by some embodiments of the present disclosure.
  • FIG. 9 is a schematic flowchart of a method for manufacturing a display substrate according to an embodiment of the disclosure.
  • FIG. 1 is a schematic structural diagram of a pixel repeating unit in a pixel arrangement structure.
  • a pixel arrangement structure includes a plurality of pixel repeating units 400, and the plurality of pixel repeating units 400 are arranged in an array along a direction 405 and a direction 406. cloth.
  • Each pixel repeating unit 400 includes a red sub-pixel 401, a blue sub-pixel 402, a first green sub-pixel 403, and a second green sub-pixel 404. As shown in FIG.
  • the red sub-pixel 401 and the blue sub-pixel 402 are arranged along the direction 405, the first green sub-pixel 403 and the second green sub-pixel 404 are arranged along the direction 406, and in the direction 405, the first green sub-pixel 403 and the second green sub-pixel 404 are located between the red sub-pixel 401 and the blue sub-pixel 402.
  • the brightness of the first green sub-pixel 403 and the second green sub-pixel 404 are inconsistent, leading to the problem of missed detection of bright spots, that is, some The green sub-pixel cannot be detected.
  • the brightness of the first green sub-pixel 403 is higher than the brightness of the second green sub-pixel 404, so that the first green sub-pixel 403 is bright and the second green sub-pixel 404 is dark.
  • each sub-pixel there is a parasitic capacitance between the anode of the light-emitting element and the gate of the driving transistor.
  • This parasitic capacitance will affect the light-emitting brightness of the light-emitting element, and the larger the parasitic capacitance, the weaker the light-emitting brightness; the smaller the parasitic capacitance, the light-emitting brightness The stronger.
  • the gate of the driving transistor in the pixel circuit for driving the first green sub-pixel 403 is not blocked by the anode in the light-emitting element of the first green sub-pixel 403
  • the gate of the driving transistor in the pixel circuit for driving the second green sub-pixel 404 is blocked by the anode in the light-emitting element of the second green sub-pixel 404.
  • the parasitic capacitance between the gate of the driving transistor of the sub-pixel 404 and the light-emitting element that is, the parasitic capacitance between the gate of the driving transistor of the first green sub-pixel 403 and the light-emitting element and the parasitic capacitance of the driving transistor of the second green sub-pixel 404
  • the parasitic capacitance between the gate and the light-emitting element which results in a difference in the brightness of the first green sub-pixel 403 and the second green sub-pixel 404 in each repeating unit, which seriously affects the display effect.
  • At least some embodiments of the present disclosure provide a display substrate and a manufacturing method thereof, a display panel, and a display device.
  • the light-emitting element of the first sub-pixel covers the gate of the driving transistor of the first sub-pixel
  • the second sub-pixel covers the gate of the driving transistor of the second sub-pixel, thereby reducing the parasitic capacitance between the light-emitting element of the first sub-pixel and the gate of the driving transistor and the difference between the light-emitting element and the driving transistor of the second sub-pixel.
  • the difference in parasitic capacitance between the gates makes the pixel brightness of the first sub-pixel and the second sub-pixel consistent, thereby improving display uniformity and display effect, and solving the problem of pixel brightness differences of the display panel.
  • the display substrate has a simple structure, is easy to design and manufacture, and has low cost.
  • FIG. 2 is a schematic block diagram of a display substrate provided by some embodiments of the present disclosure
  • FIG. 3A is a plan schematic diagram of a display substrate provided by some embodiments of the present disclosure
  • FIG. 3A is a pixel provided by some embodiments of the present disclosure
  • Fig. 3B is a schematic structural diagram of a pixel circuit of a first sub-pixel according to some embodiments of the present disclosure
  • Fig. 3C is a schematic structural diagram of a pixel circuit of a second sub-pixel according to some embodiments of the disclosure .
  • the display substrate 100 provided by the embodiment of the present disclosure includes a base substrate 10 and a plurality of repeating units 11 arranged on the base substrate 10, and each repeating unit 11 includes a plurality of sub-pixels 12.
  • Each sub-pixel 12 includes a light-emitting element 120 and a pixel circuit 121.
  • the pixel circuit 121 is used to drive the light-emitting element 120 to emit light, and the pixel circuit 121 includes a driving circuit 122.
  • the display substrate 100 may be applied to a display panel, such as an active matrix organic light emitting diode (AMOLED) display panel, etc.
  • the display substrate 100 may be an array substrate.
  • the base substrate 10 may be a suitable substrate such as a glass substrate, a quartz substrate, or a plastic substrate.
  • the light emitting element 120 of each sub-pixel 12 includes a first light emitting voltage applying electrode, a second light emitting voltage applying electrode, and a light emitting layer provided between the first light emitting voltage applying electrode and the second light emitting voltage applying electrode.
  • the plurality of sub-pixels 12 includes a first sub-pixel G1 and a second sub-pixel G2.
  • the pixel circuit 121 further includes a first light emission control circuit 123 and a second light emission control circuit 124.
  • the driving circuit 122 includes a control terminal, a first terminal, and a second terminal, and is configured to provide the light-emitting element 120 with a driving current for driving the light-emitting element 120 to emit light.
  • the first light emission control circuit 123 is connected to the first terminal of the driving circuit 122 and the first voltage terminal VDD, and is configured to realize the on or off the connection between the driving circuit 122 and the first voltage terminal VDD
  • the second The light-emitting control circuit 124 is electrically connected to the second end of the driving circuit 122 and the first light-emitting voltage applying electrode of the light-emitting element 120, and is configured to make the connection between the driving circuit 122 and the light-emitting element 120 on or off.
  • the pixel circuit 121a of the first subpixel G1 further includes a first parasitic circuit 125a
  • the pixel circuit 121b of the second subpixel G2 further includes a second parasitic circuit 125b.
  • the first parasitic circuit 125a is electrically connected to the control terminal of the driving circuit 122a of the pixel circuit 121a of the first sub-pixel G1 and the first light-emitting voltage application electrode of the light-emitting element 120a of the first sub-pixel G1, and is configured to be based on the The voltage of the first light-emitting voltage applying electrode of the light-emitting element 120a of one sub-pixel G1 controls the voltage of the control terminal of the driving circuit 122a of the pixel circuit 121a of the first sub-pixel G1.
  • the second parasitic circuit 125b is electrically connected to the control terminal of the driving circuit of the pixel circuit 121b of the second sub-pixel G2 and the first light-emitting voltage application electrode of the light-emitting element 120b of the second sub-pixel G2, and is configured to be based on the second sub-pixel
  • the voltage of the first light-emitting voltage applying electrode of the light-emitting element 120b of G2 controls the voltage of the control terminal of the driving circuit 122b of the pixel circuit 121b of the second sub-pixel G2.
  • the pixel circuit 121 may also include a parasitic circuit, which is not shown in FIG. 3A.
  • FIG. 3A does not show the first parasitic circuit and the second parasitic circuit in the pixel circuit of the first sub-pixel G1.
  • the pixel circuit 121 further includes a data writing circuit 126, a storage circuit 127, a threshold compensation circuit 128, and a reset circuit 129.
  • the data writing circuit 126 is electrically connected to the first terminal of the driving circuit 122, and is configured to write the data signal into the storage circuit 127 under the control of the scan signal;
  • the storage circuit 127 and the control terminal and the first voltage terminal of the driving circuit 122 VDD is electrically connected and configured to store data signals;
  • the threshold compensation circuit 128 is electrically connected to the control terminal and the second terminal of the drive circuit 122, and is configured to perform threshold compensation on the drive circuit 122;
  • the control terminal is electrically connected to the first light-emitting voltage application electrode of the light-emitting element 120 and is configured to reset the control terminal of the driving circuit 122 and the first light-emitting voltage application electrode of the light-emitting element 120 under the control of the reset control signal.
  • the driving circuit 122 includes a driving transistor T1
  • the control terminal of the driving circuit 122 includes the gate of the driving transistor T1
  • the first terminal of the driving circuit 122 includes the first electrode of the driving transistor T1
  • the The second terminal includes the second terminal of the driving transistor T1.
  • the data writing circuit 126 includes a data writing transistor T2
  • the storage circuit 127 includes a third capacitor C2
  • the threshold compensation circuit 128 includes a threshold compensation transistor T3
  • the first light emission control circuit 123 includes a first light emission control Transistor T4
  • the second light emission control circuit 124 includes a second light emission control transistor T5
  • the reset circuit 129 includes a first reset transistor T6 and a second reset transistor T7
  • the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.
  • the first pole of the data writing transistor T2 is electrically connected to the first pole of the driving transistor T1, and the second pole of the data writing transistor T2 is configured to be electrically connected to the data line Vd to receive the data signal.
  • the gate of the data writing transistor T2 is configured to be electrically connected to the first scan signal line Ga1 to receive the scan signal; the first pole of the third capacitor C2 is electrically connected to the first power terminal VDD, and the second electrode of the third capacitor C2
  • the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the threshold value is compensated.
  • the gate of the transistor T3 is configured to be electrically connected to the second scan signal line Ga2 to receive the compensation control signal;
  • the first electrode of the first reset transistor T6 is configured to be electrically connected to the first reset power terminal Vinit1 to receive the first reset signal ,
  • the second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1, and the gate of the first reset transistor T6 is configured to be electrically connected to the first reset control signal line Rst1 to receive the first sub-reset control signal;
  • the first electrode of the second reset transistor T7 is configured to be electrically connected to the second reset power terminal Vinit2 to receive the second reset signal, and the second electrode of the second reset transistor T7 is electrically connected to the first light-emitting voltage application electrode of the light-emitting element 120 ,
  • the gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Rst2 to receive the second sub-reset control signal;
  • the first pole of the first light emission control transistor T4 is
  • the first parasitic circuit 125a includes a first capacitor C11, and the first capacitor C11 includes a first pole CC3a and a second pole CC4a.
  • the first electrode CC3a of the first capacitor C11 is electrically connected to the first light-emitting voltage application electrode of the light-emitting element 120a of the first sub-pixel G1, and the second electrode CC4a of the first capacitor C11 is driven by the pixel circuit 121a of the first sub-pixel G1
  • the gate of the transistor T1 is electrically connected.
  • the second parasitic circuit 125b includes a second capacitor C12, and the second capacitor C12 includes a first pole and a second pole.
  • the first electrode of the second capacitor C12 is electrically connected to the first light-emitting voltage applying electrode of the light-emitting element 120b of the second sub-pixel G2, and the second electrode of the second capacitor C12 is connected to the driving transistor T1 of the pixel circuit 121b of the second sub-pixel G2.
  • the grid is electrically connected.
  • the capacitance value of the first capacitor C11 and the capacitance value of the second capacitor C12 can be the same, so that the pixel brightness of the first sub-pixel G1 and the second sub-pixel G2 can be consistent, and the display uniformity and display effect can be improved.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power terminal VSS may be a voltage source to output a constant first voltage.
  • Two voltages, the second voltage is a negative voltage, etc.
  • the second power terminal VSS may be grounded.
  • the pixel circuit 121a of the first sub-pixel G1 further includes a data writing circuit 126a, a storage circuit 127a, a threshold compensation circuit 128a, and a reset circuit 129a;
  • the pixel circuit 121b of the second sub-pixel G2 further includes a data writing circuit 126b, a storage circuit 127b, a threshold compensation circuit 128b, and a reset circuit 129b.
  • the connection relationship and function of each element in the pixel circuit 121a of the first sub-pixel G1 and the pixel circuit 121b of the second sub-pixel G2 are similar to the example described in FIG. 3A above, and the repetition is This will not be repeated here.
  • the scan signal and the compensation control signal may be the same, that is, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may be electrically connected to the same signal line, such as the first scan signal line Ga1 is used to receive the same signal (for example, a scan signal).
  • the display substrate 100 may not be provided with the second scan signal line Ga2 to reduce the number of signal lines.
  • the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may also be electrically connected to different signal lines, that is, the gate of the data writing transistor T2 is electrically connected to the first scanning signal line Ga1, and the threshold The gate of the compensation transistor T3 is electrically connected to the second scan signal line Ga2, and the first scan signal line Ga1 and the second scan signal line Ga2 transmit the same signal.
  • the scan signal and the compensation control signal may also be different, so that the gate of the data writing transistor T2 and the threshold compensation transistor T3 can be controlled separately, which increases the flexibility of controlling the pixel circuit.
  • the first light emission control signal and the second light emission control signal can be the same, that is, the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 can be electrically connected to the same One signal line, such as the first light emission control signal line EM1, to receive the same signal (for example, the first light emission control signal).
  • the display substrate 100 may not be provided with the second light emission control signal line EM2 to reduce the number of signal lines .
  • the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 may also be electrically connected to different signal lines, that is, the gate of the first light emission control transistor T4 is electrically connected to the first light emission.
  • Control signal line EM1 the gate of the second light emission control transistor T5 is electrically connected to the second light emission control signal line EM2, and the first light emission control signal line EM1 and the second light emission control signal line EM2 transmit the same signal.
  • first light emission control transistor T4 and the second light emission control transistor T5 are different types of transistors, for example, the first light emission control transistor T4 is a P-type transistor and the second light emission control transistor T5 is an N-type transistor
  • first light-emitting control signal and the second light-emitting control signal may also be different, which is not limited in the embodiment of the present disclosure.
  • the first reset control signal and the second reset control signal may be the same, that is, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may be electrically connected to the same signal line, for example, the first reset The signal line Rst1 is controlled to receive the same signal (for example, the first sub-reset control signal). At this time, the display substrate 100 may not be provided with the second reset control signal line Rst2 to reduce the number of signal lines.
  • the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may also be electrically connected to different signal lines, that is, the gate of the first reset transistor T6 is electrically connected to the first reset control signal line Rst1 , The gate of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2, and the first reset control signal line Rst1 and the second reset control signal line Rst2 transmit the same signal.
  • the first sub-reset control signal and the second sub-reset control signal may also be different.
  • the second sub-reset control signal may be the same as the scan signal, that is, the gate of the second reset transistor T7 may be electrically connected to the first scan signal line Ga1 to receive the scan signal as the second sub-reset control signal.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be DC reference voltage terminals to output a constant DC reference voltage.
  • the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 may be high-voltage terminals or low-voltage terminals, as long as they can provide a first reset signal and a second reset signal to the gate of the driving transistor T1 and the light-emitting element 120
  • the first light-emitting voltage application electrode only needs to be reset, which is not limited in the present disclosure.
  • the driving circuit 122, the data writing circuit 126, the storage circuit 127, the threshold compensation circuit 128, and the reset circuit 129 in the pixel circuit shown in FIGS. 3A-3B are only illustrative, and the driving circuit 122, data writing
  • the specific structures of the input circuit 126, the storage circuit 127, the threshold compensation circuit 128, and the reset circuit 129 can be set according to actual application requirements, which are not specifically limited in the embodiment of the present disclosure.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type MOS transistors) as an example to explain in detail the description of the present disclosure.
  • the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the first The two reset transistors T7 and so on can all be P-type transistors.
  • the transistors of the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs. .
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors. .
  • the source and drain of the transistor can be symmetric in structure, so the source and drain can be indistinguishable in physical structure.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, in the embodiments of the present disclosure, all or part of the transistors have the first pole.
  • the first pole and the second pole are interchangeable as needed.
  • each circuit in the pixel circuit 121a of the first sub-pixel G1 (for example, the driving circuit 122a, the first light emission control circuit 123a, the second light emission control circuit 124a, the data writing circuit 126a,
  • the connection relationship, structure, and type of the storage circuit 127a, the threshold compensation circuit 128a, the reset circuit 129a, etc.) correspond to the corresponding circuits in the pixel circuit 121b of the second sub-pixel G2 (for example, the drive circuit 122b, the first light emission control The circuit 123b, the second light emission control circuit 124b, the data write circuit 126b, the storage circuit 127b, the threshold compensation circuit 128b, the reset circuit 129b, etc.) have the same connection, structure and type, that is, for example, the first sub
  • the structure and type of the driving circuit 122a in the pixel circuit 121a of the pixel G1 are the same as the structure and type of the driving circuit 122b in the pixel circuit
  • each circuit in the pixel circuit 121a of the first sub-pixel G1 and each corresponding circuit in the pixel circuit 121b of the second sub-pixel G2 can be prepared simultaneously using the same process.
  • the driving circuit 122a of the second sub-pixel G2 and the driving circuit 122b of the pixel circuit 121b of the second sub-pixel G2 are manufactured at the same time using the same patterning process.
  • the signal lines electrically connected to the circuits in the pixel circuit 121a of the first sub-pixel G1 are the first scan signal line Ga1a, the second scan signal line Ga2a, and the first scan signal line Ga1a.
  • each signal line electrically connected to each circuit in the pixel circuit 121b of the second sub-pixel G2 is a first scan signal line Ga1b, a second scan signal line Ga2b, and a first reset control signal line Rst1b.
  • the pixel circuit of the sub-pixel may not only have the structure of 7T2C (that is, seven transistors, one capacitor, and one parasitic capacitor) shown in FIG. 3A, but also include other numbers.
  • the structure of the transistor such as the 6T2C structure or the 9T2C structure, is not limited in the embodiment of the present disclosure.
  • FIGS. 4A-4E are schematic diagrams of various layers of a pixel circuit provided by some embodiments of the present disclosure. The positional relationship of each circuit in the pixel circuit on the backplane is described below with reference to FIGS. 4A-4E.
  • the example shown in FIGS. 4A-4E takes the pixel circuit 121a of the first sub-pixel G1 as an example.
  • the pixel circuit 121a of the first sub-pixel G1 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, and a second light emission control transistor T5 shown in FIG. 3B.
  • FIGS. 4A-4E also show the first scan signal line Ga1a connected to the pixel circuit 121a of the first sub-pixel G1,
  • the first light-emission control signal line EM1a, the second light-emission control signal line EM2a the data line Vd
  • the second power signal lines VDD2 are electrically connected to each other.
  • the first scan signal line Ga1a and the second scan signal line Ga2a are the same signal line
  • the first reset power signal line Init1a and the second reset power signal line Init2a It is the same signal line
  • the first reset control signal line Rst1a and the second reset control signal line Rst2a are the same signal line
  • the first light emission control signal line EM1a and the second light emission control signal line EM2a are the same signal line.
  • FIG. 4A shows the active semiconductor layer 310 of the pixel circuit 121a.
  • the active semiconductor layer 310 may be formed by patterning a semiconductor material.
  • the active semiconductor layer 310 can be used to make the aforementioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6, and second reset transistor T7
  • Each active layer may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the active layer of each transistor is integrated.
  • the active semiconductor layer 310 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the gate metal layer of the pixel circuit 121a may include a first conductive layer and a second conductive layer.
  • a gate insulating layer (not shown) is formed on the aforementioned active semiconductor layer 310 to protect the aforementioned active semiconductor layer 310.
  • 4B shows the first conductive layer 320 of the pixel circuit 121a.
  • the first conductive layer 320 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 310.
  • the first conductive layer 320 may include the second electrode CC2a of the third capacitor C2, the first scan signal line Ga1a, the second scan signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first light emitting The control signal line EM1a, the second light emission control signal line EM2a, and the drive transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the first 2. Reset the gate of the transistor T7.
  • the gate of the data writing transistor T2 may be the part where the first scan signal line Ga1a overlaps the active semiconductor layer 310
  • the gate of the first light emission control transistor T4 may be the first light emission control
  • the gate of the second light emission control transistor T5 may be the first light emission control signal line EM1a/the second light emission control signal line EM2a and
  • the gate of the first reset transistor T6 is the first part where the first reset control signal line Rst1a/second reset control signal line Rst2a overlaps the active semiconductor layer 310
  • the second reset The gate of the transistor T7 is the second part where the first reset control signal line Rst1a/the second reset control signal line Rst2a overlaps the active semiconductor layer 310
  • the threshold compensation transistor T3 may be a thin film transistor with a double gate structure
  • the threshold compensation transistor T3 may
  • each dashed rectangular frame in FIG. 4A shows each part where the first conductive layer 320 and the active semiconductor layer 310 overlap.
  • the signal line EM2a is arranged along the first direction X.
  • the first scan signal line Ga1a/the second scan signal line Ga2a is located between the first reset control signal line Rst1a/the second reset control signal line Rst2a and the first light emission control signal line EM1a/the second light emission control signal line EM2a.
  • the second pole CC4a of the first capacitor C11 (that is, the second pole CC2a of the third capacitor C2) is located on the first scan signal line Ga1a/the second scan signal line Ga2a and the first light emitting control signal Line EM1/a between the second light-emitting control signal lines EM2a.
  • the protrusion protruding from the second scan signal line Ga2a is located on the side of the second scan signal line Ga2a away from the first light emission control signal line EM1a/the second light emission control signal line EM2a.
  • the gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6, and the gate of the second reset transistor T7 are all Located on the first side of the gate of the driving transistor T1, the gate of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 are both on the second side of the gate of the driving transistor T1, for example, FIGS.
  • the first side and the second side of the gate of the driving transistor T1 of the pixel circuit 121a of the first sub-pixel G1 are opposite sides of the gate of the driving transistor T1 in the first direction X,
  • the first side of the gate of the driving transistor T1 of the pixel circuit 121a of the first sub-pixel G1 may be the upper side of the gate of the driving transistor T1
  • the second side of the gate of the driving transistor T1 of 121a may be the lower side of the gate of the driving transistor T1.
  • the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located at the gate of the driving transistor T1.
  • the first gate of the threshold compensation transistor T3, the gate of the second light emission control transistor T5, and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1, for example, FIG. 4A
  • the third side and the fourth side of the gate of the driving transistor T1 of the pixel circuit 121a of the first subpixel G1 are two opposite sides of the gate of the driving transistor T1 in the second direction Y.
  • the third side of the gate of the driving transistor T1 of the pixel circuit 121a of the first sub-pixel G1 may be the gate of the driving transistor T1 of the pixel circuit 121a of the first sub-pixel G1.
  • the fourth side of the gate of the driving transistor T1 of the pixel circuit 121a of the first sub-pixel G1 may be the left side of the gate of the driving transistor T1 of the pixel circuit 121a of the first sub-pixel G1.
  • a first insulating layer (not shown) is formed on the aforementioned first conductive layer 320 to protect the aforementioned first conductive layer 320.
  • 4C shows the second conductive layer 330 of the pixel circuit 120a.
  • the second conductive layer 330 includes the first pole CC1a of the third capacitor C2, the first reset power signal line Init1a, the second reset power signal line Init2a, and the second Power signal line VDD2.
  • the second power signal line VDD2 is integrally formed with the first pole CC1a of the third capacitor C2.
  • the first pole CC1a of the third capacitor C2 and the second pole CC2a of the third capacitor C2 at least partially overlap to form a third capacitor C2.
  • a second insulating layer (not shown) is formed on the aforementioned second conductive layer 330 to protect the aforementioned second conductive layer 330.
  • 4D shows the source and drain metal layer 340 of the pixel circuit 121a.
  • the source and drain metal layer 340 includes a data line Vd and a first power signal line VDD1.
  • FIGS. 4D and 4E is a schematic diagram of the stacking positional relationship of the above-mentioned active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, and the source-drain metal layer 340.
  • the data line Vd passes through at least one via (for example, via 381a) in the gate insulating layer, the first insulating layer, and the second insulating layer to write data in the active semiconductor layer 310.
  • the source regions of the transistor T2 are connected.
  • the first power signal line VDD1 passes through at least one via (for example, via 382a) among the gate insulating layer, the first insulating layer, and the second insulating layer, and is connected to the corresponding first light emitting control transistor T4 in the active semiconductor layer 310.
  • the source regions are connected.
  • the first power signal line VDD1 is connected to the first pole CC1a of the third capacitor C2 in the second conductive layer 330 through at least one via in the second insulating layer (for example, via 3832a).
  • the first power signal line VDD1 is also connected to the second power signal line VDD2 in the second conductive layer 330 through at least one via in the second insulating layer (for example, via 3831a).
  • the source-drain metal layer 340 further includes a first connection portion 341a, a second connection portion 342a, and a third connection portion 343a.
  • One end of the first connection portion 341a passes through at least one via (for example, via 384a) among the gate insulating layer, the first insulating layer, and the second insulating layer to connect to the drain of the corresponding threshold compensation transistor T3 in the active semiconductor layer 310.
  • the electrode regions are connected, and the other end of the first connection portion 341a passes through at least one via (for example, via 385a) in the first insulating layer and the second insulating layer to the gate of the driving transistor T1 in the first conductive layer 320 ( That is, the second pole CC2a) of the third capacitor C2 is connected.
  • via 385a via 385a
  • One end of the second connecting portion 342a is connected to the first reset power signal line Init1a/the second reset power signal line Init2a through a via (for example, via 386a) in the second insulating layer, and the other end of the second connecting portion 342a It is connected to the drain region of the second reset transistor T7 in the active semiconductor layer 310 through at least one via (for example, via 387a) in the gate insulating layer, the first insulating layer, and the second insulating layer.
  • the third connection portion 343a passes through at least one via (for example, via 388a) of the gate insulating layer, the first insulating layer, and the second insulating layer, and the drain of the second light-emitting control transistor T5 in the active semiconductor layer 310.
  • the areas are connected.
  • an intermediate layer (not shown) is formed on the aforementioned source and drain metal layer 340 to protect the aforementioned source and drain metal layer 340.
  • the first light-emitting voltage application electrode of the light-emitting element of each sub-pixel may be arranged on the side of the intermediate layer away from the base substrate.
  • the first scan signal line Ga1a, the second scan signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first reset The power supply signal line Init1a and the second reset power supply signal line Init2a are both located on the first side of the gate of the driving transistor T1 of the pixel circuit 121a of the first sub-pixel G1, the first light emission control signal line EM1a and the second light emission control signal line EM2a They are all located on the second side of the driving transistor T1 of the pixel circuit 121a of the first sub-pixel G1.
  • the first scan signal line Ga1a, the second scan signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first light emission control signal line EM1a, the second light emission control signal line EM2a, the first The reset power signal line Init1a and the second reset power signal line Init2a both extend in the second direction Y, and the data line Vd extends in the first direction X.
  • the first power signal line VDD1 extends in the first direction X
  • the second power signal line VDD2 extends in the second direction Y.
  • the signal lines of the first power supply terminal VDD are gridded and wired on the display substrate, that is, on the entire display substrate, the first power supply signal line VDD1 and the second power supply signal line VDD2 are arranged in a grid pattern, so that the first power supply terminal The resistance of the VDD signal line is relatively small and the voltage drop is relatively low, thereby improving the stability of the power supply voltage provided by the first power terminal VDD.
  • the first scan signal line Ga1a, the second scan signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first light emission control signal line EM1a, and the second light emission control signal line EM2a are located in the same layer
  • the first reset power signal line Init1a, the second reset power signal line Init2a, and the second power signal line VDD2a are located in the same layer.
  • the first power signal line VDD1 and the data line Vd are located in the same layer.
  • the positional arrangement of the driving circuit, the first light emission control circuit, the second light emission control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit, and the reset circuit in each pixel circuit is not limited to FIG. 4A
  • the positions of the driving circuit, the first light-emitting control circuit, the second light-emitting control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit, and the reset circuit can be specifically set according to actual application requirements.
  • FIG. 5A is a schematic plan view of a display substrate provided by some embodiments of the present disclosure
  • FIG. 5B is a schematic plan view of a repeating unit provided by some embodiments of the present disclosure
  • FIG. 6A is another repeating unit provided by some embodiments of the present disclosure
  • FIG. 6B is a layout diagram of a display substrate provided by some embodiments of the present disclosure
  • FIG. 6C is a schematic cross-sectional structure diagram of the line L1-L1' in FIG. 6B
  • FIG. 6D is a cross-section of the line L2-L2' in FIG. 6B Schematic diagram of the structure
  • FIG. 6E is a schematic plan view of another display substrate provided by some embodiments of the present disclosure.
  • the pixel arrangement structure in the display substrate 10 may be a GGRB pixel arrangement structure to increase the PPI (pixel per inch) of the display panel including the display substrate 10.
  • the number of pixels in inches so as to increase the visual resolution of the display panel under the same display resolution.
  • each repeating unit 11 includes four sub-pixels, the four sub-pixels are the first sub-pixel G1, the second sub-pixel G2, the third sub-pixel R, and the fourth sub-pixel B, and the four sub-pixels can use GGRB Arrangement. It should be noted that only two complete repeating units 11 are shown in FIG. 5A, but the present disclosure is not limited to this.
  • the display substrate 10 includes a plurality of repeating units 11, and the plurality of repeating units 11 are along the first direction.
  • the X and Y arrays are arranged in the second direction.
  • areas 31 to 40 may be areas where the pixel circuits of each sub-pixel on the base substrate 10 are located.
  • areas 31 to 35 are located in the first row, and areas 36 to 40 are located in the second row; area 31 And 36 are in the first column, regions 32 and 37 are in the second column, regions 33 and 38 are in the third column, regions 34 and 39 are in the fourth column, and regions 35 and 40 are in the fifth column.
  • areas 31 to 35 are located in the first row, and areas 36 to 40 are located in the second row; area 31 And 36 are in the first column, regions 32 and 37 are in the second column, regions 33 and 38 are in the third column, regions 34 and 39 are in the fourth column, and regions 35 and 40 are in the fifth column.
  • the pixel circuit of the first sub-pixel G1 is located in the area 32
  • the pixel circuit of the second sub-pixel G2 is located in the area 37
  • the third sub-pixel R The pixel circuit of the fourth sub-pixel B is located in the area 38
  • the pixel circuit of the fourth sub-pixel B is located in the area 36.
  • row may refer to a row corresponding to the area where each pixel circuit is located
  • column may refer to a column corresponding to the area where each pixel circuit is located.
  • the light-emitting element 120 is configured to receive a light-emitting signal (for example, a current signal) during operation, and emit light of an intensity corresponding to the light-emitting signal.
  • the light emitting element 120 may be a light emitting diode, and the light emitting diode may be, for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED), etc., but the embodiments of the present disclosure are not limited thereto.
  • the light-emitting element 120 includes a first light-emitting voltage applying electrode 1201, a second light-emitting voltage applying electrode 1202, and a light-emitting layer provided between the first light-emitting voltage applying electrode 1201 and the second light-emitting voltage applying electrode 1202. 1203.
  • the light-emitting element of the first sub-pixel G1 includes a first light-emitting voltage applying electrode 1201a, a second light-emitting voltage applying electrode 1202, and a light-emitting layer 1203a
  • the light-emitting element of the second sub-pixel G2 includes a first light-emitting voltage.
  • the application electrode 1201b, the second light-emitting voltage application electrode 1202, and the light-emitting layer 1203a are examples of the light-emitting voltage applying electrode 1201, and the light-emitting layer 1203a.
  • the orthographic projection of the first light-emitting voltage applying electrode 1201a of the light-emitting element of the first sub-pixel G1 on the base substrate 10 and the control terminal 1221a of the driving circuit of the pixel circuit of the first sub-pixel G1 are at The orthographic projection on the base substrate 10 at least partially overlaps, and the orthographic projection of the first light-emitting voltage application electrode 1201b of the light-emitting element of the second sub-pixel G2 on the base substrate 10 and the driving circuit of the pixel circuit of the second sub-pixel G2 are at least partially overlapped.
  • the orthographic projection of the control terminal 1221b on the base substrate 10 at least partially overlaps.
  • the first light-emitting voltage applying electrode 1201a of the light-emitting element of the first sub-pixel G1 and the first light-emitting voltage applying electrode 1201b of the light-emitting element of the second sub-pixel G2 may be located on the same layer, and the first light-emitting voltage applying electrode 1201b of the light-emitting element of the first sub-pixel G1
  • the two light-emitting voltage application electrodes 1202 and the second light-emitting voltage application electrode 1202 of the light-emitting element of the second sub-pixel G2 may be integrally provided.
  • the orthographic projection of the light-emitting layer 1203a of the light-emitting element of the first sub-pixel G1 on the base substrate 10 and the orthographic projection of the light-emitting layer 1203a of the light-emitting element of the second sub-pixel G2 on the base substrate 10 are continuous.
  • the light-emitting layer 1203a of the light-emitting element of the first sub-pixel G1 and the light-emitting layer 1203a of the light-emitting element of the second sub-pixel G2 can be made from an opening in a high-definition metal mask (FMM) plate, which can effectively reduce FMM.
  • FMM high-definition metal mask
  • the difficulty of the process For example, the light-emitting layer 1203a of the light-emitting element of the first sub-pixel G1 and the light-emitting layer 1203a of the light-emitting element of the second sub-pixel G2 are integrated.
  • the material of the light-emitting layer 1203 of each sub-pixel may be selected according to the color of light emitted by the light-emitting element 120 of each sub-pixel.
  • the material of the light-emitting layer 1203 of each sub-pixel includes a fluorescent light-emitting material or a phosphorescent light-emitting material.
  • the first light-emitting voltage applying electrode 1201 is an anode
  • the second light-emitting voltage applying electrode 1202 is a cathode
  • both the first light-emitting voltage applying electrode 1201 and the second light-emitting voltage applying electrode 1202 are made of conductive materials.
  • a first organic layer is provided between the first light-emitting voltage application electrode 1201 and the light-emitting layer 1203, and a second organic layer is provided between the second light-emitting voltage application electrode 1202 and the light-emitting layer 1203.
  • the first organic layer and the second organic layer are used for leveling and can be omitted.
  • the color of the light emitted by the light-emitting element 120a of the first sub-pixel G1 is the same as the color of the light emitted by the light-emitting element 120b of the second sub-pixel G2, that is, the first sub-pixel G1 It is a sub-pixel of the same color as the second sub-pixel G2.
  • the first sub-pixel G1 and the second sub-pixel G2 are sensitive color sub-pixels.
  • the display substrate 100 adopts the red-green-blue (RGB) display mode the above-mentioned sensitive color is green, that is, the first sub-pixel G1 and the second sub-pixel G1
  • the sub-pixels G2 are all green sub-pixels.
  • the third sub-pixel R may be a red sub-pixel
  • the fourth sub-pixel B may be a blue sub-pixel.
  • the four sub-pixels in each repeating unit 11 may form two dummy pixels, and the third sub-pixel R and the fourth sub-pixel B in the repeating unit 11 are respectively shared by the two dummy pixels.
  • the sub-pixels in the multiple repeating units 11 form a pixel array. In the row direction of the pixel array, the sub-pixel density is 1.5 times the virtual pixel density, and in the column direction of the pixel array, the sub-pixel density is 1.5 times the virtual pixel density.
  • the first sub-pixel G1 and the second sub-pixel G2 belong to two virtual pixels, respectively.
  • each virtual pixel is not limited.
  • the division of virtual pixels is related to the driving mode, and the specific division mode of virtual pixels can be determined according to the actual driving mode, which is not specifically limited in the present disclosure.
  • the orthographic projection of the control terminal 1221a of the driving circuit of the pixel circuit of the first sub-pixel G1 on the base substrate 10 is located at the first light-emitting voltage application electrode 1201a of the light-emitting element 120a of the first sub-pixel G1
  • the orthographic projection of the control terminal 1221b of the driving circuit of the pixel circuit of the second sub-pixel G2 on the base substrate 10 is located at the first light-emitting voltage of the light-emitting element 120b of the second sub-pixel G2
  • the application electrode 1201b is in an orthographic projection on the base substrate 10.
  • the orthographic projection of the first light-emitting voltage applying electrode 1201a of the light-emitting element 120a of the first sub-pixel G1 on the base substrate 10 completely covers the control terminal 1221a of the driving circuit of the pixel circuit of the first sub-pixel G1 on the substrate 10
  • the orthographic projection on the substrate 10 the orthographic projection of the first light-emitting voltage applying electrode 1201b of the light-emitting element 120b of the second sub-pixel G2 on the base substrate 10 completely covers the control terminal 1221b of the driving circuit of the pixel circuit of the second sub-pixel G2
  • the orthographic projection on the base substrate 10 for example, the area of the orthographic projection of the first light-emitting voltage application electrode 1201a of the light-emitting element 120a of the first sub-pixel G1 on the base substrate 10 may be larger than the pixel circuit of the first sub-pixel G1
  • the driving circuit 122a of the pixel circuit of the first sub-pixel G1 includes a driving transistor T1
  • the control terminal 1221a of the driving circuit 122a of the pixel circuit of the first sub-pixel G1 is the first sub-pixel G1.
  • the pixel circuit drives the gate of the transistor T1
  • the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element 120a of the first sub-pixel G1 on the base substrate 10 is in line with the gate of the drive transistor T1 of the first sub-pixel G1.
  • the orthographic projections on the base substrate 10 at least partially overlap; as shown in FIG.
  • the driving circuit 122b of the pixel circuit of the second sub-pixel G2 includes a driving transistor T1
  • the control of the driving circuit 122b of the pixel circuit of the second sub-pixel G2 The terminal 1221b is the gate of the driving transistor T1 of the pixel circuit of the second sub-pixel G2.
  • the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element 120b of the second sub-pixel G2 on the base substrate 10 and the second sub-pixel G2 The orthographic projection of the gate of the driving transistor T1 on the base substrate 10 at least partially overlaps.
  • the orthographic projection of the gate of the driving transistor T1 of the first sub-pixel G1 on the base substrate 10 is located within the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element 120a of the first sub-pixel G1 on the base substrate 10.
  • the orthographic projection of the gate of the driving transistor T1 of the second sub-pixel G2 on the base substrate 10 is located in the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element 120b of the second sub-pixel G2 on the base substrate 10.
  • the orthographic projection of the control terminal 1221a of the driving circuit of the pixel circuit of the first sub-pixel G1 on the base substrate 10 and the first light-emitting voltage application electrode 1201a of the light-emitting element of the first sub-pixel G1 The area of the overlapping portion of the orthographic projection on the base substrate 10 is the first area AR1, and the orthographic projection of the control terminal 1221b of the pixel circuit of the second sub-pixel G2 on the base substrate 10 and the second sub-pixel G2 are The area of the overlapping portion of the orthographic projection of the first light-emitting voltage applying electrode 1201b of the light-emitting element on the base substrate 10 is the second area AR2, and the ratio of the first area AR1 to the second area AR2 satisfies the following relationship:
  • AR1 represents the first area
  • AR2 represents the second area
  • Amin represents the minimum ratio threshold and is 90%
  • Amax represents the maximum ratio threshold and is 110%.
  • the first area AR1 may be greater than or equal to the second area AR2.
  • the minimum ratio threshold Amin may be 90%, and the maximum ratio threshold Amax may also be 100%; in other examples, the first area AR1 may be smaller than the second area AR2. In this case, the minimum ratio threshold Amin may also be 95%, and the maximum ratio threshold Amax may also be 105%.
  • the embodiments of the present disclosure do not specifically limit the specific values of the minimum ratio threshold and the maximum ratio threshold.
  • the first area AR1 and the second area AR2 are small (for example, less than 10%)
  • the first The parasitic capacitance between the first light-emitting voltage applying electrode 1201a of the light-emitting element of the sub-pixel G1 and the control terminal 1221a of the driving circuit of the first sub-pixel G1 that is, the first capacitor C11 shown in FIG. 3B
  • the second sub-pixel G2 The difference between the parasitic capacitance (that is, the second capacitance C12 shown in FIG.
  • the ratio of the first area AR1 to the second area AR2 is between the above minimum ratio threshold and the maximum ratio threshold, even at low gray levels (such as 64 gray levels), that is, when the human eye has a high recognition ability , The user may not be able to see the brightness difference between the first sub-pixel G1 and the second sub-pixel G2, which effectively improves the display effect of the display panel and enhances the user experience.
  • the shape of the first light-emitting voltage application electrode 1201a of the light-emitting element 120a of the first sub-pixel G1 is different from the shape of the first light-emitting voltage application electrode 1201b of the light-emitting element of the second sub-pixel G2 .
  • the shape of the first light-emitting voltage application electrode 1201a of the light-emitting element of the first sub-pixel G1 may be an octagon
  • the shape of the first light-emitting voltage application electrode 1201b of the light-emitting element of the second sub-pixel G2 may be It is a pentagon.
  • the area of the orthographic projection of the first light-emitting voltage applying electrode 1201a of the light-emitting element of the first sub-pixel G1 on the base substrate 10 and the first light emission of the light-emitting element of the second sub-pixel G2 The area of the orthographic projection of the voltage application electrode 1201b on the base substrate 10 is different, and the area of the orthographic projection of the first light-emitting voltage application electrode 1201a of the light-emitting element of the first sub-pixel G1 on the base substrate 10 is larger than that of the second sub-pixel
  • the first light-emitting voltage application electrode 1201a of the light-emitting element 120a of the first sub-pixel G1 includes an auxiliary electrode block Ae, and the orthographic projection of the auxiliary electrode block Ae on the base substrate 10 and the first sub-pixel G1
  • the orthographic projection of the control terminal 1221a of the driving circuit of the pixel circuit on the base substrate 10 at least partially overlaps.
  • the orthographic projection of the control terminal 1221a of the driving circuit of the pixel circuit of the first sub-pixel G1 on the base substrate 10 is within the orthographic projection of the auxiliary electrode block Ae on the base substrate 10.
  • the orthographic projection of the gate of the driving transistor T1 of the first sub-pixel G1 on the base substrate 10 is located on the auxiliary electrode block Ae of the first light-emitting voltage application electrode of the light-emitting element 120a of the first sub-pixel G1 on the base substrate 10.
  • the orthographic projection is located on the auxiliary electrode block Ae of the first light-emitting voltage application electrode of the light-emitting element 120a of the first sub-pixel G1 on the base substrate 10.
  • the auxiliary electrode block Ae serves as the first pole CC3 of the first capacitor C11
  • the control terminal 1221a of the driving circuit 122a of the first sub-pixel G1 is multiplexed as the second pole CC4 of the first capacitor C11
  • the auxiliary electrode block Ae is the first electrode CC3 of the first capacitor C11
  • the control terminal 1221a of the driving circuit 122a of the first sub-pixel G1 (that is, the gate of the driving transistor T1 of the first sub-pixel G1) is the second electrode of the first capacitor C11. ⁇ CC4.
  • the shape of the auxiliary electrode block Ae may be a rectangle, and the shape of the orthographic projection of the auxiliary electrode block Ae on the base substrate 10 is the same as the shape of the auxiliary electrode block Ae, that is, it is also a rectangle.
  • the present disclosure is not limited to this, and the shape of the auxiliary electrode block Ae may also be pentagonal, hexagonal, oval, or the like.
  • the first light-emitting voltage application electrode 1201a of the light-emitting element 120a of the first sub-pixel G1 further includes a first driving electrode block De1, which is electrically connected to the auxiliary electrode block Ae.
  • the shape of the first driving electrode block De1 may be a pentagon, and the shape of the orthographic projection of the first driving electrode block De1 on the base substrate 10 is the same as the shape of the first driving electrode block De1 , which is also a pentagon.
  • a pentagon can be composed of a triangle and a rectangle.
  • the first driving electrode block De1 and the auxiliary electrode block Ae are integrally provided. Therefore, the shape of the first light-emitting voltage application electrode 1201a may be an octagon, and the octagon may be formed by It consists of a pentagon and a rectangle.
  • first driving electrode block De1 and the auxiliary electrode block Ae may also be separately provided, as long as the first driving electrode block De1 and the auxiliary electrode block Ae can be electrically connected to each other.
  • the first driving electrode block De1 and the auxiliary electrode block Ae may be simultaneously formed by the same patterning process.
  • the first driving electrode block De1 and the auxiliary electrode block Ae are located in the same layer.
  • the orthographic projection of the first driving electrode block De1 on the base substrate 10 the orthographic projection of the light-emitting layer 1203a of the light-emitting element of the first sub-pixel G1 on the base substrate 10, and the first sub-pixel
  • the orthographic projection of the second light-emitting voltage applying electrode 1202 of the light-emitting element of G1 on the base substrate 10 at least partially overlaps.
  • the second light-emitting voltage application electrodes of the light-emitting elements of all sub-pixels on the display substrate are integrated, that is, the second light-emitting voltage application electrode 1202 covers the entire base substrate 10, That is, the second light-emitting voltage applying electrode 1202 may be a planar electrode.
  • the second light-emitting voltage applying electrode 1202 may be a planar electrode.
  • the planar second light-emitting voltage application electrode 1202 overlaps the first light-emitting voltage application electrode 1201a of the light-emitting element of the first sub-pixel G1
  • the part can be represented as the second light-emitting voltage applying electrode 1202 of the light-emitting element of the first sub-pixel G1
  • the planar second light-emitting voltage applying electrode overlaps the first light-emitting voltage applying electrode 1201b of the light-emitting element of the second sub-pixel G2
  • the part of can be represented as the second light-emitting voltage applying electrode 1202 of the light-emitting element of the second sub-pixel G2.
  • the second light-emitting voltage application electrode 1202 of the light-emitting element of the first sub-pixel G1 and the second light-emitting voltage application electrode 1202 of the light-emitting element of the second sub-pixel G2 are integrally provided.
  • the light-emitting layer of the light-emitting element of the first sub-pixel G1 and the light-emitting layer of the light-emitting element of the second sub-pixel G2 are integrally provided.
  • the portion where the light-emitting layer 1203a overlaps the first light-emitting voltage application electrode 1201a of the light-emitting element of the first sub-pixel G1 can be expressed as the light emission of the light-emitting element of the first sub-pixel G1
  • the part where the light-emitting layer 1203a overlaps the first light-emitting voltage application electrode 1201b of the light-emitting element of the second sub-pixel G2 may be represented as the light-emitting layer of the light-emitting element of the second sub-pixel G2.
  • the display substrate 100 further includes a pixel defining layer 160, and the first light-emitting voltage application electrode of the light-emitting element of each sub-pixel is located on a side away from the base substrate 10 and includes a first opening.
  • the overlapping area of 1201a is the effective light emitting area of the first sub-pixel G1
  • the overlapping area of the first opening and the first light-emitting voltage application electrode 1201b is the effective light emitting area of the second sub-pixel G2.
  • the light-emitting layer of each light-emitting element may include the electroluminescent layer itself and other common layers located on both sides of the electroluminescent layer, for example, hole injection layer, hole transport Layer, electron injection layer, electron transport layer, etc., but in the drawings of the present disclosure, only the electroluminescent layer in the light-emitting layer is shown, and other common layers are not shown.
  • the orthographic projection of the first drive electrode block De1 on the base substrate 10 and the orthographic projection of the second light-emitting voltage application electrode 1202 of the light-emitting element of the first sub-pixel G1 on the base substrate 10 may also be
  • the orthographic projection of the first driving electrode block De1 on the base substrate 10 is located within the orthographic projection of the second light-emitting voltage applying electrode 1202 of the light-emitting element of the first sub-pixel G1 on the base substrate 10.
  • the orthographic projection of the light-emitting layer 1203a of the light-emitting element of one sub-pixel G1 on the base substrate 10 may also be located within the orthographic projection of the second light-emitting voltage applying electrode 1202 of the light-emitting element of the first sub-pixel G1 on the base substrate 10.
  • the orthographic projection of the first drive electrode block De1 on the base substrate 10 the orthographic projection of the light-emitting layer 1203a of the light-emitting element of the first sub-pixel G1 on the base substrate 10 and the orthographic projection of the first sub-pixel G1
  • the second light-emitting voltage applying electrode 1202 of the light-emitting element is in the area where the projections of the orthographic projection on the base substrate 10 overlap.
  • the light-emitting layer of the light-emitting element of the first sub-pixel G1 corresponds to the pixel defining layer
  • the part of the first opening of 160 is used for light emission.
  • the first light-emitting voltage applying electrode 1201b of the light-emitting element 120b of the second sub-pixel G2 includes a second driving electrode block De2.
  • the orthographic projection of the second driving electrode block De2 on the base substrate 10 and the orthographic projection of the control terminal 1221 b of the pixel circuit of the second sub-pixel G2 on the base substrate 10 at least partially overlap.
  • the orthographic projection of the control terminal 1221b of the driving circuit of the pixel circuit of the second sub-pixel G2 on the base substrate 10 may be located within the orthographic projection of the second driving electrode block De2 on the base substrate 10.
  • the orthographic projection of the gate of the driving transistor T1 of the second sub-pixel G2 on the base substrate 10 is located on the second driving electrode block De2 of the first light-emitting voltage application electrode of the light-emitting element 120b of the second sub-pixel G2. In the orthographic projection on the substrate 10.
  • the second drive electrode block De2 can be multiplexed as the first pole of the second capacitor C12, and the control terminal 1221b of the drive circuit 122b of the second sub-pixel G2 can be multiplexed as the second pole of the second capacitor C12, that is,
  • the second driving electrode block De2 is the first electrode of the second capacitor C12
  • the control terminal 1221b of the driving circuit 122b of the second sub-pixel G2 (that is, the gate of the driving transistor T1 of the second sub-pixel G2) is the second capacitor The second pole of C12.
  • the shape of the first driving electrode block De1 and the shape of the second driving electrode block De2 may be the same, that is, the shape of the second driving electrode block De2 may also be a pentagon.
  • the shape of the orthographic projection of the second driving electrode block De2 on the base substrate 10 is the same as the shape of the second driving electrode block De2, that is, it is also a pentagon.
  • the area of the orthographic projection of the first drive electrode block De1 on the base substrate 10 is the same as the area of the orthographic projection of the second drive electrode block De2 on the base substrate 10.
  • the shape of the first driving electrode block De1 and the shape of the second driving electrode block De2 may also be rectangular or rhombic.
  • the shape of the first driving electrode block De1 and the shape of the second driving electrode block De2 may also be different, which is not limited in the present disclosure.
  • the orthographic projection of the second drive electrode block De2 on the base substrate 10 the orthographic projection of the light-emitting layer 1203a of the light-emitting element of the second sub-pixel G2 on the base substrate 10, and the second sub-pixel
  • the orthographic projections of the second light-emitting voltage application electrode 1202 of the light-emitting element of G2 on the base substrate 10 at least partially overlap.
  • the orthographic projection of the second driving electrode block De2 on the base substrate 10 and the orthographic projection of the second light-emitting voltage application electrode 1202 of the light-emitting element of the second sub-pixel G2 on the base substrate 10 may also be Incomplete overlap, for example, the orthographic projection of the second driving electrode block De2 on the base substrate 10 is located within the orthographic projection of the second light-emitting voltage application electrode 1202 of the light-emitting element of the second sub-pixel G2 on the base substrate 10.
  • the orthographic projection of the second drive electrode block De2 on the base substrate 10 the orthographic projection of the light-emitting layer 1203a of the light-emitting element of the second sub-pixel G2 on the base substrate 10 and the orthographic projection of the second sub-pixel G2
  • the second light-emitting voltage applying electrode 1202 of the light-emitting element is in the area where the projections of the orthographic projection on the base substrate 10 overlap.
  • the light-emitting layer of the light-emitting element of the second sub-pixel G2 corresponds to the pixel defining layer 160
  • the part of the first opening is used for light emission.
  • the first sub-pixel G1 and the second sub-pixel G2 are arranged along a first direction X, which is parallel to the surface of the base substrate 10.
  • the auxiliary electrode block Ae is located on the side of the first driving electrode block De1 away from the light emitting element of the second sub-pixel G2, that is, as shown in FIG. 5B, in the first direction X ,
  • the first driving electrode block De1 is located between the auxiliary electrode block Ae and the second driving electrode block De2.
  • the orthographic projection of the auxiliary electrode block Ae on the base substrate 10 and the orthographic projection of the light-emitting layer 1203a of the light-emitting element of the first sub-pixel G1 on the base substrate 10 do not overlap.
  • the orthographic projection of the auxiliary electrode block Ae on the base substrate 10 and the orthographic projection of the light-emitting layer 1203a of the light-emitting element of the first sub-pixel G1 on the base substrate 10 do not overlap at all.
  • the first light-emitting voltage applying electrode of the light-emitting element of the first sub-pixel G1 further includes a first connection electrode block Ce1.
  • the first connection electrode block Ce1 is located at the first On the side of the driving electrode block De1 away from the light-emitting element of the second sub-pixel G2, the first connecting electrode block Ce1 is located between the auxiliary electrode block Ae and the first driving electrode block De1, and is connected to the auxiliary electrode block Ae and the first driving electrode block.
  • the blocks De1 are all electrically connected.
  • the first connecting electrode block Ce1, the auxiliary electrode block Ae, and the first driving electrode block De1 are all integrated. It should be noted that in other examples, the first connecting electrode block Ce1, the auxiliary electrode block Ae, and the first driving electrode block De1 may also be separately provided, as long as the first connecting electrode block Ce1, the auxiliary electrode block Ae, and the first The driving electrode blocks De1 can be electrically connected to each other.
  • the first connecting electrode block Ce1 is used to connect the first driving electrode block De1 and the pixel circuit of the first sub-pixel G1.
  • the first connecting electrode block Ce1, the auxiliary electrode block Ae, and the first driving electrode block De1 are located in the same layer.
  • the first connection electrode block Ce1, the auxiliary electrode block Ae, and the first driving electrode block De1 may be simultaneously formed by the same patterning process.
  • the shape of the first connecting electrode block Ce1 may be a regular shape, such as a rectangle, a rhombus, etc.; the shape of the first connecting electrode block Ce1 may also be an irregular shape.
  • the shape of the auxiliary electrode block Ae and the shape of the first connecting electrode block Ce1 are both rectangular, and in the second direction Y, the width of the auxiliary electrode block Ae is smaller than the first connecting electrode block Ae.
  • the width of a connecting electrode block Ce1, that is, the auxiliary electrode block Ae and the first connecting electrode block Ce1 form a stepped shape. In the second direction Y, the width of the first connection electrode block Ce1 is smaller than the maximum width of the first drive electrode block De1.
  • the first driving electrode block De1 has five internal angles.
  • the five internal angles may include two right angles, two obtuse angles and one acute angle.
  • the first connecting electrode block Ce1 runs along the first driving electrode block De1 from the side where the acute angle is located.
  • a driving electrode block De1 extends in a direction away from the light emitting element of the second sub-pixel G2.
  • the orthographic projection of the first connecting electrode block Ce1 on the base substrate 10 and the orthographic projection of the light-emitting layer 1203a of the light-emitting element of the first sub-pixel G1 on the base substrate 10 do not overlap, and the first The orthographic projection of a connecting electrode block Ce1 on the base substrate 10 and the orthographic projection of the control terminal 1221a of the pixel circuit of the first sub-pixel G1 on the base substrate 10 do not overlap either.
  • the present disclosure is not limited to this.
  • the orthographic projection of the first connecting electrode block Ce1 on the base substrate 10 and the orthographic projection of the control terminal 1221a of the pixel circuit of the first sub-pixel G1 on the base substrate 10 may also be partially overlapping.
  • the display substrate 100 further includes an intermediate layer 101.
  • the pixel circuit 121 of each sub-pixel is located between the intermediate layer 101 and the base substrate 10
  • the light emitting element 120 is located on the side of the intermediate layer 101 away from the base substrate 10.
  • the intermediate layer 101 is located between the light-emitting element 120 and the base substrate 10.
  • the layers where the light-emitting elements of all sub-pixels are located constitute the first functional layer group
  • the layers where the pixel circuits of all the sub-pixels are located constitute the second functional layer group, that is to say, it is perpendicular to the base substrate.
  • the first functional layer group is located on the side of the intermediate layer 101 away from the base substrate 10
  • the second functional layer group is located on the side of the intermediate layer 101 close to the base substrate 10, that is, the second functional layer
  • the group is located between the intermediate layer 101 and the base substrate 10
  • the intermediate layer 101 is located between the first functional layer group and the second functional layer group.
  • the intermediate layer 101 is located between the first functional layer group and the second functional layer group.
  • the driving circuit 122, the data writing circuit 126, the storage circuit 127, the threshold compensation circuit 128, and the reset circuit 129 shown in FIG. 3A are all located in the second functional layer group.
  • the first parasitic circuit 125a in the pixel circuit 121a of the first sub-pixel G1 and the first parasitic circuit 125b in the pixel circuit 121b of the second sub-pixel G2 are also located in the second functional layer group.
  • the first functional layer group may include multiple sub-layers.
  • the first functional layer group may include the first light-emitting voltage application electrode 1201a of the light-emitting element of the first sub-pixel G1.
  • the second functional layer group may also include multiple sublayers.
  • the second functional layer group may include the sublayer where each element in the pixel circuit of the first subpixel G2 is located.
  • the second The functional layer group may include the sublayer where the gate of the transistor is located, the sublayer where the source and drain are located, the sublayer where the active layer is located, the sublayer where the gate insulating layer is located, and so on.
  • the intermediate layer 101 may be a flat layer.
  • the first light-emitting voltage application electrode 1201a of the light-emitting element of the first sub-pixel G1 is disposed on the light-emitting element of the first sub-pixel G1.
  • the second light emitting voltage applying electrode 1202 of the light emitting element of the first sub-pixel G1 is arranged on the side of the light emitting layer 1203a of the light emitting element of the first subpixel G1 away from the intermediate layer 101 .
  • the intermediate layer 101 includes a first via h1, and the first connecting electrode block Ce1 extends to the first via h1 and is electrically connected to the pixel circuit of the first sub-pixel G1 through the first via h1
  • the first connection electrode block Ce1 is electrically connected to the second light emission control circuit 124a of the pixel circuit of the first sub-pixel G1 through the first via hole h1.
  • the first connection electrode block Ce1 may cover and fill the first via hole h1.
  • the first connection electrode block Ce1 is electrically connected to the second electrode of the second light-emitting control transistor T5 of the pixel circuit of the first sub-pixel G1 through the first via hole h1.
  • the pixel circuit 121 may include an active semiconductor layer 310, a gate metal layer (including a first conductive layer 320 and a second conductive layer 330), and a source and drain metal layer 340, which are perpendicular to In the direction of the base substrate 10, the active semiconductor layer 310 is located between the base substrate 10 and the gate metal layer, and the gate metal layer is located between the active semiconductor layer 310 and the source-drain metal layer 340, for example, the gate The first conductive layer 320 of the metal layer is located between the active semiconductor layer 310 and the second conductive layer 330 of the gate metal layer, and the second conductive layer 330 of the gate metal layer is located between the first conductive layer 320 and the gate metal layer. Between the source and drain metal layers 340.
  • the respective transistors in the pixel circuit 121 of each sub-pixel are all located in the active semiconductor layer 310, and the gates of each transistor in the pixel circuit 121 are all located in the first conductive layer 320 of the gate metal layer.
  • the source and drain of each transistor in the pixel circuit 121 are all located in the source-drain metal layer 340.
  • the first connection electrode block Ce1 extends to the source and drain metal layers of the pixel circuit through the first via hole h1.
  • the first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel G2 further includes a second connection electrode block Ce2, and the second connection electrode block Ce2 is electrically connected to the second driving electrode block De2.
  • the second connecting electrode block Ce2 and the second driving electrode block De2 are integrally provided. It should be noted that in other examples, the second connecting electrode block Ce2 and the second driving electrode block De2 can also be separately provided, as long as the second connecting electrode block Ce2 and the second driving electrode block De2 can be electrically connected to each other. .
  • the second connecting electrode block Ce2 is used to connect the second driving electrode block De2 and the pixel circuit of the second sub-pixel G2.
  • the second connecting electrode block Ce2 is located on the side of the second driving electrode block De2 away from the light-emitting element of the first sub-pixel G1, that is, as shown in FIG.
  • the second driving electrode block De2 is located between the second connecting electrode block Ce2 and the first driving electrode block De1.
  • the second connecting electrode block Ce2 and the second driving electrode block De2 are located on the same layer.
  • the second connecting electrode block Ce2 and the second driving electrode block De2 may be formed simultaneously by the same patterning process.
  • the shape of the second connecting electrode block Ce2 may be a regular shape, such as a rectangle, a rhombus, etc.; the shape of the second connecting electrode block Ce2 may also be an irregular shape.
  • the width of the second connection electrode block Ce2 is smaller than the maximum width of the second drive electrode block De2.
  • the second driving electrode block De2 has five internal angles, and the five internal angles may include two right angles, two obtuse angles and one acute angle.
  • the second connecting electrode block Ce2 runs along the first side from the side where the acute angle of the second driving electrode block De2 is located.
  • the two driving electrode blocks De2 extend in a direction away from the light-emitting element of the first sub-pixel G1.
  • the shape of the first connection electrode block Ce1 and the shape of the second connection electrode block Ce2 may be the same.
  • the orthographic projection of the second connecting electrode block Ce2 on the base substrate 10 and the orthographic projection of the light-emitting layer 1203a of the light-emitting element of the second sub-pixel G2 on the base substrate 10 do not overlap, and the first The orthographic projection of the two connecting electrode blocks Ce2 on the base substrate 10 and the orthographic projection of the control terminal 1221b of the pixel circuit of the second sub-pixel G2 on the base substrate 10 do not overlap.
  • the present disclosure is not limited to this.
  • the orthographic projection of the second connecting electrode block Ce2 on the base substrate 10 and the orthographic projection of the control terminal 1221b of the pixel circuit of the second sub-pixel G2 on the base substrate 10 may also be partially overlapping.
  • the first light-emitting voltage application electrode 1201b of the light-emitting element of the second sub-pixel G2 is disposed on the light-emitting element of the second sub-pixel G2.
  • the side of the light-emitting layer 1203a close to the intermediate layer 101, the second light-emitting voltage applying electrode 1202 of the light-emitting element of the second sub-pixel G2 is arranged on the side of the light-emitting layer 1203a of the light-emitting element of the second sub-pixel G2 away from the intermediate layer 101 .
  • the intermediate layer 101 includes a second via hole h2, and the second connecting electrode block Ce2 extends to the second via hole h2 and is electrically connected to the pixel circuit of the second sub-pixel G2 through the second via hole h2.
  • the second connection electrode block Ce2 is electrically connected to the second light emission control circuit 124b of the pixel circuit of the second sub-pixel G2 through the second via hole h2.
  • the second connection electrode block Ce2 may cover and fill the second via hole h2.
  • the second connection electrode block Ce2 is electrically connected to the second electrode of the second light-emitting control transistor T5 of the pixel circuit 121b of the second sub-pixel G2 through the second via hole h2.
  • the second connection electrode block Ce2 extends to the source and drain metal layers of the pixel circuit through the second via hole h2.
  • the third sub-pixel R and the fourth sub-pixel B are arranged along the second direction Y, and in the second direction Y, the first sub-pixel G1 and the second The sub-pixel G2 is located between the third sub-pixel R and the fourth sub-pixel B, the second direction Y is parallel to the surface of the base substrate 10, and the first direction X and the second direction Y are perpendicular to each other.
  • the line connecting the center of the first sub-pixel G1 and the center of the second sub-pixel G2 is the first center line
  • the center of the third sub-pixel R and the center of the fourth sub-pixel B are The connection is the second center line.
  • the length of the first centerline is shorter than the length of the second centerline.
  • the first center line and the second center line are perpendicular to each other and bisect each other, and the first center line is substantially parallel to the first direction X, and the second center line is substantially parallel to the second direction Y.
  • the light-emitting element of the third sub-pixel R includes a first light-emitting voltage applying electrode, a second light-emitting voltage applying electrode, and a light-emitting layer.
  • the light-emitting element of the fourth sub-pixel B includes a first light-emitting voltage applying electrode 1201d.
  • the portion where the planar second light-emitting voltage application electrode 1202 overlaps with the first light-emitting voltage application electrode of the light-emitting element of the third sub-pixel R can be represented as the third sub-pixel R
  • the second light-emitting voltage application electrode of the light-emitting element; for the fourth sub-pixel B, the area where the planar second light-emitting voltage application electrode overlaps the first light-emitting voltage application electrode of the light-emitting element of the fourth sub-pixel B can be expressed as The second light-emitting voltage application electrode of the light-emitting element of the fourth sub-pixel B.
  • the second light-emitting voltage application electrode of the light-emitting element of the first sub-pixel G1 the second light-emitting voltage application electrode of the light-emitting element of the second sub-pixel G2, and the second light-emitting voltage application of the light-emitting element of the third sub-pixel R
  • the electrode and the second light-emitting voltage applying electrode of the light-emitting element of the fourth sub-pixel B are integrated.
  • the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element of the third sub-pixel R on the base substrate 10 and the orthographic projection of the control terminal of the pixel circuit of the third sub-pixel R on the base substrate 10 Can overlap at least partially.
  • the orthographic projection of the first light-emitting voltage application electrode 1201d of the light-emitting element of the fourth sub-pixel B on the base substrate 10 and the control end of the driving circuit of the pixel circuit of the fourth sub-pixel B are on the base substrate 10.
  • the projections can also overlap at least partially.
  • the orthographic projection of the control terminal 1221d of the driving circuit of the pixel circuit of the fourth sub-pixel B on the base substrate 10 is located at the first light-emitting voltage application electrode 1201d of the light-emitting element of the fourth sub-pixel B. In the orthographic projection on the base substrate 10.
  • the first light-emitting voltage applying electrode of the light-emitting element of the third sub-pixel R includes a third driving electrode block De3 and a third connecting electrode block Ce3 that are electrically connected to each other
  • the fourth sub-pixel B The first light-emitting voltage applying electrode 1201d of the light-emitting element includes a fourth driving electrode block De4 and a fourth connection electrode block Ce4 that are electrically connected to each other.
  • the orthographic projection of the control terminal 1221c of the driving circuit of the pixel circuit of the third sub-pixel R on the base substrate 10 and the orthographic projection of the third driving electrode block De3 on the base substrate 10 at least partially overlap; as shown in FIG.
  • the orthographic projection of the control terminal 1221d of the driving circuit of the pixel circuit of the fourth sub-pixel B on the base substrate 10 and the orthographic projection of the fourth driving electrode block De4 on the base substrate 10 at least partially overlap, for example, the fourth The orthographic projection of the control terminal 1221 d of the driving circuit of the pixel circuit of the sub-pixel B on the base substrate 10 is within the orthographic projection of the fourth driving electrode block De4 on the base substrate 10.
  • the third connecting electrode block Ce3 is used to connect the third driving electrode block De3 and the pixel circuit of the third sub-pixel R; the fourth connecting electrode block Ce4 is used to connect the fourth driving electrode block De4 and the pixel of the fourth sub-pixel B Circuit.
  • the pixel circuit of the third sub-pixel R further includes a third parasitic circuit
  • the pixel circuit of the fourth sub-pixel B further includes a fourth parasitic circuit.
  • the third parasitic circuit includes a fourth capacitor
  • the fourth parasitic circuit includes a fifth capacitor.
  • the third drive electrode block De3 is multiplexed as the first pole of the fourth capacitor
  • the control terminal of the drive circuit of the third sub-pixel R is multiplexed as the second pole of the fourth capacitor
  • the fourth drive electrode block De4 is multiplexed as the fifth pole.
  • the first pole of the capacitor and the control terminal of the driving circuit of the fourth sub-pixel B are multiplexed as the second pole of the fifth capacitor.
  • the shape of the third driving electrode block De3 may be a regular hexagon, and the shape of the fourth driving electrode block De4 may also be a regular hexagon.
  • the shape of the third connecting electrode block Ce3 may be an irregular hexagon, and the shape of the fourth connecting electrode block Ce4 may also be an irregular hexagon.
  • the shape of the third driving electrode block De3 and the fourth driving electrode block De4 may also be rectangular or oblong.
  • the present disclosure does not specifically limit the shapes of the third driving electrode block De3, the third connecting electrode block Ce3, the fourth driving electrode block De4, and the fourth connecting electrode block Ce4.
  • the third connection electrode block Ce3 may be a part protruding outward from one side (for example, the side of the lower right side of the hexagon) of the third driving electrode block De3 of the hexagon;
  • the fourth connection electrode The block Ce4 may be a part protruding outward from one side of the fourth driving electrode block De4 of the hexagon (for example, the side of the lower left side of the hexagon).
  • the area of the driving electrode block of each sub-pixel can be specifically set according to the luminous efficiency of the luminescent material. For example, if the luminous efficiency of the luminescent material is higher, the area of the driving electrode block of the sub-pixel can be smaller; If the luminous efficiency is low, the area of the driving electrode block of the sub-pixel can be larger.
  • the area of the third driving electrode block De3 is smaller than the area of the fourth driving electrode block De4.
  • the area of the third driving electrode block De3 is larger than the area of the first driving electrode block De1, and the area of the third driving electrode block De3 is larger than the area of the second driving electrode block De2.
  • the third driving electrode block De3 and the third connecting electrode block Ce3 are integrally arranged, and the fourth driving electrode block De4 and the fourth connecting electrode block Ce4 are also integrally arranged.
  • the third driving electrode block De3 and the third connecting electrode block Ce3 can also be separately provided, as long as the third driving electrode block De3 and the third connecting electrode block Ce3 can be electrically connected to each other.
  • the fourth driving electrode block De4 and the fourth connecting electrode block Ce4 can also be separately provided, as long as the fourth driving electrode block De4 and the fourth connecting electrode block Ce4 can be electrically connected to each other.
  • the third driving electrode block De3 and the third connecting electrode block Ce3 are located in the same layer.
  • the fourth driving electrode block De4 and the fourth connecting electrode block Ce4 are located in the same layer.
  • the first light-emitting voltage application electrode of the light-emitting element of the third sub-pixel R is disposed on the third sub-pixel.
  • the light-emitting layer of the light-emitting element of R is close to the intermediate layer 101
  • the second light-emitting voltage applying electrode of the light-emitting element of the third sub-pixel R is disposed on the light-emitting layer of the light-emitting element of the third sub-pixel R far from the intermediate layer 101.
  • the first light-emitting voltage application electrode 1201d of the light-emitting element of the fourth sub-pixel B is provided on the light-emitting element of the fourth sub-pixel B
  • the second light-emitting voltage application electrode 1202d of the light-emitting element of the fourth sub-pixel B is disposed on the side of the light-emitting layer 1203d of the light-emitting element of the fourth sub-pixel B away from the intermediate layer 101.
  • the intermediate layer 101 includes a third via h3, and the third connecting electrode block Ce3 extends to the third via h3 and is electrically connected to the pixel circuit of the third sub-pixel R through the third via h3.
  • the third connection electrode block Ce3 may cover and fill the third via hole h3.
  • the intermediate layer 101 includes a fourth via h4, and the fourth connection electrode block Ce4 extends to the fourth via h4 and is electrically connected to the pixel circuit of the fourth sub-pixel B through the fourth via h4.
  • the fourth connection electrode block Ce4 may cover and fill the fourth via hole h4.
  • connection electrode block Ce3 extends to the source and drain metal layer of the pixel circuit through the third via hole h3; the fourth connection electrode block Ce4 extends to the source and drain metal layer of the pixel circuit through the fourth via hole h4.
  • the third connecting electrode block Ce3 extends to the source/drain metal layer of the pixel circuit through the third via hole h3 so as to communicate with the second light-emitting control transistor of the third sub-pixel R located in the source/drain metal layer of the pixel circuit.
  • Two-pole electrical connection For example, the fourth connecting electrode block Ce4 extends to the source and drain metal layer of the pixel circuit through the fourth via hole h4 so as to communicate with the second light-emitting control transistor of the fourth sub-pixel B located in the source and drain metal layer of the pixel circuit. Two-pole electrical connection.
  • the third connection electrode Ce3 is located on the third drive electrode block De3 away from the auxiliary electrode block Ae of the first sub-pixel G1.
  • the third connection electrode Ce3 is located on the side of the third drive electrode block De3 close to the fourth drive electrode block De4, that is, in the example shown in FIGS. 6A and 6B, the first The three-connection electrode block Ce3 is located on the lower right side of the third driving electrode block De3, that is, the shape of the first light-emitting voltage application electrode 1201c of the light-emitting element of the third sub-pixel R may be a Q-shaped mirror-symmetrical shape.
  • the fourth connection electrode Ce4 is located on the fourth drive electrode block De4 away from the auxiliary electrode block Ae of the first sub-pixel G1.
  • the fourth connection electrode Ce4 is located on the side of the fourth drive electrode block De4 close to the third drive electrode block De3, that is, in the example shown in FIGS. 6A and 6B, the first The four-connected electrode block Ce4 is located on the lower left side of the fourth driving electrode block De4, that is, the shape of the first light-emitting voltage application electrode 1201d of the light-emitting element of the fourth sub-pixel B may be Q-shaped.
  • the third connecting electrode Ce3 is electrically connected to the second light emission control circuit 124c of the pixel circuit of the third sub-pixel R through the third via hole h3.
  • the third connecting electrode Ce3 is electrically connected to the third sub-pixel through the third via hole h3.
  • the second electrode of the second light-emitting control transistor of the pixel circuit of R is electrically connected.
  • the fourth connection electrode block Ce4 is electrically connected to the second light emission control circuit 124d of the pixel circuit of the fourth sub-pixel B through the fourth via hole h4.
  • the fourth connection electrode block Ce4 is electrically connected through the fourth The via hole h4 is electrically connected to the second pole of the second light-emitting control transistor of the pixel circuit of the fourth sub-pixel B.
  • an intermediate layer (not shown) is formed on the source and drain metal layer 340 shown in FIG. 6D, and the first light-emitting voltage application electrode of the light-emitting element of each sub-pixel is disposed on the intermediate layer.
  • the fourth connecting electrode block Ce4 and the fourth driving electrode block De4 of the first light-emitting voltage applying electrode of the light-emitting element are both arranged on the intermediate layer, and the first connecting electrode block Ce1 of the first sub-pixel G1 is connected to the first via hole h1.
  • the second light-emitting control transistor T5 in the pixel circuit 121a of the first sub-pixel G1 is connected, and the second connection electrode block Ce2 of the second sub-pixel G2 is connected to the first in the pixel circuit 121b of the second sub-pixel G2 through the second via hole h2.
  • the two light-emitting control transistors T5 are connected.
  • the third connecting electrode block Ce3 of the third sub-pixel R is connected to the second light-emitting control transistor T5 in the pixel circuit of the third sub-pixel R through the third via hole h3.
  • the fourth connection electrode block Ce4 is connected to the second light emission control transistor T5 in the pixel circuit of the fourth sub-pixel B through the third via hole h4.
  • the orthographic projection of the auxiliary electrode block Ae of the first sub-pixel G1 on the base substrate and the orthographic projection of the gate of the driving transistor in the pixel circuit 121a of the first sub-pixel G1 on the base substrate at least partially overlap.
  • the orthographic projection of the second driving electrode block De2 of the two sub-pixels G2 on the base substrate and the orthographic projection of the gate of the driving transistor in the pixel circuit 121b of the second sub-pixel G2 on the base substrate at least partially overlap
  • the third The orthographic projection of the third driving electrode block De3 of the sub-pixel R on the base substrate and the orthographic projection of the gate of the driving transistor in the pixel circuit of the third sub-pixel R on the base substrate at least partially overlap
  • the fourth sub-pixel The orthographic projection of the fourth driving electrode block De4 of B on the base substrate and the orthographic projection of the gate of the driving transistor in the pixel circuit of the fourth sub-pixel B on the base substrate at least partially overlap.
  • FIG. 6E shows the driving electrode block of each sub-pixel, the auxiliary electrode block of each first sub-pixel, and the connecting electrode block of each sub-pixel
  • FIG. 6E also shows the process corresponding to each connecting electrode block. hole.
  • the connection electrode block of each sub-pixel may cover and fill the corresponding via hole.
  • the first connection electrode block covers and fills the first via hole h1
  • the second connection electrode block covers and fills the second via hole h2.
  • the third connection electrode block covers and fills the third via hole h3
  • the fourth connection electrode block covers and fills the fourth via hole h4.
  • each via hole is located in the corresponding Connect the top of the electrode block.
  • the vias are arranged in multiple rows of vias, and the vias in each row of vias follow the third via h3, the first via h1, and the fourth via.
  • the sequence of the hole h4 and the second via h2, that is, the third via h3, the first via h1, the fourth via h4, and the second via h2 is an arrangement period HT1.
  • the first A via hole h1 corresponds to the first sub-pixel G1 located in the second row and adjacent to the first via hole h1
  • the second via hole h2 corresponds to the second sub pixel located in the first row and adjacent to the second via hole h2 Pixel G2
  • the third via hole h3 corresponds to the third sub-pixel R located in the first row and adjacent to the third via hole h3
  • the fourth via hole h4 corresponds to located in the first row adjacent to the fourth via hole h4
  • the fourth sub-pixel B corresponds to the first sub-pixel G1 located in the second row and adjacent to the first via hole h1
  • the second via hole h2 corresponds to the second sub pixel located in the first row and adjacent to the second via hole h2 Pixel G2
  • the third via hole h3 corresponds to the third sub-pixel R located in the first row and adjacent to the third via hole h3
  • the fourth via hole h4 corresponds to located in the first row adjacent to the fourth via hole h4
  • the vias in each row of vias are located on the same straight line, that is, the first via h1, the third via h3, the second via h2, and the second via h2 in each arrangement period HT1
  • the fourth via hole h4 is located on the same straight line, and each arrangement period HT1 is also located on the same straight line.
  • the distance between any two adjacent via holes is the first fixed distance d1, that is, as shown in FIG. 6E, in the arrangement period HT1, the first via hole h1 and The distance between the fourth via hole h4 is the first fixed distance d1, the distance between the first via hole h1 and the third via hole h3 is also the first fixed distance d1, the second via hole h2 and the third via hole h3 The distance therebetween is also the first fixed distance d1, and the distance between the second via hole h2 and the fourth via hole h4 is also the first fixed distance d1.
  • "two adjacent vias" means that there is no via between the two vias, and the first fixed distance d1 can indicate the center of two adjacent vias in the second direction Y. The distance between.
  • each of the first via holes h1 and each of the second via holes h2 are arranged into a plurality of first via holes
  • each of the third via holes h3 and each of the fourth via holes h4 is arranged as a plurality of second via rows.
  • the first via rows and the second via rows are alternately arranged, that is, the plurality of first via rows can be odd rows, but more
  • the second via column is an even column.
  • each first via row each first via h1 and each second via h2 are located on the same straight line, and in each second via row, each third via h3 and each fourth via The hole h4 is also on the same straight line.
  • the distance between any adjacent first via h1 and second via h2 is the second fixed distance d2, and any adjacent third via h3 and fourth via h4
  • the distance between is the third fixed distance d3, and the second fixed distance d2 and the third fixed distance d3 are equal.
  • the second fixed distance d2 may indicate the distance between the center of the first via h1 and the center of the second via h2 that are adjacent in the first direction X
  • the third fixed distance d3 may indicate the The distance between the center of the adjacent third via hole h3 and the center of the fourth via hole h4 in a direction X.
  • the multiple repeating units 11 are arranged along the second direction Y to form multiple repeating unit groups, and the multiple repeating unit groups are arranged along the first direction X.
  • the first connection electrode block, the second connection electrode block, the third connection electrode block, and the fourth connection electrode block are located between two adjacent repeating unit groups.
  • at least a part of the auxiliary electrode block is located on the side of the auxiliary electrode block away from the first driving electrode block and between two adjacent repeating units in the repeating unit group adjacent to the repeating unit group where the auxiliary electrode block is located .
  • the P-th repeating unit group is located in the first row, and the P+1-th repeating unit group is located in the second row.
  • the repeating unit located in the P+1th repeating unit group at least a part of the auxiliary electrode block Ae is located on the side of the auxiliary electrode block Ae away from the first driving electrode block De1 and is located in the repeating unit group ( That is, between the adjacent two repeating units in the P+1th repeating unit group (that is, the Pth repeating unit group), for example, as shown in FIG. 6E, the repeating unit in the second row
  • At least a part of the auxiliary electrode block Ae in the unit extends to the first row and is located between two adjacent repeating units in the first row.
  • at least a part of the auxiliary electrode block Ae in the repeating unit in the second row is located Between adjacent third sub-pixel R and fourth sub-pixel B in the first row.
  • the second light emission control transistor of the second light emission control circuit 124a of the first sub-pixel G1 includes a second electrode 1241a (eg, drain) and an active layer 1242a.
  • the driving transistor of the driving circuit of the first sub-pixel G1 includes a gate 1221a (that is, a control terminal of the driving circuit 122a) and an active layer 1222a. It should be noted that FIG. 6C does not show the gate and first pole of the second light-emitting control transistor of the first sub-pixel G1, the first pole and the second pole of the driving transistor of the first sub-pixel G1, and so on.
  • a gate insulating layer is provided between the active semiconductor layer 310 and the first conductive layer 320, that is, as shown in FIG. 6C, a gate insulating layer is provided between the gate 1221a and the active layer 1222a of the driving transistor of the first sub-pixel G1.
  • a gate insulating layer 131 which covers the entire display substrate 100. Therefore, a gate insulating layer 131 is also provided between the gate of the second light-emitting control transistor and the active layer.
  • the gate 1221 a of the driving transistor of the first sub-pixel G1 is disposed on the side of the gate insulating layer 131 away from the base substrate 10. As shown in FIG.
  • a first emission control signal line EM1a and a second emission control circuit connected to the first emission control circuit of the first sub-pixel G1 are also provided.
  • the second light-emitting control signal line EM2a connected to the circuit.
  • the orthographic projection of the first connection electrode block Ce1 on the base substrate 10 and the second emission control signal line EM2a ie, the second emission control signal line EM2a
  • the orthographic projections of the first emission control signal line EM1a) connected to the first emission control circuit of the first sub-pixel G1 on the base substrate 10 at least partially overlap.
  • a first insulating layer 132 is further provided on the gate 1221a of the driving transistor of the first sub-pixel G1, and a first insulating layer 132 is provided on the side of the first insulating layer 132 away from the base substrate 10.
  • a second insulating layer 133 is provided on the side of the second pole CC2a of the third capacitor C2 away from the base substrate 10.
  • the second electrode 1241a of the second light-emitting control transistor of the first sub-pixel G1 is arranged on the side of the second insulating layer 133 away from the base substrate 10, and passes through the second insulating layer 133, the first insulating layer 132 and the gate electrode.
  • the via 388a of the insulating layer 131 is electrically connected to the active layer 1242a of the second light emission control transistor.
  • the first insulating layer 132 and the second insulating layer 133 also cover the entire display substrate 100.
  • a first connection portion 341a of the first sub-pixel G1 is further provided on the side of the second insulating layer 133 away from the base substrate 10, and the first connection portion 341a of the first sub-pixel G1 penetrates through the second insulating layer 133.
  • the first pole CC1a of the third capacitor C2 of the first sub-pixel G1 and the via 385a of the first insulating layer 132 are electrically connected to the gate 1221a of the driving transistor of the first sub-pixel G1.
  • the first pole CC3a ie, the auxiliary electrode block Ae
  • the second pole CC4a ie, the first sub-pixel of the first capacitor C11
  • metal layers such as the first electrode CC1a of the third capacitor C2 of the first sub-pixel G1, the first connection portion 341a of the first sub-pixel G1, and so on.
  • Parasitic capacitance may also exist between the electrode block Ae and the first connection portion 341a of the first sub-pixel G1, and there may also be parasitic capacitance between the auxiliary electrode block Ae and the first pole CC1a of the third capacitor C2 of the first sub-pixel G1. Capacitance, there may also be a parasitic capacitance between the first pole CC1a of the third capacitor C2 of the first sub-pixel G1 and the first connection portion 341a of the first sub-pixel G1. At the gate of the driving transistor of the first sub-pixel G1 There may also be a parasitic capacitance between 1221a and the first connecting portion 341a of the first sub-pixel G1.
  • the gate 1221a of the driving transistor of the first sub-pixel G1 and the first pole CC1a of the third capacitor C2 of the first sub-pixel G1 There may also be parasitic capacitances between them, and the positions and sizes of these parasitic capacitances are related to the specific layout structure of the display substrate, which is not described in detail in this disclosure.
  • the second electrode 1241a and the first connecting portion 341a of the second light-emitting control transistor of the first sub-pixel G1 are both located in the source and drain metal layer 340 of the pixel circuit, and the gate 1221a of the driving transistor of the first sub-pixel G1 and The first emission control signal line EM1a/the second emission control signal line EM2a are both located in the first conductive layer 320 of the pixel circuit, and the first pole CC1a of the third capacitor C2 of the first sub-pixel G1 is located in the second conductive layer of the pixel circuit
  • the active layer 1242a of the second light emission control transistor and the active layer 1222a of the driving transistor of the first subpixel G1 are located in the active semiconductor layer 310 of the pixel circuit.
  • the first connecting electrode block Ce1 extends to the source and drain metal layer 340 of the pixel circuit through the first via hole h1, so as to interact with the second light emission control of the first sub-pixel G1 in the source and drain metal layer 340 of the pixel circuit.
  • the second pole 1241a of the transistor is electrically connected.
  • a first reset power supply connected to the pixel circuit of the second sub-pixel G2 is provided between the first connection electrode block Ce1 and the base substrate 10.
  • the signal line Init1b/the second reset power signal line Init2b, at least part of the second connection portion 342b of the second sub-pixel G2 and the via hole 386b, the second connection portion 342b of the second sub-pixel G2 passes through the via hole 386b and the first The reset power signal line Init1b/the second reset power signal line Init2b are electrically connected.
  • the first reset power signal line Init1b/the second reset power signal line Init2b is located in the second conductive layer 330 of the pixel circuit.
  • a first reset control connected to the pixel circuit of the second sub-pixel G2 is provided between the first drive electrode block De1 and the base substrate 10.
  • the second pole 1291b of the first reset transistor T6 of the second subpixel G2 also the second pole of the threshold compensation transistor T3 of the second subpixel G2), the first pole of the first reset transistor T6 of the second subpixel G2 1292b (also the first pole of the second reset transistor T7 of the second sub-pixel G2), the second connection portion 342b of the second sub-pixel G2 passes through the via 387b to the first electrode of the first reset transistor T6 of the second sub-pixel G2
  • One pole 1292b is electrical
  • the second light emission control transistor of the second light emission control circuit 124b of the second sub-pixel G2 includes a second electrode 1241b (eg, drain) and an active layer 1242b.
  • the driving transistor of the driving circuit of the second sub-pixel G2 includes a gate 1221b (that is, a control terminal of the driving circuit 122b) and an active layer 1222b. It should be noted that FIG. 6C does not show the gate and first pole of the second light emission control transistor of the second sub-pixel G2, the first pole and the second pole of the driving transistor of the second sub-pixel G2, and so on.
  • a gate insulating layer 131 is also provided between the gate 1221b and the active layer 1222b of the driving transistor of the second sub-pixel G2.
  • a first insulating layer 132 is also provided on the gate 1221b of the driving transistor of the second sub-pixel G2.
  • a first pole CC1b of the third capacitor C2 of the second sub-pixel G2 is provided on the side of the first insulating layer 132 away from the base substrate 10.
  • the second electrode 1241b of the second light emission control transistor of the second sub-pixel G2 is arranged on the side of the second insulating layer 133 away from the base substrate 10, and passes through the second insulating layer 133, the first insulating layer 132 and the gate electrode.
  • the via 388b of the insulating layer 131 is electrically connected to the active layer 1242b of the second light-emitting control transistor of the second sub-pixel G2.
  • a first emission control signal line EM1b and a second emission control signal line EM1b connected to the first emission control circuit of the second sub-pixel G2 are further provided on the side of the gate insulating layer 131 away from the base substrate 10.
  • the orthographic projection of the second connecting electrode block Ce2 on the base substrate 10 and the second emission control signal line EM2b ie, the second emission control signal line EM2b
  • the orthographic projections of the first emission control signal line EM1b) connected to the first emission control circuit of the second sub-pixel G2 on the base substrate 10 at least partially overlap.
  • a first scan signal line Ga1b electrically connected to the data writing transistor of the second sub-pixel G2 and a second The threshold value of the sub-pixel G2 compensates the second scanning signal line Ga2b to which the transistor is electrically connected.
  • the first connecting portion 341b of the second sub-pixel G2 is further provided on the side of the second insulating layer 133 away from the base substrate 10, and the first connecting portion 341b of the second sub-pixel G2 passes through the second insulating layer 133.
  • the first electrode CC1b of the third capacitor C2 of the second sub-pixel G2 and the via 385b of the first insulating layer 132 are electrically connected to the gate 1221b of the driving transistor of the second sub-pixel G2.
  • the orthographic projection of the first connection portion 341b of the second sub-pixel G2 on the base substrate 10 and the orthographic projection of the gate 1221b of the driving transistor of the second sub-pixel G2 on the base substrate 10 at least partially overlap, that is, The orthographic projection of the first connecting portion 341b on the base substrate 10, the orthographic projection of the gate 1221b of the driving transistor of the second sub-pixel G2 on the base substrate 10, and the orthographic projection of the second drive electrode block De2 on the base substrate 10
  • the orthographic projections overlap at least partially.
  • the first pole CC1b ie, the second driving electrode block De2
  • the second pole ie, the second sub-pixel
  • the second capacitor ie, the second sub-pixel
  • Parasitic capacitance may also exist between the second sub-pixel G2 and the first pole CC1b of the third capacitor C2 of the second sub-pixel G2 and the first connection portion 341b of the second sub-pixel G2. There may also be a parasitic capacitance between the gate 1221b of the driving transistor and the first connection portion 341b of the second sub-pixel G2. The gate 1221b of the driving transistor of the second sub-pixel G2 and the third capacitor C2 of the second sub-pixel G2 There may also be parasitic capacitances between the first poles CC1b. The positions and sizes of these parasitic capacitances are related to the specific layout structure of the display substrate, which is not described in detail in this disclosure.
  • the second electrode 1241b and the first connecting portion 341b of the second light-emitting control transistor of the second sub-pixel G2 are both located in the source and drain metal layer 340 of the pixel circuit, and the gate 1221b of the driving transistor of the second sub-pixel G2 and The first light emission control signal line EM1b/the second light emission control signal line EM2b is located in the first conductive layer 320 of the pixel circuit, and the first pole CC1b of the third capacitor C2 of the second sub-pixel G2 is located in the second conductive layer 330 of the pixel circuit
  • the active layer 1242b of the second light emission control transistor and the active layer 1222b of the driving transistor are located in the active semiconductor layer 310 of the pixel circuit.
  • the second connecting electrode block Ce2 extends to the source and drain metal layer 340 of the pixel circuit through the second via hole h2, so as to communicate with the second light-emitting control transistor of the second sub-pixel G2 located on the source and drain metal layer 340 of the pixel circuit.
  • the second pole 1241b is electrically connected.
  • the orthographic projection of the first light-emitting voltage application electrode of the second sub-pixel G2 on the base substrate is consistent with the active semiconductor layer corresponding to the pixel circuit of the second sub-pixel G2 on the base substrate.
  • the shape of the overlapped portion of the orthographic projection on the upper projection may include a "several" shape, and the active semiconductor layer corresponding to the "several" shape includes the active layer of the driving transistor of the pixel circuit of the second sub-pixel G2.
  • the portion of the active semiconductor layer corresponding to the pixel circuit of the second sub-pixel G2 that overlaps the first light-emitting voltage application electrode of the second sub-pixel G2 may include the portion of the second sub-pixel G2.
  • the active layer of the driving transistor of the pixel circuit may also include the second light-emitting control of the pixel circuit of the second sub-pixel G2. Drain region of transistor T5.
  • the orthographic projection of the first light-emitting voltage application electrode of the second sub-pixel G2 on the base substrate is similar to that of the source and drain metal layers corresponding to the pixel circuit of the second sub-pixel G2 on the base substrate.
  • the orthographic projections on the substrate partially overlap.
  • the portion of the source and drain metal layer corresponding to the pixel circuit of the second sub-pixel G2 that overlaps the first light-emitting voltage application electrode of the second sub-pixel G2 includes a portion of the first connection portion (That is, the portion of the first connecting portion that overlaps the gate of the driving transistor of the pixel circuit of the second sub-pixel G2) and the third connecting portion (that is, the second light-emitting control transistor T5 of the pixel circuit of the second sub-pixel G2) Drain), a part of the first power supply signal line VDD1, etc.
  • the active semiconductor layer corresponding to the pixel circuit of the second sub-pixel G2 crosses the first light-emitting voltage application electrode of the first sub-pixel G1.
  • the overlapped part may include the active layer and drain region of the first reset transistor T6 and the second reset transistor T7 in the reset circuit 129b in the pixel circuit of the second sub-pixel G2, and the active layer in the pixel circuit of the first sub-pixel G1.
  • the orthographic projection of the first light-emitting voltage application electrode of the first sub-pixel G1 on the base substrate corresponds to the source and drain metal layers of the pixel circuit of the first sub-pixel G1 on the base substrate.
  • the orthographic projection on the substrate and the orthographic projection of the source and drain metal layers corresponding to the pixel circuit of the second sub-pixel G2 on the base substrate partially overlap.
  • the portion of the source and drain metal layer corresponding to the pixel circuit of the second sub-pixel G2 that overlaps the first light-emitting voltage application electrode of the first sub-pixel G1 includes the first connection portion Part of the first connection part (that is, the part that overlaps the drain region of the threshold compensation transistor), the second connection part (that is, the drain of the second reset transistor of the pixel circuit of the second sub-pixel G2 and the first reset power supply The connection between the signal lines) and a part of the first power supply signal line VDD1, etc.
  • the portion of the source and drain metal layer corresponding to the pixel circuit of the first sub-pixel G1 that overlaps the first light-emitting voltage applying electrode of the first sub-pixel G1 includes a part of the first connection portion (that is, the portion of the first connection portion and the first The portion where the gate of the driving transistor of the pixel circuit of the sub-pixel G1 overlaps) and the third connection portion (that is, the drain of the second light-emitting control transistor of the pixel circuit of the first sub-pixel G1), and the like.
  • the second light emission control transistor of the second light emission control circuit 124d of the fourth sub-pixel B includes a second electrode 1241d (eg, drain) and an active layer 1242c.
  • the driving transistor of the driving circuit of the third sub-pixel R includes a gate 1221d (that is, a control terminal of the driving circuit 122d) and an active layer 1222d. It should be noted that FIG. 6D does not show the gate and first pole of the second light emission control transistor of the fourth sub-pixel B, the first pole and the second pole of the driving transistor of the fourth sub-pixel B, and so on.
  • a gate insulating layer 131 is provided between the gate 1221d of the driving transistor of the fourth subpixel B and the active layer 1222d, and a gate insulating layer 131 is provided on the gate 1221d of the driving transistor of the fourth subpixel B.
  • a first insulating layer 132 is also provided.
  • a first pole CC1d of the third capacitor C2 of the fourth sub-pixel B is provided on the side of the first insulating layer 132 away from the base substrate 10.
  • the second electrode 1241d of the second light-emitting control transistor of the fourth sub-pixel B is disposed on the side of the second insulating layer 133 away from the base substrate 10, and passes through the second insulating layer 133, the first insulating layer 132 and the gate electrode.
  • the via 388d of the insulating layer 131 is electrically connected to the active layer 1242d of the second light-emitting control transistor of the fourth sub-pixel B.
  • a first emission control signal line EM1d and a second emission control signal line EM1d connected to the first emission control circuit of the fourth sub-pixel B are also provided on the side of the gate insulating layer 131 away from the base substrate 10.
  • the second emission control signal line EM2d connected to the emission control circuit.
  • the first emission control signal line EM1d and the second emission control signal line EM2d corresponding to the fourth sub-pixel B are the same Signal line
  • the first emission control signal line EM1d/second emission control signal line EM2d and the first emission control signal line EM1b/second emission control signal line EM2b corresponding to the second sub-pixel G2 in the second row are also It is the same signal line.
  • the orthographic projection of the fourth connection electrode block Ce4 on the base substrate 10 and the second emission control signal line EM2d ie, the second emission control signal line EM2d
  • the orthographic projections of the first emission control signal line EM1d) connected to the first emission control circuit of the fourth sub-pixel B on the base substrate 10 at least partially overlap.
  • a first scan signal line Ga1d electrically connected to the data writing transistor of the fourth sub-pixel B and a fourth The threshold of the sub-pixel B compensates the second scanning signal line Ga2d to which the transistor is electrically connected.
  • the first scanning signal line Ga1d and the second scanning signal line Ga2d corresponding to the fourth sub-pixel B are the same signal line
  • the first scan signal line Ga1d/second scan signal line Ga2d and the first scan signal line Ga1b/second scan signal line Ga2b corresponding to the second sub-pixel G2 in the second row are also the same signal line.
  • the first connecting portion 341d of the fourth sub-pixel B is further provided on the side of the second insulating layer 133 away from the base substrate 10, and the first connecting portion 341d of the fourth sub-pixel B penetrates through the second insulating layer 133.
  • the first pole CC1d of the third capacitor C2 of the fourth sub-pixel B and the via 385d of the first insulating layer 132 are electrically connected to the gate 1221d of the driving transistor of the fourth sub-pixel B.
  • the orthographic projection of the first connection portion 341d of the fourth sub-pixel B on the base substrate 10 and the orthographic projection of the gate 1221d of the driving transistor of the fourth sub-pixel B on the base substrate 10 at least partially overlap, that is, The orthographic projection of the first connecting portion 341d on the base substrate 10, the orthographic projection of the gate 1221d of the driving transistor of the fourth sub-pixel B on the base substrate 10, and the fourth driving electrode block De4 on the base substrate 10
  • the orthographic projections overlap at least partially.
  • a fourth driving electrode block De4 and the gate 1221d of the driving transistor of the fourth sub-pixel B are also provided.
  • the gate 1221d of the driving transistor of the fourth sub-pixel B and the first connection portion 341d of the fourth sub-pixel B There may also be parasitic capacitances between them. There may also be parasitic capacitances between the gate 1221d of the driving transistor of the fourth sub-pixel B and the first pole CC1d of the third capacitor C2 of the fourth sub-pixel B. The location of these parasitic capacitances The size and the size are related to the specific layout structure of the display substrate, which is not described in detail in the present disclosure.
  • a first reset power signal line Init1d/second reset power signal line Init2 and a via hole 386d connected to the pixel circuit of the fourth sub-pixel B are provided on the base substrate 10; In the direction of the base substrate 10, at least part of the second connection portion 342d of the fourth sub-pixel B is provided between the fourth drive electrode block Ce1 and the base substrate 10, and the second connection portion of the fourth sub-pixel B 342d is electrically connected to the first reset power signal line Init1d/the second reset power signal line Init2d through the via 386d.
  • a first reset control connected to the pixel circuit of the fourth sub-pixel B is provided between the fourth drive electrode block De4 and the base substrate 10.
  • the signal line Rst1d/the second reset control signal line Rst2d, at least part of the second connection portion 342d of the fourth sub-pixel B, the first connection portion 341d of the fourth sub-pixel B, the via hole 387d, the via hole 384d, and the fourth sub-pixel B The second pole 1291d of the first reset transistor T6 of the pixel B (also the second pole of the threshold compensation transistor T3 of the fourth sub-pixel B), the first pole 1292d of the first reset transistor T6 of the fourth sub-pixel B (also Is the first pole of the second reset transistor T7 of the fourth sub-pixel B), the second connection portion 342d of the fourth sub-pixel B passes through the via 387d and the first pole 1292d of the first reset transistor T6 of the fourth sub-pixel B Electrically
  • the second electrode 1241d and the first connection portion 341d of the second light-emitting control transistor of the fourth sub-pixel B are both located in the source and drain metal layer 340 of the pixel circuit, and the gate 1221d of the driving transistor of the fourth sub-pixel B and The first light emission control signal line EM1d/the second light emission control signal line EM2d is located in the first conductive layer 320 of the gate metal layer of the pixel circuit of the fourth sub-pixel B, and the first electrode of the third capacitor C2 of the fourth sub-pixel B CC1d and the first reset power signal line Init1d/the second reset power signal line Init2d are located in the second conductive layer 330 of the pixel circuit, and the active layer 1242d of the second light-emitting control transistor of the fourth sub-pixel B and the active layer of the driving transistor are active
  • the layer 1222d is located in the active semiconductor layer 310 of the pixel circuit.
  • the fourth connecting electrode block Ce4 extends to the source and drain metal layer of the pixel circuit through the fourth via hole h4 so as to communicate with the second light-emitting control transistor of the fourth sub-pixel B located in the source and drain metal layer of the pixel circuit.
  • the two poles 1241d are electrically connected.
  • each circuit in the pixel circuit of the third sub-pixel R and the pixel circuit of the fourth sub-pixel B (for example, the drive circuit, the first light-emission control circuit, the second light-emission control circuit, the storage circuit, the reset circuit, and the threshold compensation circuit , Data writing circuit, etc.) are the same as the example shown in FIG. 3A.
  • the embodiment of the present disclosure also provides a display substrate.
  • the display substrate 100 includes a base substrate 10 and a plurality of repeating units 11 arranged on the base substrate 10, and each repeating unit 11 includes a plurality of sub-pixels 12.
  • Each sub-pixel 12 includes a light-emitting element 120 and a pixel circuit 121.
  • the pixel circuit 121 is used to drive the light-emitting element 120 to emit light, and the pixel circuit 121 includes a driving circuit 122.
  • the driving circuits 122 of a plurality of sub-pixels 12 are arranged in an array on the base substrate 10.
  • regions 31 to 40 may be the areas where the driving circuits of each sub-pixel on the base substrate 10 are located.
  • the example shown in 5A shows a driving circuit with two rows and five columns.
  • the driving circuit of the pixel circuit of the first sub-pixel G1 is located in area 32
  • the driving circuit of the pixel circuit of the second sub-pixel G2 is located in area 37.
  • the driving circuit of the pixel circuit of the third sub-pixel R is located in the area 38
  • the driving circuit of the pixel circuit of the fourth sub-pixel B is located in the area 36.
  • row may refer to a row corresponding to the area where each pixel circuit is located
  • column may refer to a column corresponding to the area where each pixel circuit is located.
  • the light emitting element 120 of each sub-pixel includes a first light emitting voltage applying electrode, a second light emitting voltage applying electrode, and a light emitting layer provided between the first light emitting voltage applying electrode and the second light emitting voltage applying electrode.
  • the first light-emitting voltage applying electrode is an anode
  • the second light-emitting voltage applying electrode is a cathode.
  • the plurality of sub-pixels 12 includes a first sub-pixel G1 and a second sub-pixel G2.
  • the color of the light emitted by the light-emitting element of the first sub-pixel G1 is the same as the color of the light emitted by the light-emitting element of the second sub-pixel G2.
  • the first sub-pixel G1 and the second sub-pixel G2 are both green sub-pixels.
  • the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel G1 and the first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel G2 are arranged along the first direction X.
  • the first light-emitting voltage applying electrode 1201a of the light-emitting element of the first sub-pixel G1 includes an auxiliary electrode block Ae, a first driving electrode block De1, and a first connecting electrode block Ce1.
  • a driving electrode block De1 and a first connection electrode block Ce1 are electrically connected to each other.
  • the first light-emitting voltage applying electrode 1201b of the light-emitting element of the second sub-pixel G2 includes a second driving electrode block De2 and a second connecting electrode block Ce2, and a second driving electrode block De2 and a second connecting electrode.
  • Block Ce2 is electrically connected.
  • the area of the first light-emitting voltage application electrode 1201a of the light-emitting element of the first sub-pixel G1 and the area of the first light-emitting voltage application electrode 1201b of the light-emitting element of the second sub-pixel G2 are different, for example, the area of the first sub-pixel G1
  • the area of the first light-emitting voltage applying electrode 1201a of the light-emitting element is larger than the area of the first light-emitting voltage applying electrode 1201b of the light-emitting element of the second sub-pixel G2.
  • the auxiliary electrode block Ae is located on the side of the control end of the driving circuit of the pixel circuit of the first sub-pixel G1 away from the base substrate 10, and the second driving electrode block De2 is located in the pixel of the second sub-pixel G2.
  • the control end of the driving circuit of the circuit is on the side away from the base substrate 10.
  • the shape of the auxiliary electrode block Ae is different from the shape of the second drive electrode block De2, that is to say, the first sub-pixel G1 located at the first sub-pixel G1 on the side away from the base substrate 10 of the control end of the driving circuit of the pixel circuit
  • the shape of the anode portion of the sub-pixel G1 is different from the shape of the anode portion of the second sub-pixel G2 on the side away from the base substrate 10 at the control end of the driving circuit of the pixel circuit of the second sub-pixel G2.
  • the driving circuit 122 of the pixel circuit 121 of each sub-pixel includes a driving transistor T1.
  • the auxiliary electrode block Ae is located on the side of the gate of the drive transistor T1 of the pixel circuit of the first sub-pixel G1 away from the base substrate 10, and the second drive electrode block De2 is located at the side of the drive transistor T1 of the pixel circuit of the second sub-pixel G2. The side of the gate away from the base substrate 10.
  • the orthographic projection of the auxiliary electrode block Ae on the base substrate and the orthographic projection of the gate of the driving transistor T1 of the pixel circuit of the first sub-pixel G1 on the base substrate at least partially overlap
  • the second driving electrode block De2 is on the base substrate.
  • the orthographic projection on the base substrate and the orthographic projection of the gate of the driving transistor T1 of the pixel circuit of the second sub-pixel G2 on the base substrate at least partially overlap.
  • the area of the overlap between the orthographic projection of the auxiliary electrode block Ae on the base substrate and the orthographic projection of the gate of the driving transistor T1 of the pixel circuit of the first sub-pixel G1 on the base substrate is the first area
  • the second The area of the overlapping portion of the orthographic projection of the driving electrode block De2 on the base substrate and the orthographic projection of the gate of the driving transistor T1 of the pixel circuit of the second sub-pixel G2 on the base substrate is the second area
  • the first area and The ratio of the second area satisfies the following relationship:
  • AR1 represents the first area
  • AR2 represents the second area
  • Amin represents the minimum ratio threshold and is 90%
  • Amax represents the maximum ratio threshold and is 110%.
  • the shape of the first driving electrode block De1 and the shape of the auxiliary electrode block Ae are different, and the shape of the first driving electrode block De1 is the same as the shape of the second driving electrode block De2, for example,
  • the shape of the first driving motor block De1 and the shape of the second driving electrode block De2 may both be pentagonal, and the shape of the auxiliary electrode block Ae may be a rectangle.
  • the present disclosure is not limited to this.
  • the shape of the first drive motor block De1 and the shape of the second drive electrode block De2 may also be rectangular, etc., and the shape of the auxiliary electrode block Ae may also be pentagonal, hexagonal, oval, etc. .
  • the area of the orthographic projection of the first drive electrode block De1 on the base substrate 10 is the same as the area of the orthographic projection of the second drive electrode block De2 on the base substrate 10.
  • the shape of the first connection electrode block Ce1 and the shape of the second connection electrode block Ce2 may also be the same.
  • the shape of the first connection electrode block Ce1 and the shape of the second connection electrode block Ce2 The shape can be rectangular.
  • the area of the orthographic projection of the first connection electrode block Ce1 on the base substrate 10 is the same as the area of the orthographic projection of the second connection electrode block Ce2 on the base substrate 10.
  • the shape of the first connecting electrode block Ce1 and the shape of the second connecting electrode block Ce2 may also be different, and/or, the first connecting electrode block Ce1 is on the base substrate
  • the area of the orthographic projection on 10 and the area of the orthographic projection of the second connection electrode block Ce2 on the base substrate 10 may also be different.
  • the control terminal of the driving circuit of the pixel circuit of the first sub-pixel G1 and the control terminal of the driving circuit of the pixel circuit of the second sub-pixel G2 are arranged along the first direction X, that is, the first
  • the gate of the driving transistor T1 of the pixel circuit of one sub-pixel G1 and the gate of the driving transistor T1 of the pixel circuit of the second sub-pixel G2 are arranged along the first direction X.
  • the first driving electrode block De1 is located at the control end of the driving circuit of the pixel circuit of the first sub-pixel G1. Side of the end.
  • the first driving electrode block De1 is located at the control end of the driving circuit of the pixel circuit of the first sub-pixel G1 and the pixel circuit of the second sub-pixel G2. Between the control terminals of the drive circuit.
  • the first connecting electrode block Ce1 is located on the side of the first driving electrode block De1 away from the control end of the driving circuit of the pixel circuit of the second sub-pixel G2.
  • the first connecting electrode block Ce1 is located between the control terminal of the pixel circuit of the first sub-pixel G1 and the control terminal of the pixel circuit of the second sub-pixel G2. That is, in the first direction X, the first connecting electrode block Ce1 and the first driving electrode block De1 are both located at the control end of the driving circuit of the pixel circuit of the first sub-pixel G1 and the pixel circuit of the second sub-pixel G2. Between the control terminals of the drive circuit.
  • the first connection electrode block Ce1 is located on the side of the first drive electrode block De1 away from the second drive electrode block De2, that is, the first drive electrode block De1 is located on the first connection electrode block. Between Ce1 and the second driving electrode block De2.
  • the first connecting electrode block Ce1 is located between the first driving electrode block De1 and the auxiliary electrode block Ae, that is, the auxiliary electrode block Ae is located on the first connecting electrode block Ce1 away from the first driving electrode block.
  • the electrode block De1 One side of the electrode block De1.
  • the second connecting electrode block Ce2 is located on the side of the control terminal of the pixel circuit of the second sub-pixel G2 away from the control terminal of the pixel circuit of the first sub-pixel G1.
  • the second drive electrode block De2 is located between the second connection electrode block Ce2 and the first drive electrode block De1, that is, the second connection electrode block Ce2 is located on the second drive electrode block De2 away from the first Drive one side of the electrode block De1.
  • the plurality of sub-pixels 12 further include a third sub-pixel R and a fourth sub-pixel B.
  • the first light-emitting voltage applying electrode of the light-emitting element of the third sub-pixel R and the first light-emitting voltage applying electrode of the light-emitting element of the fourth sub-pixel B are arranged along the second direction Y.
  • the first direction X and the second direction Y are perpendicular to each other.
  • the first light-emitting voltage application electrode of the light-emitting element of the third sub-pixel R includes a third drive electrode block De3 and a third connection electrode block Ce3, and a third drive electrode block De3 and a third connection electrode block. Ce3 are electrically connected to each other.
  • the orthographic projection of the third driving electrode block De3 on the base substrate and the orthographic projection of the control end of the driving circuit of the pixel circuit of the third sub-pixel R on the base substrate at least partially overlap.
  • the first light-emitting voltage application electrode of the light-emitting element of the fourth sub-pixel B includes a fourth drive electrode block De4 and a fourth connection electrode block Ce4, and a fourth drive electrode block De4 and a fourth connection electrode block. Ce4 are electrically connected to each other.
  • the fourth driving electrode block De4 is located on the side of the control end of the driving circuit of the pixel circuit of the fourth sub-pixel B away from the base substrate 10.
  • the fourth driving electrode block De4 is on the base substrate.
  • the orthographic projection of the fourth sub-pixel B at least partially overlaps the orthographic projection of the control end of the driving circuit of the pixel circuit of the fourth sub-pixel B on the base substrate.
  • the distance between the center of the control terminal (ie the gate of the driving transistor) of the pixel circuit of the first sub-pixel G1 and the center of the first driving electrode block De1 is greater than that of the second sub-pixel G1.
  • center may refer to the geometric center of the physical shape of the element.
  • elements such as the gate of the driving transistor and the anode of the light-emitting element are generally designed in regular shapes, such as rectangles, hexagons, pentagons, trapezoids or other shapes.
  • the center of the element for example, the gate of the driving transistor or the anode of the light-emitting element, etc.
  • the shapes of the gates of the driving transistors and the anodes of the light-emitting elements formed will generally deviate from the regular shapes designed above.
  • the corners of the aforementioned regular shape may become rounded corners. Therefore, the shape of the gate of the driving transistor and the anode of the light-emitting element may be rounded corners.
  • the shapes of the gates of the drive transistors and the anodes of the light-emitting elements that are actually manufactured may have other changes from the designed shapes. For example, the shape of a sub-pixel designed as a hexagon may become approximately elliptical in actual manufacturing. Therefore, the center of elements such as the gate of the driving transistor and the anode of the light-emitting element may not be the exact geometric center of the irregular shape of the sub-pixel formed.
  • the center of the element may have a certain offset from the geometric center of the shape of the element.
  • the "center" may also indicate the center of gravity of the element.
  • the embodiment of the present disclosure also provides a display substrate.
  • the display substrate 100 includes a base substrate 10 and a plurality of repeating units 11 arranged on the base substrate 10, and each repeating unit 11 includes a plurality of sub-pixels 12.
  • Each sub-pixel 12 includes a light-emitting element 120 and a pixel circuit 121, and the pixel circuit 121 is used to drive the light-emitting element 120 to emit light.
  • the light-emitting element of each sub-pixel includes a first light-emitting voltage applying electrode, a second light-emitting voltage applying electrode, and a light-emitting layer provided between the first light-emitting voltage applying electrode and the second light-emitting voltage applying electrode.
  • the pixel circuit 121 of each sub-pixel includes a driving circuit 122, a second light emission control circuit 124, and a reset circuit 129.
  • the second light emission control circuit 124 is electrically connected to the second light emission control signal line EM2, the second end of the driving circuit 122, and the first light emission voltage application electrode of the light emitting element 120, and is configured to be connected to the second light emission control signal line EM2.
  • the connection between the driving circuit 122 and the light emitting element 120 is turned on or off under the control of the provided second light emitting control signal.
  • the reset circuit 129 is electrically connected to the control terminal of the drive circuit 122 and the first reset control signal line Rst1, and is configured to control the control terminal of the drive circuit 122 under the control of the first sub-reset control signal provided by the first reset control signal line Rst1 Perform a reset.
  • the second light emission control signal line EM2 and the first reset control signal line Rst1 are arranged along the first direction X.
  • the second emission control signal line EM2a connected to the second emission control circuit of the first sub-pixel G1 and the first emission control signal line EM2a connected to the reset circuit of the first sub-pixel G1
  • the reset control signal line Rst1a is arranged along the first direction X.
  • the plurality of sub-pixels 12 include a first sub-pixel G1 and a second sub-pixel G2.
  • the color of the light emitted by the light-emitting element of the first sub-pixel G1 and the color of the light emitted by the light-emitting element of the second sub-pixel G2 are the same, and the shape of the first light-emitting voltage applying electrode of the light-emitting element of the first sub-pixel G1 is the same as The shapes of the first light-emitting voltage application electrodes of the light-emitting elements of the second sub-pixel G2 are different.
  • the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel G1 on the base substrate and the first reset control connected to the reset circuit of the pixel circuit of the second sub-pixel G2 The orthographic projection of the signal line Rst1b on the base substrate and the orthographic projection of the second emission control signal line EM2a connected to the second emission control circuit of the pixel circuit of the first sub-pixel G1 on the base substrate at least partially overlap.
  • the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element of the two sub-pixel G2 on the base substrate and the second light-emitting control signal line EM2b connected to the second light-emitting control circuit of the pixel circuit of the second sub-pixel G2 are on the substrate
  • the orthographic projections on the substrate at least partially overlap.
  • the reset circuit 129 is also electrically connected to the first light-emitting voltage applying electrode of the light-emitting element and the second reset control signal line Rst2, and is configured as a second sub-reset provided on the second reset control signal line Rst2.
  • the first light-emitting voltage applying electrode of the light-emitting element is reset under the control of the control signal.
  • the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same signal line.
  • the pixel circuit 121 of each sub-pixel further includes a data writing circuit 126.
  • the data writing circuit 126 is electrically connected to the first end of the driving circuit 122 and the first scan signal line Ga1, and is configured to The data signal is written into the control terminal of the driving circuit 122 under the control of the scan signal provided by the first scan signal line Ga1.
  • the first scan signal line Ga1 is located between the second light emission control signal line EM1 and the first reset control signal line Rst1, as shown in FIG. 4B.
  • the The first scan signal line Ga1a connected to the data writing circuit of one sub-pixel G1 is located at the second light-emitting control signal line EM2a connected to the second light-emitting control circuit of the first sub-pixel G1 and is connected to the reset of the first sub-pixel G1.
  • the circuit is connected between the first reset control signal line Rst1a.
  • the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel G1 and the first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel G2 are arranged along the first direction X.
  • the first scanning signal line Ga1b connected to the data writing circuit of the pixel circuit of the second sub-pixel G2 is located in the first light-emitting element of the first sub-pixel G1.
  • the reset circuit 129 of each sub-pixel is also electrically connected to the first reset power signal line, and the reset circuit 129 is configured to be controlled by the first reset power signal line provided by the first reset control signal line according to the first reset power signal line.
  • the provided first reset signal resets the control terminal of the driving circuit 1222.
  • the reset circuit 129 of each sub-pixel is also electrically connected to the second reset power signal line, and the reset circuit 129 is configured to be controlled by the second reset power signal line provided by the second reset control signal line according to the second reset power signal line.
  • the provided second reset signal resets the first light-emitting voltage applying electrode of the light-emitting element.
  • the first reset power signal line and the second reset power signal line are the same signal line.
  • the first reset power signal line is located on the side of the first reset control signal line away from the second light-emitting control signal line, that is, the first reset control signal line is located on the first reset power signal line. Line and the second light-emitting control signal line.
  • the first reset power signal line Init1a connected to the reset circuit of the first sub-pixel G1 is located at the reset circuit of the first sub-pixel G1.
  • the side of the connected first reset control signal line Rst1a away from the second emission control signal line EM2a connected to the second emission control circuit of the first sub-pixel G1, that is, the first reset control signal line Rst1a is located at the first reset power source Between the signal line Init1a and the second light emission control signal line EM2a.
  • the second light emission control signal line, the first reset control signal line, the first scan signal line, and the first reset power signal line all extend in the second direction, and the second direction and the first direction are perpendicular to each other.
  • the second light emission control signal line, the first reset control signal line, the first scan signal line, and the first reset power signal line are parallel to each other, for example, substantially parallel. As shown in FIG.
  • the second emission control signal line EM2a connected to the second emission control circuit of the first sub-pixel G1, and the first emission control signal line EM2a connected to the reset circuit of the first sub-pixel G1
  • the reset control signal line Rst1a, the first scanning signal line Ga1a connected to the data writing circuit of the first sub-pixel G1, and the first reset power signal line Init1a connected to the reset circuit of the first sub-pixel G1 are all along the second The directions Y extend and are approximately parallel to each other.
  • each signal line for example, the second light-emitting control signal line, the first reset control signal line, the first scan signal line, and the first reset power signal line
  • each signal line may not be a straight line in microscopic view, but extend in the second direction Y in a wave shape.
  • the orthographic projection of the first light-emitting voltage application electrode of the light-emitting element of the first sub-pixel G1 on the base substrate is also connected to the first reset circuit of the pixel circuit of the second sub-pixel G2.
  • the orthographic projection of the power signal line Rst1b on the base substrate at least partially overlaps.
  • the first light-emitting voltage applying electrode of the light-emitting element of the first sub-pixel G1 includes an auxiliary electrode block Ae, a first driving electrode block De1, and a first connecting electrode block Ce1.
  • the driving electrode block De1 and the first connection electrode block Ce1 are electrically connected to each other, and are arranged along the first direction X.
  • the first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel G2 includes a second drive electrode block De2 and a second connection electrode block Ce2.
  • the second drive electrode block De2 and the second connection electrode block Ce2 are electrically connected and run along the first Arranged in direction X.
  • the first connecting electrode block Ce1 and the auxiliary electrode Ae block are both located on the side of the first driving electrode block De1 away from the second driving electrode block De2, and the first connecting electrode block Ce1 is located on the auxiliary electrode Ae.
  • the second connecting electrode block Ce2 is located on the side of the second driving electrode block De2 away from the first driving electrode block De1.
  • the orthographic projection of the first drive electrode block De1 on the base substrate and the first reset control signal line Rst1b connected to the reset circuit of the pixel circuit of the second sub-pixel G2 on the base substrate are at least partially overlapped, and the first connection electrode block Ce1 is on the base substrate.
  • the projection and the orthographic projection on the base substrate of the second emission control signal line EM1a connected to the second emission control circuit of the pixel circuit of the first sub-pixel G1 at least partially overlap.
  • the auxiliary electrode block Ae is located on the second emission control signal line EM1a connected to the second emission control circuit of the pixel circuit of the first sub-pixel G1 away from the first emission voltage of the emission element of the second sub-pixel G2 The side where the electrode is applied.
  • the orthographic projection of the second connecting electrode block Ce2 on the base substrate and the second emission control signal line EM1b connected to the second emission control circuit of the pixel circuit of the second sub-pixel G2 are on the substrate.
  • the orthographic projection on the substrate at least partially overlaps.
  • the second driving electrode block De2 is located at the second light-emitting control signal line EM1b connected to the second light-emitting control circuit of the pixel circuit of the second sub-pixel G2 and Between the first scanning signal line Ga1b connected to the data writing circuit of the pixel circuit of the two sub-pixels G2.
  • FIG. 7 is a schematic diagram of a partial structure of a display panel provided by some embodiments of the present disclosure.
  • the display panel 700 includes the display substrate 100 described in any of the above embodiments.
  • a plurality of repeating units 11 are arranged along the second direction Y to form a plurality of repeating unit groups
  • FIG. 7 shows two repeating unit groups, and the two repeating unit groups are respectively the Pth repeating unit.
  • the unit group and the P+1th repeating unit group, the Pth repeating unit group and the P+1th repeating unit group are two adjacent repeating unit groups, for example, P is a positive integer greater than or equal to 1.
  • the multiple repeating unit groups are arranged along the first direction X. That is, the multiple repeating units 11 in the display substrate 100 are arranged in an array along the first direction X and the second direction Y.
  • the P-th repeating unit group is located in the first row, and the P+1-th repeating unit group is located in the second row.
  • FIG. 7 does not show the light emission of each sub-pixel.
  • the connection electrode block of the component is located in the first row, and the P+1-th repeating unit group is located in the second row.
  • the extension of the line connecting the center of the first sub-pixel G1 and the second sub-pixel G2 of the repeating unit in the P-th repeating unit group and the first sub-pixel of the repeating unit in the P+1-th repeating unit group does not overlap.
  • the extension line of the line connecting the centers of the first sub-pixel G1 and the second sub-pixel G2 of the repeating unit in the P-th repeating unit group passes through between two adjacent repeating units in the P+1-th repeating unit group.
  • the extension of the line connecting the centers of the first sub-pixel G1 and the second sub-pixel G2 of the repeating unit in the P+1th repeating unit group passes through the Pth repeating unit group The center of the gap between two adjacent repeating units.
  • the display panel 700 may be a liquid crystal display panel or an organic light emitting diode (OLED) display panel or the like.
  • the display substrate 100 may be an array substrate or a color filter substrate.
  • the display panel 700 is an organic light emitting diode display panel
  • the display substrate 100 may be an array substrate.
  • the display panel 700 may be a rectangular panel, a circular panel, an oval panel, a polygonal panel, or the like.
  • the display panel 700 may not only be a flat panel, but also a curved panel, or even a spherical panel.
  • the display panel 700 may also have a touch function, that is, the display panel 600 may be a touch display panel.
  • the display panel 700 can be applied to any products or components with display functions such as mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators, etc.
  • Embodiments of the present disclosure also provide a display device.
  • FIG. 8A is a schematic block diagram of a display device provided by some embodiments of the present disclosure
  • FIG. 8B is a schematic structural diagram of a display device provided by some embodiments of the present disclosure.
  • the display device 800 provided by the embodiment of the present disclosure includes a display panel 801, the display panel 801 includes a display substrate 802, the display panel 801 is the display panel 700 described in any of the above embodiments, and the display substrate 802 is The display substrate 100 described in any of the above embodiments.
  • the display device 800 may further include a driving chip 803, and the driving chip 803 is electrically connected to the display panel 801.
  • the driving chip 803 is located on the side of the first sub-pixel G1 away from the second sub-pixel G2 in each repeating unit 11.
  • the first sub-pixel G1 and the second sub-pixel G2 in each repeating unit 11 on the display substrate 802 are arranged along the first direction X.
  • the driving chip 803 is located in each repeating unit.
  • the first sub-pixel G1 in the unit 11 is on a side away from the second sub-pixel G2. That is, in the first direction X, the distance between the first sub-pixel G1 and the driving chip 803 is smaller than the distance between the second sub-pixel G2 and the driving chip 803.
  • the first sub-pixel G1 is closer to the upper side of the display panel 801 than the second sub-pixel G2, so that the driving chip 803 may be located on the upper side of the display panel 801.
  • the driving chip 803 may be a semiconductor chip, and may include a data driver.
  • the data driver in the driving chip 803 is used to drive a plurality of data lines in the display panel 801.
  • the data driver can provide data signals to the plurality of data lines.
  • the display device 800 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • the other components of the display device 800 should be understood by those of ordinary skill in the art. It will not be repeated here, nor should it be used as a limitation to the present invention.
  • FIG. 9 is a schematic flowchart of a method for preparing a display substrate provided by an embodiment of the present disclosure.
  • the preparation method of the display substrate may include:
  • S11 Form multiple repeating units on the base substrate.
  • each repeating unit includes a plurality of sub-pixels, each sub-pixel includes a pixel circuit and a light-emitting element, and the light-emitting element includes a first light-emitting voltage applying electrode, a second light-emitting voltage applying electrode, and a first light-emitting voltage applying electrode.
  • the light-emitting layer between the electrode and the second light-emitting voltage applying electrode, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the color of the light emitted by the light-emitting element of the first sub-pixel and the light-emitting element of the second sub-pixel
  • the color of light is the same, and the shape of the first light-emitting voltage applying electrode of the light-emitting element of the first sub-pixel is different from the shape of the first light-emitting voltage applying electrode of the light-emitting element of the second sub-pixel.
  • the orthographic projection of a light-emitting voltage application electrode on the base substrate and the orthographic projection of the control terminal of the pixel circuit of the first sub-pixel on the base substrate at least partially overlap, and the first light-emitting element of the second sub-pixel emits light.
  • the orthographic projection of the voltage application electrode on the base substrate and the orthographic projection of the control end of the driving circuit of the pixel circuit of the second sub-pixel on the base substrate at least partially overlap.
  • step S11 when the first light-emitting voltage applying electrode of the light-emitting element of the first sub-pixel is formed, the first driving electrode block and the auxiliary electrode block are formed through one patterning process, and the auxiliary electrode block is on the base substrate.
  • the orthographic projection and the orthographic projection of the control terminal of the driving circuit of the pixel circuit of the first sub-pixel on the base substrate at least partially overlap, for example, the control terminal of the driving circuit of the pixel circuit of the first sub-pixel is on the base substrate.
  • the projection is in the orthographic projection of the auxiliary electrode block on the base substrate.
  • one patterning process may include operations such as photolithography coating, exposure, development, etching, and photoresist stripping.
  • the first connection electrode block may also be formed while the first driving electrode block and the auxiliary electrode block are formed.
  • step S11 when the first light-emitting voltage application electrode of the light-emitting element of the second sub-pixel is formed, the second driving electrode block is formed, and the orthographic projection of the second driving electrode block on the base substrate and the second sub-pixel
  • the orthographic projection of the control end of the driving circuit of the pixel circuit of the pixel on the base substrate at least partially overlaps, for example, the orthographic projection of the control end of the driving circuit of the second sub-pixel pixel circuit on the base substrate is located on the second driving electrode
  • the block is in the orthographic projection on the base substrate.
  • the second driving electrode block and the second connection electrode block may be formed by one patterning process.

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Abstract

一种显示基板及其制备方法、显示面板、显示装置。显示基板(100)包括衬底基板(10)和重复单元(11)，重复单元(11)包括多个子像素(12)，包括第一子像素(G1)和第二子像素(G2)，第一子像素(G1)的发光元件(120a)发出的光的颜色和第二子像素(G2)的发光元件(120b)发出的光的颜色相同，第一子像素(G1)的发光元件(120a)的第一发光电压施加电极(1201a)的形状和第二子像素(G2)的发光元件(120b)的第一发光电压施加电极(1201b)的形状不相同，每个子像素(12)包括发光元件(120)和驱动发光元件(120)发光的像素电路(121)，第一子像素(G1)的发光元件(120a)的第一发光电压施加电极(1201a)在衬底基板(10)上的正投影与第一子像素(G1)的像素电路(121a)的驱动电路(122a)的控制端在衬底基板(10)上的正投影至少部分重叠，第二子像素(G2)的发光元件(120b)的第一发光电压施加电极(1201b)在衬底基板(10)上的正投影与第二子像素(G2)的像素电路(121b)的驱动电路(122b)的控制端在衬底基板(10)上的正投影至少部分重叠。

Description

显示基板及其制备方法、显示面板、显示装置 技术领域
本公开的实施例涉及一种显示基板及其制备方法、显示面板、显示装置。
背景技术
随着有源矩阵有机发光二极管(Active-matrix organic light-emitting diode，AMOLED)在显示领域的迅猛发展，人们对显示效果的要求越来越高。由于具有显示质量高等优点，高分辨率显示装置的应用范围也越来越广。通常，可通过减小像素的尺寸和减小像素间的间距来提高显示装置的分辨率。
发明内容
本公开至少一些实施例提供一种显示基板，包括衬底基板和设置在所述衬底基板上的多个重复单元，每个所述重复单元包括多个子像素，每个所述子像素包括发光元件和驱动所述发光元件发光的像素电路，所述像素电路包括驱动电路，所述发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在所述第一发光电压施加电极和所述第二发光电压施加电极之间的发光层，所述多个子像素包括第一子像素和第二子像素，所述第一子像素的发光元件发出的光的颜色和所述第二子像素的发光元件发出的光的颜色相同，所述第一子像素的发光元件的第一发光电压施加电极的形状和所述第二子像素的发光元件的第一发光电压施加电极的形状不相同，所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影与所述第一子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠，所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影与所述第二子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的面积和所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的面积不相同。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素的像素电 路的驱动电路的控制端在所述衬底基板上的正投影和所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的重叠部分的面积为第一面积，所述第二子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影和所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的重叠部分的面积为第二面积，所述第一面积和所述第二面积的比值满足以下关系式：
Amin≤A1/A2≤Amax，
其中，A1表示所述第一面积，A2表示所述第二面积，Amin表示最小比值阈值，且为90％，Amax表示最大比值阈值，且为110％。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影位于所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影内；所述第二子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影位于所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影内。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素的发光元件的发光层在所述衬底基板上的正投影与所述第二子像素的发光元件的发光层在所述衬底基板上的正投影是连续的。
例如，在本公开一些实施例提供的显示基板中，所述像素电路还包括第一发光控制电路和第二发光控制电路，所述驱动电路包括控制端、第一端和第二端，且被配置为为所述发光元件提供驱动所述发光元件发光的驱动电流；所述第一发光控制电路与所述驱动电路的第一端和第一电压端连接，且被配置为实现所述驱动电路和所述第一电压端之间的连接导通或断开，所述第二发光控制电路与所述驱动电路的第二端和所述发光元件的第一发光电压施加电极电连接，且被配置为实现所述驱动电路和所述发光元件之间的连接导通或断开。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素的像素电路还包括第一寄生电路，所述第二子像素的像素电路还包括第二寄生电路，所述第一寄生电路与所述第一子像素的像素电路的驱动电路的控制端和所述第一子像素的发光元件的第一发光电压施加电极电连接，且被配置为基于所述第一子像素的发光元件的第一发光电压施加电极的电压控制所述第一子像素的像素电路的驱动电路的控制端的电压，所述第二寄生电路与所述第二子像素的像素电路的驱动电路的控制端和所述第二子像素的发光元件的第一发光电压 施加电极电连接，且被配置为基于所述第二子像素的发光元件的第一发光电压施加电极的电压控制所述第二子像素的像素电路的驱动电路的控制端的电压。
例如，在本公开一些实施例提供的显示基板中，所述第一寄生电路包括第一电容，所述第一电容包括第一极和第二极，所述第一子像素的发光元件的第一发光电压施加电极包括辅助电极块，所述辅助电极块在所述衬底基板上的正投影与所述第一子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠，所述辅助电极块作为所述第一电容的第一极，所述第一子像素的驱动电路的控制端复用为所述第一电容的第二极。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素的发光元件的第一发光电压施加电极还包括第一驱动电极块，所述第一驱动电极块和所述辅助电极块电连接，所述第一驱动电极块在所述衬底基板上的正投影、所述第一子像素的发光元件的发光层在所述衬底基板上的正投影和所述第一子像素的发光元件的第二发光电压施加电极在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一些实施例提供的显示基板中，所述第二寄生电路包括第二电容，所述第二电容包括第一极和第二极，所述第二子像素的发光元件的第一发光电压施加电极包括第二驱动电极块，所述第二驱动电极块在所述衬底基板上的正投影与所述第二子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠，所述第二驱动电极块在所述衬底基板上的正投影、所述第二子像素的发光元件的发光层在所述衬底基板上的正投影和所述第二子像素的发光元件的第二发光电压施加电极在所述衬底基板上的正投影至少部分重叠，所述第二驱动电极块复用为所述第二电容的第一极，所述第二子像素的驱动电路的控制端复用为所述第二电容的第二极。
例如，在本公开一些实施例提供的显示基板中，所述第一驱动电极块的形状与所述第二驱动电极块的形状相同，所述第一驱动电极块在所述衬底基板上的正投影的面积与所述第二驱动电极块在所述衬底基板上的正投影的面积相同。
例如，在本公开一些实施例提供的显示基板中，在所述每个重复单元中，所述第一子像素和所述第二子像素沿第一方向排列，所述第一方向平行于所述衬底基板的表面，在所述第一方向上，所述辅助电极块位于所述第一驱动电极块的远离所述第二子像素的发光元件的一侧。
例如，在本公开一些实施例提供的显示基板中，所述辅助电极块在所述衬底基板上的正投影与所述第一子像素的发光元件的发光层在所述衬底基板上的正投影不重叠。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素的发光元件的第一发光电压施加电极还包括第一连接电极块，在所述第一方向上，所述第一连接电极块位于所述第一驱动电极块的远离所述第二子像素的发光元件的一侧，所述第一连接电极块位于所述辅助电极块和所述第一驱动电极块之间，且与所述辅助电极块和所述第一驱动电极块均电连接。
例如，本公开一些实施例提供的显示基板还包括中间层，在垂直于所述衬底基板的表面的方向上，所述像素电路位于所述中间层和所述衬底基板之间，所述发光元件位于所述中间层的远离所述衬底基板的一侧，所述中间层包括第一过孔，所述第一连接电极块延伸至所述第一过孔且通过所述第一过孔与所述第一子像素的像素电路电连接。
例如，在本公开一些实施例提供的显示基板中，所述第二子像素的发光元件的第一发光电压施加电极还包括第二连接电极块，所述第二连接电极块与所述第二驱动电极块电连接，在所述第一方向上，所述第二连接电极块位于所述第二驱动电极块的远离所述第一子像素的发光元件的一侧。
例如，在本公开一些实施例提供的显示基板中，所述中间层包括第二过孔，所述第二连接电极块延伸至所述第二过孔且通过所述第二过孔与所述第二子像素的像素电路电连接。
例如，在本公开一些实施例提供的显示基板中，所述第一连接电极块通过所述第一过孔与所述第一子像素的像素电路的第二发光控制电路电连接，所述第二连接电极块通过所述第二过孔与所述第二子像素的像素电路的第二发光控制电路电连接。
例如，在本公开一些实施例提供的显示基板中，所述像素电路包括有源半导体层、栅极金属层和源漏极金属层，在垂直于所述衬底基板的方向上，所述有源半导体层位于所述衬底基板与所述栅极金属层之间，所述栅极金属层位于所述有源半导体层和所述源漏极金属层之间，所述第一连接电极块通过所述第一过孔延伸到所述像素电路的源漏极金属层，所述第二连接电极块通过所述第二过孔延伸到所述像素电路的源漏极金属层。
例如，在本公开一些实施例提供的显示基板中，所述多个子像素还包括第 三子像素和第四子像素，在所述每个重复单元中，所述第三子像素和所述第四子像素沿第二方向排列，且在所述第二方向上，所述第一子像素和所述第二子像素位于所述第三子像素和所述第四子像素之间，所述第二方向平行于所述衬底基板的表面，且所述第一方向和所述第二方向相互垂直。
例如，在本公开一些实施例提供的显示基板中，所述第三子像素的发光元件的第一发光电压施加电极包括彼此电连接的第三驱动电极块和第三连接电极块，所述第四子像素的发光元件的第一发光电压施加电极包括彼此电连接的第四驱动电极块和第四连接电极块，所述中间层包括第三过孔和第四过孔，所述第三连接电极块延伸至所述第三过孔且通过所述第三过孔与所述第三子像素的像素电路电连接，所述第四连接电极块延伸至所述第四过孔且通过所述第四过孔与所述第四子像素的像素电路电连接。
例如，在本公开一些实施例提供的显示基板中，在所述每个重复单元中，在所述第一方向上，所述第三连接电极位于所述第三驱动电极块的远离所述辅助电极块的一侧，在所述第二方向上，所述第三连接电极位于所述第三驱动电极块的靠近所述第四驱动电极块的一侧，在所述第一方向上，所述第四连接电极位于所述第四驱动电极块的远离所述辅助电极块的一侧，在所述第二方向上，所述第四连接电极位于所述第四驱动电极块的靠近所述第三驱动电极块的一侧。
例如，在本公开一些实施例提供的显示基板中，所述第三连接电极块通过所述第三过孔与所述第三子像素的像素电路的第二发光控制电路电连接，所述第四连接电极块通过所述第四过孔与所述第四子像素的像素电路的第二发光控制电路电连接。
例如，在本公开一些实施例提供的显示基板中，所述多个重复单元沿第二方向排列以形成多个重复单元组，所述多个重复单元组沿所述第一方向排列，在所述第一方向上，所述第一连接电极块、所述第二连接电极块、所述第三连接电极块和所述第四连接电极块位于相邻两个重复单元组之间，在所述第一方向上，所述辅助电极块的至少一部分位于在所述辅助电极块远离所述第一驱动电极块的一侧且与所述辅助电极块所在的重复单元组相邻的重复单元组中的相邻两个重复单元之间。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素和所述第二子像素均为绿色子像素，所述第三子像素为红色子像素，所述第四子像素为 蓝色子像素。
例如，在本公开一些实施例提供的显示基板中，所述像素电路还包括数据写入电路、存储电路、阈值补偿电路和复位电路，所述数据写入电路与所述驱动电路的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入所述存储电路；所述存储电路与所述驱动电路的控制端和所述第一电压端电连接，且被配置为存储所述数据信号；所述阈值补偿电路与所述驱动电路的控制端和第二端电连接，且被配置为对所述驱动电路进行阈值补偿；所述复位电路与所述驱动电路的控制端和所述发光元件的第一发光电压施加电极电连接，且配置为在复位控制信号的控制下对所述驱动电路的控制端和所述发光元件的第一发光电压施加电极进行复位。
例如，在本公开一些实施例提供的显示基板中，所述驱动电路包括驱动晶体管，所述驱动电路的控制端包括所述驱动晶体管的栅极，所述驱动电路的第一端包括所述驱动晶体管的第一极，所述驱动电路的第二端包括所述驱动晶体管的第二极，所述数据写入电路包括数据写入晶体管，所述存储电路包括第三电容，所述阈值补偿电路包括阈值补偿晶体管，所述复位电路包括第一复位晶体管和第二复位晶体管，所述第一发光控制电路包括第一发光控制晶体管，所述第二发光控制电路包括第二发光控制晶体管，所述复位控制信号包括第一子复位控制信号和第二子复位控制信号，所述数据写入晶体管的第一极与所述驱动晶体管的第一极电连接，所述数据写入晶体管的第二极被配置为接收所述数据信号，所述数据写入晶体管的栅极被配置为接收所述扫描信号；所述第三电容的第一极与所述第一电源端电连接，所述第三电容的第二极与所述驱动晶体管的栅极电连接；所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极电连接，所述阈值补偿晶体管的栅极被配置为接收补偿控制信号；所述第一复位晶体管的第一极被配置为接收第一复位信号，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连接，所述第一复位晶体管的栅极被配置为接收所述第一子复位控制信号；所述第二复位晶体管的第一极被配置为接收第二复位信号，所述第二复位晶体管的第二极与所述发光元件的第一发光电压施加电极电连接，所述第二复位晶体管的栅极被配置为接收所述第二子复位控制信号；所述第一发光控制晶体管的第一极与所述第一电源端电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第一发光控制晶体管的栅极被配置 为接收第一发光控制信号，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光元件的第一发光电压施加电极电连接，所述第二发光控制晶体管的栅极被配置为接收第二发光控制信号。
本公开一些实施例还提供一种显示面板，包括根据上述任一项所述的显示基板。
本公开一些实施例还提供一种显示装置，包括根据上述任一项所述的显示面板。
例如，本公开一些实施例提供的显示装置还包括：驱动芯片，所述驱动芯片与所述显示面板电连接，且所述驱动芯片位于每个所述重复单元中的第一子像素的远离第二子像素的一侧。
例如，在本公开一些实施例提供的显示装置中，在每个所述重复单元中，所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的面积大于所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的面积。
本公开一些实施例还提供一种用于制备根据上述任一项所述的显示基板的制备方法，包括：提供所述衬底基板，在所述衬底基板上形成所述多个重复单元，其中，每个所述重复单元包括多个子像素，每个所述子像素包括像素电路和发光元件，所述发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在所述第一发光电压施加电极和所述第二发光电压施加电极之间的发光层，所述多个子像素包括第一子像素和第二子像素，所述第一子像素的发光元件发出的光的颜色和所述第二子像素的发光元件发出的光的颜色相同，所述第一子像素的发光元件的第一发光电压施加电极的形状和所述第二子像素的发光元件的第一发光电压施加电极的形状不相同，所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影与所述第一子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠，所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影与所述第二子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠。
本公开一些实施例还提供一种显示基板，包括衬底基板和设置在所述衬底基板上的多个重复单元，每个所述重复单元包括多个子像素，每个所述子像素 包括发光元件和驱动所述发光元件发光的像素电路，所述像素电路包括驱动电路，所述发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在所述第一发光电压施加电极和所述第二发光电压施加电极之间的发光层，所述多个子像素的驱动电路在所述衬底基板上阵列排布，所述多个子像素包括第一子像素和第二子像素，所述第一子像素的发光元件发出的光的颜色和所述第二子像素的发光元件发出的光的颜色相同，所述第一子像素的发光元件的第一发光电压施加电极包括辅助电极块、第一驱动电极块和第一连接电极块，所述第一驱动电极块、所述辅助电极块和所述第一连接电极块彼此电连接，所述第二子像素的发光元件的第一发光电压施加电极包括第二驱动电极块和第二连接电极块，所述第二驱动电极块和所述第二连接电极块电连接，所述辅助电极块位于所述第一子像素的像素电路的驱动电路的控制端的远离所述衬底基板的一侧，所述第二驱动电极块位于所述第二子像素的像素电路的驱动电路的控制端的远离所述衬底基板的一侧。
例如，在本公开一些实施例提供的显示基板中，所述第一驱动电极块的形状和所述辅助电极块的形状不相同，所述第一驱动电极块的形状与所述第二驱动电极块的形状相同，所述第一驱动电极块在所述衬底基板上的正投影的面积与所述第二驱动电极块在所述衬底基板上的正投影的面积相同。
例如，在本公开一些实施例提供的显示基板中，所述第一连接电极块的形状与所述第二连接电极块的形状相同，所述第一连接电极块在所述衬底基板上的正投影的面积与所述第二连接电极块在所述衬底基板上的正投影的面积相同。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素的像素电路的驱动电路的控制端和所述第二子像素的像素电路的驱动电路的控制端沿第一方向排布，在所述第一方向上，所述第一驱动电极块位于所述第一子像素的像素电路的驱动电路的控制端靠近所述第二子像素的像素电路的驱动电路的控制端的一侧。
例如，在本公开一些实施例提供的显示基板中，在所述第一方向上，所述第一驱动电极块位于所述第一子像素的像素电路的驱动电路的控制端和所述第二子像素的像素电路的驱动电路的控制端之间。
例如，在本公开一些实施例提供的显示基板中，在所述第一方向上，所述第一连接电极块位于所述第一驱动电极块的远离所述第二子像素的像素电路 的驱动电路的控制端的一侧。
例如，在本公开一些实施例提供的显示基板中，在所述第一方向上，所述第一连接电极块位于所述第一子像素的像素电路的驱动电路的控制端和所述第二子像素的像素电路的驱动电路的控制端之间。
例如，在本公开一些实施例提供的显示基板中，在所述第一方向上，所述第一连接电极块位于所述第一驱动电极块和所述辅助电极块之间。
例如，在本公开一些实施例提供的显示基板中，在所述第一方向上，所述第二连接电极块位于所述第二子像素的像素电路的驱动电路的控制端的远离所述第一子像素的像素电路的驱动电路的控制端的一侧，所述第二驱动电极块位于所述第二连接电极块和所述第一驱动电极块之间。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素的像素电路的驱动电路的控制端的中心和所述第一驱动电极块的中心之间的距离大于所述第二子像素的像素电路的驱动电路的控制端的中心和所述第二驱动电极块的中心之间的距离。
本公开一些实施例还提供一种显示基板，包括衬底基板和设置在所述衬底基板上的多个重复单元，每个所述重复单元包括多个子像素，每个所述子像素包括发光元件和驱动所述发光元件发光的像素电路，所述发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在所述第一发光电压施加电极和所述第二发光电压施加电极之间的发光层，所述像素电路包括驱动电路、第二发光控制电路和复位电路，所述第二发光控制电路电连接至第二发光控制信号线、所述驱动电路的第二端、所述发光元件的第一发光电压施加电极，且被配置为在所述第二发光控制信号线提供的第二发光控制信号的控制下实现所述驱动电路和所述发光元件之间的连接导通或断开，所述复位电路电连接至所述驱动电路的控制端和第一复位控制信号线，且配置为在所述第一复位控制信号线提供的第一子复位控制信号的控制下对所述驱动电路的控制端进行复位，所述第二发光控制信号线和所述第一复位控制信号线沿第一方向排布，所述多个子像素包括第一子像素和第二子像素，所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影和与所述第二子像素的像素电路的复位电路连接的第一复位控制信号线在所述衬底基板上的正投影、与所述第一子像素的像素电路的第二发光控制电路连接的第二发光控制信号线在所述衬底基板上的正投影均至少部分重叠，所述第二子像素的发光元件的第一发光 电压施加电极在所述衬底基板上的正投影和与所述第二子像素的像素电路的第二发光控制电路连接的第二发光控制信号线在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一些实施例提供的显示基板中，所述像素电路还包括数据写入电路，所述数据写入电路电连接至所述驱动电路的第一端和第一扫描信号线，且被配置为在所述第一扫描信号线提供的扫描信号的控制下将数据信号写入所述驱动电路的控制端，在所述第一方向上，所述第一扫描信号线位于所述第二发光控制信号线和所述第一复位控制信号线之间，所述第一子像素的发光元件的第一发光电压施加电极和所述第二子像素的发光元件的第一发光电压施加电极沿所述第一方向排布，在所述第一方向上，与所述第二子像素的像素电路的数据写入电路连接的第一扫描信号线位于所述第一子像素的发光元件的第一发光电压施加电极和所述第二子像素的发光元件的第一发光电压施加电极之间。
例如，在本公开一些实施例提供的显示基板中，所述复位电路还与第一复位电源信号线电连接，所述复位电路配置为在所述第一复位控制信号线提供的第一子复位控制信号的控制下根据所述第一复位电源信号线提供的第一复位信号对所述驱动电路的控制端进行复位，在所述第一方向上，所述第一复位电源信号线位于所述第一复位控制信号线的远离所述第二发光控制信号线的一侧，所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影还和与所述第二子像素的像素电路的复位电路连接的第一复位电源信号线在所述衬底基板上的正投影至少部分重叠。
例如，在本公开一些实施例提供的显示基板中，所述第二发光控制信号线、所述第一复位控制信号线、所述第一扫描信号线和所述第一复位电源信号线均沿第二方向延伸，所述第二方向与所述第一方向相互垂直。
例如，在本公开一些实施例提供的显示基板中，所述第二发光控制信号线、所述第一复位控制信号线、所述第一扫描信号线和所述第一复位电源信号线彼此平行。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素的发光元件的第一发光电压施加电极包括辅助电极块、第一驱动电极块和第一连接电极块，所述第一驱动电极块、所述辅助电极块和所述第一连接电极块彼此电连接，且沿所述第一方向排布，所述第二子像素的发光元件的第一发光电压施加电极 包括第二驱动电极块和第二连接电极块，所述第二驱动电极块和所述第二连接电极块电连接，且沿所述第一方向排布，在所述第一方向上，所述第一连接电极块和所述辅助电极块均位于所述第一驱动电极块的远离所述第二驱动电极块的一侧，所述第一连接电极块位于所述辅助电极块和所述第一驱动电极块之间，所述第二连接电极块位于所述第二驱动电极块的远离所述第一驱动电极块的一侧，所述第一驱动电极块在所述衬底基板上的正投影和与所述第二子像素的像素电路的复位电路连接的第一复位控制信号线在所述衬底基板上的正投影、与所述第二子像素的像素电路的复位电路连接的第一复位电源信号线在所述衬底基板上的正投影均至少部分重叠，所述第一连接电极块在所述衬底基板上的正投影和与所述第一子像素的像素电路的第二发光控制电路连接的第二发光控制信号线在所述衬底基板上的正投影至少部分重叠，在所述第一方向上，所述辅助电极块位于与所述第一子像素的像素电路的第二发光控制电路连接的第二发光控制信号线的远离所述第二子像素的发光元件的第一发光电压施加电极的一侧，所述第二连接电极块在所述衬底基板上的正投影和与所述第二子像素的像素电路的第二发光控制电路连接的第二发光控制信号线在所述衬底基板上的正投影至少部分重叠，在所述第一方向上，所述第二驱动电极块位于与所述第二子像素的像素电路的第二发光控制电路连接的第二发光控制信号线和与所述第二子像素的像素电路的数据写入电路连接的第一扫描信号线之间。
例如，在本公开一些实施例提供的显示基板中，所述第一子像素的发光元件发出的光的颜色和所述第二子像素的发光元件发出的光的颜色相同，所述第一子像素的发光元件的第一发光电压施加电极的形状和所述第二子像素的发光元件的第一发光电压施加电极的形状不相同。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种像素排列结构中的像素重复单元的结构示意图；
图2为本公开一些实施例提供的一种显示基板的示意性框图；
图3A为本公开一些实施例提供的一种像素电路的结构示意图；
图3B为本公开一些实施例提供的一种第一子像素的像素电路的结构示意图；
图3C为本公开一些实施例提供的一种第二子像素的像素电路的结构示意图；
图4A-4E为本公开一些实施例提供的一种像素电路的各层的示意图；
图5A为本公开一些实施例提供的一种显示基板的平面示意图；
图5B为本公开一些实施例提供的一种重复单元的平面示意图；
图6A为本公开一些实施例提供的另一种重复单元的平面示意图；
图6B为本公开一些实施例提供的一种显示基板的布局图；
图6C为图6B中线L1-L1'的截面结构示意图；
图6D为图6B中线L2-L2'的截面结构示意图；
图6E为本公开一些实施例提供的又一种显示基板的平面示意图；
图7为本公开一些实施例提供的一种显示面板的局部结构示意图；
图8A为本公开一些实施例提供的一种显示装置的示意性框图；
图8B为本公开一些实施例提供的一种显示装置的结构示意图；
图9为本公开一实施例提供的一种显示基板的制备方法的示意性流程图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关 系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
图1为一种像素排列结构中的像素重复单元的结构示意图，如图1所示，一种像素排列结构包括多个像素重复单元400，多个像素重复单元400沿方向405和方向406阵列排布。每个像素重复单元400包括红色子像素401、蓝色子像素402、第一绿色子像素403和第二绿色子像素404。如图1所示，红色子像素401和蓝色子像素402沿405方向排列，第一绿色子像素403和第二绿色子像素404沿方向406排列，且在方向405上，第一绿色子像素403和第二绿色子像素404位于红色子像素401和蓝色子像素402之间。
在对图1所示的像素排列结构中的各个子像素进行点灯检测的过程中，由于第一绿色子像素403和第二绿色子像素404的亮度不一致，从而导致亮点漏检的问题，即部分绿色子像素无法被检测到。根据实验结果可知，第一绿色子像素403的亮度比第二绿色子像素404的亮度高，从而出现第一绿色子像素403发亮，而第二绿色子像素404发暗的现象。
每个子像素中，发光元件的阳极和驱动晶体管的栅极之间存在寄生电容，该寄生电容会影响发光元件的发光亮度，且寄生电容越大，发光亮度越弱；寄生电容越小，发光亮度越强。通过对像素排列结构进行分析可知，在该像素排列结构中，用于驱动第一绿色子像素403的像素电路中的驱动晶体管的栅极未被第一绿色子像素403的发光元件中的阳极遮挡，而用于驱动第二绿色子像素404的像素电路中的驱动晶体管的栅极被第二绿色子像素404的发光元件中的阳极遮挡。由此，第一绿色子像素403的驱动晶体管的栅极和发光元件之间不存在寄生电容，或者第一绿色子像素403的驱动晶体管的栅极和发光元件之间的寄生电容小于第二绿色子像素404的驱动晶体管的栅极和发光元件之间的寄生电容，即第一绿色子像素403的驱动晶体管的栅极和发光元件之间的寄生电容和第二绿色子像素404的驱动晶体管的栅极和发光元件之间的寄生电容存在较大的差异，从而导致每个重复单元中的第一绿色子像素403和第二绿色子像素404的亮度差异，严重影响显示效果。
本公开至少一些实施例提供一种显示基板及其制备方法、显示面板、显示装置，在该显示基板中，第一子像素的发光元件覆盖第一子像素的驱动晶体管的栅极，第二子像素的发光元件也覆盖第二子像素的驱动晶体管的栅极，从而 减小第一子像素的发光元件和驱动晶体管的栅极之间的寄生电容和第二子像素的发光元件和驱动晶体管的栅极之间的寄生电容的差异，使第一子像素和第二子像素的像素亮度均达到一致，从而提高显示均匀性和显示效果，解决显示面板的像素亮度差异的问题。另外，该显示基板结构简单，易于设计制造，成本较低。
下面结合附图对本公开的几个实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图2为本公开一些实施例提供的一种显示基板的示意性框图，图3A为本公开一些实施例提供的一种显示基板的平面示意图，图3A为本公开一些实施例提供的一种像素电路的结构示意图，图3B为本公开一些实施例提供的一种第一子像素的像素电路的结构示意图，图3C为本公开一些实施例提供的一种第二子像素的像素电路的结构示意图。
例如，如图2所示，本公开的实施例提供的显示基板100包括衬底基板10和设置在衬底基板10上的多个重复单元11，每个重复单元11包括多个子像素12。每个子像素12包括发光元件120和像素电路121，像素电路121用于驱动发光元件120发光，像素电路121包括驱动电路122。
例如，显示基板100可以应用于显示面板，例如有源矩阵有机发光二极管(AMOLED)显示面板等。显示基板100可以为阵列基板。
例如，衬底基板10可以为玻璃基板、石英基板、塑料基板等合适的基板。
例如，每个子像素12的发光元件120包括第一发光电压施加电极、第二发光电压施加电极和设置在第一发光电压施加电极和第二发光电压施加电极之间的发光层。
例如，多个子像素12包括第一子像素G1和第二子像素G2。
例如，如图3A所示，像素电路121还包括第一发光控制电路123和第二发光控制电路124。驱动电路122包括控制端、第一端和第二端，且被配置为为发光元件120提供驱动发光元件120发光的驱动电流。例如，第一发光控制电路123与驱动电路122的第一端和第一电压端VDD连接，且被配置为实现驱动电路122和第一电压端VDD之间的连接导通或断开，第二发光控制电路124与驱动电路122的第二端和发光元件120的第一发光电压施加电极电连接，且被配置为实现驱动电路122和发光元件120之间的连接导通或断开。
例如，如图3B和图3C所示，第一子像素G1的像素电路121a还包括第 一寄生电路125a，第二子像素G2的像素电路121b还包括第二寄生电路125b。例如，第一寄生电路125a与第一子像素G1的像素电路121a的驱动电路122a的控制端和第一子像素G1的发光元件120a的第一发光电压施加电极电连接，且被配置为基于第一子像素G1的发光元件120a的第一发光电压施加电极的电压控制第一子像素G1的像素电路121a的驱动电路122a的控制端的电压。第二寄生电路125b与第二子像素G2的像素电路121b的驱动电路的控制端和第二子像素G2的发光元件120b的第一发光电压施加电极电连接，且被配置为基于第二子像素G2的发光元件120b的第一发光电压施加电极的电压控制第二子像素G2的像素电路121b的驱动电路122b的控制端的电压。
需要说明的是，像素电路121还可以包括寄生电路，而图3A中未示出该寄生电路，例如，图3A未示出了第一子像素G1的像素电路中的第一寄生电路和第二子像素G2的像素电路中的第二寄生电路。
例如，如图3A所示，像素电路121还包括数据写入电路126、存储电路127、阈值补偿电路128和复位电路129。数据写入电路126与驱动电路122的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储电路127；存储电路127与驱动电路122的控制端和第一电压端VDD电连接，且被配置为存储数据信号；阈值补偿电路128与驱动电路122的控制端和第二端电连接，且被配置为对驱动电路122进行阈值补偿；复位电路129与驱动电路122的控制端和发光元件120的第一发光电压施加电极电连接，且配置为在复位控制信号的控制下对驱动电路122的控制端和发光元件120的第一发光电压施加电极进行复位。
例如，如图3A所示，驱动电路122包括驱动晶体管T1，驱动电路122的控制端包括驱动晶体管T1的栅极，驱动电路122的第一端包括驱动晶体管T1的第一极，驱动电路122的第二端包括驱动晶体管T1的第二极。
例如，如图3A所示，数据写入电路126包括数据写入晶体管T2，存储电路127包括第三电容C2，阈值补偿电路128包括阈值补偿晶体管T3，第一发光控制电路123包括第一发光控制晶体管T4，第二发光控制电路124包括第二发光控制晶体管T5，复位电路129包括第一复位晶体管T6和第二复位晶体管T7，复位控制信号可以包括第一子复位控制信号和第二子复位控制信号。
例如，如图3A所示，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线Vd电连接以接 收数据信号，数据写入晶体管T2的栅极被配置为与第一扫描信号线Ga1电连接以接收扫描信号；第三电容C2的第一极与第一电源端VDD电连接，第三电容C2的第二极与驱动晶体管T1的栅极电连接；阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与第二扫描信号线Ga2电连接以接收补偿控制信号；第一复位晶体管T6的第一极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的栅极电连接，第一复位晶体管T6的栅极被配置为与第一复位控制信号线Rst1电连接以接收第一子复位控制信号；第二复位晶体管T7的第一极被配置为与第二复位电源端Vinit2电连接以接收第二复位信号，第二复位晶体管T7的第二极与发光元件120的第一发光电压施加电极电连接，第二复位晶体管T7的栅极被配置为与第二复位控制信号线Rst2电连接以接收第二子复位控制信号；第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶体管T4的栅极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与发光元件120的第一发光电压施加电极电连接，第二发光控制晶体管T5的栅极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号；发光元件120的第二发光电压施加电极与第二电源端VSS电连接。
例如，如图3B所示，对于第一子像素G1，第一寄生电路125a包括第一电容C11，第一电容C11包括第一极CC3a和第二极CC4a。第一电容C11的第一极CC3a与第一子像素G1的发光元件120a的第一发光电压施加电极电连接，第一电容C11的第二极CC4a与第一子像素G1的像素电路121a的驱动晶体管T1的栅极电连接。
例如，如图3C所示，对于第二子像素G2，第二寄生电路125b包括第二电容C12，第二电容C12包括第一极和第二极。第二电容C12的第一极与第二子像素G2的发光元件120b的第一发光电压施加电极电连接，第二电容C12的第二极与第二子像素G2的像素电路121b的驱动晶体管T1的栅极电连接。
例如，第一电容C11的电容值和第二电容C12的电容值可以相同，从而可以使第一子像素G1和第二子像素G2的像素亮度均达到一致，提高显示均匀 性和显示效果。
例如，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图3A所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
例如，对于第一子像素G1，如图3B所示，第一子像素G1的像素电路121a还包括数据写入电路126a、存储电路127a、阈值补偿电路128a和复位电路129a；对于第二子像素G2，如图3C所示，第二子像素G2的像素电路121b还包括数据写入电路126b、存储电路127b、阈值补偿电路128b和复位电路129b。第一子像素G1的像素电路121a和第二子像素G2的像素电路121b中的各个电路中的各个元件的连接关系以及作用等均与上面对图3A描述的示例相类似，重复之处在此不再赘述。
例如，如图3A所示，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极可以电连接到同一条信号线，例如第一扫描信号线Ga1，以接收相同的信号(例如，扫描信号)，此时，显示基板100可以不设置第二扫描信号线Ga2，减少信号线的数量。又例如，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T2的栅极电连接到第一扫描信号线Ga1，阈值补偿晶体管T3的栅极电连接到第二扫描信号线Ga2，而第一扫描信号线Ga1和第二扫描信号线Ga2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得数据写入晶体管T2的栅极和阈值补偿晶体管T3可以被分开单独控制，增加控制像素电路的灵活性。
例如，如图3A-3B所示，第一发光控制信号和第二发光控制信号可以相同，即，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极可以电连接到同一条信号线，例如第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板100可以不设置第二发光控制信号线EM2，减少信号线的数量。又例如，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T4的栅极电连接到第一发光控制信号线EM1，第二发光控制晶体管T5的 栅极电连接到第二发光控制信号线EM2，而第一发光控制信号线EM1和第二发光控制信号线EM2传输的信号相同。
需要说明的是，当第一发光控制晶体管T4和第二发光控制晶体管T5为不同类型的晶体管，例如，第一发光控制晶体管T4为P型晶体管，而第二发光控制晶体管T5为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。
例如，第一子复位控制信号和第二子复位控制信号可以相同，即，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极可以电连接到同一条信号线，例如第一复位控制信号线Rst1，以接收相同的信号(例如，第一子复位控制信号)，此时，显示基板100可以不设置第二复位控制信号线Rst2，减少信号线的数量。又例如，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极也可以分别电连接至不同的信号线，即第一复位晶体管T6的栅极电连接到第一复位控制信号线Rst1，第二复位晶体管T7的栅极电连接到第二复位控制信号线Rst2，而第一复位控制信号线Rst1和第二复位控制信号线Rst2传输的信号相同。需要说明的是，第一子复位控制信号和第二子复位控制信号也可以不相同。
例如，在一些示例中，第二子复位控制信号可以与扫描信号相同，即第二复位晶体管T7的栅极可以电连接到第一扫描信号线Ga1以接收扫描信号作为第二子复位控制信号。
例如，第一复位电源端Vinit1和第二复位电源端Vinit2可以为直流参考电压端，以输出恒定的直流参考电压。第一复位电源端Vinit1和第二复位电源端Vinit2可以为高压端，也可以为低压端，只要其能够提供第一复位信号和第二复位信号以对驱动晶体管T1的栅极和发光元件120的第一发光电压施加电极进行复位即可，本公开对此不作限制。
需要说明的是，图3A-3B所示的像素电路中的驱动电路122、数据写入电路126、存储电路127、阈值补偿电路128和复位电路129仅为示意性的，驱动电路122、数据写入电路126、存储电路127、阈值补偿电路128和复位电路129等电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
例如，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，驱动 晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
需要说明的是，除了设置位置以外，第一子像素G1的像素电路121a中的各个电路(例如，驱动电路122a、第一发光控制电路123a、第二发光控制电路124a、数据写入电路126a、存储电路127a、阈值补偿电路128a、复位电路129a等)的连接关系、结构和类型等分别与第二子像素G2的像素电路121b中的对应的各个电路(例如，驱动电路122b、第一发光控制电路123b、第二发光控制电路124b、数据写入电路126b、存储电路127b、阈值补偿电路128b、复位电路129b等)的连接关系、结构和类型等均相同，也就是说，例如，第一子像素G1的像素电路121a中的驱动电路122a的结构和类型等均与第二子像素G2的像素电路121b中的驱动电路122b的结构和类型等相同。且，第一子像素G1的像素电路121a中的各个电路与第二子像素G2的像素电路121b中的对应的各个电路可以采用同一工艺同时制备，例如，第一子像素G1的像素电路121a中的驱动电路122a与第二子像素G2的像素电路121b中的驱动电路122b采用同一构图工艺同时制备得到。
值得注意的是，如图3B所示，与第一子像素G1的像素电路121a中的各个电路电连接的各条信号线分别为第一扫描信号线Ga1a、第二扫描信号线Ga2a、第一复位控制信号线Rst1a、第二复位控制信号线Rst2a、第一复位电源端Vinit1a、第二复位电源端Vinit2a、第一发光控制信号线EM1a、第二发光控制信号线EM2a、数据线Vd。如图3C所示，与第二子像素G2的像素电路121b中的各个电路电连接的各条信号线分别为第一扫描信号线Ga1b、第二扫描信 号线Ga2b、第一复位控制信号线Rst1b、第二复位控制信号线Rst2b、第一复位电源端Vinit1b、第二复位电源端Vinit2b、第一发光控制信号线EM1b、第二发光控制信号线EM2b、数据线Vd。
需要说明的是，在本公开实施例中，子像素的像素电路除了可以为图3A所示的7T2C(即七个晶体管、一个电容和一个寄生电容)的结构之外，还可以为包括其他数量的晶体管的结构，如6T2C结构或者9T2C结构，本公开实施例对此不作限定。
图4A-4E为本公开一些实施例提供的一种像素电路的各层的示意图。下面结合附图4A-4E描述像素电路中的各个电路在背板上的位置关系，图4A-4E所示的示例以第一子像素G1的像素电路121a为例。如图3B所示，该第一子像素G1的像素电路121a包括图3B所示的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7、第一电容C11、第三电容C2，图4A-4E还示出了连接到第一子像素G1的像素电路121a的第一扫描信号线Ga1a、第二扫描信号线Ga2a、第一复位控制信号线Rst1a、第二复位控制信号线Rst2a、第一复位电源端Vinit1a的第一复位电源信号线Init1a、第二复位电源端Vinit2a的第二复位电源信号线Init2a、第一发光控制信号线EM1a、第二发光控制信号线EM2a、数据线Vd、第一电源端VDD的第一电源信号线VDD1、第二电源信号线VDD2，第一电源信号线VDD1和第二电源信号线VDD2彼此电连接。需要说明的是，在图4A至4E所示的示例中，第一扫描信号线Ga1a和第二扫描信号线Ga2a为同一条信号线，第一复位电源信号线Init1a和第二复位电源信号线Init2a为同一条信号线，第一复位控制信号线Rst1a和第二复位控制信号线Rst2a为同一条信号线，第一发光控制信号线EM1a和第二发光控制信号线EM2a为同一条信号线。
例如，图4A示出了该像素电路121a的有源半导体层310。有源半导体层310可采用半导体材料图案化形成。有源半导体层310可用于制作上述的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的有源层，各有源层可包括源极区域、漏极区域和源极区域和漏极区域之间的沟道区。例如，各晶体管的有源层一体设置。
例如，有源半导体层310可采用非晶硅、多晶硅、氧化物半导体材料等制 作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
例如，像素电路121a的栅极金属层可以包括第一导电层和第二导电层。在上述的有源半导体层310上形成有栅极绝缘层(未示出)，用于保护上述的有源半导体层310。图4B示出了该像素电路121a的第一导电层320，第一导电层320设置在栅极绝缘层上，从而与有源半导体层310绝缘。第一导电层320可以包括第三电容C2的第二极CC2a、第一扫描信号线Ga1a、第二扫描信号线Ga2a、第一复位控制信号线Rst1a、第二复位控制信号线Rst2a、第一发光控制信号线EM1a、第二发光控制信号线EM2a、以及驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的栅极。
例如，如图4B所示，数据写入晶体管T2的栅极可以为第一扫描信号线Ga1a与有源半导体层310交叠的部分，第一发光控制晶体管T4的栅极可以为第一发光控制信号线EM1a/第二发光控制信号线EM2a与有源半导体层310交叠的第一部分，第二发光控制晶体管T5的栅极可以为第一发光控制信号线EM1a/第二发光控制信号线EM2a与有源半导体层310交叠的第二部分，第一复位晶体管T6的栅极为第一复位控制信号线Rst1a/第二复位控制信号线Rst2a与有源半导体层310交叠的第一部分，第二复位晶体管T7的栅极为第一复位控制信号线Rst1a/第二复位控制信号线Rst2a与有源半导体层310交叠的第二部分，阈值补偿晶体管T3可为双栅结构的薄膜晶体管，阈值补偿晶体管T3的第一个栅极可为第二扫描信号线Ga2a与有源半导体层310交叠的部分，阈值补偿晶体管T3的第二个栅极可为从第二扫描信号线Ga2a突出的突出部与有源半导体层310交叠的部分；如图3B和4B所示，驱动晶体管T1的栅极可为第一电容C11的第二极CC4a和第三电容C2的第二极CC2a。
需要说明的是，图4A中的各虚线矩形框示出了第一导电层320与有源半导体层310交叠的各个部分。
例如，如图4B所示，第一扫描信号线Ga1a/第二扫描信号线Ga2a、第一复位控制信号线Rst1a/第二复位控制信号线Rst2a和第一发光控制信号线EM1a/第二发光控制信号线EM2a沿第一方向X排布。第一扫描信号线Ga1a/第二扫描信号线Ga2a位于第一复位控制信号线Rst1a/第二复位控制信号线Rst2a和第一发光控制信号线EM1a/第二发光控制信号线EM2a之间。
例如，在第一方向X上，第一电容C11的第二极CC4a(即第三电容C2的第二极CC2a)位于第一扫描信号线Ga1a/第二扫描信号线Ga2a和第一发光控制信号线EM1/a第二发光控制信号线EM2a之间。从第二扫描信号线Ga2a突出的突出部位于第二扫描信号线Ga2a的远离第一发光控制信号线EM1a/第二发光控制信号线EM2a的一侧。
例如，如图4A所示，在第一方向X上，数据写入晶体管T2的栅极、阈值补偿晶体管T3的栅极、第一复位晶体管T6的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第一侧，第一发光控制晶体管T4的栅极、第二发光控制晶体管T5的栅极均位于驱动晶体管T1的栅极的第二侧，例如，图6A-6E所示的示例中，第一子像素G1的像素电路121a的驱动晶体管T1的栅极的第一侧和第二侧为在第一方向X上驱动晶体管T1的栅极的彼此相对的两侧，例如，如图4A-4E所示，第一子像素G1的像素电路121a的驱动晶体管T1的栅极的第一侧可以为驱动晶体管T1的栅极的上侧，第一子像素G1的像素电路121a的驱动晶体管T1的栅极的第二侧可以为驱动晶体管T1的栅极的下侧。
例如，在一些实施例中，如图4A-4E所示，在第二方向Y上，数据写入晶体管T2的栅极和第一发光控制晶体管T4的栅极均位于驱动晶体管T1的栅极的第三侧，阈值补偿晶体管T3的第一个栅极、第二发光控制晶体管T5的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第四侧，例如，图4A-4E所示的示例中，第一子像素G1的像素电路121a的驱动晶体管T1的栅极的第三侧和第四侧为在第二方向Y上驱动晶体管T1的栅极的彼此相对的两侧，例如，如图4A-4E所示，第一子像素G1的像素电路121a的驱动晶体管T1的栅极的第三侧可以为第一子像素G1的像素电路121a的驱动晶体管T1的栅极的右侧，第一子像素G1的像素电路121a的驱动晶体管T1的栅极的第四侧可以为第一子像素G1的像素电路121a的驱动晶体管T1的栅极的左侧。
例如，在上述的第一导电层320上形成有第一绝缘层(未示出)，用于保护上述的第一导电层320。图4C示出了该像素电路120a的第二导电层330，第二导电层330包括第三电容C2的第一极CC1a、第一复位电源信号线Init1a、第二复位电源信号线Init2a、第二电源信号线VDD2。第二电源信号线VDD2与第三电容C2的第一极CC1a一体形成。第三电容C2的第一极CC1a与第三电容C2的第二极CC2a至少部分重叠以形成第三电容C2。
例如，在上述的第二导电层330上形成有第二绝缘层(未示出)，用于保护上述的第二导电层330。图4D示出了该像素电路121a的源漏极金属层340，源漏极金属层340包括数据线Vd和第一电源信号线VDD1。
图4E为上述的有源半导体层310、第一导电层320、第二导电层330和源漏极金属层340的层叠位置关系的示意图。如图4D和4E所示，数据线Vd通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔381a)与有源半导体层310中的数据写入晶体管T2的源极区域相连。第一电源信号线VDD1通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔382a)与有源半导体层310中对应的第一发光控制晶体管T4的源极区域相连。第一电源信号线VDD1通过第二绝缘层中的至少一个过孔(例如，过孔3832a)与第二导电层330中的第三电容C2的第一极CC1a相连。第一电源信号线VDD1还通过第二绝缘层中的至少一个过孔(例如，过孔3831a)与第二导电层330中的第二电源信号线VDD2相连。
例如，如图4D和4E所示，源漏极金属层340还包括第一连接部341a、第二连接部342a和第三连接部343a。第一连接部341a的一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔384a)与有源半导体层310中对应的阈值补偿晶体管T3的漏极区域相连，第一连接部341a的另一端通过第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔385a)与第一导电层320中的驱动晶体管T1的栅极(即第三电容C2的第二极CC2a)相连。第二连接部342a的一端通过第二绝缘层中的一个过孔(例如，过孔386a)与第一复位电源信号线Init1a/第二复位电源信号线Init2a相连，第二连接部342a的另一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔387a)与有源半导体层310中的第二复位晶体管T7的漏极区域相连。第三连接部343a通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔388a)与有源半导体层310中的第二发光控制晶体管T5的漏极区域相连。
例如，在上述的源漏极金属层340上形成有中间层(未示出)，用于保护上述的源漏极金属层340。各个子像素的发光元件的第一发光电压施加电极可设置在中间层远离衬底基板的一侧。
例如，如图4A-4E所示，在第一方向X上，第一扫描信号线Ga1a、第二扫描信号线Ga2a、第一复位控制信号线Rst1a、第二复位控制信号线Rst2a、第 一复位电源信号线Init1a和第二复位电源信号线Init2a均位于第一子像素G1的像素电路121a的驱动晶体管T1的栅极的第一侧，第一发光控制信号线EM1a、第二发光控制信号线EM2a均位于第一子像素G1的像素电路121a的驱动晶体管T1的第二侧。
例如，第一扫描信号线Ga1a、第二扫描信号线Ga2a、第一复位控制信号线Rst1a、第二复位控制信号线Rst2a、第一发光控制信号线EM1a、第二发光控制信号线EM2a、第一复位电源信号线Init1a和第二复位电源信号线Init2a均沿第二方向Y延伸，数据线Vd沿第一方向X延伸。
例如，第一电源信号线VDD1沿第一方向X延伸，第二电源信号线VDD2沿第二方向Y延伸。第一电源端VDD的信号线在显示基板上网格化布线，也就是说，在整个显示基板上，第一电源信号线VDD1和第二电源信号线VDD2呈网格状排列，从而第一电源端VDD的信号线的电阻较小、压降较低，进而可以提高第一电源端VDD提供的电源电压的稳定性。
例如，第一扫描信号线Ga1a、第二扫描信号线Ga2a、第一复位控制信号线Rst1a、第二复位控制信号线Rst2a、第一发光控制信号线EM1a、第二发光控制信号线EM2a位于同一层，第一复位电源信号线Init1a、第二复位电源信号线Init2a和第二电源信号线VDD2a位于同一层。第一电源信号线VDD1和数据线Vd位于同一层。
需要说明的是，每个像素电路中的驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、存储电路、阈值补偿电路和复位电路等的位置排布关系不限于图4A-4E所示的示例，根据实际应用需求，可以具体设置驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、存储电路、阈值补偿电路和复位电路的位置。
图5A为本公开一些实施例提供的一种显示基板的平面示意图；图5B为本公开一些实施例提供的一种重复单元的平面示意图；图6A为本公开一些实施例提供的另一种重复单元的平面示意图；图6B为本公开一些实施例提供的一种显示基板的布局图；图6C为图6B中线L1-L1'的截面结构示意图；图6D为图6B中线L2-L2'的截面结构示意图；图6E为本公开一些实施例提供的又一种显示基板的平面示意图。
例如，如图5A所示，在本公开的一些实施例中，显示基板10中的像素排列结构可以为GGRB像素排列结构，以增加包含该显示基板10的显示面板的 PPI(pixel per inch，每英寸的像素数)，从而在显示分辨率相同的情况下，增大显示面板的视觉分辨率。例如，每个重复单元11包括四个子像素，四个子像素分别为第一子像素G1、第二子像素G2、第三子像素R和第四子像素B，且该四个子像素可以采用GGRB的排列方式。需要说明的是，在图5A中仅示出了两个完整的重复单元11，但本公开不限于此，显示基板10上包括有多个重复单元11，且多个重复单元11沿第一方向X和第二方向Y阵列排布。
例如，如图5A所示，区域31至40可以为衬底基板10上各个子像素的像素电路所在区域，例如，区域31至35位于第一行，区域36至40位于第二行；区域31和36位于第一列，区域32和37位于第二列，区域33和38位于第三列，区域34和39位于第四列，区域35和40位于第五列。例如，在图5A所示的示例中，在虚线圈出的重复单元11中，第一子像素G1的像素电路位于区域32，第二子像素G2的像素电路位于区域37，第三子像素R的像素电路位于区域38，第四子像素B的像素电路位于区域36。
需要说明的是，在本公开中，“行”可以表示各个像素电路所在区域对应的行，“列”可以表示各个像素电路所在区域对应的列。
例如，发光元件120被配置为在工作时接收发光信号(例如，可以为电流信号)，并发出与该发光信号相对应强度的光。发光元件120可以为发光二极管，发光二极管例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)等，但本公开的实施例不限于此。
例如，如图6C所示，发光元件120包括第一发光电压施加电极1201、第二发光电压施加电极1202和设置在第一发光电压施加电极1201和第二发光电压施加电极1202之间的发光层1203。例如，如图6C所示，第一子像素G1的发光元件包括第一发光电压施加电极1201a、第二发光电压施加电极1202和发光层1203a，第二子像素G2的发光元件包括第一发光电压施加电极1201b、第二发光电压施加电极1202和发光层1203a。
例如，如图6C所示，第一子像素G1的发光元件的第一发光电压施加电极1201a在衬底基板10上的正投影与第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影至少部分重叠，第二子像素G2的发光元件的第一发光电压施加电极1201b在衬底基板10上的正投影与第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影至少部分重叠。
例如，第一子像素G1的发光元件的第一发光电压施加电极1201a和第二子像素G2的发光元件的第一发光电压施加电极1201b可以位于同一层，第一子像素G1的发光元件的第二发光电压施加电极1202和第二子像素G2的发光元件的第二发光电压施加电极1202可以一体设置。
例如，第一子像素G1的发光元件的发光层1203a在衬底基板10上的正投影与第二子像素G2的发光元件的发光层1203a在衬底基板10上的正投影是连续的，也就是说，第一子像素G1的发光元件的发光层1203a和第二子像素G2的发光元件的发光层1203a可以由高精细金属掩模(FMM)板中的一个开孔制作，可以有效降低FMM的工艺难度。例如，第一子像素G1的发光元件的发光层1203a和第二子像素G2的发光元件的发光层1203a为一个整体。
例如，每个子像素的发光层1203的材料可以根据每个子像素的发光元件120发射光的颜色的不同进行选择。每个子像素的发光层1203的材料包括荧光发光材料或磷光发光材料等。例如，在一些实施例中，第一发光电压施加电极1201为阳极，第二发光电压施加电极1202为阴极，第一发光电压施加电极1201和第二发光电压施加电极1202均采用导电材料制备。需要说明的是，在一些示例中，第一发光电压施加电极1201和发光层1203之间设置有第一有机层，第二发光电压施加电极1202和发光层1203之间设置有第二有机层。第一有机层和第二有机层用于起平坦作用，可以被省略。
例如，在每个重复单元11中，第一子像素G1的发光元件120a发出的光的颜色和第二子像素G2的发光元件120b发出的光的颜色相同，也就是说，第一子像素G1和第二子像素G2为相同颜色的子像素。例如，第一子像素G1和第二子像素G2为敏感颜色子像素，当显示基板100采用红绿蓝(RGB)显示模式时，上述的敏感颜色为绿色，即第一子像素G1和第二子像素G2均为绿色子像素。例如，第三子像素R可以为红色子像素，第四子像素B可以为蓝色子像素。
例如，每个重复单元11中的四个子像素可以形成两个虚拟像素，重复单元11中的第三子像素R和第四子像素B分别被所述两个虚拟像素共用。多个重复单元11中的子像素形成像素阵列，在像素阵列的行方向上，子像素密度是虚拟像素密度的1.5倍，在像素阵列的列方向上，子像素密度是虚拟像素密度的1.5倍。
例如，第一子像素G1和第二子像素G2分别属于两个虚拟像素。
需要说明的是，第一，由于第三子像素R和第四子像素B是被相邻的两个虚拟像素共享，因而每个虚拟像素的边界也是非常模糊的，因而，本公开实施例并不对每个虚拟像素的形状进行限定。第二、虚拟像素的划分与驱动方式相关，虚拟像素的具体划分方式可以根据实际的驱动方式确定，本公开对此不作具体限制。
例如，如图6C所示，第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影位于第一子像素G1的发光元件120a的第一发光电压施加电极1201a在衬底基板10上的正投影内；第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影位于第二子像素G2的发光元件120b的第一发光电压施加电极1201b在衬底基板10上的正投影内。也就是说，第一子像素G1的发光元件120a的第一发光电压施加电极1201a在衬底基板10上的正投影完全覆盖第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影，第二子像素G2的发光元件120b的第一发光电压施加电极1201b在衬底基板10上的正投影完全覆盖第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影，例如，第一子像素G1的发光元件120a的第一发光电压施加电极1201a在衬底基板10上的正投影的面积可以大于第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影的面积，第二子像素G2的发光元件120b的第一发光电压施加电极1201b在衬底基板10上的正投影的面积可以大于第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影的面积。
例如，如图3B所示，当第一子像素G1的像素电路的驱动电路122a包括驱动晶体管T1时，第一子像素G1的像素电路的驱动电路122a的控制端1221a为第一子像素G1的像素电路驱动晶体管T1的栅极，则第一子像素G1的发光元件120a的第一发光电压施加电极在衬底基板10上的正投影与第一子像素G1的驱动晶体管T1的栅极在衬底基板10上的正投影至少部分重叠；如图3C所示，当第二子像素G2的像素电路的驱动电路122b包括驱动晶体管T1时，第二子像素G2的像素电路的驱动电路122b的控制端1221b为第二子像素G2的像素电路的驱动晶体管T1的栅极，第二子像素G2的发光元件120b的第一发光电压施加电极在衬底基板10上的正投影与第二子像素G2的驱动晶体管T1的栅极在衬底基板10上的正投影至少部分重叠。
例如，第一子像素G1的驱动晶体管T1的栅极在衬底基板10上的正投影位于第一子像素G1的发光元件120a的第一发光电压施加电极在衬底基板10上的正投影内；第二子像素G2的驱动晶体管T1的栅极在衬底基板10上的正投影位于第二子像素G2的发光元件120b的第一发光电压施加电极在衬底基板10上的正投影内。
例如，如图6C所示，第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影和第一子像素G1的发光元件的第一发光电压施加电极1201a在衬底基板10上的正投影的重叠部分的面积为第一面积AR1，第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影和第二子像素G2的发光元件的第一发光电压施加电极1201b在衬底基板10上的正投影的重叠部分的面积为第二面积AR2，第一面积AR1和第二面积AR2的比值满足以下关系式：
Amin≤AR1/AR2≤Amax，
其中，AR1表示第一面积，AR2表示第二面积，Amin表示最小比值阈值，且为90％，Amax表示最大比值阈值，且为110％。
例如，在一些示例中，第一面积AR1可以大于等于第二面积AR2，此时，最小比值阈值Amin可以为90％，最大比值阈值Amax也可以为100％；在另一些示例中，第一面积AR1可以小于第二面积AR2，此时，最小比值阈值Amin也可以为95％，最大比值阈值Amax也可以为105％。本公开的实施例对最小比值阈值和最大比值阈值的具体值不作具体限制，只要保证第一面积AR1和第二面积AR2之间的差异较小(例如，小于10％)，进而可以保证第一子像素G1的发光元件的第一发光电压施加电极1201a和第一子像素G1的驱动电路的控制端1221a之间的寄生电容(即图3B所示的第一电容C11)和第二子像素G2的发光元件的第一发光电压施加电极1201b和第二子像素G2的驱动电路的控制端1221b之间的寄生电容(即图3C所示的第二电容C12)之间的差异也较小(例如，小于10％)，从而提高包含该显示基板100的显示面板的显示效果即可。例如，第一面积AR1和第二面积AR2的比值处于上述最小比值阈值和最大比值阈值之间时，即使在低灰阶(如64灰阶)下，即在人眼识别能力较高的情况下，用户也可能并无法看出第一子像素G1和第二子像素G2之间的亮度差异，有效改善显示面板的显示效果，提升用户体验。
例如，如图5A和5B所示，第一子像素G1的发光元件120a的第一发光 电压施加电极1201a的形状与第二子像素G2的发光元件的第一发光电压施加电极1201b的形状不相同。例如，在一些示例中，第一子像素G1的发光元件的第一发光电压施加电极1201a的形状可以为八边形，第二子像素G2的发光元件的第一发光电压施加电极1201b的形状可以为五边形。
例如，在每个重复单元11中，第一子像素G1的发光元件的第一发光电压施加电极1201a在衬底基板10上的正投影的面积和第二子像素G2的发光元件的第一发光电压施加电极1201b在衬底基板10上的正投影的面积不相同，第一子像素G1的发光元件的第一发光电压施加电极1201a在衬底基板10上的正投影的面积大于第二子像素G2的发光元件的第一发光电压施加电极1201b在衬底基板10上的正投影的面积。
例如，如图5B所示，第一子像素G1的发光元件120a的第一发光电压施加电极1201a包括辅助电极块Ae，辅助电极块Ae在衬底基板10上的正投影与第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影至少部分重叠。例如，在一些示例中，第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影位于辅助电极块Ae在衬底基板10上的正投影内。
例如，第一子像素G1的驱动晶体管T1的栅极在衬底基板10上的正投影位于第一子像素G1的发光元件120a的第一发光电压施加电极的辅助电极块Ae在衬底基板10上的正投影内。
例如，辅助电极块Ae作为第一电容C11的第一极CC3，第一子像素G1的驱动电路122a的控制端1221a复用为第一电容C11的第二极CC4，也就是说，辅助电极块Ae即为第一电容C11的第一极CC3，第一子像素G1的驱动电路122a的控制端1221a(即第一子像素G1的驱动晶体管T1的栅极)即为第一电容C11的第二极CC4。
例如，如图5B所示，辅助电极块Ae的形状可以为矩形，且辅助电极块Ae在衬底基板10上的正投影的形状与辅助电极块Ae的形状相同，即也为矩形。但本公开不限于此，辅助电极块Ae的形状也可以为五边形、六边形、椭圆形等。
例如，如图5B所示，第一子像素G1的发光元件120a的第一发光电压施加电极1201a还包括第一驱动电极块De1，第一驱动电极块De1和辅助电极块Ae电连接。
例如，如图5B所示，第一驱动电极块De1的形状可以为五边形，且第一驱动电极块De1在衬底基板10上的正投影的形状与第一驱动电极块De1的形状相同，即也为五边形。五边形可以是由一个三角形和一个矩形组成。
例如，在5B所示的示例中，第一驱动电极块De1和辅助电极块Ae一体设置，由此，第一发光电压施加电极1201a的形状可以为八边形，且该八边形可以是由一个五边形和一个矩形组成。
需要说明的是，在另一些示例中，第一驱动电极块De1和辅助电极块Ae也可以分别单独设置，只要第一驱动电极块De1和辅助电极块Ae能够彼此电连接即可。
例如，第一驱动电极块De1和辅助电极块Ae可以由同一构图工艺同时形成。
例如，如图6C所示，第一驱动电极块De1和辅助电极块Ae位于同一层。
例如，如图6C所示，第一驱动电极块De1在衬底基板10上的正投影、第一子像素G1的发光元件的发光层1203a在衬底基板10上的正投影和第一子像素G1的发光元件的第二发光电压施加电极1202在衬底基板10上的正投影至少部分重叠。
例如，在一些实施例中，显示基板上所有子像素的发光元件的第二发光电压施加电极均一体设置，也就是说，第二发光电压施加电极1202整层覆盖在整个衬底基板10上，即第二发光电压施加电极1202可以为一个面状电极。例如，如图6C所示，对于第一子像素G1和第二子像素G2，面状的第二发光电压施加电极1202与第一子像素G1的发光元件的第一发光电压施加电极1201a交叠的部分可以表示为第一子像素G1的发光元件的第二发光电压施加电极1202，面状的第二发光电压施加电极与第二子像素G2的发光元件的第一发光电压施加电极1201b交叠的部分可以表示为第二子像素G2的发光元件的第二发光电压施加电极1202。第一子像素G1的发光元件的第二发光电压施加电极1202和第二子像素G2的发光元件的第二发光电压施加电极1202一体设置。
例如，如图6C所示，第一子像素G1的发光元件的发光层和第二子像素G2的发光元件的发光层一体设置。对于第一子像素G1和第二子像素G2，发光层1203a与第一子像素G1的发光元件的第一发光电压施加电极1201a交叠的部分可以表示为第一子像素G1的发光元件的发光层，发光层1203a与第二子像素G2的发光元件的第一发光电压施加电极1201b交叠的部分可以表示为 第二子像素G2的发光元件的发光层。
例如，如图6C所示，显示基板100还包括像素界定层160，位于各个子像素的发光元件的第一发光电压施加电极远离衬底基板10的一侧且包括第一开口，第一开口暴露第一子像素G1的发光元件的第一发光电压施加电极1201a和第二子像素G2的发光元件的第一发光电压施加电极1201b，第一子像素G1的发光元件的发光层1203a和第二子像素G2的发光元件的发光层1203a的至少部分位于第一开口内并覆盖第一发光电压施加电极1201a和第一发光电压施加电极1201b的被暴露的部分，第一开口与第一发光电压施加电极1201a交叠的部分区域为第一子像素G1的有效发光区，第一开口与第一发光电压施加电极1201b交叠的部分区域为第二子像素G2的有效发光区。
需要说明的是，在本公开的实施例中，每个发光元件的发光层可以包括电致发光层本身以及位于电致发光层两侧的其他公共层，例如，空穴注入层、空穴传输层、电子注入层以及电子传输层等等，但是在本公开的附图中，仅示出了发光层中的电致发光层，而没有示出其他公共层。
例如，在一些示例中，第一驱动电极块De1在衬底基板10上的正投影和第一子像素G1的发光元件的第二发光电压施加电极1202在衬底基板10上的正投影也可以不完全重叠，例如，第一驱动电极块De1在衬底基板10上的正投影位于第一子像素G1的发光元件的第二发光电压施加电极1202在衬底基板10上的正投影内，第一子像素G1的发光元件的发光层1203a在衬底基板10上的正投影也可以位于第一子像素G1的发光元件的第二发光电压施加电极1202在衬底基板10上的正投影内。
需要说明的是，在第一驱动电极块De1在衬底基板10上的正投影、第一子像素G1的发光元件的发光层1203a在衬底基板10上的正投影和第一子像素G1的发光元件的第二发光电压施加电极1202在衬底基板10上的正投影的投影重叠的区域内，对于第一子像素G1，第一子像素G1的发光元件的发光层的对应于像素界定层160的第一开口的部分用于发光。
例如，如图5B所示，第二子像素G2的发光元件120b的第一发光电压施加电极1201b包括第二驱动电极块De2。第二驱动电极块De2在衬底基板10上的正投影与第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影至少部分重叠。例如，在一些示例中，第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影可以位于第二驱动 电极块De2在衬底基板10上的正投影内。例如，第二子像素G2的驱动晶体管T1的栅极在衬底基板10上的正投影位于第二子像素G2的发光元件120b的第一发光电压施加电极的第二驱动电极块De2在衬底基板10上的正投影内。
例如，第二驱动电极块De2可以复用为第二电容C12的第一极，第二子像素G2的驱动电路122b的控制端1221b复用为第二电容C12的第二极，也就是说，第二驱动电极块De2即为第二电容C12的第一极，第二子像素G2的驱动电路122b的控制端1221b(即第二子像素G2的驱动晶体管T1的栅极)即为第二电容C12的第二极。
例如，如图5B所示，第一驱动电极块De1的形状与第二驱动电极块De2的形状可以相同，即，第二驱动电极块De2的形状也可以为五边形。第二驱动电极块De2在衬底基板10上的正投影的形状与第二驱动电极块De2的形状相同，即也为五边形。
例如，第一驱动电极块De1在衬底基板10上的正投影的面积与第二驱动电极块De2在衬底基板10上的正投影的面积相同。
需要说明的是，在一些实施例中，第一驱动电极块De1的形状与第二驱动电极块De2的形状也可以为矩形或菱形等。第一驱动电极块De1的形状与第二驱动电极块De2的形状也可以不相同，本公开对此不作限制。
例如，如图6C所示，第二驱动电极块De2在衬底基板10上的正投影、第二子像素G2的发光元件的发光层1203a在衬底基板10上的正投影和第二子像素G2的发光元件的第二发光电压施加电极1202在衬底基板10上的正投影均至少部分重叠。
例如，在一些示例中，第二驱动电极块De2在衬底基板10上的正投影和第二子像素G2的发光元件的第二发光电压施加电极1202在衬底基板10上的正投影也可以不完全重叠，例如，第二驱动电极块De2在衬底基板10上的正投影位于第二子像素G2的发光元件的第二发光电压施加电极1202在衬底基板10上的正投影内。
需要说明的是，在第二驱动电极块De2在衬底基板10上的正投影、第二子像素G2的发光元件的发光层1203a在衬底基板10上的正投影和第二子像素G2的发光元件的第二发光电压施加电极1202在衬底基板10上正投影的投影重叠的区域内，对于第二子像素G2，第二子像素G2的发光元件的发光层的对应于像素界定层160的第一开口的部分用于发光。
例如，如图5A和5B所示，在每个重复单元11中，第一子像素G1和第二子像素G2沿第一方向X排列，第一方向X平行于衬底基板10的表面。例如，在第一方向X上，辅助电极块Ae位于第一驱动电极块De1的远离第二子像素G2的发光元件的一侧，也就是说，如图5B所示，在第一方向X上，第一驱动电极块De1位于辅助电极块Ae和第二驱动电极块De2之间。
例如，如图6C所示，辅助电极块Ae在衬底基板10上的正投影与第一子像素G1的发光元件的发光层1203a在衬底基板10上的正投影不重叠。例如，在一些示例中，辅助电极块Ae在衬底基板10上的正投影与第一子像素G1的发光元件的发光层1203a在衬底基板10上的正投影完全不重叠。
例如，如图6A和6B所示，第一子像素G1的发光元件的第一发光电压施加电极还包括第一连接电极块Ce1，在第一方向X上，第一连接电极块Ce1位于第一驱动电极块De1的远离第二子像素G2的发光元件的一侧，第一连接电极块Ce1位于辅助电极块Ae和第一驱动电极块De1之间，且与辅助电极块Ae和第一驱动电极块De1均电连接。
例如，在一些实施例中，第一连接电极块Ce1、辅助电极块Ae和第一驱动电极块De1均一体设置。需要说明的是，在另一些示例中，第一连接电极块Ce1、辅助电极块Ae和第一驱动电极块De1也可以分别单独设置，只要第一连接电极块Ce1、辅助电极块Ae和第一驱动电极块De1能够彼此电连接即可。
例如，第一连接电极块Ce1用于连接第一驱动电极块De1与第一子像素G1的像素电路。
例如，如图6C所示，第一连接电极块Ce1、辅助电极块Ae和第一驱动电极块De1位于同一层。第一连接电极块Ce1、辅助电极块Ae和第一驱动电极块De1可以由同一构图工艺同时形成。
例如，第一连接电极块Ce1的形状可以为规则形状，例如，矩形、菱形等；第一连接电极块Ce1的形状也可以为不规则形状。
例如，如图6A和6B所示，在一些示例中，辅助电极块Ae的形状和第一连接电极块Ce1的形状均为矩形，且在第二方向Y上，辅助电极块Ae的宽度小于第一连接电极块Ce1的宽度，即辅助电极块Ae和第一连接电极块Ce1形成阶梯状。在第二方向Y上，第一连接电极块Ce1的宽度小于第一驱动电极块De1的最大宽度。
例如，第一驱动电极块De1具有五个内角，五个内角可以包括两个直角、 两个钝角和一个锐角，第一连接电极块Ce1从第一驱动电极块De1的锐角所在的一侧沿第一驱动电极块De1的远离第二子像素G2的发光元件的方向延伸。
例如，在一些实施例中，第一连接电极块Ce1在衬底基板10上的正投影与第一子像素G1的发光元件的发光层1203a在衬底基板10上的正投影不重叠，且第一连接电极块Ce1在衬底基板10上的正投影与第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影也不重叠。但本公开不限于此，第一连接电极块Ce1在衬底基板10上的正投影与第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影也可以部分重叠。需要说明的是，当第一连接电极块Ce1在衬底基板10上的正投影与第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影部分重叠时，第一连接电极块Ce1在衬底基板10上的正投影与第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影之间的重叠部分的面积小于辅助电极块Ae在衬底基板10上的正投影与第一子像素G1的像素电路的驱动电路的控制端1221a在衬底基板10上的正投影之间的重叠部分的面积。
例如，如图6C和6D所示，显示基板100还包括中间层101。在垂直于衬底基板10的表面的方向上，每个子像素的像素电路121位于中间层101和衬底基板10之间，发光元件120位于中间层101的远离衬底基板10的一侧，也就是说，中间层101位于发光元件120和衬底基板10之间。
例如，在一些实施例中，所有子像素的发光元件所在的层构成第一功能层组，所有子像素的像素电路所在的层构成第二功能层组，也就是说，在垂直于衬底基板10的表面的方向上，第一功能层组位于中间层101的远离衬底基板10的一侧，第二功能层组位于中间层101的靠近衬底基板10的一侧，即第二功能层组位于中间层101和衬底基板10之间，中间层101位于第一功能层组和第二功能层组之间。中间层101位于第一功能层组和第二功能层组之间。例如，图3A所示的驱动电路122、数据写入电路126、存储电路127、阈值补偿电路128和复位电路129等均位于第二功能层组中。例如，第一子像素G1的像素电路121a中第一寄生电路125a和第二子像素G2的像素电路121b中第一寄生电路125b也位于第二功能层组中。
需要说明的是，在本公开的实施例中，第一功能层组可以包括多个子层， 例如，第一功能层组可以包括第一子像素G1的发光元件的第一发光电压施加电极1201a所在的子层、第一子像素G1的发光元件的第二发光电压施加电极1202所在的子层、第一子像素G1的发光元件的发光层1203a所在的子层。类似地，第二功能层组也可以包括多个子层，例如，第二功能层组可以包括第一子像素G2的像素电路中的各个元件所在的子层，当像素电路包括晶体管时，第二功能层组可以包括晶体管的栅极所在的子层、源漏极所在的子层、有源层所在的子层、栅极绝缘层所在的子层等。
例如，中间层101可以为一平坦层。例如，如图6C和6D所示，在垂直于衬底基板10的表面的方向上，第一子像素G1的发光元件的第一发光电压施加电极1201a设置在第一子像素G1的发光元件的发光层1203a的靠近中间层101的一侧，第一子像素G1的发光元件的第二发光电压施加电极1202设置在第一子像素G1的发光元件的发光层1203a的远离中间层101的一侧。
例如，如图6C所示，中间层101包括第一过孔h1，第一连接电极块Ce1延伸至第一过孔h1处且通过第一过孔h1与第一子像素G1的像素电路电连接，例如，第一连接电极块Ce1通过第一过孔h1与第一子像素G1的像素电路的第二发光控制电路124a电连接。例如，第一连接电极块Ce1可以覆盖并填充第一过孔h1。
例如，在第一子像素G1中，第一连接电极块Ce1通过第一过孔h1与第一子像素G1的像素电路的第二发光控制晶体管T5的第二极电连接。
例如，如图4A-4E所示，像素电路121可以包括有源半导体层310、栅极金属层(包括第一导电层320和第二导电层330)和源漏极金属层340，在垂直于衬底基板10的方向上，有源半导体层310位于衬底基板10与栅极金属层之间，栅极金属层位于有源半导体层310和源漏极金属层340之间，例如，栅极金属层的第一导电层320位于有源半导体层310和栅极金属层的第二导电层330之间，栅极金属层的第二导电层330位于栅极金属层的第一导电层320和源漏极金属层340之间。
例如，在本公开中，每个子像素的像素电路121中的各个晶体管(例如，驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7等)的有源层均位于有源半导体层310内，像素电路121中的各个晶体管的栅极均位于栅极金属层的第一导电层320内，像素电路121中的各个晶体管的源极和 漏极均位于源漏极金属层340内。
例如，第一连接电极块Ce1通过第一过孔h1延伸到像素电路的源漏极金属层。
例如，第二子像素G2的发光元件的第一发光电压施加电极还包括第二连接电极块Ce2，第二连接电极块Ce2与第二驱动电极块De2电连接。例如，在一些实施例中，第二连接电极块Ce2与第二驱动电极块De2一体设置。需要说明的是，在另一些示例中，第二连接电极块Ce2与第二驱动电极块De2也可以分别单独设置，只要第二连接电极块Ce2与第二驱动电极块De2能够彼此电连接即可。
例如，第二连接电极块Ce2用于连接第二驱动电极块De2与第二子像素G2的像素电路。
例如，如图6A和6B所示，在第一方向X上，第二连接电极块Ce2位于第二驱动电极块De2的远离第一子像素G1的发光元件的一侧，也就是说，如图6A和6B所示，在第一方向X上，第二驱动电极块De2位于第二连接电极块Ce2和第一驱动电极块De1之间。
例如，如图6C所示，第二连接电极块Ce2与第二驱动电极块De2位于同一层。第二连接电极块Ce2与第二驱动电极块De2可以由同一构图工艺同时形成。
例如，第二连接电极块Ce2的形状可以为规则形状，例如，矩形、菱形等；第二连接电极块Ce2的形状也可以为不规则形状。
例如，在一些示例中，在第二方向Y上，第二连接电极块Ce2的宽度小于第二驱动电极块De2的最大宽度。例如，第二驱动电极块De2具有五个内角，五个内角可以包括两个直角、两个钝角和一个锐角，第二连接电极块Ce2从第二驱动电极块De2的锐角所在的一侧沿第二驱动电极块De2的远离第一子像素G1的发光元件的方向延伸。
例如，在一些示例中，第一连接电极块Ce1的形状和第二连接电极块Ce2的形状可以相同。
例如，在一些实施例中，第二连接电极块Ce2在衬底基板10上的正投影与第二子像素G2的发光元件的发光层1203a在衬底基板10上的正投影不重叠，且第二连接电极块Ce2在衬底基板10上的正投影与第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影也不重叠。但本 公开不限于此，第二连接电极块Ce2在衬底基板10上的正投影与第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影也可以部分重叠。需要说明的是，当第二连接电极块Ce2在衬底基板10上的正投影与第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影部分重叠时，第二连接电极块Ce2在衬底基板10上的正投影与第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影之间的重叠部分的面积小于第二驱动电极块De2在衬底基板10上的正投影与第二子像素G2的像素电路的驱动电路的控制端1221b在衬底基板10上的正投影之间的重叠部分的面积。
例如，与第一子像素G1类似，在垂直于衬底基板10的表面的方向上，第二子像素G2的发光元件的第一发光电压施加电极1201b设置在第二子像素G2的发光元件的发光层1203a的靠近中间层101的一侧，第二子像素G2的发光元件的第二发光电压施加电极1202设置在第二子像素G2的发光元件的发光层1203a的远离中间层101的一侧。
例如，如图6C所示，中间层101包括第二过孔h2，第二连接电极块Ce2延伸至第二过孔h2处且通过第二过孔h2与第二子像素G2的像素电路电连接，例如，第二连接电极块Ce2通过第二过孔h2与第二子像素G2的像素电路的第二发光控制电路124b电连接。例如，第二连接电极块Ce2可以覆盖并填充第二过孔h2。
例如，在第二子像素G2中，第二连接电极块Ce2通过第二过孔h2与第二子像素G2的像素电路121b的第二发光控制晶体管T5的第二极电连接。
例如，第二连接电极块Ce2通过第二过孔h2延伸到像素电路的源漏极金属层。
例如，如图5A所示，在每个重复单元11中，第三子像素R和第四子像素B沿第二方向Y排列，且在第二方向Y上，第一子像素G1和第二子像素G2位于第三子像素R和第四子像素B之间，第二方向Y平行于衬底基板10的表面，且第一方向X和第二方向Y相互垂直。
例如，在每个重复单元11内，第一子像素G1的中心和第二子像素G2的中心的连线为第一中心线，第三子像素R的中心和第四子像素B的中心的连线为第二中心线。第一中心线的长度短于第二中心线的长度。例如，第一中心线和第二中心线相互垂直平分，且第一中心线与第一方向X大致平行，第二中 心线与第二方向Y大致平行。
例如，第三子像素R的发光元件包括第一发光电压施加电极、第二发光电压施加电极和发光层，如图6D所示，第四子像素B的发光元件包括第一发光电压施加电极1201d、第二发光电压施加电极1202d和发光层1203d。需要说明的是，对于第三子像素R，面状的第二发光电压施加电极1202与第三子像素R的发光元件的第一发光电压施加电极交叠的部分可以表示为第三子像素R的发光元件的第二发光电压施加电极；对于第四子像素B，面状的第二发光电压施加电极与第四子像素B的发光元件的第一发光电压施加电极交叠的部分可以表示为第四子像素B的发光元件的第二发光电压施加电极。也就是说，第一子像素G1的发光元件的第二发光电压施加电极、第二子像素G2的发光元件的第二发光电压施加电极、第三子像素R的发光元件的第二发光电压施加电极、第四子像素B的发光元件的第二发光电压施加电极为一个整体。
例如，第三子像素R的发光元件的第一发光电压施加电极在衬底基板10上的正投影与第三子像素R的像素电路的驱动电路的控制端在衬底基板10上的正投影可以至少部分重叠。
例如，第四子像素B的发光元件的第一发光电压施加电极1201d在衬底基板10上的正投影与第四子像素B的像素电路的驱动电路的控制端在衬底基板10上的正投影也可以至少部分重叠。例如，如图6D所示，第四子像素B的像素电路的驱动电路的控制端1221d在衬底基板10上的正投影位于第四子像素B的发光元件的第一发光电压施加电极1201d在衬底基板10上的正投影内。
例如，如图6A和6B所示，第三子像素R的发光元件的第一发光电压施加电极包括彼此电连接的第三驱动电极块De3和第三连接电极块Ce3，第四子像素B的发光元件的第一发光电压施加电极1201d包括彼此电连接的第四驱动电极块De4和第四连接电极块Ce4。例如，第三子像素R的像素电路的驱动电路的控制端1221c在衬底基板10上的正投影与第三驱动电极块De3在衬底基板10上的正投影至少部分重叠；如图6D所示，第四子像素B的像素电路的驱动电路的控制端1221d在衬底基板10上的正投影和第四驱动电极块De4在衬底基板10上的正投影至少部分重叠，例如，第四子像素B的像素电路的驱动电路的控制端1221d在衬底基板10上的正投影位于第四驱动电极块De4在衬底基板10上的正投影内。
例如，第三连接电极块Ce3用于连接第三驱动电极块De3与第三子像素R 的像素电路；第四连接电极块Ce4用于连接第四驱动电极块De4与第四子像素B的像素电路。
例如，第三子像素R的像素电路还包括第三寄生电路，第四子像素B的像素电路还包括第四寄生电路。第三寄生电路包括第四电容，第四寄生电路包括第五电容。第三驱动电极块De3复用为第四电容的第一极，第三子像素R的驱动电路的控制端复用为第四电容的第二极；第四驱动电极块De4复用为第五电容的第一极，第四子像素B的驱动电路的控制端复用为第五电容的第二极。
例如，第三驱动电极块De3的形状可以为规则的六边形，第四驱动电极块De4的形状也可以为规则的六边形。第三连接电极块Ce3的形状可以为不规则的六边形，第四连接电极块Ce4的形状也可以为不规则的六边形。
需要说明的是，在一些实施例中，第三驱动电极块De3和第四驱动电极块De4的形状也可以为矩形或长椭圆形等。本公开对第三驱动电极块De3、第三连接电极块Ce3、第四驱动电极块De4和第四连接电极块Ce4的形状不作具体限制。
例如，第三连接电极块Ce3可以为从六边形的第三驱动电极块De3的一条侧边(例如，六边形的右下侧的侧边)向外凸出的部分；第四连接电极块Ce4可以为从六边形的第四驱动电极块De4的一条侧边(例如，六边形的左下侧的侧边)向外凸出的部分。
需要说明的是，各子像素的驱动电极块的面积可以根据发光材料的发光效率具体设置，例如发光材料的发光效率较高，则子像素的驱动电极块的面积可以较小；而发光材料的发光效率较低，则子像素的驱动电极块的面积可以较大。例如，在一些实施例中，第三驱动电极块De3的面积小于第四驱动电极块De4的面积。第三驱动电极块De3的面积大于第一驱动电极块De1的面积，第三驱动电极块De3的面积大于第二驱动电极块De2的面积。
例如，在一些实施例中，第三驱动电极块De3和第三连接电极块Ce3一体设置，第四驱动电极块De4和第四连接电极块Ce4也一体设置。需要说明的是，在另一些示例中，第三驱动电极块De3和第三连接电极块Ce3也可以分别单独设置，只要第三驱动电极块De3和第三连接电极块Ce3能够彼此电连接即可，同理，第四驱动电极块De4和第四连接电极块Ce4也可以分别单独设置，只要第四驱动电极块De4和第四连接电极块Ce4能够彼此电连接即可。
例如，第三驱动电极块De3和第三连接电极块Ce3位于同一层。如图6D 所示，第四驱动电极块De4和第四连接电极块Ce4位于同一层。
例如，与第一子像素G1和第二子像素G2类似，在垂直于衬底基板10的表面的方向上，第三子像素R的发光元件的第一发光电压施加电极设置在第三子像素R的发光元件的发光层的靠近中间层101的一侧，第三子像素R的发光元件的第二发光电压施加电极设置在第三子像素R的发光元件的发光层的远离中间层101的一侧；如图6D所示，在垂直于衬底基板10的表面的方向上，第四子像素B的发光元件的第一发光电压施加电极1201d设置在第四子像素B的发光元件的发光层1203d的靠近中间层101的一侧，第四子像素B的发光元件的第二发光电压施加电极1202d设置在第四子像素B的发光元件的发光层1203d的远离中间层101的一侧。
例如，如图6B所示，中间层101包括第三过孔h3，第三连接电极块Ce3延伸至第三过孔h3处且通过第三过孔h3与第三子像素R的像素电路电连接。例如，第三连接电极块Ce3可以覆盖并填充第三过孔h3。
例如，如图6D所示，中间层101包括第四过孔h4，第四连接电极块Ce4延伸至第四过孔h4处且通过第四过孔h4与第四子像素B的像素电路电连接。例如，第四连接电极块Ce4可以覆盖并填充第四过孔h4。
例如，第三连接电极块Ce3通过第三过孔h3延伸到像素电路的源漏极金属层；第四连接电极块Ce4通过第四过孔h4延伸到像素电路的源漏极金属层。
例如，第三连接电极块Ce3通过第三过孔h3延伸到像素电路的源漏极金属层，以与位于像素电路的源漏极金属层的第三子像素R的第二发光控制晶体管的第二极电连接。例如，第四连接电极块Ce4通过第四过孔h4延伸到像素电路的源漏极金属层，以与位于像素电路的源漏极金属层的第四子像素B的第二发光控制晶体管的第二极电连接。
例如，如图6A和6B所示，在每个重复单元11中，在第一方向X上，第三连接电极Ce3位于第三驱动电极块De3的远离第一子像素G1的辅助电极块Ae的一侧，在第二方向Y上，第三连接电极Ce3位于第三驱动电极块De3的靠近第四驱动电极块De4的一侧，也就是说，在图6A和6B所示的示例中，第三连接电极块Ce3位于第三驱动电极块De3的右下侧，即第三子像素R的发光元件的第一发光电压施加电极1201c的形状可以为Q字镜像对称的形状。
例如，如图6A和6B所示，在每个重复单元11中，在第一方向X上，第四连接电极Ce4位于第四驱动电极块De4的远离第一子像素G1的辅助电极块 Ae的一侧，在第二方向Y上，第四连接电极Ce4位于第四驱动电极块De4的靠近第三驱动电极块De3的一侧，也就是说，在图6A和6B所示的示例中，第四连接电极块Ce4位于第四驱动电极块De4的左下侧，即第四子像素B的发光元件的第一发光电压施加电极1201d的形状可以为Q形。
例如，第三连接电极Ce3通过第三过孔h3与第三子像素R的像素电路的第二发光控制电路124c电连接，例如，第三连接电极Ce3通过第三过孔h3与第三子像素R的像素电路的第二发光控制晶体管的第二极电连接。
例如，如图6D所示，第四连接电极块Ce4通过第四过孔h4与第四子像素B的像素电路的第二发光控制电路124d电连接，例如，第四连接电极块Ce4通过第四过孔h4与第四子像素B的像素电路的第二发光控制晶体管的第二极电连接。
例如，如图6B所示，在图6D所示的源漏极金属层340上形成有中间层(未示出)，各个子像素的发光元件的第一发光电压施加电极设置在中间层上。第一子像素G1的发光元件的第一发光电压施加电极的第一连接电极块Ce1、第一驱动电极块De1和辅助电极块Ae、第二子像素G2的发光元件的第一发光电压施加电极的第二连接电极块Ce2、第二驱动电极块De2、第三子像素R的发光元件的第一发光电压施加电极的第三连接电极块Ce3、第三驱动电极块De3、第四子像素B的发光元件的第一发光电压施加电极的第四连接电极块Ce4、第四驱动电极块De4均设置在中间层上，第一子像素G1的第一连接电极块Ce1通过第一过孔h1与第一子像素G1的像素电路121a中的第二发光控制晶体管T5连接，第二子像素G2的第二连接电极块Ce2通过第二过孔h2与第二子像素G2的像素电路121b中的第二发光控制晶体管T5连接，第三子像素R的第三连接电极块Ce3通过第三过孔h3与第三子像素R的像素电路中的第二发光控制晶体管T5连接，第四子像素B的第四连接电极块Ce4通过第三过孔h4与第四子像素B的像素电路中的第二发光控制晶体管T5连接。
例如，第一子像素G1的辅助电极块Ae在衬底基板上的正投影与第一子像素G1的像素电路121a中的驱动晶体管的栅极在衬底基板上的正投影至少部分重叠，第二子像素G2的第二驱动电极块De2在衬底基板上的正投影与第二子像素G2的像素电路121b中的驱动晶体管的栅极在衬底基板上的正投影至少部分重叠，第三子像素R的第三驱动电极块De3在衬底基板上的正投影与第三子像素R的像素电路中的驱动晶体管的栅极在衬底基板上的正投影至 少部分重叠，第四子像素B的第四驱动电极块De4在衬底基板上的正投影与第四子像素B的像素电路中的驱动晶体管的栅极在衬底基板上的正投影至少部分重叠。
需要说明的是，图6E示出了各个子像素的驱动电极块、各第一子像素的辅助电极块和各个子像素的连接电极块，图6E还示出了与各个连接电极块对应的过孔。需要说明的是，各个子像素的连接电极块可以覆盖并填充对应的过孔，例如，第一连接电极块覆盖并填充第一过孔h1，第二连接电极块覆盖并填充第二过孔h2，第三连接电极块覆盖并填充第三过孔h3，第四连接电极块覆盖并填充第四过孔h4，然而，为了示出各个过孔的位置，在图6E中各个过孔位于对应的连接电极块上方。
例如，如图6E所示，在第二方向Y上，各过孔排列为多行过孔，每行过孔中的各个过孔按照第三过孔h3、第一过孔h1、第四过孔h4和第二过孔h2的顺序排列，即第三过孔h3、第一过孔h1、第四过孔h4和第二过孔h2为一个排列周期HT1，在该排列周期HT1中，第一过孔h1对应位于第二行且与该第一过孔h1相邻的第一子像素G1，第二过孔h2对应位于第一行且与该第二过孔h2相邻的第二子像素G2，第三过孔h3对应位于第一行且与该第三过孔h3相邻的第三子像素R，第四过孔h4对应位于第一行与该第四过孔h4相邻的第四子像素B。
例如，在第二方向Y上，每行过孔中的各个过孔位于同一条直线上，即每个排列周期HT1中的第一过孔h1、第三过孔h3、第二过孔h2和第四过孔h4位于同一条直线上，且各个排列周期HT1也位于同一条直线上。
例如，在第二方向Y上，任意相邻的两个过孔之间的距离为第一固定距离d1，也就是说，如图6E所示，在排列周期HT1中，第一过孔h1和第四过孔h4之间的距离为第一固定距离d1，第一过孔h1和第三过孔h3之间的距离也为第一固定距离d1，第二过孔h2和第三过孔h3之间的距离也为第一固定距离d1，第二过孔h2和第四过孔h4之间的距离也为第一固定距离d1。需要说明的是，“相邻的两个过孔”表示该两个过孔之间不存在过孔，第一固定距离d1可以表示在第二方向Y上相邻的两个过孔的中心之间的距离。
例如，如图6E所示，在第一方向X上，各第一过孔h1和各第二过孔h2排列为多个第一过孔列，各第三过孔h3和各第四过孔h4排列为多个第二过孔列，在第二方向Y上，第一过孔列和第二过孔列交替排列，也就是说，多个第 一过孔列可以为奇数列，而多个第二过孔列则为偶数列。在每个第一过孔列中，各第一过孔h1和各第二过孔h2位于同一条直线上，在每个第二过孔列中，各第三过孔h3和各第四过孔h4也位于同一条直线上。
例如，在第一方向X上，任意相邻的第一过孔h1和第二过孔h2之间的距离为第二固定距离d2，任意相邻的第三过孔h3和第四过孔h4之间的距离为第三固定距离d3，第二固定距离d2和第三固定距离d3相等。需要说明的是，第二固定距离d2可以表示在第一方向X上相邻的第一过孔h1的中心和第二过孔h2的中心之间的距离，第三固定距离d3可以表示在第一方向X上相邻的第三过孔h3的中心和第四过孔h4的中心之间的距离。
例如，多个重复单元11沿第二方向Y排列以形成多个重复单元组，多个重复单元组沿第一方向X排列。如图6E所示，在第一方向X上，第一连接电极块、第二连接电极块、第三连接电极块和第四连接电极块位于相邻两个重复单元组之间，在第一方向X上，辅助电极块的至少一部分位于在辅助电极块远离第一驱动电极块的一侧且与辅助电极块所在的重复单元组相邻的重复单元组中的相邻两个重复单元之间。例如，在一些实施例中，第P个重复单元组位于第一行，第P+1个重复单元组位于第二行。对于位于第P+1个重复单元组中的重复单元，辅助电极块Ae的至少一部分位于在辅助电极块Ae远离第一驱动电极块De1的一侧且与辅助电极块Ae所在的重复单元组(即第P+1个重复单元组)相邻的重复单元组(即第P个重复单元组)中的相邻两个重复单元之间，例如，如图6E所示，位于第二行的重复单元中的辅助电极块Ae的至少一部分延伸至第一行，且位于第一行的相邻两个重复单元之间，例如，位于第二行的重复单元中的辅助电极块Ae的至少一部分位于第一行的相邻的第三子像素R和第四子像素B之间。
例如，如图6C所示，第一子像素G1的第二发光控制电路124a的第二发光控制晶体管包括第二极1241a(例如，漏极)和有源层1242a。第一子像素G1的驱动电路的驱动晶体管包括栅极1221a(即驱动电路122a的控制端)和有源层1222a。需要说明的是，图6C没有示出第一子像素G1的第二发光控制晶体管的栅极和第一极、第一子像素G1的驱动晶体管的第一极和第二极等。
例如，有源半导体层310和第一导电层320之间设置有栅极绝缘层，即如图6C所示，在第一子像素G1的驱动晶体管的栅极1221a和有源层1222a之间设置有栅极绝缘层131，栅极绝缘层131覆盖在整个显示基板100上，由此， 第二发光控制晶体管的栅极和有源层之间也设置有栅极绝缘层131。第一子像素G1的驱动晶体管的栅极1221a设置在栅极绝缘层131的远离衬底基板10的一侧。如图6C所示，在栅极绝缘层131的远离衬底基板10的一侧还设置有与第一子像素G1的第一发光控制电路连接的第一发光控制信号线EM1a和第二发光控制电路连接的第二发光控制信号线EM2a。
例如，如图6C所示，第一连接电极块Ce1在衬底基板10上的正投影和与第一子像素G1的像素电路的第二发光控制电路连接的第二发光控制信号线EM2a(即与第一子像素G1的第一发光控制电路连接的第一发光控制信号线EM1a)在衬底基板10上的正投影均至少部分重叠。
例如，如图6C所示，在第一子像素G1的驱动晶体管的栅极1221a上还设置有第一绝缘层132，在第一绝缘层132的远离衬底基板10的一侧设置有第一子像素G1的第三电容C2的第一极CC1a。在第三电容C2的第二极CC2a的远离衬底基板10的一侧设置有第二绝缘层133。第一子像素G1的第二发光控制晶体管的第二极1241a设置在第二绝缘层133的远离衬底基板10的一侧，且通过贯穿第二绝缘层133、第一绝缘层132和栅极绝缘层131的过孔388a与第二发光控制晶体管的有源层1242a电连接。例如，第一绝缘层132和第二绝缘层133也覆盖在整个显示基板100上。
例如，在第二绝缘层133的远离衬底基板10的一侧还设置有第一子像素G1的第一连接部341a，第一子像素G1的第一连接部341a通过贯穿第二绝缘层133、第一子像素G1的第三电容C2的第一极CC1a和第一绝缘层132的过孔385a与第一子像素G1的驱动晶体管的栅极1221a电连接。第一连接部341a在衬底基板10上的正投影和第一子像素G1的驱动晶体管的栅极1221a在衬底基板10上的正投影至少部分重叠，也就是说，第一连接部341a在衬底基板10上的正投影、第一子像素G1的驱动晶体管的栅极1221a在衬底基板10上的正投影和辅助电极块Ae在衬底基板10上的正投影至少部分重叠。
需要说明的是，对于第一子像素G1，在垂直于衬底基板10的方向上，第一电容C11的第一极CC3a(即辅助电极块Ae)和第二极CC4a(即第一子像素G1的驱动晶体管的栅极1221a)之间，还设置有第一子像素G1的第三电容C2的第一极CC1a、第一子像素G1的第一连接部341a等金属层，因此，在辅助电极块Ae和第一子像素G1的第一连接部341a之间也可能存在寄生电容，在辅助电极块Ae和第一子像素G1的第三电容C2的第一极CC1a之间也可能 存在寄生电容，在第一子像素G1的第三电容C2的第一极CC1a和第一子像素G1的第一连接部341a之间也可能存在寄生电容，在第一子像素G1的驱动晶体管的栅极1221a和第一子像素G1的第一连接部341a之间也可能存在寄生电容，在第一子像素G1的驱动晶体管的栅极1221a和第一子像素G1的第三电容C2的第一极CC1a之间也可能存在寄生电容，这些寄生电容的位置和大小等与显示基板的具体版图(Layout)结构相关，对此，本公开不作详细描述。
例如，第一子像素G1的第二发光控制晶体管的第二极1241a、第一连接部341a均位于像素电路的源漏极金属层340中，第一子像素G1的驱动晶体管的栅极1221a和第一发光控制信号线EM1a/第二发光控制信号线EM2a均位于像素电路的第一导电层320中，第一子像素G1的第三电容C2的第一极CC1a位于像素电路的第二导电层330中，第一子像素G1的第二发光控制晶体管的有源层1242a和驱动晶体管的有源层1222a位于像素电路的有源半导体层310中。
例如，第一连接电极块Ce1通过第一过孔h1延伸到像素电路的源漏极金属层340，以与位于像素电路的源漏极金属层340中的第一子像素G1的第二发光控制晶体管的第二极1241a电连接。
例如，如图6C所示，在垂直于衬底基板10的方向上，在第一连接电极块Ce1和衬底基板10之间设置有与第二子像素G2的像素电路连接的第一复位电源信号线Init1b/第二复位电源信号线Init2b、第二子像素G2的第二连接部342b的至少部分和过孔386b，第二子像素G2的第二连接部342b通过该过孔386b与第一复位电源信号线Init1b/第二复位电源信号线Init2b电连接。
例如，第一复位电源信号线Init1b/第二复位电源信号线Init2b位于像素电路的第二导电层330中。
例如，如图6C所示，在垂直于衬底基板10的方向上，在第一驱动电极块De1和衬底基板10之间设置有与第二子像素G2的像素电路连接的第一复位控制信号线Rst1a/第二复位控制信号线Rst2a、第二子像素G2的第二连接部342b的至少部分、第二子像素G2的第一连接部341b的至少部分、过孔387b、过孔384b、第二子像素G2的第一复位晶体管T6的第二极1291b(也为第二子像素G2的阈值补偿晶体管T3的第二极)、第二子像素G2的第一复位晶体管T6的第一极1292b(也为第二子像素G2的第二复位晶体管T7的第一极)，第二子像素G2的第二连接部342b通过过孔387b与第二子像素G2的第一复 位晶体管T6的第一极1292b电连接，第二子像素G2的第一连接部341b通过过孔384b与第二子像素G2的第一复位晶体管T6的第二极1291b电连接。
例如，如图6C所示，第二子像素G2的第二发光控制电路124b的第二发光控制晶体管包括第二极1241b(例如，漏极)和有源层1242b。第二子像素G2的驱动电路的驱动晶体管包括栅极1221b(即驱动电路122b的控制端)和有源层1222b。需要说明的是，图6C没有示出第二子像素G2的第二发光控制晶体管的栅极和第一极、第二子像素G2的驱动晶体管的第一极和第二极等。
例如，在第二子像素G2的驱动晶体管的栅极1221b和有源层1222b之间也设置有栅极绝缘层131。在第二子像素G2的驱动晶体管的栅极1221b上也设置有第一绝缘层132。在第一绝缘层132的远离衬底基板10的一侧设置有第二子像素G2的第三电容C2的第一极CC1b。第二子像素G2的第二发光控制晶体管的第二极1241b设置在第二绝缘层133的远离衬底基板10的一侧，且通过贯穿第二绝缘层133、第一绝缘层132和栅极绝缘层131的过孔388b与第二子像素G2的第二发光控制晶体管的有源层1242b电连接。
例如，如图6C所示，在栅极绝缘层131的远离衬底基板10的一侧还设置有与第二子像素G2的第一发光控制电路连接的第一发光控制信号线EM1b和第二发光控制电路连接的第二发光控制信号线EM2b。
例如，如图6C所示，第二连接电极块Ce2在衬底基板10上的正投影和与第二子像素G2的像素电路的第二发光控制电路连接的第二发光控制信号线EM2b(即与第二子像素G2的第一发光控制电路连接的第一发光控制信号线EM1b)在衬底基板10上的正投影均至少部分重叠。
例如，如图6C所示，在栅极绝缘层131的远离衬底基板10的一侧还设置有与第二子像素G2的数据写入晶体管电连接的第一扫描信号线Ga1b和与第二子像素G2的阈值补偿晶体管电连接的第二扫描信号线Ga2b。
例如，在第二绝缘层133的远离衬底基板10的一侧还设置有第二子像素G2的第一连接部341b，第二子像素G2的第一连接部341b通过贯穿第二绝缘层133、第二子像素G2的第三电容C2的第一极CC1b和第一绝缘层132的过孔385b与第二子像素G2的驱动晶体管的栅极1221b电连接。第二子像素G2的第一连接部341b在衬底基板10上的正投影和第二子像素G2的驱动晶体管的栅极1221b在衬底基板10上的正投影至少部分重叠，也就是说，第一连接部341b在衬底基板10上的正投影、第二子像素G2的驱动晶体管的栅极1221b 在衬底基板10上的正投影和第二驱动电极块De2在衬底基板10上的正投影至少部分重叠。
需要说明的是，对于第二子像素G2，在垂直于衬底基板10的方向上，第二电容C12的第一极CC1b(即第二驱动电极块De2)和第二极(即第二子像素G2的驱动晶体管的栅极1221b)之间，还设置有第二子像素G2的第三电容C2的第一极CC1b、第二子像素G2的第一连接部341b等金属层，因此，在第二驱动电极块De2和第二子像素G2的第一连接部341b之间也可能存在寄生电容，在第二驱动电极块De2和第二子像素G2的第三电容C2的第一极CC1b之间也可能存在寄生电容，在第二子像素G2的第三电容C2的第一极CC1b和第二子像素G2的第一连接部341b之间也可能存在寄生电容，在第二子像素G2的驱动晶体管的栅极1221b和第二子像素G2的第一连接部341b之间也可能存在寄生电容，在第二子像素G2的驱动晶体管的栅极1221b和第二子像素G2的第三电容C2的第一极CC1b之间也可能存在寄生电容，这些寄生电容的位置和大小等与显示基板的具体版图(Layout)结构相关，对此，本公开不作详细描述。
例如，第二子像素G2的第二发光控制晶体管的第二极1241b、第一连接部341b均位于像素电路的源漏极金属层340中，第二子像素G2的驱动晶体管的栅极1221b和第一发光控制信号线EM1b/第二发光控制信号线EM2b位于像素电路的第一导电层320中，第二子像素G2的第三电容C2的第一极CC1b位于像素电路的第二导电层330中，第二子像素G2的第二发光控制晶体管的有源层1242b和驱动晶体管的有源层1222b位于像素电路的有源半导体层310中。
例如，第二连接电极块Ce2通过第二过孔h2延伸到像素电路的源漏极金属层340，以与位于像素电路的源漏极金属层340的第二子像素G2的第二发光控制晶体管的第二极1241b电连接。
例如，如图6B和图6C所示，第二子像素G2的第一发光电压施加电极在衬底基板上的正投影与第二子像素G2的像素电路对应的有源半导体层在衬底基板上的正投影的重叠部分的形状可以包括“几”字形，该“几”字形对应的有源半导体层部分包括第二子像素G2的像素电路的驱动晶体管的有源层。在垂直于衬底基板的方向上，第二子像素G2的像素电路对应的有源半导体层的与第二子像素G2的第一发光电压施加电极交叠的部分可以包括第二子像素G2的 像素电路的驱动晶体管的有源层。此外，第二子像素G2的像素电路对应的有源半导体层的与第二子像素G2的第一发光电压施加电极交叠的部分还可以包括第二子像素G2的像素电路的第二发光控制晶体管T5的漏极区域。
例如，如图6B和图6C所示，第二子像素G2的第一发光电压施加电极在衬底基板上的正投影与第二子像素G2的像素电路对应的源漏极金属层在衬底基板上的正投影部分重叠。在垂直于衬底基板的方向上，第二子像素G2的像素电路对应的源漏极金属层的与第二子像素G2的第一发光电压施加电极交叠的部分包括第一连接部的一部分(即第一连接部的与第二子像素G2的像素电路的驱动晶体管的栅极交叠的部分)和第三连接部(即第二子像素G2的像素电路的第二发光控制晶体管T5的漏极)、第一电源信号线VDD1的一部分等。
例如，如图6B和图6C所示，在垂直于衬底基板的方向上，第二子像素G2的像素电路对应的有源半导体层的与第一子像素G1的第一发光电压施加电极交叠的部分可以包括第二子像素G2的像素电路中的复位电路129b中的第一复位晶体管T6和第二复位晶体管T7的有源层、漏极区域、第一子像素G1的像素电路中的驱动晶体管的有源层(“几”字形)的一部分、第一子像素G1的像素电路的第二发光控制晶体管T5的漏极区域等。
例如，如图6B和图6C所示，第一子像素G1的第一发光电压施加电极在衬底基板上的正投影与第一子像素G1的像素电路对应的源漏极金属层在衬底基板上的正投影、第二子像素G2的像素电路对应的源漏极金属层在衬底基板上的正投影均部分重叠。例如，在垂直于衬底基板的方向上，第二子像素G2的像素电路对应的源漏极金属层的与第一子像素G1的第一发光电压施加电极交叠的部分包括第一连接部的一部分(即第一连接部的与阈值补偿晶体管的漏极区域交叠的部分)、第二连接部(即第二子像素G2的像素电路的第二复位晶体管的漏极和第一复位电源信号线之间的连接部)和第一电源信号线VDD1的一部分等。第一子像素G1的像素电路对应的源漏极金属层的与第一子像素G1的第一发光电压施加电极交叠的部分包括第一连接部的一部分(即第一连接部的与第一子像素G1的像素电路的驱动晶体管的栅极交叠的部分)和第三连接部(即第一子像素G1的像素电路的第二发光控制晶体管的漏极)等。例如，如图6D所示，第四子像素B的第二发光控制电路124d的第二发光控制晶体管包括第二极1241d(例如，漏极)和有源层1242c。第三子像素R的驱动电路的驱动晶体管包括栅极1221d(即驱动电路122d的控制端)和有源层1222d。 需要说明的是，图6D没有示出第四子像素B的第二发光控制晶体管的栅极和第一极、第四子像素B的驱动晶体管的第一极和第二极等。
例如，如图6D所示，在第四子像素B的驱动晶体管的栅极1221d和有源层1222d之间设置有栅极绝缘层131，在第四子像素B的驱动晶体管的栅极1221d上也设置有第一绝缘层132。在第一绝缘层132的远离衬底基板10的一侧设置有第四子像素B的第三电容C2的第一极CC1d。第四子像素B的第二发光控制晶体管的第二极1241d设置在第二绝缘层133的远离衬底基板10的一侧，且通过贯穿第二绝缘层133、第一绝缘层132和栅极绝缘层131的过孔388d与第四子像素B的第二发光控制晶体管的有源层1242d电连接。
例如，如图6D所示，在栅极绝缘层131的远离衬底基板10的一侧还设置有与第四子像素B的第一发光控制电路连接的第一发光控制信号线EM1d和第二发光控制电路连接的第二发光控制信号线EM2d。例如，如图6B和图6C所示，对于位于第二行的第四子像素B，与该第四子像素B对应的第一发光控制信号线EM1d和第二发光控制信号线EM2d为同一条信号线，且该第一发光控制信号线EM1d/第二发光控制信号线EM2d和与位于第二行的第二子像素G2对应的第一发光控制信号线EM1b/第二发光控制信号线EM2b也为同一条信号线。
例如，如图6D所示，第四连接电极块Ce4在衬底基板10上的正投影和与第四子像素B的像素电路的第二发光控制电路连接的第二发光控制信号线EM2d(即与第四子像素B的第一发光控制电路连接的第一发光控制信号线EM1d)在衬底基板10上的正投影均至少部分重叠。
例如，如图6D所示，在栅极绝缘层131的远离衬底基板10的一侧还设置有与第四子像素B的数据写入晶体管电连接的第一扫描信号线Ga1d和与第四子像素B的阈值补偿晶体管电连接的第二扫描信号线Ga2d。例如，如图6B和图6C所示，对于位于第二行的第四子像素B，与该第四子像素B对应的第一扫描信号线Ga1d和第二扫描信号线Ga2d为同一条信号线，且该第一扫描信号线Ga1d/第二扫描信号线Ga2d和与位于第二行的第二子像素G2对应的第一扫描信号线Ga1b/第二扫描信号线Ga2b也为同一条信号线。
例如，在第二绝缘层133的远离衬底基板10的一侧还设置有第四子像素B的第一连接部341d，第四子像素B的第一连接部341d通过贯穿第二绝缘层133、第四子像素B的第三电容C2的第一极CC1d和第一绝缘层132的过孔 385d与第四子像素B的驱动晶体管的栅极1221d电连接。第四子像素B的第一连接部341d在衬底基板10上的正投影和第四子像素B的驱动晶体管的栅极1221d在衬底基板10上的正投影至少部分重叠，也就是说，第一连接部341d在衬底基板10上的正投影、第四子像素B的驱动晶体管的栅极1221d在衬底基板10上的正投影和第四驱动电极块De4在衬底基板10上的正投影至少部分重叠。
需要说明的是，对于第四子像素B，在垂直于衬底基板10的方向上，第四驱动电极块De4和第四子像素B的驱动晶体管的栅极1221d之间，还设置有第四子像素B的第三电容C2的第一极CC1d、第四子像素B的第一连接部341d等金属层，因此，在第四驱动电极块De4和第四子像素B的第一连接部341d之间也可能存在寄生电容，在第四驱动电极块De4和第四子像素B的第三电容C2的第一极CC1d之间也可能存在寄生电容，在第四子像素B的第三电容C2的第一极CC1d和第四子像素B的第一连接部341d之间也可能存在寄生电容，在第四子像素B的驱动晶体管的栅极1221d和第四子像素B的第一连接部341d之间也可能存在寄生电容，在第四子像素B的驱动晶体管的栅极1221d和第四子像素B的第三电容C2的第一极CC1d之间也可能存在寄生电容，这些寄生电容的位置和大小等与显示基板的具体版图(Layout)结构相关，对此，本公开不作详细描述。
例如，如图6D所示，在衬底基板10上设置有与第四子像素B的像素电路连接的第一复位电源信号线Init1d/第二复位电源信号线Init2和和过孔386d；在垂直于衬底基板10的方向上，在第四驱动电极块Ce1和衬底基板10之间设置有第四子像素B的第二连接部342d的至少部分，第四子像素B的第二连接部342d通过该过孔386d与第一复位电源信号线Init1d/第二复位电源信号线Init2d电连接。
例如，如图6D所示，在垂直于衬底基板10的方向上，在第四驱动电极块De4和衬底基板10之间设置有与第四子像素B的像素电路连接的第一复位控制信号线Rst1d/第二复位控制信号线Rst2d、第四子像素B的第二连接部342d的至少部分、第四子像素B的第一连接部341d、过孔387d、过孔384d、第四子像素B的第一复位晶体管T6的第二极1291d(也为第四子像素B的阈值补偿晶体管T3的第二极)、第四子像素B的第一复位晶体管T6的第一极1292d(也为第四子像素B的第二复位晶体管T7的第一极)，第四子像素B的第二 连接部342d通过过孔387d与第四子像素B的第一复位晶体管T6的第一极1292d电连接，第四子像素B的第一连接部341d通过过孔384d与第四子像素B的第一复位晶体管T6的第二极1291d电连接。
例如，第四子像素B的第二发光控制晶体管的第二极1241d、第一连接部341d均位于像素电路的源漏极金属层340中，第四子像素B的驱动晶体管的栅极1221d和第一发光控制信号线EM1d/第二发光控制信号线EM2d位于第四子像素B的像素电路的栅极金属层第一导电层320中，第四子像素B的第三电容C2的第一极CC1d和第一复位电源信号线Init1d/第二复位电源信号线Init2d位于像素电路的第二导电层330中，第四子像素B的第二发光控制晶体管的有源层1242d和驱动晶体管的有源层1222d位于像素电路的有源半导体层310中。
例如，第四连接电极块Ce4通过第四过孔h4延伸到像素电路的源漏极金属层，以与位于像素电路的源漏极金属层的第四子像素B的第二发光控制晶体管的第二极1241d电连接。
例如，第三子像素R的像素电路和第四子像素B的像素电路中的各个电路(例如，驱动电路、第一发光控制电路、第二发光控制电路、存储电路、复位电路、阈值补偿电路、数据写入电路等)的连接关系与图3A所示的示例相同。
本公开的实施例还提供一种显示基板。如图2所示，显示基板100包括衬底基板10和设置在衬底基板10上的多个重复单元11，每个重复单元11包括多个子像素12。每个子像素12包括发光元件120和像素电路121，像素电路121用于驱动发光元件120发光，像素电路121包括驱动电路122。
例如，如图5A所示，多个子像素12的驱动电路122在衬底基板10上阵列排布，例如，区域31至40可以为衬底基板10上各个子像素的驱动电路所在区域，在图5A所示的示例中示出了两行五列的驱动电路。例如，在图3A所示的示例中，在虚线圈出的重复单元11中，第一子像素G1的像素电路的驱动电路位于区域32，第二子像素G2的像素电路的驱动电路位于区域37，第三子像素R的像素电路的驱动电路位于区域38，第四子像素B的像素电路的驱动电路位于区域36。
需要说明的是，在本公开中，“行”可以表示各个像素电路所在区域对应的行，“列”可以表示各个像素电路所在区域对应的列。
例如，每个子像素的发光元件120包括第一发光电压施加电极、第二发光电压施加电极和设置在第一发光电压施加电极和第二发光电压施加电极之间的发光层。例如，在一些实施例中，第一发光电压施加电极为阳极，第二发光电压施加电极为阴极。
例如，如图5A和6A所示，多个子像素12包括第一子像素G1和第二子像素G2。例如，第一子像素G1的发光元件发出的光的颜色和第二子像素G2的发光元件发出的光的颜色相同，例如，第一子像素G1和第二子像素G2均为绿色子像素。
例如，如图6A所示，第一子像素G1的发光元件的第一发光电压施加电极和第二子像素G2的发光元件的第一发光电压施加电极沿第一方向X排布。
例如，如图6A所示，第一子像素G1的发光元件的第一发光电压施加电极1201a包括辅助电极块Ae、第一驱动电极块De1和第一连接电极块Ce1，辅助电极块Ae、第一驱动电极块De1和第一连接电极块Ce1彼此电连接。
例如，如图6A所示，第二子像素G2的发光元件的第一发光电压施加电极1201b包括第二驱动电极块De2和第二连接电极块Ce2，第二驱动电极块De2和第二连接电极块Ce2电连接。
例如，第一子像素G1的发光元件的第一发光电压施加电极1201a的面积和第二子像素G2的发光元件的第一发光电压施加电极1201b的面积不相同，例如，第一子像素G1的发光元件的第一发光电压施加电极1201a的面积大于第二子像素G2的发光元件的第一发光电压施加电极1201b的面积。
例如，如图6B所示，辅助电极块Ae位于第一子像素G1的像素电路的驱动电路的控制端的远离衬底基板10的一侧，第二驱动电极块De2位于第二子像素G2的像素电路的驱动电路的控制端的远离衬底基板10的一侧。例如，辅助电极块Ae的形状与第二驱动电极块De2的形状不相同，也就是说，位于第一子像素G1的像素电路的驱动电路的控制端的远离衬底基板10的一侧的第一子像素G1的阳极部分的形状与位于第二子像素G2的像素电路的驱动电路的控制端的远离衬底基板10的一侧的第二子像素G2的阳极部分的形状不相同。
例如，如图3A所示，每个子像素的像素电路121的驱动电路122包括驱动晶体管T1。辅助电极块Ae位于第一子像素G1的像素电路的驱动晶体管T1的栅极的远离衬底基板10的一侧，第二驱动电极块De2位于第二子像素G2 的像素电路的驱动晶体管T1的栅极的远离衬底基板10的一侧。
例如，辅助电极块Ae在衬底基板上的正投影与第一子像素G1的像素电路的驱动晶体管T1的栅极在衬底基板上的正投影至少部分重叠，第二驱动电极块De2在衬底基板上的正投影与第二子像素G2的像素电路的驱动晶体管T1的栅极在衬底基板上的正投影至少部分重叠。
例如，辅助电极块Ae在衬底基板上的正投影与第一子像素G1的像素电路的驱动晶体管T1的栅极在衬底基板上的正投影的重叠部分的面积为第一面积，第二驱动电极块De2在衬底基板上的正投影与第二子像素G2的像素电路的驱动晶体管T1的栅极在衬底基板上的正投影的重叠部分的面积为第二面积，第一面积和第二面积的比值满足以下关系式：
Amin≤AR1/AR2≤Amax，
其中，AR1表示第一面积，AR2表示第二面积，Amin表示最小比值阈值，且为90％，Amax表示最大比值阈值，且为110％。
例如，如图6A和图6B所示，第一驱动电极块De1的形状和辅助电极块Ae的形状不相同，第一驱动电极块De1的形状与第二驱动电极块De2的形状相同，例如，第一驱动电机块De1的形状和第二驱动电极块De2的形状均可以为五边形，辅助电极块Ae的形状可以为矩形。但本公开不限于此，第一驱动电机块De1的形状和第二驱动电极块De2的形状也可以为矩形等，辅助电极块Ae的形状也可以为五边形、六边形、椭圆形等。
例如，第一驱动电极块De1在衬底基板10上的正投影的面积与第二驱动电极块De2在衬底基板10上的正投影的面积相同。
例如，如图6A和图6B所示，第一连接电极块Ce1的形状与第二连接电极块Ce2的形状也可以相同，例如，第一连接电极块Ce1的形状与第二连接电极块Ce2的形状均可以为矩形。
例如，第一连接电极块Ce1在衬底基板10上的正投影的面积与第二连接电极块Ce2在衬底基板10上的正投影的面积相同。
需要说明的是，在本公开的一些实施例中，第一连接电极块Ce1的形状与第二连接电极块Ce2的形状也可以不相同，和/或，第一连接电极块Ce1在衬底基板10上的正投影的面积与第二连接电极块Ce2在衬底基板10上的正投影的面积也可以不相同。
例如，如图6B所示，第一子像素G1的像素电路的驱动电路的控制端和 第二子像素G2的像素电路的驱动电路的控制端沿第一方向X排布，也就是说，第一子像素G1的像素电路的驱动晶体管T1的栅极和第二子像素G2的像素电路的驱动晶体管T1的栅极沿第一方向X排布。
例如，如图6B所示，在第一方向X上，第一驱动电极块De1位于第一子像素G1的像素电路的驱动电路的控制端靠近第二子像素G2的像素电路的驱动电路的控制端的一侧。例如，在一些示例中，如图6B所示，在第一方向X上，第一驱动电极块De1位于第一子像素G1的像素电路的驱动电路的控制端和第二子像素G2的像素电路的驱动电路的控制端之间。
例如，如图6B所示，在第一方向X上，第一连接电极块Ce1位于第一驱动电极块De1的远离第二子像素G2的像素电路的驱动电路的控制端的一侧。例如，在第一方向X上，第一连接电极块Ce1位于第一子像素G1的像素电路的驱动电路的控制端和第二子像素G2的像素电路的驱动电路的控制端之间。也就是说，在第一方向X上，第一连接电极块Ce1和第一驱动电极块De1均位于第一子像素G1的像素电路的驱动电路的控制端和第二子像素G2的像素电路的驱动电路的控制端之间。
例如，在第一方向X上，第一连接电极块Ce1位于第一驱动电极块De1的远离第二驱动电极块De2的一侧，也就是说，第一驱动电极块De1位于第一连接电极块Ce1和第二驱动电极块De2之间。
例如，在第一方向X上，第一连接电极块Ce1位于第一驱动电极块De1和辅助电极块Ae之间，也就是说，辅助电极块Ae位于第一连接电极块Ce1的远离第一驱动电极块De1的一侧。
例如，在第一方向X上，第二连接电极块Ce2位于第二子像素G2的像素电路的驱动电路的控制端的远离第一子像素G1的像素电路的驱动电路的控制端的一侧。
例如，在第一方向X上，第二驱动电极块De2位于第二连接电极块Ce2和第一驱动电极块De1之间，即第二连接电极块Ce2位于第二驱动电极块De2的远离第一驱动电极块De1的一侧。
例如，如图5A所示，多个子像素12还包括第三子像素R和第四子像素B。例如，第三子像素R的发光元件的第一发光电压施加电极和第四子像素B的发光元件的第一发光电压施加电极沿第二方向Y排布。第一方向X和第二方向Y相互垂直。
例如，如图6A所示，第三子像素R的发光元件的第一发光电压施加电极包括第三驱动电极块De3和第三连接电极块Ce3，第三驱动电极块De3和第三连接电极块Ce3彼此电连接。例如，第三驱动电极块De3在衬底基板上的正投影与第三子像素R的像素电路的驱动电路的控制端在衬底基板上的正投影至少部分重叠。
例如，如图6A所示，第四子像素B的发光元件的第一发光电压施加电极包括第四驱动电极块De4和第四连接电极块Ce4，第四驱动电极块De4和第四连接电极块Ce4彼此电连接。例如，如图6B示，第四驱动电极块De4位于第四子像素B的像素电路的驱动电路的控制端的远离衬底基板10的一侧，例如，第四驱动电极块De4在衬底基板上的正投影与第四子像素B的像素电路的驱动电路的控制端在衬底基板上的正投影至少部分重叠。
例如，在第一方向X上，第一子像素G1的像素电路的驱动电路的控制端(即驱动晶体管的栅极)的中心和第一驱动电极块De1的中心之间的距离大于第二子像素G2的像素电路的驱动电路的控制端的中心和第二驱动电极块De2的中心之间的距离。
需要说明的是，在本公开中，“中心”可以表示元件的物理形状的几何中心。在对像素排列结构进行设计时，驱动晶体管的栅极、发光元件的阳极等元件一般会设计为规则的形状，比如，矩形、六边形、五边形、梯形或其他形状。在进行设计时，元件(例如，驱动晶体管的栅极或发光元件的阳极等)的中心可以是上述规则形状的几何中心。然而，在实际制造工艺中，所形成的驱动晶体管的栅极、发光元件的阳极等元件的形状一般会与上述设计的规则形状有一定的偏差。例如，上述规则的形状的各个角可能会变成圆角，因此，驱动晶体管的栅极、发光元件的阳极等元件的形状可以为圆角图形。此外，实际制造的驱动晶体管的栅极、发光元件的阳极等元件的形状还可能会与设计的形状有其他的变化。例如，设计为六边形的子像素的形状在实际制造中可能变成近似椭圆形。因此，驱动晶体管的栅极、发光元件的阳极等元件的中心也可能并非制作形成的子像素的不规则形状的严格的几何中心。在本公开的实施例中，元件的中心可以与元件的形状的几何中心有一定的偏移量。此外，“中心”也可以表示元件的重心。
本公开的实施例还提供一种显示基板。如图2所示，显示基板100包括衬底基板10和设置在衬底基板10上的多个重复单元11，每个重复单元11包括 多个子像素12。每个子像素12包括发光元件120和像素电路121，像素电路121用于驱动发光元件120发光。
例如，每个子像素的发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在第一发光电压施加电极和第二发光电压施加电极之间的发光层。
例如，如图3A所示，每个子像素的像素电路121包括驱动电路122、第二发光控制电路124和复位电路129。
例如，第二发光控制电路124电连接至第二发光控制信号线EM2、驱动电路122的第二端、发光元件120的第一发光电压施加电极，且被配置为在第二发光控制信号线EM2提供的第二发光控制信号的控制下实现驱动电路122和发光元件120之间的连接导通或断开。
复位电路129电连接至驱动电路122的控制端和第一复位控制信号线Rst1，且配置为在第一复位控制信号线Rst1提供的第一子复位控制信号的控制下对驱动电路122的控制端进行复位。
例如，第二发光控制信号线EM2和第一复位控制信号线Rst1沿第一方向X排布。如图4B所示，对于第一子像素G1，与该第一子像素G1的第二发光控制电路连接的第二发光控制信号线EM2a和与该第一子像素G1的复位电路连接的第一复位控制信号线Rst1a沿第一方向X排布。
例如，如图5A所示，多个子像素12包括第一子像素G1和第二子像素G2。例如，第一子像素G1的发光元件发出的光的颜色和第二子像素G2的发光元件发出的光的颜色相同，第一子像G1素的发光元件的第一发光电压施加电极的形状和第二子像素G2的发光元件的第一发光电压施加电极的形状不相同。
例如，如图6B所示，第一子像素G1的发光元件的第一发光电压施加电极在衬底基板上的正投影和与第二子像素G2的像素电路的复位电路连接的第一复位控制信号线Rst1b在衬底基板上的正投影、与第一子像素G1的像素电路的第二发光控制电路连接的第二发光控制信号线EM2a在衬底基板上的正投影均至少部分重叠，第二子像素G2的发光元件的第一发光电压施加电极在衬底基板上的正投影和与第二子像素G2的像素电路的第二发光控制电路连接的第二发光控制信号线EM2b在衬底基板上的正投影至少部分重叠。
例如，如图3A所示，复位电路129还电连接至发光元件的第一发光电压 施加电极和第二复位控制信号线Rst2，且配置为在第二复位控制信号线Rst2提供的第二子复位控制信号的控制下对发光元件的第一发光电压施加电极进行复位。例如，在一些实施例中，第一复位控制信号线Rst1和第二复位控制信号线Rst2为同一条信号线。
例如，如图3A所示，每个子像素的像素电路121还包括数据写入电路126，数据写入电路126电连接至驱动电路122的第一端和第一扫描信号线Ga1，且被配置为在第一扫描信号线Ga1提供的扫描信号的控制下将数据信号写入驱动电路122的控制端。
例如，在第一方向X上，第一扫描信号线Ga1位于第二发光控制信号线EM1和第一复位控制信号线Rst1之间，如图4B所示，对于第一子像素G1，与该第一子像素G1的数据写入电路连接的第一扫描信号线Ga1a位于与该第一子像素G1的第二发光控制电路连接的第二发光控制信号线EM2a和与该第一子像素G1的复位电路连接的第一复位控制信号线Rst1a之间。
例如，如图6A所示，第一子像素G1的发光元件的第一发光电压施加电极和第二子像素G2的发光元件的第一发光电压施加电极沿第一方向X排布。
例如，如图6B所示，在第一方向X上，与第二子像素G2的像素电路的数据写入电路连接的第一扫描信号线Ga1b位于第一子像素G1的发光元件的第一发光电压施加电极和第二子像素G2的发光元件的第一发光电压施加电极之间。
例如，每个子像素的复位电路129还与第一复位电源信号线电连接，复位电路129配置为在第一复位控制信号线提供的第一子复位控制信号的控制下根据第一复位电源信号线提供的第一复位信号对驱动电路1222的控制端进行复位。
例如，每个子像素的复位电路129还与第二复位电源信号线电连接，复位电路129配置为在第二复位控制信号线提供的第二子复位控制信号的控制下根据第二复位电源信号线提供的第二复位信号对发光元件的第一发光电压施加电极进行复位。例如，在一些实施例中，第一复位电源信号线和第二复位电源信号线为同一条信号线。
例如，在第一方向X上，第一复位电源信号线位于第一复位控制信号线的远离第二发光控制信号线的一侧，也就是说，第一复位控制信号线位于第一复位电源信号线和第二发光控制信号线。如图4E所示，对于第一子像素G1，在 第一方向X上，与该第一子像素G1的复位电路连接的第一复位电源信号线Init1a位于与该第一子像素G1的复位电路连接的第一复位控制信号线Rst1a的远离与该第一子像素G1的第二发光控制电路连接的第二发光控制信号线EM2a的一侧，即第一复位控制信号线Rst1a位于第一复位电源信号线Init1a和第二发光控制信号线EM2a之间。
例如，第二发光控制信号线、第一复位控制信号线、第一扫描信号线和第一复位电源信号线均沿第二方向延伸，第二方向与第一方向相互垂直。例如，第二发光控制信号线、第一复位控制信号线、第一扫描信号线和第一复位电源信号线彼此平行，例如，大致平行。如图4E所示，对于第一子像素G1，与该第一子像素G1的第二发光控制电路连接的第二发光控制信号线EM2a、与该第一子像素G1的复位电路连接的第一复位控制信号线Rst1a、与该第一子像素G1的数据写入电路连接的第一扫描信号线Ga1a和与该第一子像素G1的复位电路连接的第一复位电源信号线Init1a均沿第二方向Y延伸，且彼此大致平行。
需要说明的是，在本公开中，“延伸”表示各条信号线(例如，第二发光控制信号线、第一复位控制信号线、第一扫描信号线和第一复位电源信号线)大体上的走线方向，各条信号线在微观上可能并不是直线，而是呈波浪状沿第二方向Y延伸。
例如，如图6B所示，第一子像素G1的发光元件的第一发光电压施加电极在衬底基板上的正投影还和与第二子像素G2的像素电路的复位电路连接的第一复位电源信号线Rst1b在衬底基板上的正投影至少部分重叠。
例如，如图6A所示，第一子像素G1的发光元件的第一发光电压施加电极包括辅助电极块Ae、第一驱动电极块De1和第一连接电极块Ce1，辅助电极块Ae、第一驱动电极块De1和第一连接电极块Ce1彼此电连接，且沿第一方向X排布。第二子像素G2的发光元件的第一发光电压施加电极包括第二驱动电极块De2和第二连接电极块Ce2，第二驱动电极块De2和第二连接电极块Ce2电连接，且沿第一方向X排布。
例如，在第一方向X上，第一连接电极块Ce1和辅助电极Ae块均位于第一驱动电极块De1的远离第二驱动电极块De2的一侧，第一连接电极块Ce1位于辅助电极Ae和第一驱动电极块De1之间，第二连接电极块Ce2位于第二驱动电极块De2的远离第一驱动电极块De1的一侧。
例如，如图6B所示，第一驱动电极块De1在衬底基板上的正投影和与第二子像素G2的像素电路的复位电路连接的第一复位控制信号线Rst1b在衬底基板上的正投影、与第二子像素G2的像素电路的复位电路连接的第一复位电源信号线Init1b在衬底基板上的正投影均至少部分重叠，第一连接电极块Ce1在衬底基板上的正投影和与第一子像素G1的像素电路的第二发光控制电路连接的第二发光控制信号线EM1a在衬底基板上的正投影至少部分重叠。在第一方向上，辅助电极块Ae位于与第一子像素G1的像素电路的第二发光控制电路连接的第二发光控制信号线EM1a的远离第二子像素G2的发光元件的第一发光电压施加电极的一侧。
例如，如图6B所示，第二连接电极块Ce2在衬底基板上的正投影和与第二子像素G2的像素电路的第二发光控制电路连接的第二发光控制信号线EM1b在衬底基板上的正投影至少部分重叠，在第一方向X上，第二驱动电极块De2位于与第二子像素G2的像素电路的第二发光控制电路连接的第二发光控制信号线EM1b和与第二子像素G2的像素电路的数据写入电路连接的第一扫描信号线Ga1b之间。
本公开的实施例还提供一种显示面板。图7为本公开一些实施例提供的一种显示面板的局部结构示意图。例如，如图7所示，显示面板700包括上述任一实施例所述的显示基板100。
例如，如图7所示，多个重复单元11沿第二方向Y排列以形成多个重复单元组，图7示出了两个重复单元组，且两个重复单元组分别为第P个重复单元组和第P+1个重复单元组，第P个重复单元组和第P+1个重复单元组为相邻的两个重复单元组，例如，P为大于等于1的正整数。多个重复单元组沿第一方向X排列。也就是说，显示基板100中的多个重复单元11沿第一方向X和第二方向Y呈阵列排布。
需要说明的是，参考上面的图5A和图6E，第P个重复单元组位于第一行，第P+1个重复单元组位于第二行，图7中并没有示出各个子像素的发光元件的连接电极块。
例如，第P个重复单元组中的重复单元的第一子像素G1和第二子像素G2的中心的连线的延长线和第P+1个重复单元组中的重复单元的第一子像素G1和第二子像素G2的中心的连线的延长线不重合。例如，第P个重复单元组中的重复单元的第一子像素G1和第二子像素G2的中心的连线的延长线穿过第 P+1个重复单元组中相邻两个重复单元之间的间隔的中心，类似地，第P+1个重复单元组中的重复单元的第一子像素G1和第二子像素G2的中心的连线的延长线穿过第P个重复单元组中相邻两个重复单元之间的间隔的中心。
例如，显示面板700可以为液晶显示面板或有机发光二极管(OLED)显示面板等。例如，当显示面板700为液晶显示面板时，显示基板100可以为阵列基板，也可以为彩膜基板。当显示面板700为有机发光二极管显示面板时，显示基板100可以为阵列基板。
例如，显示面板700可以为矩形面板、圆形面板、椭圆形面板或多边形面板等。另外，显示面板700不仅可以为平面面板，也可以为曲面面板，甚至球面面板。
例如，显示面板700还可以具备触控功能，即显示面板600可以为触控显示面板。
例如，显示面板700可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
本公开的实施例还提供一种显示装置，图8A为本公开一些实施例提供的一种显示装置的示意性框图，图8B为本公开一些实施例提供的一种显示装置的结构示意图。
例如，如图8A所示，本公开实施例提供的显示装置800包括显示面板801，显示面板801包括显示基板802，显示面板801为上述任一实施例所述的显示面板700，显示基板802为上述任一实施例所述的显示基板100。
例如，如图8A所示，显示装置800还可以包括驱动芯片803，驱动芯片803与显示面板801电连接。
例如，驱动芯片803位于每个重复单元11中的第一子像素G1的远离第二子像素G2的一侧。如图8B所示，显示基板802上的每个重复单元11中的第一子像素G1和第二子像素G2沿第一方向X排列，在第一方向X上，驱动芯片803位于每个重复单元11中的第一子像素G1的远离第二子像素G2的一侧。也就是说，在第一方向X上，第一子像素G1与驱动芯片803之间的距离小于第二子像素G2与驱动芯片803之间的距离。例如，在图8B所示的示例中，相对于第二子像素G2，第一子像素G1更靠近显示面板801的上侧，从而驱动芯片803可以位于显示面板801的上侧。
例如，驱动芯片803可以为半导体芯片，且可以包括数据驱动器。驱动芯 片803中的数据驱动器用于驱动显示面板801中的多条数据线，例如，数据驱动器可以向多条数据线提供数据信号。
例如，显示装置800可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是，对于该显示装置800的其它组成部分(例如控制装置、图像数据编码/解码装置、栅极驱动器、定时控制器、时钟电路等)均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
本公开的实施例还提供一种用于制备根据上述任一实施例所述的显示基板的制备方法，图9为本公开一实施例提供的一种显示基板的制备方法的示意性流程图。
例如，如图9所示，显示基板的制备方法可以包括：
S10：提供衬底基板，
S11：在衬底基板上形成多个重复单元。
例如，在步骤S11中，每个重复单元包括多个子像素，每个子像素包括像素电路和发光元件，发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在第一发光电压施加电极和第二发光电压施加电极之间的发光层，多个子像素包括第一子像素和第二子像素，第一子像素的发光元件发出的光的颜色和第二子像素的发光元件发出的光的颜色相同，第一子像素的发光元件的第一发光电压施加电极的形状和第二子像素的发光元件的第一发光电压施加电极的形状不相同，第一子像素的发光元件的第一发光电压施加电极在衬底基板上的正投影与第一子像素的像素电路的驱动电路的控制端在衬底基板上的正投影至少部分重叠，第二子像素的发光元件的第一发光电压施加电极在衬底基板上的正投影与第二子像素的像素电路的驱动电路的控制端在衬底基板上的正投影至少部分重叠。
例如，在步骤S11中，在形成第一子像素的发光元件的第一发光电压施加电极时，通过一次构图工艺形成第一驱动电极块和辅助电极块，且辅助电极块在衬底基板上的正投影与第一子像素的像素电路的驱动电路的控制端在衬底基板上的正投影至少部分重叠，例如，第一子像素的像素电路的驱动电路的控制端在衬底基板上的正投影位于辅助电极块在衬底基板上的正投影内。例如，在本公开的实施例中，一次构图工艺可以包括：光刻涂覆、曝光、显影、刻蚀和光刻胶剥离等操作。
需要说明的是，当第一发光电压施加电极包括第一连接电极块时，在形成第一驱动电极块和辅助电极块的同时，还可以形成第一连接电极块。
例如，在步骤S11中，在形成第二子像素的发光元件的第一发光电压施加电极时，形成第二驱动电极块，且第二驱动电极块在衬底基板上的正投影与第二子像素的像素电路的驱动电路的控制端在衬底基板上的正投影至少部分重叠，例如，第二子像素的像素电路的驱动电路的控制端在衬底基板上的正投影位于第二驱动电极块在衬底基板上的正投影内。
需要说明的是，当第二发光电压施加电极包括第二连接电极块时，可以通过一次构图工艺形成第二驱动电极块和第二连接电极块。
值得注意的是，关于重复单元的详细说明可以参考上述显示基板的实施例中的相关描述，重复之处在此不再赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (49)

  1. 一种显示基板，包括衬底基板和设置在所述衬底基板上的多个重复单元，
    其中，每个所述重复单元包括多个子像素，每个所述子像素包括发光元件和驱动所述发光元件发光的像素电路，
    所述像素电路包括驱动电路，
    所述发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在所述第一发光电压施加电极和所述第二发光电压施加电极之间的发光层，
    所述多个子像素包括第一子像素和第二子像素，所述第一子像素的发光元件发出的光的颜色和所述第二子像素的发光元件发出的光的颜色相同，所述第一子像素的发光元件的第一发光电压施加电极的形状和所述第二子像素的发光元件的第一发光电压施加电极的形状不相同，
    所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影与所述第一子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠，
    所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影与所述第二子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的显示基板，其中，所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的面积和所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的面积不相同。
  3. 根据权利要求1或2所述的显示基板，其中，所述第一子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影和所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的重叠部分的面积为第一面积，所述第二子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影和所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的重叠部分的面积为第二面积，
    所述第一面积和所述第二面积的比值满足以下关系式：
    Amin≤A1/A2≤Amax，
    其中，A1表示所述第一面积，A2表示所述第二面积，Amin表示最小比值阈值，且为90％，Amax表示最大比值阈值，且为110％。
  4. 根据权利要求1-3任一项所述的显示基板，其中，所述第一子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影位于所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影内；
    所述第二子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影位于所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影内。
  5. 根据权利要求1-4任一项所述的显示基板，其中，所述第一子像素的发光元件的发光层在所述衬底基板上的正投影与所述第二子像素的发光元件的发光层在所述衬底基板上的正投影是连续的。
  6. 根据权利要求1-5任一项所述的显示基板，其中，所述像素电路还包括第一发光控制电路和第二发光控制电路，
    所述驱动电路包括控制端、第一端和第二端，且被配置为为所述发光元件提供驱动所述发光元件发光的驱动电流；
    所述第一发光控制电路与所述驱动电路的第一端和第一电压端连接，且被配置为实现所述驱动电路和所述第一电压端之间的连接导通或断开，
    所述第二发光控制电路与所述驱动电路的第二端和所述发光元件的第一发光电压施加电极电连接，且被配置为实现所述驱动电路和所述发光元件之间的连接导通或断开。
  7. 根据权利要求6所述的显示基板，其中，所述第一子像素的像素电路还包括第一寄生电路，所述第二子像素的像素电路还包括第二寄生电路，
    所述第一寄生电路与所述第一子像素的像素电路的驱动电路的控制端和所述第一子像素的发光元件的第一发光电压施加电极电连接，且被配置为基于所述第一子像素的发光元件的第一发光电压施加电极的电压控制所述第一子像素的像素电路的驱动电路的控制端的电压，
    所述第二寄生电路与所述第二子像素的像素电路的驱动电路的控制端和所述第二子像素的发光元件的第一发光电压施加电极电连接，且被配置为基于所述第二子像素的发光元件的第一发光电压施加电极的电压控制所述第二子像素的像素电路的驱动电路的控制端的电压。
  8. 根据权利要求7所述的显示基板，其中，所述第一寄生电路包括第一 电容，所述第一电容包括第一极和第二极，
    所述第一子像素的发光元件的第一发光电压施加电极包括辅助电极块，所述辅助电极块在所述衬底基板上的正投影与所述第一子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠，
    所述辅助电极块作为所述第一电容的第一极，所述第一子像素的驱动电路的控制端复用为所述第一电容的第二极。
  9. 根据权利要求8所述的显示基板，其中，所述第一子像素的发光元件的第一发光电压施加电极还包括第一驱动电极块，所述第一驱动电极块和所述辅助电极块电连接，
    所述第一驱动电极块在所述衬底基板上的正投影、所述第一子像素的发光元件的发光层在所述衬底基板上的正投影和所述第一子像素的发光元件的第二发光电压施加电极在所述衬底基板上的正投影至少部分重叠。
  10. 根据权利要求9所述的显示基板，其中，所述第二寄生电路包括第二电容，所述第二电容包括第一极和第二极，
    所述第二子像素的发光元件的第一发光电压施加电极包括第二驱动电极块，所述第二驱动电极块在所述衬底基板上的正投影与所述第二子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠，
    所述第二驱动电极块在所述衬底基板上的正投影、所述第二子像素的发光元件的发光层在所述衬底基板上的正投影和所述第二子像素的发光元件的第二发光电压施加电极在所述衬底基板上的正投影至少部分重叠，
    所述第二驱动电极块复用为所述第二电容的第一极，所述第二子像素的驱动电路的控制端复用为所述第二电容的第二极。
  11. 根据权利要求10所述的显示基板，其中，所述第一驱动电极块的形状与所述第二驱动电极块的形状相同，所述第一驱动电极块在所述衬底基板上的正投影的面积与所述第二驱动电极块在所述衬底基板上的正投影的面积相同。
  12. 根据权利要求10或11所述的显示基板，其中，在所述每个重复单元中，所述第一子像素和所述第二子像素沿第一方向排列，所述第一方向平行于所述衬底基板的表面，
    在所述第一方向上，所述辅助电极块位于所述第一驱动电极块的远离所述第二子像素的发光元件的一侧。
  13. 根据权利要求8-12任一项所述的显示基板，其中，所述辅助电极块在 所述衬底基板上的正投影与所述第一子像素的发光元件的发光层在所述衬底基板上的正投影不重叠。
  14. 根据权利要求12所述的显示基板，其中，所述第一子像素的发光元件的第一发光电压施加电极还包括第一连接电极块，
    在所述第一方向上，所述第一连接电极块位于所述第一驱动电极块的远离所述第二子像素的发光元件的一侧，所述第一连接电极块位于所述辅助电极块和所述第一驱动电极块之间，且与所述辅助电极块和所述第一驱动电极块均电连接。
  15. 根据权利要求14所述的显示基板，还包括中间层，
    其中，在垂直于所述衬底基板的表面的方向上，所述像素电路位于所述中间层和所述衬底基板之间，所述发光元件位于所述中间层的远离所述衬底基板的一侧，
    所述中间层包括第一过孔，所述第一连接电极块延伸至所述第一过孔且通过所述第一过孔与所述第一子像素的像素电路电连接。
  16. 根据权利要求15所述的显示基板，其中，所述第二子像素的发光元件的第一发光电压施加电极还包括第二连接电极块，所述第二连接电极块与所述第二驱动电极块电连接，
    在所述第一方向上，所述第二连接电极块位于所述第二驱动电极块的远离所述第一子像素的发光元件的一侧。
  17. 根据权利要求16所述的显示基板，其中，
    所述中间层包括第二过孔，所述第二连接电极块延伸至所述第二过孔且通过所述第二过孔与所述第二子像素的像素电路电连接。
  18. 根据权利要求16或17所述的显示基板，其中，所述第一连接电极块通过所述第一过孔与所述第一子像素的像素电路的第二发光控制电路电连接，所述第二连接电极块通过所述第二过孔与所述第二子像素的像素电路的第二发光控制电路电连接。
  19. 根据权利要求16-18任一项所述的显示基板，其中，所述像素电路包括有源半导体层、栅极金属层和源漏极金属层，在垂直于所述衬底基板的方向上，所述有源半导体层位于所述衬底基板与所述栅极金属层之间，所述栅极金属层位于所述有源半导体层和所述源漏极金属层之间，
    所述第一连接电极块通过所述第一过孔延伸到所述像素电路的源漏极金 属层，
    所述第二连接电极块通过所述第二过孔延伸到所述像素电路的源漏极金属层。
  20. 根据权利要求16-19任一项所述的显示基板，其中，所述多个子像素还包括第三子像素和第四子像素，
    其中，在所述每个重复单元中，所述第三子像素和所述第四子像素沿第二方向排列，且在所述第二方向上，所述第一子像素和所述第二子像素位于所述第三子像素和所述第四子像素之间，
    所述第二方向平行于所述衬底基板的表面，且所述第一方向和所述第二方向相互垂直。
  21. 根据权利要求20所述的显示基板，其中，所述第三子像素的发光元件的第一发光电压施加电极包括彼此电连接的第三驱动电极块和第三连接电极块，所述第四子像素的发光元件的第一发光电压施加电极包括彼此电连接的第四驱动电极块和第四连接电极块，
    所述中间层包括第三过孔和第四过孔，所述第三连接电极块延伸至所述第三过孔且通过所述第三过孔与所述第三子像素的像素电路电连接，所述第四连接电极块延伸至所述第四过孔且通过所述第四过孔与所述第四子像素的像素电路电连接。
  22. 根据权利要求21所述的显示基板，其中，在所述每个重复单元中，
    在所述第一方向上，所述第三连接电极位于所述第三驱动电极块的远离所述辅助电极块的一侧，在所述第二方向上，所述第三连接电极位于所述第三驱动电极块的靠近所述第四驱动电极块的一侧，
    在所述第一方向上，所述第四连接电极位于所述第四驱动电极块的远离所述辅助电极块的一侧，在所述第二方向上，所述第四连接电极位于所述第四驱动电极块的靠近所述第三驱动电极块的一侧。
  23. 根据权利要求21或22所述的显示基板，其中，所述第三连接电极块通过所述第三过孔与所述第三子像素的像素电路的第二发光控制电路电连接，
    所述第四连接电极块通过所述第四过孔与所述第四子像素的像素电路的第二发光控制电路电连接。
  24. 根据权利要求21-23任一项所述的显示基板，其中，所述多个重复单元沿第二方向排列以形成多个重复单元组，所述多个重复单元组沿所述第一方 向排列，
    在所述第一方向上，所述第一连接电极块、所述第二连接电极块、所述第三连接电极块和所述第四连接电极块位于相邻两个重复单元组之间，
    在所述第一方向上，所述辅助电极块的至少一部分位于在所述辅助电极块远离所述第一驱动电极块的一侧且与所述辅助电极块所在的重复单元组相邻的重复单元组中的相邻两个重复单元之间。
  25. 根据权利要求20-24任一项所述的显示基板，其中，所述第一子像素和所述第二子像素均为绿色子像素，所述第三子像素为红色子像素，所述第四子像素为蓝色子像素。
  26. 根据权利要求6-25任一项所述的显示基板，其中，所述像素电路还包括数据写入电路、存储电路、阈值补偿电路和复位电路，
    所述数据写入电路与所述驱动电路的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入所述存储电路；
    所述存储电路与所述驱动电路的控制端和所述第一电压端电连接，且被配置为存储所述数据信号；
    所述阈值补偿电路与所述驱动电路的控制端和第二端电连接，且被配置为对所述驱动电路进行阈值补偿；
    所述复位电路与所述驱动电路的控制端和所述发光元件的第一发光电压施加电极电连接，且配置为在复位控制信号的控制下对所述驱动电路的控制端和所述发光元件的第一发光电压施加电极进行复位。
  27. 根据权利要求26所述的显示基板，其中，所述驱动电路包括驱动晶体管，所述驱动电路的控制端包括所述驱动晶体管的栅极，所述驱动电路的第一端包括所述驱动晶体管的第一极，所述驱动电路的第二端包括所述驱动晶体管的第二极，
    所述数据写入电路包括数据写入晶体管，所述存储电路包括第三电容，所述阈值补偿电路包括阈值补偿晶体管，所述复位电路包括第一复位晶体管和第二复位晶体管，所述第一发光控制电路包括第一发光控制晶体管，所述第二发光控制电路包括第二发光控制晶体管，所述复位控制信号包括第一子复位控制信号和第二子复位控制信号，
    所述数据写入晶体管的第一极与所述驱动晶体管的第一极电连接，所述数据写入晶体管的第二极被配置为接收所述数据信号，所述数据写入晶体管的栅 极被配置为接收所述扫描信号；
    所述第三电容的第一极与所述第一电源端电连接，所述第三电容的第二极与所述驱动晶体管的栅极电连接；
    所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极电连接，所述阈值补偿晶体管的栅极被配置为接收补偿控制信号；
    所述第一复位晶体管的第一极被配置为接收第一复位信号，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连接，所述第一复位晶体管的栅极被配置为接收所述第一子复位控制信号；
    所述第二复位晶体管的第一极被配置为接收第二复位信号，所述第二复位晶体管的第二极与所述发光元件的第一发光电压施加电极电连接，所述第二复位晶体管的栅极被配置为接收所述第二子复位控制信号；
    所述第一发光控制晶体管的第一极与所述第一电源端电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第一发光控制晶体管的栅极被配置为接收第一发光控制信号，
    所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光元件的第一发光电压施加电极电连接，所述第二发光控制晶体管的栅极被配置为接收第二发光控制信号。
  28. 一种显示面板，包括根据权利要求1-27任一项所述的显示基板。
  29. 一种显示装置，包括：根据权利要求28所述的显示面板。
  30. 根据权利要求29所述的显示装置，还包括：驱动芯片，
    其中，所述驱动芯片与所述显示面板电连接，且所述驱动芯片位于每个所述重复单元中的第一子像素的远离第二子像素的一侧。
  31. 根据权利要求29所述的显示装置，其中，在每个所述重复单元中，所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的面积大于所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影的面积。
  32. 一种用于制备根据权利要求1-27任一项所述的显示基板的制备方法，包括：
    提供所述衬底基板，
    在所述衬底基板上形成所述多个重复单元，其中，每个所述重复单元包括 多个子像素，每个所述子像素包括像素电路和发光元件，所述发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在所述第一发光电压施加电极和所述第二发光电压施加电极之间的发光层，所述多个子像素包括第一子像素和第二子像素，所述第一子像素的发光元件发出的光的颜色和所述第二子像素的发光元件发出的光的颜色相同，所述第一子像素的发光元件的第一发光电压施加电极的形状和所述第二子像素的发光元件的第一发光电压施加电极的形状不相同，所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影与所述第一子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠，所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影与所述第二子像素的像素电路的驱动电路的控制端在所述衬底基板上的正投影至少部分重叠。
  33. 一种显示基板，包括衬底基板和设置在所述衬底基板上的多个重复单元，
    其中，每个所述重复单元包括多个子像素，每个所述子像素包括发光元件和驱动所述发光元件发光的像素电路，所述像素电路包括驱动电路，所述发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在所述第一发光电压施加电极和所述第二发光电压施加电极之间的发光层，
    所述多个子像素的驱动电路在所述衬底基板上阵列排布，
    所述多个子像素包括第一子像素和第二子像素，所述第一子像素的发光元件发出的光的颜色和所述第二子像素的发光元件发出的光的颜色相同，
    所述第一子像素的发光元件的第一发光电压施加电极包括辅助电极块、第一驱动电极块和第一连接电极块，所述第一驱动电极块、所述辅助电极块和所述第一连接电极块彼此电连接，
    所述第二子像素的发光元件的第一发光电压施加电极包括第二驱动电极块和第二连接电极块，所述第二驱动电极块和所述第二连接电极块电连接，
    所述辅助电极块位于所述第一子像素的像素电路的驱动电路的控制端的远离所述衬底基板的一侧，
    所述第二驱动电极块位于所述第二子像素的像素电路的驱动电路的控制端的远离所述衬底基板的一侧。
  34. 根据权利要求33所述的显示基板，其中，所述第一驱动电极块的形状和所述辅助电极块的形状不相同，所述第一驱动电极块的形状与所述第二驱 动电极块的形状相同，所述第一驱动电极块在所述衬底基板上的正投影的面积与所述第二驱动电极块在所述衬底基板上的正投影的面积相同。
  35. 根据权利要求33或34所述的显示基板，其中，所述第一连接电极块的形状与所述第二连接电极块的形状相同，所述第一连接电极块在所述衬底基板上的正投影的面积与所述第二连接电极块在所述衬底基板上的正投影的面积相同。
  36. 根据权利要求33-35任一项所述的显示基板，其中，所述第一子像素的像素电路的驱动电路的控制端和所述第二子像素的像素电路的驱动电路的控制端沿第一方向排布，
    在所述第一方向上，所述第一驱动电极块位于所述第一子像素的像素电路的驱动电路的控制端靠近所述第二子像素的像素电路的驱动电路的控制端的一侧。
  37. 根据权利要求36所述的显示基板，其中，在所述第一方向上，所述第一驱动电极块位于所述第一子像素的像素电路的驱动电路的控制端和所述第二子像素的像素电路的驱动电路的控制端之间。
  38. 根据权利要求37所述的显示基板，其中，在所述第一方向上，所述第一连接电极块位于所述第一驱动电极块的远离所述第二子像素的像素电路的驱动电路的控制端的一侧。
  39. 根据权利要求38所述的显示基板，其中，在所述第一方向上，所述第一连接电极块位于所述第一子像素的像素电路的驱动电路的控制端和所述第二子像素的像素电路的驱动电路的控制端之间。
  40. 根据权利要求38或39所述的显示基板，其中，在所述第一方向上，所述第一连接电极块位于所述第一驱动电极块和所述辅助电极块之间。
  41. 根据权利要求36-40任一项所述的显示基板，其中，在所述第一方向上，所述第二连接电极块位于所述第二子像素的像素电路的驱动电路的控制端的远离所述第一子像素的像素电路的驱动电路的控制端的一侧，
    所述第二驱动电极块位于所述第二连接电极块和所述第一驱动电极块之间。
  42. 根据权利要求33-41任一项所述的显示基板，其中，所述第一子像素的像素电路的驱动电路的控制端的中心和所述第一驱动电极块的中心之间的距离大于所述第二子像素的像素电路的驱动电路的控制端的中心和所述第二 驱动电极块的中心之间的距离。
  43. 一种显示基板，包括衬底基板和设置在所述衬底基板上的多个重复单元，
    其中，每个所述重复单元包括多个子像素，每个所述子像素包括发光元件和驱动所述发光元件发光的像素电路，
    所述发光元件包括第一发光电压施加电极、第二发光电压施加电极和设置在所述第一发光电压施加电极和所述第二发光电压施加电极之间的发光层，
    所述像素电路包括驱动电路、第二发光控制电路和复位电路，
    所述第二发光控制电路电连接至第二发光控制信号线、所述驱动电路的第二端、所述发光元件的第一发光电压施加电极，且被配置为在所述第二发光控制信号线提供的第二发光控制信号的控制下实现所述驱动电路和所述发光元件之间的连接导通或断开，
    所述复位电路电连接至所述驱动电路的控制端和第一复位控制信号线，且配置为在所述第一复位控制信号线提供的第一子复位控制信号的控制下对所述驱动电路的控制端进行复位，
    所述第二发光控制信号线和所述第一复位控制信号线沿第一方向排布，
    所述多个子像素包括第一子像素和第二子像素，
    所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影和与所述第二子像素的像素电路的复位电路连接的第一复位控制信号线在所述衬底基板上的正投影、与所述第一子像素的像素电路的第二发光控制电路连接的第二发光控制信号线在所述衬底基板上的正投影均至少部分重叠，
    所述第二子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影和与所述第二子像素的像素电路的第二发光控制电路连接的第二发光控制信号线在所述衬底基板上的正投影至少部分重叠。
  44. 根据权利要求43所述的显示基板，其中，所述像素电路还包括数据写入电路，
    所述数据写入电路电连接至所述驱动电路的第一端和第一扫描信号线，且被配置为在所述第一扫描信号线提供的扫描信号的控制下将数据信号写入所述驱动电路的控制端，
    在所述第一方向上，所述第一扫描信号线位于所述第二发光控制信号线和 所述第一复位控制信号线之间，
    所述第一子像素的发光元件的第一发光电压施加电极和所述第二子像素的发光元件的第一发光电压施加电极沿所述第一方向排布，
    在所述第一方向上，与所述第二子像素的像素电路的数据写入电路连接的第一扫描信号线位于所述第一子像素的发光元件的第一发光电压施加电极和所述第二子像素的发光元件的第一发光电压施加电极之间。
  45. 根据权利要求43或44所述的显示基板，其中，所述复位电路还与第一复位电源信号线电连接，
    所述复位电路配置为在所述第一复位控制信号线提供的第一子复位控制信号的控制下根据所述第一复位电源信号线提供的第一复位信号对所述驱动电路的控制端进行复位，
    在所述第一方向上，所述第一复位电源信号线位于所述第一复位控制信号线的远离所述第二发光控制信号线的一侧，
    所述第一子像素的发光元件的第一发光电压施加电极在所述衬底基板上的正投影还和与所述第二子像素的像素电路的复位电路连接的第一复位电源信号线在所述衬底基板上的正投影至少部分重叠。
  46. 根据权利要求45所述的显示基板，其中，所述第二发光控制信号线、所述第一复位控制信号线、所述第一扫描信号线和所述第一复位电源信号线均沿第二方向延伸，所述第二方向与所述第一方向相互垂直。
  47. 根据权利要求45或46所述的显示基板，其中，所述第二发光控制信号线、所述第一复位控制信号线、所述第一扫描信号线和所述第一复位电源信号线彼此平行。
  48. 根据权利要求45-47任一项所述的显示基板，其中，所述第一子像素的发光元件的第一发光电压施加电极包括辅助电极块、第一驱动电极块和第一连接电极块，所述第一驱动电极块、所述辅助电极块和所述第一连接电极块彼此电连接，且沿所述第一方向排布，
    所述第二子像素的发光元件的第一发光电压施加电极包括第二驱动电极块和第二连接电极块，所述第二驱动电极块和所述第二连接电极块电连接，且沿所述第一方向排布，
    在所述第一方向上，所述第一连接电极块和所述辅助电极块均位于所述第一驱动电极块的远离所述第二驱动电极块的一侧，所述第一连接电极块位于所 述辅助电极块和所述第一驱动电极块之间，所述第二连接电极块位于所述第二驱动电极块的远离所述第一驱动电极块的一侧，
    所述第一驱动电极块在所述衬底基板上的正投影和与所述第二子像素的像素电路的复位电路连接的第一复位控制信号线在所述衬底基板上的正投影、与所述第二子像素的像素电路的复位电路连接的第一复位电源信号线在所述衬底基板上的正投影均至少部分重叠，
    所述第一连接电极块在所述衬底基板上的正投影和与所述第一子像素的像素电路的第二发光控制电路连接的第二发光控制信号线在所述衬底基板上的正投影至少部分重叠，
    在所述第一方向上，所述辅助电极块位于与所述第一子像素的像素电路的第二发光控制电路连接的第二发光控制信号线的远离所述第二子像素的发光元件的第一发光电压施加电极的一侧，
    所述第二连接电极块在所述衬底基板上的正投影和与所述第二子像素的像素电路的第二发光控制电路连接的第二发光控制信号线在所述衬底基板上的正投影至少部分重叠，
    在所述第一方向上，所述第二驱动电极块位于与所述第二子像素的像素电路的第二发光控制电路连接的第二发光控制信号线和与所述第二子像素的像素电路的数据写入电路连接的第一扫描信号线之间。
  49. 根据权利要求43-48任一项所述的显示基板，其中，所述第一子像素的发光元件发出的光的颜色和所述第二子像素的发光元件发出的光的颜色相同，所述第一子像素的发光元件的第一发光电压施加电极的形状和所述第二子像素的发光元件的第一发光电压施加电极的形状不相同。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113506539A (zh) * 2021-07-19 2021-10-15 Oppo广东移动通信有限公司 显示模组和显示设备
CN113920934A (zh) * 2021-09-30 2022-01-11 成都京东方光电科技有限公司 显示基板和显示装置
WO2023051109A1 (zh) * 2021-09-30 2023-04-06 京东方科技集团股份有限公司 显示基板、显示面板和显示装置
EP4207301A4 (en) * 2021-06-10 2023-12-27 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE AND DISPLAY DEVICE
US20240046880A1 (en) * 2021-04-01 2024-02-08 Boe Technology Group Co., Ltd. Pixel drive circuit and driving method thereof, and display panel

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6566289B2 (ja) * 2014-11-26 2019-08-28 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 表示デバイス及び電気光学装置並びに電気機器並びにメタルマスク並びに画素アレイ
CN113906494B (zh) * 2020-05-06 2023-09-15 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
KR20220016347A (ko) * 2020-07-30 2022-02-09 삼성디스플레이 주식회사 표시 장치 및 그의 제조 방법
CN114255703B (zh) * 2020-09-21 2023-06-16 京东方科技集团股份有限公司 显示基板及显示装置
GB2616569A (en) * 2021-04-28 2023-09-13 Boe Technology Group Co Ltd Display substrate and display panel
EP4207296A4 (en) * 2021-04-30 2024-05-29 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE AND DISPLAY DEVICE
TWI828189B (zh) * 2021-07-08 2024-01-01 南韓商Ｌｇ顯示器股份有限公司 像素電路及包含該像素電路的顯示裝置
CN113763874B (zh) * 2021-09-16 2023-09-26 京东方科技集团股份有限公司 显示基板及显示装置
CN116981300A (zh) * 2022-04-29 2023-10-31 京东方科技集团股份有限公司 显示面板及显示装置
CN114843288A (zh) * 2022-05-18 2022-08-02 京东方科技集团股份有限公司 显示基板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070290973A1 (en) * 2006-06-14 2007-12-20 Au Optronics Corporation Structure of pixel circuit for display and driving method thereof
CN106293244A (zh) * 2016-08-30 2017-01-04 京东方科技集团股份有限公司 触控显示面板及其驱动方法以及触控显示装置
CN107256695A (zh) * 2017-07-31 2017-10-17 上海天马有机发光显示技术有限公司 像素电路、其驱动方法、显示面板及显示装置
CN109491158A (zh) * 2018-11-16 2019-03-19 昆山龙腾光电有限公司 一种显示面板及显示装置
CN109559679A (zh) * 2017-09-26 2019-04-02 京东方科技集团股份有限公司 触控显示面板及其驱动方法、像素电路、电子装置

Family Cites Families (198)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4491863A (en) 1979-12-04 1985-01-01 Mitsubishi Denki Kabushiki Kaisha Color display apparatus
JPS60120398A (ja) 1983-12-02 1985-06-27 シチズン時計株式会社 マトリクス形カラー表示装置の駆動方法
US5341153A (en) 1988-06-13 1994-08-23 International Business Machines Corporation Method of and apparatus for displaying a multicolor image
JP2584490B2 (ja) 1988-06-13 1997-02-26 三菱電機株式会社 マトリクス型カラ−液晶表示装置
US6681053B1 (en) 1999-08-05 2004-01-20 Matsushita Electric Industrial Co., Ltd. Method and apparatus for improving the definition of black and white text and graphics on a color matrix digital display device
US6950115B2 (en) 2001-05-09 2005-09-27 Clairvoyante, Inc. Color flat panel display sub-pixel arrangements and layouts
JP3620490B2 (ja) 2000-11-22 2005-02-16 ソニー株式会社 アクティブマトリクス型表示装置
US7123277B2 (en) 2001-05-09 2006-10-17 Clairvoyante, Inc. Conversion of a sub-pixel format data to another sub-pixel data format
TWI227340B (en) 2002-02-25 2005-02-01 Himax Tech Inc Color filter and liquid crystal display
TW200413725A (en) 2002-09-30 2004-08-01 Oncotherapy Science Inc Method for diagnosing non-small cell lung cancers
JP4003714B2 (ja) 2003-08-11 2007-11-07 セイコーエプソン株式会社 電気光学装置及び電子機器
US7525526B2 (en) 2003-10-28 2009-04-28 Samsung Electronics Co., Ltd. System and method for performing image reconstruction and subpixel rendering to effect scaling for multi-mode display
EP1704555A4 (en) 2003-12-15 2009-03-11 Genoa Color Technologies Ltd MULTIPLE PRIMARY LIQUID CRYSTAL DISPLAY
TWI258721B (en) 2004-08-10 2006-07-21 Ind Tech Res Inst Full-color organic electroluminescence device
US7733359B1 (en) 2004-09-15 2010-06-08 Rockwell Collins, Inc. Pixel structure for electrical flat panel displays
WO2006115165A1 (ja) 2005-04-22 2006-11-02 Sharp Kabushiki Kaisha 表示装置
US8207924B2 (en) 2006-02-02 2012-06-26 Sharp Kabushiki Kaisha Display device
US20070205423A1 (en) 2006-03-03 2007-09-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
GB2437110B (en) 2006-04-12 2009-01-28 Cambridge Display Tech Ltd Optoelectronic display and method of manufacturing the same
US20080001525A1 (en) 2006-06-30 2008-01-03 Au Optronics Corporation Arrangements of color pixels for full color OLED
CN101192382B (zh) 2006-11-29 2010-11-10 群康科技(深圳)有限公司 液晶显示器
JP2008225179A (ja) 2007-03-14 2008-09-25 Sony Corp 表示装置、表示装置の駆動方法、および電子機器
TWI359626B (en) 2007-03-22 2012-03-01 Au Optronics Corp Electro-luminescence display
CN101393924B (zh) * 2007-09-21 2015-08-12 北京京东方光电科技有限公司 电致发光显示面板
KR101479994B1 (ko) 2007-11-13 2015-01-07 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
US8330352B2 (en) 2007-11-13 2012-12-11 Samsung Display Co., Ltd. Organic light emitting diode display and method for manufacturing the same
US20090128900A1 (en) 2007-11-15 2009-05-21 Idyllic Spectrum Sdn Bhd Autostereoscopic display
RU2453879C2 (ru) 2008-03-31 2012-06-20 Шарп Кабусики Кайся Жидкокристаллическое устройство отображения
JP2010212814A (ja) 2009-03-06 2010-09-24 Sharp Corp キャリブレーション装置、キャリブレーション方法、キャリブレーションプログラム、コンピュータ読み取り可能な記録媒体、及び画像入力装置
WO2010113357A1 (ja) 2009-04-03 2010-10-07 シャープ株式会社 ドナー基板、転写膜の製造方法、及び、有機電界発光素子の製造方法
CN101582241B (zh) 2009-06-11 2011-10-05 数能科技股份有限公司 大型发光二极管显示器的显示方法
KR20110013691A (ko) 2009-08-03 2011-02-10 삼성모바일디스플레이주식회사 화소구조 및 그를 이용한 유기전계발광표시장치
CA2686174A1 (en) 2009-12-01 2011-06-01 Ignis Innovation Inc High reslution pixel architecture
RU2512680C1 (ru) * 2010-02-26 2014-04-10 Шарп Кабусики Кайся Жидкокристаллическое устройство отображения
KR101663564B1 (ko) 2010-03-26 2016-10-17 엘지디스플레이 주식회사 유기전계발광소자 및 이의 제조방법
US9041625B2 (en) 2010-04-21 2015-05-26 Lg Display Co., Ltd. Subpixel arrangement structure for a display device and display device
KR20110129531A (ko) 2010-05-26 2011-12-02 삼성모바일디스플레이주식회사 유기전계발광 표시장치의 화소배열구조
KR101189025B1 (ko) 2010-05-31 2012-10-08 삼성디스플레이 주식회사 유기전계발광 표시장치의 화소배열구조
US20120039034A1 (en) 2010-08-13 2012-02-16 Mary Lou Jepsen Transflective LCD With Arcuate Pixel Portions
US9583034B2 (en) 2010-10-15 2017-02-28 Lg Display Co., Ltd. Subpixel arrangement structure for display device
US8599118B2 (en) * 2011-02-16 2013-12-03 Global Oled Technology Llc Chiplet display with electrode connectors
US8520114B2 (en) 2011-06-01 2013-08-27 Global Oled Technology Llc Apparatus for displaying and sensing images
KR101845332B1 (ko) 2011-06-13 2018-05-21 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
JP2014225329A (ja) 2011-09-12 2014-12-04 シャープ株式会社 発光デバイス、表示装置、及び照明装置
KR101615332B1 (ko) 2012-03-06 2016-04-26 삼성디스플레이 주식회사 유기 발광 표시 장치의 화소 배열 구조
KR101943995B1 (ko) 2012-06-27 2019-01-31 삼성디스플레이 주식회사 유기전계발광 표시장치
KR102063973B1 (ko) 2012-09-12 2020-01-09 삼성디스플레이 주식회사 유기전계발광 표시장치 및 그의 구동방법
EP3780113A1 (en) 2012-09-13 2021-02-17 Samsung Display Co., Ltd. Pixel arrangement structure for organic light emitting diode display
WO2014080625A1 (ja) 2012-11-22 2014-05-30 株式会社ニコン 撮像素子および撮像ユニット
KR101999560B1 (ko) * 2012-11-28 2019-07-15 삼성디스플레이 주식회사 유기 발광 표시 장치
TWI559524B (zh) 2013-01-15 2016-11-21 友達光電股份有限公司 電激發光顯示面板之畫素結構
KR102124040B1 (ko) 2013-02-01 2020-06-29 삼성디스플레이 주식회사 박막 증착용 마스크, 이의 제조 방법, 및 이를 이용한 유기 발광 표시 장치의 제조 방법
TWI520323B (zh) 2013-02-08 2016-02-01 中華映管股份有限公司 有機發光顯示裝置之畫素結構
JPWO2014136149A1 (ja) 2013-03-04 2017-02-09 株式会社Ｊｏｌｅｄ Ｅｌ表示装置
KR102030799B1 (ko) 2013-03-11 2019-10-11 삼성디스플레이 주식회사 유기발광표시장치
WO2014149864A1 (en) * 2013-03-15 2014-09-25 LuxVue Technology Corporation Light emitting diode display with redundancy scheme and method of fabricating a light emitting diode display with integrated defect detection test
JP5849981B2 (ja) 2013-03-25 2016-02-03 ソニー株式会社 表示装置および電子機器
KR102096051B1 (ko) 2013-03-27 2020-04-02 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 이를 포함하는 유기 발광 표시 장치
TWI478128B (zh) 2013-05-23 2015-03-21 Au Optronics Corp 發光二極體顯示面板
KR20150005264A (ko) 2013-07-05 2015-01-14 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
KR102190843B1 (ko) 2013-07-09 2020-12-15 삼성디스플레이 주식회사 단위 화소 및 이를 구비한 유기 발광 표시 장치
CN103366683B (zh) 2013-07-12 2014-10-29 上海和辉光电有限公司 像素阵列、显示器以及将图像呈现于显示器上的方法
KR20150008712A (ko) 2013-07-15 2015-01-23 삼성디스플레이 주식회사 신호 처리 방법, 신호 처리 장치, 및 신호 처리 장치를 포함하는 표시 장치
KR102136275B1 (ko) 2013-07-22 2020-07-22 삼성디스플레이 주식회사 유기 발광 소자 및 이의 제조 방법
US20150062140A1 (en) 2013-08-29 2015-03-05 Monotype Imaging Inc. Dynamically Adjustable Distance Fields for Adaptive Rendering
CN103489401B (zh) * 2013-09-03 2016-11-23 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板和显示装置
KR102103499B1 (ko) 2013-10-16 2020-04-23 삼성디스플레이 주식회사 유기 발광 표시 장치
US10103205B2 (en) 2013-11-04 2018-10-16 Shenzhen Yunyinggu Technology Co., Ltd. Subpixel arrangements of displays and method for rendering the same
CN103559866B (zh) 2013-11-08 2016-07-06 京东方科技集团股份有限公司 一种图像显示控制方法及装置
JP6207367B2 (ja) 2013-12-05 2017-10-04 株式会社ジャパンディスプレイ 有機エレクトロルミネッセンス表示装置
KR20150067624A (ko) 2013-12-10 2015-06-18 삼성디스플레이 주식회사 유기발광표시장치
CN103714775B (zh) 2013-12-30 2016-06-01 北京京东方光电科技有限公司 像素阵列及其驱动方法、显示面板和显示装置
KR102205401B1 (ko) 2014-01-14 2021-01-21 삼성디스플레이 주식회사 유기발광표시장치
JP2015138955A (ja) 2014-01-24 2015-07-30 凸版印刷株式会社 薄膜トランジスタアレイ基板、ｅｌ表示装置、および、薄膜トランジスタアレイ基板の製造方法
JP6248269B2 (ja) 2014-02-06 2017-12-20 株式会社Ｊｏｌｅｄ 表示装置
US9337241B2 (en) 2014-03-19 2016-05-10 Apple Inc. Pixel patterns for organic light-emitting diode display
CN103928498A (zh) 2014-04-23 2014-07-16 何东阳 有关于一种amoled高分辨率的显示器件
JP6369799B2 (ja) 2014-04-23 2018-08-08 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 画素アレイ及び電気光学装置並びに電気機器
CN103985735A (zh) 2014-04-25 2014-08-13 友达光电股份有限公司 一种显示面板
KR102146828B1 (ko) 2014-04-25 2020-08-24 삼성디스플레이 주식회사 표시장치
CN103985738B (zh) 2014-05-08 2015-06-17 京东方科技集团股份有限公司 像素结构和显示装置
CN104037202B (zh) 2014-06-12 2017-08-04 上海和辉光电有限公司 一种amoled显示器件及其子像素结构的制备方法
CN104166260B (zh) 2014-08-04 2016-09-07 京东方科技集团股份有限公司 显示基板及其驱动方法和显示装置
CN104269411B (zh) 2014-09-11 2018-07-27 京东方科技集团股份有限公司 显示面板、有机发光二极管显示器和显示装置
US11711958B2 (en) 2014-09-11 2023-07-25 Boe Technology Group Co., Ltd. Display panel and display device
US11004905B2 (en) 2014-09-11 2021-05-11 Boe Technology Group Co., Ltd. Display panel and display device
CN104282727B (zh) 2014-09-30 2017-08-29 京东方科技集团股份有限公司 一种像素结构及其显示方法、显示装置
JP2016075868A (ja) 2014-10-09 2016-05-12 Ｎｌｔテクノロジー株式会社 画素アレイ及び電気光学装置並びに電気機器並びに画素レンダリング方法
CN105552099A (zh) 2014-10-29 2016-05-04 上海和辉光电有限公司 一种oled像素排列结构
CN104332486A (zh) 2014-10-29 2015-02-04 上海和辉光电有限公司 Oled像素排列结构
KR102296918B1 (ko) 2014-11-03 2021-09-02 삼성디스플레이 주식회사 표시 장치, 이의 표시 제어 방법 및 장치
JP6474232B2 (ja) 2014-11-05 2019-02-27 株式会社ジャパンディスプレイ 表示装置
JP6521610B2 (ja) 2014-11-10 2019-05-29 株式会社ジャパンディスプレイ 画像表示装置
CN104362170B (zh) 2014-11-28 2017-04-12 京东方科技集团股份有限公司 一种有机电致发光显示器件、其驱动方法及相关装置
CA2872563A1 (en) 2014-11-28 2016-05-28 Ignis Innovation Inc. High pixel density array architecture
KR102232694B1 (ko) * 2014-12-03 2021-03-29 삼성디스플레이 주식회사 유기 발광 표시 패널 및 그 제조 방법
KR20160072370A (ko) 2014-12-12 2016-06-23 삼성디스플레이 주식회사 표시 장치
CN104576695B (zh) 2014-12-22 2017-08-25 信利（惠州）智能显示有限公司 Oled像素排列结构及显示装置
CN104465714B (zh) 2014-12-30 2017-04-26 京东方科技集团股份有限公司 一种像素结构及其显示方法、显示装置
KR102458687B1 (ko) 2014-12-31 2022-10-26 삼성디스플레이 주식회사 유기 발광 표시 장치의 제조 방법
CN104537974B (zh) 2015-01-04 2017-04-05 京东方科技集团股份有限公司 数据获取子模块及方法、数据处理单元、***和显示装置
JP6654280B2 (ja) 2015-01-14 2020-02-26 天馬微電子有限公司 画素アレイ及び電気光学装置並びに電気機器並びに画素アレイの駆動方法
CN104536632B (zh) 2015-01-26 2017-07-21 京东方科技集团股份有限公司 一种内嵌式触摸屏及显示装置
CN104637987A (zh) 2015-02-06 2015-05-20 友达光电股份有限公司 一种主动矩阵有机发光显示器及其像素结构
CN104597655B (zh) 2015-02-13 2017-06-27 京东方科技集团股份有限公司 一种像素排列结构、显示面板及显示装置
KR20160104804A (ko) 2015-02-26 2016-09-06 삼성디스플레이 주식회사 유기 발광 표시 장치
TWI555195B (zh) 2015-03-27 2016-10-21 友達光電股份有限公司 顯示器的畫素排列結構
KR20160129185A (ko) 2015-04-29 2016-11-09 삼성디스플레이 주식회사 유기 발광 표시 장치
CN104835468B (zh) 2015-05-21 2018-02-13 深圳市华星光电技术有限公司 液晶面板及其驱动方法
CN104835444B (zh) 2015-06-05 2017-07-14 京东方科技集团股份有限公司 一种显示方法及显示装置
CN106486514B (zh) 2015-08-31 2023-12-01 昆山国显光电有限公司 像素结构以及oled显示面板
KR102532899B1 (ko) * 2015-11-04 2023-05-17 삼성디스플레이 주식회사 유기 발광 표시 패널
CN105242436B (zh) 2015-11-06 2018-08-17 上海天马有机发光显示技术有限公司 一种阵列基板、显示面板及显示装置
CN105280139B (zh) 2015-11-11 2018-05-01 深圳市华星光电技术有限公司 Amoled亮度补偿方法及amoled驱动***
KR102430444B1 (ko) 2015-12-18 2022-08-09 삼성디스플레이 주식회사 마스크 조립체, 이를 이용한 표시 장치의 제조 장치 및 표시 장치의 제조 방법
CN205231065U (zh) 2015-12-23 2016-05-11 昆山国显光电有限公司 像素结构及显示器
US9984624B2 (en) 2015-12-28 2018-05-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, driver IC, and electronic device
KR102515628B1 (ko) 2015-12-31 2023-03-29 엘지디스플레이 주식회사 유기 발광 표시 패널
CN106935618B (zh) 2015-12-31 2019-08-27 昆山国显光电有限公司 Oled像素排列方法
CN205608350U (zh) 2015-12-31 2016-09-28 上海中航光电子有限公司 一种显示屏及显示器
KR102447506B1 (ko) 2016-01-05 2022-09-27 삼성디스플레이 주식회사 표시 장치의 표시 제어 방법 및 장치
CN105741774B (zh) 2016-01-28 2018-03-20 京东方科技集团股份有限公司 一种图像处理方法及其装置、显示装置
CN105529008B (zh) 2016-02-01 2018-03-30 深圳市华星光电技术有限公司 液晶显示面板的驱动方法
US11233096B2 (en) 2016-02-18 2022-01-25 Boe Technology Group Co., Ltd. Pixel arrangement structure and driving method thereof, display substrate and display device
CN107644888A (zh) 2016-07-22 2018-01-30 京东方科技集团股份有限公司 像素排列结构、显示基板、显示装置、制作方法及掩膜版
US11264430B2 (en) 2016-02-18 2022-03-01 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel arrangement structure with misaligned repeating units, display substrate, display apparatus and method of fabrication thereof
US10854684B2 (en) 2016-02-18 2020-12-01 Boe Technology Group Co., Ltd. Pixel arrangement structure and driving method thereof, display substrate and display device
CN205355055U (zh) 2016-02-18 2016-06-29 京东方科技集团股份有限公司 一种像素排列结构、显示面板及显示装置
CN110133899A (zh) 2018-02-09 2019-08-16 京东方科技集团股份有限公司 像素排列结构、显示基板、显示装置
CN110137215A (zh) 2018-02-09 2019-08-16 京东方科技集团股份有限公司 像素排列结构、显示基板和显示装置
CN110134353B (zh) 2018-02-09 2021-04-27 京东方科技集团股份有限公司 颜色补偿方法、补偿装置以及显示装置
KR102533412B1 (ko) 2016-03-21 2023-05-17 엘지전자 주식회사 유기 발광 다이오드 표시 장치 및 그의 동작 방법
TWI585968B (zh) 2016-03-22 2017-06-01 群創光電股份有限公司 顯示裝置
CN107275361B (zh) 2016-04-08 2020-10-02 乐金显示有限公司 有机发光显示装置
CN107275359B (zh) 2016-04-08 2021-08-13 乐金显示有限公司 有机发光显示装置
KR101826432B1 (ko) 2016-04-08 2018-02-07 엘지디스플레이 주식회사 유기 발광 표시 장치
KR101698718B1 (ko) 2016-04-29 2017-01-20 엘지디스플레이 주식회사 유기 발광 표시 장치
CN106094334B (zh) 2016-06-21 2020-03-31 北京京东方光电科技有限公司 显示面板及显示装置
CN105911785B (zh) 2016-06-30 2019-08-23 上海中航光电子有限公司 一种显示面板和显示装置
CN205845956U (zh) 2016-07-22 2016-12-28 京东方科技集团股份有限公司 像素排列结构、显示基板、显示装置及掩膜版
CN105976757B (zh) 2016-07-26 2019-01-18 京东方科技集团股份有限公司 像素排列结构、像素电路、显示面板及驱动方法
CN106097962B (zh) * 2016-08-19 2018-09-07 京东方科技集团股份有限公司 显示基板、显示设备及区域补偿方法
CN107817632A (zh) 2016-09-13 2018-03-20 京东方科技集团股份有限公司 一种液晶显示面板及显示装置
JP2018049774A (ja) 2016-09-23 2018-03-29 株式会社ジャパンディスプレイ 表示装置
KR20180038112A (ko) 2016-10-05 2018-04-16 삼성디스플레이 주식회사 헤드 마운티드 디스플레이 장치
CN206163494U (zh) 2016-11-16 2017-05-10 京东方科技集团股份有限公司 像素排列结构、有机电致发光器件、显示装置、掩模板
CN106782371B (zh) 2016-12-20 2018-01-19 惠科股份有限公司 液晶显示器件及其液晶显示面板的驱动方法
CN106601167B (zh) 2016-12-20 2019-10-01 上海天马有机发光显示技术有限公司 一种显示面板的灰阶补偿方法、装置和***
CN106531770A (zh) 2016-12-23 2017-03-22 京东方科技集团股份有限公司 一种有机电致发光显示面板、其制作方法及显示装置
CN106591776B (zh) 2016-12-28 2019-12-03 武汉华星光电技术有限公司 精细掩膜板及其制作方法
KR20180076813A (ko) 2016-12-28 2018-07-06 엘지디스플레이 주식회사 전계 발광 표시 장치
EP3343544B1 (en) 2016-12-28 2022-06-15 Vestel Elektronik Sanayi ve Ticaret A.S. Method for a display device
CN106782307B (zh) 2017-01-25 2019-07-05 上海天马有机发光显示技术有限公司 一种oled显示面板的灰阶补偿方法以及灰阶补偿***
CN106940978B (zh) 2017-05-15 2019-10-25 上海天马有机发光显示技术有限公司 有机发光显示面板及其驱动方法、有机发光显示装置
KR102391918B1 (ko) 2017-05-23 2022-04-29 삼성디스플레이 주식회사 유기발광표시장치
CN106991957B (zh) 2017-06-07 2020-02-21 京东方科技集团股份有限公司 一种像素结构、显示基板、显示装置和显示方法
CN107293571B (zh) 2017-06-09 2019-09-20 深圳市华星光电技术有限公司 Oled显示面板的像素排列结构及oled显示面板
CN110264898B (zh) 2017-06-12 2022-02-15 Oppo广东移动通信有限公司 像素阵列及显示器
CN107248393B (zh) 2017-07-24 2019-04-26 上海交通大学 像素驱动单元及其形成方法、显示背板、像素驱动电路
KR102448031B1 (ko) 2017-07-28 2022-09-28 삼성디스플레이 주식회사 센서 일체형 표시장치
CN107393468B (zh) 2017-08-24 2019-10-22 京东方科技集团股份有限公司 一种显示面板的色偏校正方法及色偏校正装置
WO2019042013A1 (zh) 2017-08-31 2019-03-07 昆山国显光电有限公司 像素结构及显示装置
CN107342037B (zh) 2017-09-01 2020-12-08 京东方科技集团股份有限公司 数据转化方法、装置和计算机可读存储介质
CN107481668B (zh) * 2017-09-01 2020-07-24 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN107731870B (zh) 2017-09-28 2020-12-22 上海天马有机发光显示技术有限公司 有机发光二极管像素结构及包含其的显示面板、显示装置
CN107481671B (zh) 2017-09-29 2019-11-01 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板、显示装置
CN107665684B (zh) 2017-10-13 2020-01-14 深圳吉迪思电子科技有限公司 一种色彩Mura补偿方法
CN107910348B (zh) 2017-10-26 2021-03-16 上海天马有机发光显示技术有限公司 一种显示面板和显示装置
CN110720146A (zh) 2017-11-03 2020-01-21 深圳市柔宇科技有限公司 像素阵列、显示面板及电子装置
US10283086B1 (en) 2017-11-06 2019-05-07 Novatek Microelectronics Corp. Display device with novel sub-pixel configuration
KR20190072108A (ko) 2017-12-15 2019-06-25 조율호 피라미드 서브 픽셀 배열 구조를 갖는 표시 장치
CN107895568A (zh) 2017-12-28 2018-04-10 深圳市华星光电技术有限公司 液晶显示装置
WO2019134521A1 (zh) 2018-01-02 2019-07-11 京东方科技集团股份有限公司 像素排布结构、其制作方法、显示面板、显示装置和掩模板
CN109994505A (zh) 2018-01-02 2019-07-09 京东方科技集团股份有限公司 一种像素排布结构及相关装置
WO2019134522A1 (zh) 2018-01-02 2019-07-11 京东方科技集团股份有限公司 像素排布结构、其制作方法、显示面板、显示装置和掩模板
CN108364983A (zh) 2018-02-01 2018-08-03 武汉华星光电半导体显示技术有限公司 像素排列结构
CN207883217U (zh) 2018-02-09 2018-09-18 京东方科技集团股份有限公司 显示基板和显示装置
CN207781608U (zh) 2018-02-09 2018-08-28 京东方科技集团股份有限公司 显示基板和显示装置
CN207781607U (zh) 2018-02-09 2018-08-28 京东方科技集团股份有限公司 像素排列结构、显示基板和显示装置
CN115542617A (zh) 2018-02-09 2022-12-30 京东方科技集团股份有限公司 显示基板和显示装置
CN108493221B (zh) 2018-04-17 2020-03-31 京东方科技集团股份有限公司 一种像素排列结构、显示面板、掩膜版组件及蒸镀设备
CN108649000B (zh) 2018-05-08 2021-01-26 京东方科技集团股份有限公司 测试基板及其制备方法、检测方法、显示基板、显示装置
JP7117158B2 (ja) 2018-06-01 2022-08-12 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 表示装置及びその制御方法
KR102493488B1 (ko) 2018-06-15 2023-02-01 삼성디스플레이 주식회사 표시 장치
CN108831912B (zh) * 2018-06-15 2020-11-24 京东方科技集团股份有限公司 Oled阵列基板及制造其的方法、oled像素电路以及显示装置
CN109037287A (zh) 2018-07-27 2018-12-18 京东方科技集团股份有限公司 子像素排列结构、掩膜装置、显示面板及显示装置
CN109638035B (zh) 2018-11-13 2021-02-26 武汉华星光电半导体显示技术有限公司 像素排列结构及有机发光二极管显示装置
CN109844624B (zh) * 2018-11-15 2022-02-22 京东方科技集团股份有限公司 包括多个子像素的显示面板、对置基板、阵列基板、操作以及制造显示面板的方法
CN113823240B (zh) 2018-12-13 2023-04-18 京东方科技集团股份有限公司 显示装置
CN109671759A (zh) 2018-12-18 2019-04-23 武汉华星光电半导体显示技术有限公司 Oled像素结构
CN112313802B (zh) 2018-12-28 2024-06-21 京东方科技集团股份有限公司 显示基板、精细金属掩模板组以及制作方法
US11232750B2 (en) 2019-01-29 2022-01-25 Boe Technology Group Co., Ltd. Display substrate, display panel, and manufacturing method and driving method of display substrate
CN109817672B (zh) * 2019-01-29 2020-12-29 京东方科技集团股份有限公司 有机电致发光显示基板及其制造方法、显示面板、装置
US11581385B2 (en) 2019-03-28 2023-02-14 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate having additional pad layer
CN110010021A (zh) 2019-04-26 2019-07-12 京东方科技集团股份有限公司 无机发光二极管显示基板、显示装置及驱动方法
KR102656408B1 (ko) 2019-05-13 2024-04-15 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
KR20210012089A (ko) 2019-07-23 2021-02-03 삼성디스플레이 주식회사 표시 장치의 오버드라이빙 데이터 획득 방법, 표시 장치의 구동 방법, 및 표시 장치
CN112309329B (zh) 2019-08-02 2024-03-01 天马日本株式会社 显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070290973A1 (en) * 2006-06-14 2007-12-20 Au Optronics Corporation Structure of pixel circuit for display and driving method thereof
CN106293244A (zh) * 2016-08-30 2017-01-04 京东方科技集团股份有限公司 触控显示面板及其驱动方法以及触控显示装置
CN107256695A (zh) * 2017-07-31 2017-10-17 上海天马有机发光显示技术有限公司 像素电路、其驱动方法、显示面板及显示装置
CN109559679A (zh) * 2017-09-26 2019-04-02 京东方科技集团股份有限公司 触控显示面板及其驱动方法、像素电路、电子装置
CN109491158A (zh) * 2018-11-16 2019-03-19 昆山龙腾光电有限公司 一种显示面板及显示装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240046880A1 (en) * 2021-04-01 2024-02-08 Boe Technology Group Co., Ltd. Pixel drive circuit and driving method thereof, and display panel
EP4207301A4 (en) * 2021-06-10 2023-12-27 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE AND DISPLAY DEVICE
CN113506539A (zh) * 2021-07-19 2021-10-15 Oppo广东移动通信有限公司 显示模组和显示设备
CN113920934A (zh) * 2021-09-30 2022-01-11 成都京东方光电科技有限公司 显示基板和显示装置
WO2023051109A1 (zh) * 2021-09-30 2023-04-06 京东方科技集团股份有限公司 显示基板、显示面板和显示装置
GB2619676A (en) * 2021-09-30 2023-12-13 Boe Technology Group Co Ltd Display substrate, display panel, and display apparatus

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