WO2019184355A1 - 显示驱动电路及其控制方法、显示装置 - Google Patents

显示驱动电路及其控制方法、显示装置 Download PDF

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Publication number
WO2019184355A1
WO2019184355A1 PCT/CN2018/114004 CN2018114004W WO2019184355A1 WO 2019184355 A1 WO2019184355 A1 WO 2019184355A1 CN 2018114004 W CN2018114004 W CN 2018114004W WO 2019184355 A1 WO2019184355 A1 WO 2019184355A1
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Prior art keywords
signal
sub
circuit
control
display data
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PCT/CN2018/114004
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English (en)
French (fr)
Inventor
田振国
胡双
熊丽军
陈帅
唐滔良
董兴
梁雪波
张智
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US16/610,999 priority Critical patent/US10930191B2/en
Publication of WO2019184355A1 publication Critical patent/WO2019184355A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display driving circuit, a control method thereof, and a display device.
  • a display device such as a TFT-LCD (Thin Film Transistor Liquid Crystal Display) provides a clock signal (CLK) to the gate driving circuit during display.
  • CLK clock signal
  • the gate drive circuit is enabled to gate the gate lines row by row.
  • Some embodiments of the present disclosure provide a display driving circuit including a control sub-circuit and a gate driving sub-circuit connected to the control sub-circuit.
  • the control subcircuit is configured to receive an active display data strobe signal and provide a plurality of valid clock signals to the gate drive subcircuit in accordance with the valid display data strobe signal.
  • the control sub-circuit is further configured to: when the effective display data strobe signal is lost, generate a first signal adjustment instruction, and control each stage shift in the gate driving sub-circuit according to the first signal adjustment instruction The output of the bit register outputs a non-strobe signal.
  • the control subcircuit includes a timing controller and a level shifter coupled to the timing controller.
  • the timing controller includes a signal generating component configured to receive the valid display data strobe signal and output a plurality of initial clock signals to the level shifter according to the valid display data strobe signal .
  • the level shifter is configured to convert the plurality of initial clock signals into the plurality of active clock signals, each of the plurality of initial clock signals having a magnitude that is less than a magnitude of the converted active clock signal.
  • control subcircuit further includes a signal determination component and an instruction generation component coupled to the signal determination component.
  • the signal determining component is configured to determine whether it is low.
  • the command generating component is configured to receive a determination result of the signal determining component, and generate the first signal adjustment command when the signal determining component determines that the valid display data strobe signal is lost.
  • the instruction generating component is further configured to generate a second signal adjustment instruction when the signal determining component determines that the valid display data strobe signal is not lost.
  • control subcircuit further includes a triggering element coupled to the command generating component.
  • the trigger element is also coupled to a total reset terminal to which each stage shift register of the gate drive sub-circuit is connected.
  • the triggering component is configured to provide a first enable signal to a total reset terminal to which each stage shift register of the gate drive sub-circuit is connected according to the first signal adjustment instruction.
  • control subcircuit further includes a trigger component coupled to the command generating component; the trigger component is coupled to a level shifter, the trigger component configured to adjust according to the first signal An instruction to control the level shifter to stop performing a charge sharing operation.
  • control sub-circuit further includes a trigger element coupled to the instruction generating component; the trigger component configured to control the level shifter to perform a charge sharing operation in accordance with a second signal conditioning instruction.
  • the signal determination component, the instruction generation component, and the trigger component are integrated in the timing controller.
  • a method for controlling any of the display driving circuits as described above comprising: controlling a sub-circuit to receive an effective display data strobe signal, and according to the effective display
  • the data strobe signal provides a plurality of valid clock signals to the gate driving sub-circuit; and the control sub-circuit determines that the valid display data strobe signal is lost, generates a first signal adjustment instruction, and adjusts the instruction according to the first signal
  • the output of each stage shift register in the gate drive sub-circuit is controlled to output a non-strobe signal.
  • control subcircuit includes a timing controller, a level shifter, a signal determining component, an instruction generating component, and a triggering component.
  • control sub-circuit determines that the valid display data strobe signal is lost, generates a first signal adjustment instruction, and controls each of the gate drive sub-circuits according to the first signal adjustment instruction.
  • the output of the stage shift register outputs a non-strobe signal including:
  • the signal determining component determines whether the valid display data strobe signal is continuously low for at least one period. If the signal determining component determines that the valid display data strobe signal is continuously low for at least one period, the level shifter maintains a charge sharing operation, and outputs a plurality of initial clock signals output by the timing controller Each of the conversions is an intermediate voltage that is greater than the valley voltage of the active clock signal and less than the peak voltage of the active clock signal.
  • the instruction generating component generates the first signal adjustment instruction, and the triggering component provides a first resetting end connected to each of the gate drive sub-circuits according to the first signal adjustment instruction An enable signal. Under the control of the first enable signal from the total reset terminal, the voltage at the output of the shift register is pulled down to the first voltage terminal for outputting a low level.
  • the shift register includes a first reset transistor.
  • the gate of the first reset transistor is connected to the total reset terminal, the first pole is connected to the output end of the shift register, and the second pole is connected to the first voltage terminal.
  • the voltage at the output of the shift register is pulled down to the first voltage terminal for outputting a low level, including:
  • the first reset transistor is turned on under the control of the first enable signal of the total reset terminal, and the output terminal of the shift register is electrically connected to the first voltage terminal.
  • the shift register further includes a second reset transistor.
  • the gate of the second reset transistor is connected to the total reset terminal, the first pole is connected to the pull-up node in the shift register, and the second pole is connected to the first voltage terminal.
  • the method further includes: under the control of the first enable signal from the total reset terminal, the second reset transistor is turned on, and the pull-up node is electrically connected to the first voltage terminal.
  • control subcircuit includes a timing controller, a level shifter, a signal determining component, an instruction generating component, and a triggering component.
  • control sub-circuit determines that the valid display data strobe signal is lost, generates a first signal adjustment instruction, and controls each of the gate drive sub-circuits according to the first signal adjustment instruction.
  • the output of the stage shift register outputs a non-strobe signal, including:
  • the signal determining component determines whether the valid display data strobe signal is continuously low for at least one period. And if the signal determining component determines that the valid display data strobe signal is continuously low for at least one period, the instruction generating component generates the first signal adjustment instruction.
  • the triggering component controls the level shifter to stop performing a charge sharing operation according to the first signal adjustment instruction.
  • Each of the plurality of valid clock signals provided by the level shifter to the gate drive sub-circuit is continuously the non-strobe signal for at least one period.
  • the method further includes: if the signal determining component determines that the valid display data strobe signal is not continuously low for at least one period, the instruction generating component generates a second signal adjustment instruction, where The triggering component controls the level shifter to perform a charge sharing operation according to the second signal adjustment instruction.
  • the controlling the level shifter to stop performing a charge sharing operation comprises: the charge sharing control terminal of the level shifter receiving a second enable signal, in a second from the charge sharing control terminal Under the control of the enable signal, the level shifter stops performing the charge sharing operation.
  • the method further comprises: controlling the sub-circuit to drive to the gate The input of the first stage shift register in the sub-circuit outputs a start signal.
  • the display driver circuit further includes a source driver sub-circuit coupled to the timing controller.
  • the method further includes: the timing controller outputting a data voltage for displaying a black image to the source driving sub-circuit.
  • Some embodiments of the present disclosure provide a computer device including a memory, a processor, a computer program stored on the processor, and a processor executing the computer program to implement any one of the methods described above.
  • Some embodiments of the present disclosure provide a display device including any of the display driving circuits described above.
  • FIG. 2a is a schematic structural diagram of a display driving circuit according to some embodiments of the present disclosure.
  • 2b is a schematic structural diagram of another display driving circuit according to some embodiments of the present disclosure.
  • FIG. 2c is a schematic structural view of the control subcircuit of FIG. 2b;
  • 2d is a schematic structural diagram of another display driving circuit according to some embodiments of the present disclosure.
  • FIG. 3 is a flowchart of a control method of a display driving circuit according to some embodiments of the present disclosure
  • FIG. 5 is a flowchart of an implementation process of S102 in FIG. 3;
  • FIG. 6 is a schematic structural diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 7 is a flow chart of another implementation process of S102 in FIG. 3;
  • FIG. 8 is another timing diagram of each signal involved in S102 of FIG.
  • TCON generates CLK based on the received front end signal.
  • the level shifter connected to TCON controls CLK to transition to an intermediate level such that a row of gate lines receiving the CLK is gated.
  • the source drive circuit no longer supplies the data signal to the data line.
  • a row of sub-pixels controlled by the gated gate lines is rapidly discharged through the data lines connected thereto, thereby causing a difference in charges in the sub-pixels of the row and charges in a few rows of sub-pixels in the vicinity. This causes display defects such as display flash lines.
  • Some embodiments of the present disclosure provide a display driving circuit including a control sub-circuit 10 and a gate driving sub-circuit 20 connected to the control sub-circuit 10, as shown in FIG. 2a.
  • the control sub-circuit 10 is configured to receive a valid display data strobe signal (Data Enable, DE) and provide a plurality of valid clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ...) to the gate drive sub-circuit 20 in accordance with DE.
  • a valid display data strobe signal Data Enable, DE
  • GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4 a plurality of valid clock signals
  • FIG. 2a four effective clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4) are illustrated, but the disclosure is not limited thereto, and "multiple" in the present disclosure means two or more.
  • the control sub-circuit 10 is further configured to generate a first signal adjustment command when the DE is lost, and control the output OUT output of each stage shift register (RS) in the gate drive sub-circuit 20 according to the first signal adjustment command.
  • Non-strobe signal In this case, a gate line (Gate) connected to the output terminal of the RS receives the non-strobe signal, thereby being in a state of not being gated.
  • control sub-circuit 10 determines that the DE is lost, and the control sub-circuit 10 determines that the DE is continuously low for a predetermined period of time, indicating that the DE is lost.
  • the preset time mentioned above may be set as needed, for example, the preset time may be at least one period of DE.
  • the non-gating signal refers to a signal that causes the gate line receiving the non-strobe signal to be in an un-strobed state.
  • the gate line that is not gated cannot turn on the TFT electrically connected to the gate line.
  • the TFT connected to the gate line in each sub-pixel of the display device is N-type, and when the gate of the TFT receives a low level through the gate line connected thereto, the TFT is turned off, thereby making The gate line connected to the TFT is in a state of not being gated.
  • the TFT connected to the gate line in each sub-pixel of the display device is P-type, and when the gate of the TFT receives a high level through the gate line connected thereto, the TFT is turned off, thereby The gate line connected to the TFT is placed in a state of not being gated.
  • the following embodiments are described by taking an example in which the TFT connected to the gate line in each sub-pixel of the display device is an N-type.
  • the non-strobe signal is a low level VGL. .
  • the valleys of the above-described effective clock signals are at a low level VGL, and the peak is at a high level VGH.
  • the high level and the low level are relative concepts.
  • the low level voltage is negative and the high level voltage is positive.
  • the low level VGL can be -5V, and the high level VGH is 5V. .
  • the low and high voltages are both positive, for example, the low level VGL is 5V and the high level VGH is 10V.
  • the effective clock signal (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ...) voltage varies between -8V and 32V.
  • control sub-circuit 10 includes a timing controller (TCON) and a level shifter (LS) coupled to the TCON.
  • TCON timing controller
  • LS level shifter
  • the TCON is configured to receive the DE and output a plurality of initial clock signals (CLK1, CLK2, CLK3, CLK4, ...) to the LS according to the DE.
  • each of the plurality of initial clock signals (CLK1, CLK2, CLK3, CLK4, ...) varies from 0 to 2.5V.
  • the LS is configured to boost the voltage amplitude of each of the plurality of initial clock signals (CLK1, CLK2, CLK3, CLK4, ...) to be converted into a plurality of valid clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ...) . That is, the plurality of valid clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ...) are in one-to-one correspondence with the plurality of initial clock signals (CLK1, CLK2, CLK3, CLK4, ). The amplitude of each active clock signal is greater than the amplitude of the corresponding initial clock signal.
  • the LS performs a charge share operation to convert each of the plurality of initial clock signals (CLK1, CLK2, CLK3, CLK4, ...) to an intermediate voltage Vm. Then, the Vm corresponding to each initial clock signal is converted into an effective clock signal by, for example, a boosting element, to obtain the above-mentioned plurality of valid clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ).
  • the voltage value of the intermediate voltage Vm is greater than the valley voltage VGL of the effective clock signal, and is smaller than the peak voltage VGH of the effective clock signal.
  • the intermediate voltage Vm may be about 15V.
  • LS In the process of normal display (ie, when DE is not lost), LS needs to convert multiple initial clock signals (CLK1, CLK2, CLK3, CLK4, ...) with smaller amplitude into multiple effective clock signals with larger amplitude. (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4). If each initial clock signal is directly converted into a valid clock signal, since the voltage amplitude difference between the two is large, a large power consumption is required during the conversion process, so the LS can perform the above-described charge sharing operation, The peak voltage and valley voltage of each initial clock signal are first converted to an intermediate voltage Vm.
  • each of the clock signals (LS_CLK1, LS_CLK2, LS_CLK3, LS_CLK4, ...) after the LS conversion, that is, each of the plurality of valid clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ...) is In the process of changing the peak to the valley, the intermediate voltage Vm is first converted to the above, and then converted to the valley voltage VGL.
  • Each of the plurality of clock signals (LS_CLK1, LS_CLK2, LS_CLK3, LS_CLK4, ...) after the LS conversion, that is, each of the plurality of valid clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ...) is in the valley direction
  • the intermediate voltage Vm is first converted and then converted to the peak voltage VGH. Thereby, the variation of the voltage is reduced, which is beneficial to reducing the power consumption during the voltage change.
  • the LS still performs the charge sharing operation described above.
  • the control sub-circuit 10 can determine whether the DE is lost, for example, whether DE is continuously low for at least one period, and when the control sub-circuit 10 determines that DE is continuously low for at least one period, the DE is indicated. When the signal is discontinuous, the DE signal is lost. In this case, the control sub-circuit 10 generates a first signal adjustment command, and controls the output terminal OUT of each stage RS in the gate drive sub-circuit 20 to output a non-strobe signal according to the first signal adjustment command, for example, low. Level VGL.
  • the row gate line does not turn on the TFT connected to the gate line, and at this time, is controlled by the gate line.
  • the charge on the pixel electrode of one row of sub-pixels is not discharged through the data line (Data), while the picture of the previous frame is held for display.
  • the sub-pixels of the row have a charge corresponding to the charge of the sub-pixels of the adjacent upper and lower rows, so that the display can be displayed due to a large difference in the charge of the adjacent sub-pixels.
  • a problem such as a flash line or the like is displayed.
  • control sub-circuit 10 The specific structure of the control sub-circuit 10 will be described in detail below.
  • control sub-circuit 10 further includes a signal determining component 101 and an instruction generating component 102.
  • the signal judging element 101 is configured to judge whether DE is lost, for example, to determine whether DE is continuously low for at least one period.
  • the signal decision component 101 is a decoder in the TCON for decoding the DE, and the decoder can determine whether the DE signal is lost during the decoding process.
  • the signal judging element 101 is integrated in the TCON.
  • the command generating element 102 is configured to receive the determination result of the signal judging element 101, and to generate the first signal adjustment command described above when the signal judging element 101 judges that the DE is continuously low for at least one period.
  • the instruction generation component 102 is further configured to generate a second signal adjustment instruction when the signal determination component 101 determines that DE has not been continuously low for at least one period.
  • control subcircuit 10 further includes a triggering element 103 coupled to the command generating component 102.
  • the triggering element 103 is also coupled to the total reset terminal TRST to which each stage RS of the gate drive sub-circuit 20 is connected.
  • the triggering component 103 is configured to provide a first enable signal to the total reset terminal TRST connected to each stage RS of the gate driving sub-circuit 20 according to the first signal adjustment instruction, thereby further controlling the output end of each stage RS.
  • the OUT output is the low level of the above non-strobe signal.
  • the triggering element 103 is coupled to the charge sharing control terminal VGP of the LS.
  • the triggering element 103 is configured to control the LS to stop performing a charge sharing operation in accordance with the first signal conditioning instruction.
  • the triggering component 103 provides a second enable signal, such as a high level VGH, to the charge sharing control terminal VGP of the LS according to the first signal adjustment instruction generated by the instruction generation component 102, such that the LS stops performing the charge sharing operation. .
  • the triggering component 102 when the DE signal returns to normal, is configured to control the LS to perform a charge sharing operation in accordance with the second signal conditioning instruction generated by the instruction generation component 102 to reduce the initial clock signal (CLK1, CLK2, CLK3, CLK4%) Power consumption when converted to multiple active clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ).
  • the above-described instruction generation component 102 and trigger component 102 are also integrated in the TCON.
  • the display driving circuit 01 includes a control sub-circuit 10 and a gate driving connected to the control sub-circuit 10.
  • Subcircuit 20 is a control sub-circuit 10 and a gate driving connected to the control sub-circuit 10.
  • control method includes:
  • the control sub-circuit 10 receives the valid display data strobe signal (Data Enable, DE), and provides a plurality of valid clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ...) to the gate driving sub-circuit 20 according to the DE.
  • Data Enable DE
  • GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4 valid clock signals
  • control sub-circuit 10 includes a TCON and an LS coupled to the TCON.
  • the above S101 includes:
  • TCON receives DE and outputs a plurality of initial clock signals (CLK1, CLK2, CLK3, CLK4, ...) to LS according to DE.
  • the LS performs a charge sharing operation, converts each of the plurality of initial clock signals (CLK1, CLK2, CLK3, CLK4, ...) into an intermediate voltage Vm, and then corresponds each initial clock signal by, for example, a boosting element.
  • the Vm is converted into a valid clock signal, and a plurality of valid clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ...) are obtained, and each of the plurality of initial clock signals (CLK1, CLK2, CLK3, CLK4, ...) is realized.
  • the voltage amplitude is increased to convert to multiple valid clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ). In this case, the amplitude of each valid clock signal is greater than the amplitude of the corresponding initial clock signal.
  • the control sub-circuit 10 determines that the DE is lost, generates a first signal adjustment command, and controls the output end OUT of each stage shift register (RS) in the gate drive sub-circuit 20 according to the first signal adjustment command. Gating signal.
  • the gate line (Gate) connected to the RS described above receives the non-strobe signal, thereby being in a state of not being gated.
  • the control sub-circuit 10 judges that the DE is lost, and generates a first signal adjustment command. For example, the control sub-circuit 10 determines that the DE is continuously low for at least one period, and generates a first signal adjustment command.
  • the control subcircuit 10 includes a signal determination component 101, an instruction generation component 102, and a trigger component 103.
  • the signal judging element 101 can decode the DE input to the TCON.
  • the command generating component 102 is connected to the signal determining component 101, and the command generating component 102 generates a first signal adjusting command based on the determination result of the signal determining component 101.
  • the triggering component 103 connected to the command generating component 102 receives the first signal adjusting command, and controls the output terminal OUT of each stage RS in the gate driving sub-circuit 20 to output a non-strobe signal according to the first signal adjusting command.
  • control method of the display driving circuit provided by some embodiments of the present disclosure has the same technical effects as the structure of the display driving circuit provided by the foregoing embodiments, and details are not described herein again.
  • control sub-circuit 10 includes TCON, LS, the signal judging element 101, the command generating element and 102, and the trigger element 103, the implementation process of the above S102 will be described in detail.
  • the foregoing S102 may include:
  • the signal determining component 101 determines whether the DE is continuously low for at least one period.
  • the LS maintains a charge share operation, and outputs a plurality of initial clock signals (CLK1, CLK2) of TCON.
  • CLK3, CLK4, ...) is converted to an intermediate voltage Vm. That is, in the DE loss phase, the LS converts each of the plurality of initial clock signals (CLK1, CLK2, CLK3, CLK4, ...) into the intermediate voltage Vm, and outputs it to the gate driving sub-circuit 20.
  • the intermediate voltage is greater than the valley voltage of the active clock signal and less than the peak voltage of the active clock signal.
  • the command generating component 102 generates a first signal adjustment command.
  • the trigger component 103 provides the total reset terminal TRST connected to each stage RS of the gate driving sub-circuit 20 according to the first signal adjustment command.
  • the first enable signal is provided.
  • the triggering element 103 is caused to control the output terminal OUT of each stage RS in the gate driving sub-circuit 20 to output a non-strobe signal according to the first signal adjustment command.
  • the first enable signal is used to enable the TFT connected to the total reset terminal TRST in the RS.
  • the first enable signal is at a high level VGH; when the TFT is of a P type, the first enable signal is at a low level VGL.
  • the embodiment of the present disclosure is described by taking an example in which the TFTs in the RS are all N-type.
  • the non-strobe signal is a low level output by the first voltage terminal V1.
  • the DE is continuously low for at least one period, that is, after the DE is lost, the first enable signal can be outputted by the trigger element 103 in the TCON to control the total reset terminal TRST, thereby further controlling each level of RS.
  • the output terminal OUT outputs a low level as the above non-strobe signal.
  • the RS includes a first reset transistor Mtr1.
  • the gate of the first reset transistor Mtr1 is connected to the total reset terminal TRST, the first pole is connected to the output terminal OUT of the RS, and the second pole is connected to the first voltage terminal V1.
  • the above S203 includes:
  • the first reset transistor Mtr1 Under the control of the first enable signal from the total reset terminal TRST, the first reset transistor Mtr1 is turned on, and the output terminal OUT of the RS is electrically connected to the first voltage terminal V1.
  • the signal of the output terminal OUT of the RS is pulled down to the first voltage terminal V1 by the turned-on first reset transistor Mtr1.
  • the first voltage terminal V1 can output a low level VGL.
  • the signal received by the gate line connected to the output terminal OUT of the RS is a non-strobe signal.
  • the TFT in a row of sub-pixels controlled by the gate line cannot be turned on, so the row of sub-pixels The charge on the middle pixel electrode is not quickly released, so that the row of sub-pixels maintains the picture of the previous frame.
  • each stage RS Since all RSs are provided with the above-mentioned total reset terminal TRST, the output terminal OUT of each stage RS outputs the above non-strobe signal, so that all the gate lines are in an un-strobed state, in which case, all The sub-pixels maintain the display data of the previous frame for display. Thereby solving the problem that a part of the sub-pixel discharge causes a flash line on the display screen.
  • the shift register further includes a second reset transistor Mtr2.
  • the gate of the second reset transistor Mtr2 is connected to the total reset terminal TRST, the first pole is connected to the pull-up node PU in the RS, and the second pole is connected to the first voltage terminal V1.
  • the method further includes: under the control of the first enable signal from the total reset terminal TRST, the second reset transistor Mtr2 is turned on, and the pull-up node PU is electrically connected to the first voltage terminal V1.
  • the potential of the pull-up node PU is pulled down to the low level VGL outputted by the first voltage terminal V1 through the turned-on second reset transistor Mtr2.
  • the driving transistor Md is in an off state, and thus, even if the LS performs a charge sharing operation, the intermediate voltage Vm output from the clock signal terminal GS_CLK cannot be transmitted to the output terminal OUT of the RS through the driving transistor Md, and the clock signal can be avoided.
  • the intermediate voltage Vm outputted by the terminal GS_CLK affects the output signal of the output terminal OUT of the RS, thereby preventing the gate line connected to the output terminal OUT of the RS from being gated.
  • the first reset source of the first reset transistor Mtr1 and the second reset transistor Mtr2, and the second pole may be a drain. In other embodiments, the first reset drain of the first reset transistor Mtr1 and the second reset transistor Mtr2, and the second pole may be a source.
  • the implementation process of the above S102 includes:
  • the signal determining component 101 determines whether the DE is continuously low for at least one period.
  • the command generating component 102 If the signal determining component 101 determines that DE is continuously low level VGL for at least one period, the command generating component 102 generates a first signal adjusting command, and the triggering component 103 controls the LS to stop performing the charge sharing operation according to the first signal adjusting command. .
  • Each of the plurality of valid clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ...) supplied by the LS to the gate driving sub-circuit 20 is continuously a non-strobe signal for at least one period.
  • the non-strobe signal is, for example, a low level VGL.
  • the S301 includes: when the DE is continuously low level VGL in at least one period, as shown in FIG. 2c, the triggering component 103 generates a first signal adjustment instruction according to the instruction generating component 102, to the LS.
  • the charge sharing control terminal VGP provides a second enable signal.
  • the charge sharing control terminal VGP of the LS receives the second enable signal, and the LS stops performing the charge sharing operation under the control of the second enable signal from the charge share control terminal VGP.
  • the triggering element 103 reaches the purpose of controlling the output terminal OUT of each stage RS in the gate driving sub-circuit 20 to output a non-strobe signal according to the first signal adjustment instruction.
  • the second enable signal received by the charge sharing control terminal VGP of the LS may be a high level VGH.
  • each of the plurality of valid clock signals (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, ...) will follow (Follow) the change of DE, and then transition to a low level.
  • the low level is supplied as a non-strobe signal to a gate line connected to the output terminal OUT of the RS, and at this time, the TFT in one row of sub-pixels controlled by the gate line cannot be turned on. Therefore, the charge on the pixel electrode in the row of sub-pixels is not quickly released, so that the row of sub-pixels maintains the picture of the previous frame.
  • the initial clock signals (CLK1, CLK2, CLK3, CLK4, ...) are directly converted to (GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, %) without going through the intermediate voltage Vm. This solution can be adopted without considering the influence of power consumption.
  • the control sub-circuit 10 controls the LS to perform the above-described charge sharing operation to lower the initial clock signal ( CLK1, CLK2, CLK3, CLK4, 7)
  • the power consumption during conversion to the active clock signals GS_CLK1, GS_CLK2, GS_CLK3, GS_CLK4, .
  • the method further includes:
  • the signal judging component 101 judges whether DE is continuously low for at least one period, and if the signal judging component 101 judges that DE is not continuously low for at least one period, the command generating component 102 generates a second signal adjustment command.
  • the triggering component 103 controls the LS to perform the above-described charge sharing operation according to the second signal adjustment command.
  • the display drive circuit described above further includes a source drive sub-circuit 30 coupled to the TCON. Based on this, when DE is continuously low level VGL for at least one period, TCON enters a Mute mode, so that the TCON can output a data voltage Vdata for displaying a black image to the source driving sub-circuit 30. In this way, the power consumption of the source driver sub-circuit 30 can be reduced.
  • the source drive sub-circuit 30 When DE returns to normal, TCON switches from the Mute mode back to the normal mode, and the source drive sub-circuit 30 outputs the data voltage Vdata for normal display.
  • the above method further includes:
  • the control sub-circuit 10 outputs a start signal STV to the input terminal Input of the first stage RS in the gate drive sub-circuit 20.
  • a plurality of cascaded RSs in the gate drive sub-circuit 20 can perform a shift register function from the first stage RS. In this way, the gate lines in the display panel are scanned line by line from the beginning to display a new one frame.
  • Some embodiments of the present disclosure provide a computer device including a memory, a processor.
  • the memory stores a computer program executable on the processor, and the processor implements any one of the methods described above when executing the computer program.
  • the computer device has the same technical effects as the control method provided by the foregoing embodiment, and details are not described herein again.
  • the above memory includes various media that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.
  • Some embodiments of the present disclosure provide a computer readable medium storing a computer program that, when executed by a processor, implements any of the methods described above.
  • the computer readable medium has the same technical effects as the control method provided by the foregoing embodiment, and details are not described herein again.
  • Some embodiments of the present disclosure provide a display device including any of the display driving circuits described above.
  • the display device has the same technical effects as the display driving circuit provided in the foregoing embodiment, and details are not described herein again.
  • the display device includes a display panel.
  • the display driving circuit described above is directly fabricated on a non-display area of the display panel by a patterning process (eg, a Mask process).
  • the display driving circuit described above is integrated on a chip, and then the chip is bonded to the display panel.
  • the present disclosure does not limit the manner in which the above display driving circuit is disposed, but is within the protection scope of the present disclosure.
  • the display device may be a liquid crystal display device or an organic light emitting diode display device.
  • the display device can be used to form any product or component having a display function, such as a display, a television, a digital photo frame, a mobile phone, or a tablet.

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Abstract

显示驱动电路（01）包括控制子电路（10）以及栅极驱动子电路（20），控制子电路（10）配置为接收有效显示数据选通信号（DE），并根据有效显示数据选通信号（DE）向栅极驱动子电路（20）提供多个有效时钟信号（GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……），控制子电路（10）还配置为判断有效显示数据选通信号（DE）丢失时，生成第一信号调整指令，并根据第一信号调整指令控制栅极驱动子电路（10）中的每一级移位寄存器（RS）的输出端（OUT）输出非选通信号。

Description

显示驱动电路及其控制方法、显示装置
本公开要求于2018年3月26日提交中国专利局、申请号为201810252721.X、申请名称为“一种显示驱动电路及其控制方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示驱动电路及其控制方法、显示装置。
背景技术
显示装置，例如TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示装置)在显示过程中，时序控制器(Timer Control，TCON)会向栅极驱动电路提供时钟信号(CLK)，以使得栅极驱动电路能够逐行对栅线进行选通。
发明内容
本公开的一些实施例提供一种显示驱动电路，所述显示驱动电路包括控制子电路以及与所述控制子电路相连接的栅极驱动子电路。所述控制子电路配置为接收有效显示数据选通信号，并根据所述有效显示数据选通信号向所述栅极驱动子电路提供多个有效时钟信号。所述控制子电路还配置为判断所述有效显示数据选通信号丢失时，生成第一信号调整指令，并根据所述第一信号调整指令控制所述栅极驱动子电路中的每一级移位寄存器的输出端输出非选通信号。
在一些实施例中，所述控制子电路包括时序控制器以及与所述时序控制器相连接的电平转换器。所述时序控制器包括信号生成元件，所述信号生成元件配置为接收所述有效显示数据选通信号，并根据所述有效显示数据选通信号向所述电平转换器输出多个初始时钟信号。所述电平转换器配置为将所述多个初始时钟信号转换为所述多个有效时钟信号，所述多个初始时钟信号中每个的幅值小于转换后的有效时钟信号的幅值。
在一些实施例中，所述控制子电路还包括信号判断元件以及与所述信号判断元件相连接的指令生成元件。所述信号判断元件配置为判断是否低电平。所述指令生成元件配置为接收所述信号判断元件的判断结果，并当 所述信号判断元件判断所述有效显示数据选通信号丢失时，生成所述第一信号调整指令。
在此基础上，在一些实施例中，所述指令生成元件还配置为当所述信号判断元件判断所述有效显示数据选通信号未丢失时，生成第二信号调整指令。
在一些实施例中，所述控制子电路还包括与所述指令生成元件相连接的触发元件。所述触发元件还与所述栅极驱动子电路中的每一级移位寄存器所连接的总复位端相连接。所述触发元件配置为根据所述第一信号调整指令，向所述栅极驱动子电路中的每一级移位寄存器所连接的总复位端提供第一使能信号。
在一些实施例中，所述控制子电路还包括与所述指令生成元件相连接的触发元件；所述触发元件与电平转换器相连接，所述触发元件配置为根据所述第一信号调整指令，控制所述电平转换器停止执行电荷共享操作。
在一些实施例中，所述控制子电路还包括与所述指令生成元件相连接的触发元件；所述触发元件配置为根据第二信号调整指令，控制所述电平转换器执行电荷共享操作。
在一些实施例中，所述信号判断元件、所述指令生成元件以及所述触发元件集成于所述时序控制器中。
本公开实施例的另一方面，提供一种用于控制如上所述的任意一种显示驱动电路的方法，所述方法包括：控制子电路接收有效显示数据选通信号，并根据所述有效显示数据选通信号向栅极驱动子电路提供多个有效时钟信号；所述控制子电路判断所述有效显示数据选通信号丢失时，生成第一信号调整指令，并根据所述第一信号调整指令控制所述栅极驱动子电路中的每一级移位寄存器的输出端输出非选通信号。
在一些实施例中，所述控制子电路包括时序控制器、电平转换器、信号判断元件、指令生成元件和触发元件。
在此基础上，所述控制子电路判断所述有效显示数据选通信号丢失时，生成第一信号调整指令，并根据所述第一信号调整指令控制所述栅极驱动子电路中的每一级移位寄存器的输出端输出非选通信号包括：
所述信号判断元件判断所述有效显示数据选通信号在至少一个周期内是否连续为低电平。若所述信号判断元件判断所述有效显示数据选通信号在至少一个周期内连续为低电平，则，所述电平转换器保持电荷共享操作， 将时序控制器输出的多个初始时钟信号中的每个转换为中间电压，所述中间电压大于有效时钟信号的波谷电压，小于有效时钟信号的波峰电压。所述指令生成元件生成所述第一信号调整指令，所述触发元件根据所述第一信号调整指令向所述栅极驱动子电路中的每一级移位寄存器所连接的总复位端提供第一使能信号。在来自所述总复位端的第一使能信号的控制下，所述移位寄存器的输出端的电压下拉至用于输出低电平的第一电压端。
在一些实施例中，所述移位寄存器包括第一复位晶体管。所述第一复位晶体管的栅极连接到所述总复位端，第一极连接到所述移位寄存器的输出端，第二极与所述第一电压端相连接。
在此基础上，在来自所述总复位端的第一使能信号的控制下，所述移位寄存器的输出端的电压下拉至用于输出低电平的第一电压端，包括：在来自所述总复位端的第一使能信号的控制下，所述第一复位晶体管导通，所述移位寄存器的输出端与所述第一电压端电连接。
在一些实施例中，移位寄存器还包括第二复位晶体管。第二复位晶体管的栅极连接到总复位端，第一极连接到移位寄存器中的上拉节点，第二极与第一电压端相连接。
在此基础上，所述方法还包括：在来自总复位端的第一使能信号的控制下，第二复位晶体管导通，上拉节点与第一电压端电连接。
在一些实施例中，所述控制子电路包括时序控制器、电平转换器、信号判断元件、指令生成元件和触发元件。
在此基础上，所述控制子电路判断所述有效显示数据选通信号丢失时，生成第一信号调整指令，并根据所述第一信号调整指令控制所述栅极驱动子电路中的每一级移位寄存器的输出端输出非选通信号，包括：
所述信号判断元件判断所述有效显示数据选通信号在至少一个周期内是否连续为低电平。若所述信号判断元件判断所述有效显示数据选通信号在至少一个周期内连续为低电平，则，所述指令生成元件生成所述第一信号调整指令。所述触发元件根据所述第一信号调整指令控制所述电平转换器停止执行电荷共享操作。所述电平转换器向栅极驱动子电路提供的所述多个有效时钟信号的每个在至少一个周期内连续为所述非选通信号。
基于此，所述方法还包括：若所述信号判断元件判断所述有效显示数据选通信号未在至少一个周期内连续为低电平，则所述指令生成元件生成第二信号调整指令，所述触发元件根据所述第二信号调整指令控制所述电 平转换器执行电荷共享操作。
在一些实施例中，所述控制所述电平转换器停止执行电荷共享操作包括：所述电平转换器的电荷共享控制端接收第二使能信号，在来自所述电荷共享控制端的第二使能信号的控制下，所述电平转换器停止执行电荷共享操作。
在一些实施例中，在有效显示数据选通信号在至少一个周期内连续为低电平之后，且当有效显示数据选通信号为方波信号时，方法还包括：控制子电路向栅极驱动子电路中第一级移位寄存器的输入端输出起始信号。
在一些实施例中，所述显示驱动电路还包括与所述时序控制器相连接的源极驱动子电路。当所述有效显示数据选通信号在至少一个周期内连续为低电平时，所述方法还包括：所述时序控制器向所述源极驱动子电路输出用于显示黑色图像的数据电压。
本公开的一些实施例提供一种计算机设备，包括存储器、处理器；存储器上存储有可在处理器上运行的计算机程序，处理器执行计算机程序时实现上述的任意一种方法。
本公开的一些实施例提供一种显示装置，包括如上所述的任意一种显示驱动电路。
附图说明
为了更清楚地说明本公开的实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术提供的一种信号时序图；
图2a为本公开一些实施例提供的一种显示驱动电路的结构示意图；
图2b为本公开一些实施例提供的另一种显示驱动电路的结构示意图；
图2c为图2b中控制子电路的一种结构示意图；
图2d为本公开一些实施例提供的另一种显示驱动电路的结构示意图；
图3为本公开一些实施例提供的一种显示驱动电路的控制方法流程图；
图4为图3中S102所涉及到的各个信号的一种时序图；
图5为图3中S102的一种实现过程流程图；
图6为本公开一些实施例提供的移位寄存器的结构示意图；
图7为图3中S102的另一种实现过程流程图；
图8为图3中S102所涉及到的各个信号的另一种时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
TCON根据所接收的前端信号生成CLK。如图1所示，当前端信号出现不连续时，会导致CLK出现信号丢失。在此情况下，与TCON连接的电平转换器会控制CLK转变为中间电平，从而使得接收该CLK的一行栅线被选通。然而，当上述前端信号不连续时，源极驱动电路不再向数据线提供数据信号。这样一来，被选通的栅线所控制的一行亚像素会通过其连接的数据线进行快速放电，从而导致该行亚像素中的电荷与其附近的几行亚像素中的电荷出现差异，进而导致出现显示闪横线等显示不良。
本公开的一些实施例提供一种显示驱动电路，如图2a所示，该显示驱动电路包括控制子电路10以及与控制子电路10相连接的栅极驱动子电路20。
控制子电路10配置为接收有效显示数据选通信号(Data Enable，DE)，并根据DE向栅极驱动子电路20提供多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)。图2a中以四个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4)进行示意，但本公开的并不限于此，本公开中“多个”指两个及以上。
控制子电路10还配置为判断DE丢失时，生成第一信号调整指令，并根据该第一信号调整指令控制栅极驱动子电路20中的每一级移位寄存器(RS)的输出端OUT输出非选通信号。在此情况下，与RS的输出端相连接的栅线(Gate)接收到该非选通信号，从而处于未被选通的状态。
在一些实施例中，控制子电路10判断DE丢失为，控制子电路10判断DE在一预设时间内连续为低电平，即表示该DE丢失。上述的预设时间可以根据需要进行设定，例如，该预设时间可以为DE的至少一个周期。
需要说明的是，本公开的实施例中，非选通信号是指，使得接收到该 非选通信号的栅线处于未被选通状态的信号。未被选通的栅线无法将与该栅线电连接的TFT导通。
在一些实施例中，显示装置的每个亚像素中与栅线相连接的TFT为N型，当该TFT的栅极通过与其相连接的栅线接收到低电平时，该TFT截止，从而使得与该TFT相连接的栅线处于未被选通的状态。在另一些实施例中，显示装置的每个亚像素中与栅线相连接的TFT为P型，当该TFT的栅极通过与其相连接的栅线接收到高电平时，该TFT截止，从而使得与该TFT相连接的栅线处于未被选通的状态。
为了方便说明，以下实施例均是以显示装置的每个亚像素中与栅线相连接的TFT为N型为例进行的说明，在此情况下，上述的非选通信号为低电平VGL。
此外，如图4所示，上述的有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)的波谷为低电平VGL，波峰为高电平VGH。高电平与低电平为相对概念，在一些实施例中，低电平的电压为负，高电平的电压为正，例如，低电平VGL可以为-5V，高电平VGH为5V。在另一些实施例中，低电平和高电平的电压均为正，例如，低电平VGL为5V，高电平VGH为10V。在一些实施例中，有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)电压的变化范围在-8V～32V之间。
在一些实施例中，如图2a所示，该控制子电路10包括时序控制器(TCON)以及与TCON相连接的电平转换器(Level Shifter，LS)。
TCON配置为接收DE，并根据DE向LS输出多个初始时钟信号(CLK1、CLK2、CLK3、CLK4……)。
在一些实施例中，多个初始时钟信号(CLK1、CLK2、CLK3、CLK4……)中每个的变化范围为0～2.5V。
LS配置为将该多个初始时钟信号(CLK1、CLK2、CLK3、CLK4……)中每个的电压幅值进行提升，从而转换为多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)。即，多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)与多个初始时钟信号(CLK1、CLK2、CLK3、CLK4……)一一对应。每个有效时钟信号的幅值大于对应的初始时钟信号的幅值。
在一些实施例中，该LS执行电荷共享(Charge share)操作，将多个初始时钟信号(CLK1、CLK2、CLK3、CLK4……)中的每个转换为中间 电压Vm。然后，再通过例如升压元件将每个初始时钟信号对应的Vm转换为有效时钟信号，得到上述的多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)。
该中间电压Vm的电压值大于有效时钟信号的波谷电压VGL，小于有效时钟信号的波峰电压VGH。例如，当有效时钟信号的电压在-8V～32V的范围内变化时，该中间电压Vm可以为15V左右。
在正常显示的过程(即DE未丢失时)中，LS需要将幅值较小的多个初始时钟信号(CLK1、CLK2、CLK3、CLK4……)转换成幅值较大的多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)。如果将每个初始时钟信号直接转换为有效时钟信号，由于两者之间的电压幅值差距较大，转换过程中需要消耗较大的功耗，因此该LS可以执行上述的电荷共享操作，将每个初始时钟信号的波峰电压和波谷电压先转换至一中间电压Vm。这样一来，经过该LS转换后的时钟信号(LS_CLK1、LS_CLK2、LS_CLK3、LS_CLK4……)的每个，即多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)的每个，在由波峰向波谷变化的过程中，先转变为上述的中间电压Vm，然后再转变为波谷电压VGL。经过该LS转换后的多个时钟信号(LS_CLK1、LS_CLK2、LS_CLK3、LS_CLK4……)的每个，即多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)的每个，在由波谷向波峰变化的过程中，先转变为中间电压Vm，然后再转变为波峰电压VGH。从而使得电压的变化幅度减小，有利于降低电压变化过程中的功耗。当DE丢失后，LS仍然执行上述的电荷共享操作。
由上述可知，控制子电路10可以判断DE是否丢失，例如判断DE在至少一个周期内是否连续为低电平，当控制子电路10判断DE在至少一个周期内连续为低电平时，说明该DE出现了信号不连续的情况，该DE信号丢失。在此情况下，该控制子电路10生成第一信号调整指令，并根据该第一信号调整指令控制栅极驱动子电路20中的每一级RS的输出端OUT输出非选通信号，例如低电平VGL。基于此，由于该低电平VGL使得本应该被选通的栅线未被选通，因此该行栅线不会将与该栅线相连接的TFT导通，此时，被该栅线控制的一行亚像素的像素电极上的电荷不会通过数据线(Data)放电，而保持上一帧的画面进行显示。这样一来，该行亚像素具有的电荷与其相邻的上、下几行的亚像素具有的电荷相当，从而能够 解决由于相邻几行亚像素具有的电荷存在较大差异，而导致出现显示闪横线等显示不良现象的问题。
以下对控制子电路10的具体结构进行详细的说明。
在一些实施例中，如图2b或图2c所示，控制子电路10还包括信号判断元件101、指令生成元件102。
信号判断元件101配置为判断DE是否丢失，例如判断DE在至少一个周期内是否连续为低电平。
在一些实施例中，该信号判断元件101为TCON中用于对DE进行解码的解码器，该解码器在解码的过程中，就可以判断出DE信号是否丢失。在此情况下，信号判断元件101集成于TCON中。
此外，指令生成元件102配置为接收信号判断元件101的判断结果，并当信号判断元件101判断DE在至少一个周期内连续为低电平时，生成上述的第一信号调整指令。
在此基础上，在一些实施例中，指令生成元件102还配置为当该信号判断元件101判断DE未在至少一个周期内连续为低电平时，生成第二信号调整指令。
在一些实施例中，如图2b或图2c所示，控制子电路10还包括与指令生成元件102相连接的触发元件103。
如图2b所示，触发元件103还与栅极驱动子电路20中的每一级RS所连接的总复位端TRST相连接。该触发元件103配置为根据第一信号调整指令，向栅极驱动子电路20中的每一级RS所连接的总复位端TRST提供第一使能信号，从而进一步控制每一级RS的输出端OUT输出作为上述非选通信号的低电平。
在一些实施例中，触发元件103与LS的电荷共享控制端VGP相连接。触发元件103配置为根据第一信号调整指令，控制LS停止执行电荷共享操作。在一些实施例中，触发元件103根据指令生成元件102生成的第一信号调整指令，向LS的电荷共享控制端VGP提供第二使能信号，例如高电平VGH，使得LS停止执行电荷共享操作。
在一些实施例中，当DE信号恢复正常后，触发元件102配置为根据指令生成元件102生成的第二信号调整指令，控制LS执行电荷共享操作，以降低初始时钟信号(CLK1、CLK2、CLK3、CLK4……)转换为多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)时的功 耗。
基于此，为了提高电子器件的集成性能，在一些实施例中，上述的指令生成元件102和触发元件102也集成于TCON中。
本公开的一些实施例提供一种用于控制上述任意一种显示驱动电路的方法，如图2a所示，该显示驱动电路01包括控制子电路10以及与控制子电路10相连接的栅极驱动子电路20。
在此情况下，如图3所示，所述控制方法包括：
S101、控制子电路10接收有效显示数据选通信号(Data Enable，DE)，并根据DE向栅极驱动子电路20提供多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)。
在一些实施例中，如图2a所示，该控制子电路10包括TCON以及与TCON相连接的LS。在此情况下，上述S101包括：
首先，TCON接收DE，并根据DE向LS输出多个初始时钟信号(CLK1、CLK2、CLK3、CLK4……)。
接下来，LS执行电荷共享操作，将该多个初始时钟信号(CLK1、CLK2、CLK3、CLK4……)中的每个转换为中间电压Vm，再通过例如升压元件将每个初始时钟信号对应的Vm转换为有效时钟信号，得到多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)，实现将该多个初始时钟信号(CLK1、CLK2、CLK3、CLK4……)中的每个的电压幅值提升，从而转换为多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)的目的。在此情况下，每个有效时钟信号的幅值大于对应的初始时钟信号的幅值。
S102、控制子电路10判断DE丢失时，生成第一信号调整指令，并根据该第一信号调整指令控制栅极驱动子电路20中的每一级移位寄存器(RS)的输出端OUT输出非选通信号。
在此情况下，与上述RS相连接的栅线(Gate)接收到该非选通信号，从而处于未被选通的状态。
控制子电路10判断DE丢失，生成第一信号调整指令，例如，控制子电路10判断DE在至少一个周期内连续为低电平，生成第一信号调整指令。
在一些实施例中，如图2b或2c所示，控制子电路10包括信号判断元件101、指令生成元件102以及触发元件103。基于此，在该信号判断元件101为TCON中的解码器的情况下，该信号判断元件101可以对输入至 TCON的DE进行解码。信号判断元件101解码的过程中，判断DE信号是否丢失，当DE在至少一个周期内连续为低电平时，该DE信号丢失。指令生成元件102与该信号判断元件101相连接，指令生成元件102根据该信号判断元件101的判断结果生成第一信号调整指令。与指令生成元件102相连接的触发元件103接收该第一信号调整指令，并根据第一信号调整指令控制栅极驱动子电路20中的每一级RS的输出端OUT输出非选通信号。
本公开一些实施例提供的显示驱动电路的控制方法与前述实施例提供的显示驱动电路的结构具有相同的技术效果，此处不再赘述。
以下，在控制子电路10包括TCON、LS、信号判断元件101、指令生成元件和102以及触发元件103的情况下，对上述S102的实现过程进行详细的举例说明。
在一些实施例中，在触发元件103与栅极驱动子电路20中的每一级RS所连接的总复位端TRST相连接的情况下，上述S102，如图5所示，可以包括：
S201、信号判断元件101判断DE在至少一个周期内是否连续为低电平。
S202、如图4所示，若信号判断元件判断DE在至少一个周期内连续为低电平，则，LS保持电荷共享(Charge share)操作，将TCON输出的多个初始时钟信号(CLK1、CLK2、CLK3、CLK4……)中的每个转换为中间电压Vm。即，在DE丢失阶段，LS将多个初始时钟信号(CLK1、CLK2、CLK3、CLK4……)中的每个转换为中间电压Vm，便输出至栅极驱动子电路20。
该中间电压大于有效时钟信号的波谷电压，小于有效时钟信号的波峰电压。
S203、指令生成元件102生成第一信号调整指令，如图2b所示，触发元件103根据该第一信号调整指令向栅极驱动子电路20中的每一级RS所连接的总复位端TRST提供第一使能信号。
基于此，使得触发元件103达到根据第一信号调整指令，控制栅极驱动子电路20中的每一级RS的输出端OUT输出非选通信号的目的。
需要说明的是，该第一使能信号用于开启RS中与该总复位端TRST相连接的TFT。在此情况下，当该TFT为N型时，第一使能信号为高电平 VGH；当该TFT为P型时，第一使能信号为低电平VGL。本公开的实施例是以RS中的TFT均为N型为例进行的说明。
S204、在来自总复位端TRST的第一使能信号的控制下，RS的输出端OUT的电压下拉至用于输出低电平VGL的第一电压端V1。
此时，上述非选通信号为该第一电压端V1输出的低电平。
在此情况下，DE在至少一个周期内连续为低电平，即该DE丢失后，可以通过TCON中的触发元件103控制总复位端TRST输出第一使能信号，从而进一步控制每一级RS的输出端OUT输出作为上述非选通信号的低电平。
在一些实施例中，如图6所示，该RS包括第一复位晶体管Mtr1。该第一复位晶体管Mtr1的栅极连接到总复位端TRST，第一极连接到RS的输出端OUT，第二极与第一电压端V1相连接。
在此基础上，上述S203包括：
在来自总复位端TRST的第一使能信号的控制下，第一复位晶体管Mtr1导通，RS的输出端OUT与第一电压端V1电连接。
在此情况下，通过导通的第一复位晶体管Mtr1将RS的输出端OUT的信号拉低至第一电压端V1。其中，该第一电压端V1可以输出低电平VGL。这样一来，与该RS的输出端OUT相连接的栅线接收到的信号为非选通信号，此时，被该栅线控制的一行亚像素中的TFT无法被开启，因此该行亚像素中像素电极上的电荷不会被快速释放，从而使得该行亚像素保持上一帧的画面。
由于所有RS均设置有上述总复位端TRST，因此每一级RS的输出端OUT都会输出上述非选通信号，从而使得所有的栅线均处于未被选通的状态，在此情况下，所有的亚像素均保持上一帧的显示数据进行显示。从而解决了部分亚像素放电导致显示画面出现闪横线的问题。
为了在DE丢失后，进一步提高显示画面的均匀性，在一些实施例中，如图6所示，上述的移位寄存器还包括第二复位晶体管Mtr2。该第二复位晶体管Mtr2的栅极连接到总复位端TRST，第一极连接到RS中的上拉节点PU，第二极与第一电压端V1相连接。在此情况下，所述方法还包括：在来自总复位端TRST的第一使能信号的控制下，第二复位晶体管Mtr2导通，上拉节点PU与第一电压端V1电连接。这样一来，通过导通的第二复位晶体管Mtr2，将上拉节点PU的电位下拉至第一电压端V1输出的低 电平VGL。在此情况下，可以确保驱动晶体管Md处于截止状态，从而，即使LS执行电荷共享操作，时钟信号端GS_CLK输出的中间电压Vm也无法通过驱动晶体管Md传输至RS的输出端OUT，能够避免时钟信号端GS_CLK输出的中间电压Vm对RS的输出端OUT输出信号的影响，进而避免与该RS的输出端OUT相连接的栅线被选通。
在一些实施例中，第一复位晶体管Mtr1和第二复位晶体管Mtr2的第一极为源极，第二极可以为漏极。在另一些实施例中，第一复位晶体管Mtr1和第二复位晶体管Mtr2的第一极为漏极，第二极可以为源极。
在一些实施例中，在触发元件103还与LS上的电荷共享控制端VGP相连接的情况下，上述S102的实现过程，如图7所示，包括：
S301、信号判断元件101判断DE在至少一个周期内是否连续为低电平。
S302、若信号判断元件101判断DE在至少一个周期内连续为低电平VGL，则，指令生成元件102生成第一信号调整指令，触发元件103根据第一信号调整指令控制LS停止执行电荷共享操作。
S303、LS向栅极驱动子电路20提供的多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)的每个在至少一个周期内连续为非选通信号。该非选通信号例如为低电平VGL。
在一些实施例中，该S301包括：当DE在至少一个周期内连续为低电平VGL时，如图2c所示，触发元件103根据指令生成元件102生成的第一信号调整指令，向LS的电荷共享控制端VGP提供第二使能信号。LS的电荷共享控制端VGP接收第二使能信号，在来自该电荷共享控制端VGP的第二使能信号的控制下，LS停止执行电荷共享操作。从而使得触发元件103达到根据第一信号调整指令，控制栅极驱动子电路20中的每一级RS的输出端OUT输出非选通信号的目的。这样一来，只需要向该LS上的电荷共享控制端VGP提供第二使能信号，便可以在该电荷共享控制端VGP的控制下，使得LS停止执行电荷共享操作。因此，无需单独设置用于控制LS停止执行电荷共享操作的电路结构，从而能够简化控制方法以及整个显示驱动电路的结构。
在一些实施例中，如图8所示，LS的电荷共享控制端VGP接收的第二使能信号可以为高电平VGH。
由上述可知，当DE信号丢失后，可以通过LS的电荷共享控制端VGP 控制LS停止执行电荷共享操作。这样一来，如图8所示，多个有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)中的每个会跟随(Follow)DE的变化，进而转变为低电平。该低电平作为非选通信号提供至与该RS的输出端OUT相连接的栅线，此时，被该栅线控制的一行亚像素中的TFT无法被开启。因此，该行亚像素中像素电极上的电荷不会被快速释放，从而使得该行亚像素保持上一帧的画面。
由于LS停止执行电荷共享操作后，初始时钟信号(CLK1、CLK2、CLK3、CLK4……)会在不经过中间电压Vm的情况下，直接转换至(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)，所以该方案可以在不考虑功耗影响的情况下采用。
在一些实施例中，当DE信号恢复正常后，即信号判断元件101判断DE未在至少一个周期内连续为低电平时，控制子电路10控制LS执行上述电荷共享操作，以降低初始时钟信号(CLK1、CLK2、CLK3、CLK4……)向有效时钟信号(GS_CLK1、GS_CLK2、GS_CLK3、GS_CLK4……)转换过程中的功耗。
基于此，为了达到降低功耗的目的，在一些实施例中，所述方法还包括：
信号判断元件101判断DE在至少一个周期内是否连续为低电平，若信号判断元件101判断DE未在至少一个周期内连续为低电平，则，该指令生成元件102生成第二信号调整指令，触发元件103根据该第二信号调整指令控制LS执行上述的电荷共享操作。
在一些实施例中，如图2d所示，上述的显示驱动电路还包括与TCON相连接的源极驱动子电路30。基于此，当DE在至少一个周期内连续为低电平VGL时，TCON进入静音(Mute)模式，从而可以使得该TCON向源极驱动子电路30输出用于显示黑色图像的数据电压Vdata。这样一来，可以减少源极驱动子电路30的功耗。
当DE恢复正常时，TCON从Mute模式切换回正常模式，源极驱动子电路30输出用于正常显示的数据电压Vdata。在此情况下，对图4或图8所对应的控制方案中的任意一种方案中，当DE恢复正常后，即在DE在至少一个周期内连续为低电平之后，且当所述DE输出正常方波信号时，上述方法还包括：
控制子电路10向栅极驱动子电路20中第一级RS的输入端Input输出 起始信号STV。在此情况下，栅极驱动子电路20中多个级联的RS可以从第一级RS开始执行移位寄存功能。这样一来，显示面板中的栅线从头开始逐行进行扫描，以显示新的一帧画面。
本公开的一些实施例提供一种计算机设备，包括存储器、处理器。该存储器上存储有可在处理器上运行的计算机程序，处理器执行计算机程序时实现如上所述的任意一种方法。该计算机设备具有与前述实施例提供的控制方法相同的技术效果，此处不再赘述。
在一些实施例中，上述存储器包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
本公开的一些实施例提供一种计算机可读介质，其存储有计算机程序，所述计算机程序被处理器执行时实现如上所述的任意一种方法。该计算机可读介质具有与前述实施例提供的控制方法相同的技术效果，此处不再赘述。
本公开的一些实施例提供一种显示装置，该显示装置包括如上所述的任意一种显示驱动电路。该显示装置具有与前述实施例提供的显示驱动电路相同的技术效果，此处不再赘述。
该显示装置包括显示面板。在一些实施例中，上述的显示驱动电路通过构图工艺(例如Mask工艺)直接制作于显示面板的非显示区域。在另一些实施例中，上述的显示驱动电路集成于芯片上，然后将该芯片绑定(Bonding)于显示面板上。本公开对上述显示驱动电路的设置方式不做限定，但均属于本公开的保护范围内。
显示装置可以为液晶显示装置或者有机发光二极管显示装置。例如，该显示装置可以用于构成显示器、电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
以上所述，仅为本公开的一些实施方式，但本公开的保护范围并不局限于此。任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示驱动电路，包括控制子电路以及与所述控制子电路相连接的栅极驱动子电路；
    所述控制子电路配置为接收有效显示数据选通信号，并根据所述有效显示数据选通信号向所述栅极驱动子电路提供多个有效时钟信号；所述控制子电路还配置为判断所述有效显示数据选通信号丢失时，生成第一信号调整指令，并根据所述第一信号调整指令控制所述栅极驱动子电路中的每一级移位寄存器的输出端输出非选通信号。
  2. 根据权利要求1所述的显示驱动电路，其中，所述控制子电路包括时序控制器以及与所述时序控制器相连接的电平转换器；
    所述时序控制器配置为接收所述有效显示数据选通信号，并根据所述有效显示数据选通信号向所述电平转换器输出多个初始时钟信号；
    所述电平转换器配置为将所述多个初始时钟信号转换为所述多个有效时钟信号，所述多个初始时钟信号中每个的幅值小于转换后的有效时钟信号的幅值。
  3. 根据权利要求1或2所述的显示驱动电路，其中，所述控制子电路还包括信号判断元件以及与所述信号判断元件相连接的指令生成元件；
    所述信号判断元件配置为判断所述有效显示数据选通信号是否丢失；
    所述指令生成元件配置为接收所述信号判断元件的判断结果，并当所述信号判断元件判断所述有效显示数据选通信号丢失时，生成所述第一信号调整指令。
  4. 根据权利要求3所述的显示驱动电路，其中，所述指令生成元件还配置为当所述信号判断元件判断所述有效显示数据选通信号未丢失时，生成第二信号调整指令。
  5. 根据权利要求3或4所述的显示驱动电路，其中，所述控制子电路还包括与所述指令生成元件相连接的触发元件；
    所述触发元件还与所述栅极驱动子电路中的每一级移位寄存器所连接的总复位端相连接；所述触发元件配置为根据所述第一信号调整指令，向所述栅极驱动子电路中的每一级移位寄存器所连接的总复位端提供第一使能信号。
  6. 根据权利要求2-4任一项所述的显示驱动电路，其中，所述控制子电路还包括与所述指令生成元件相连接的触发元件；
    所述触发元件与电平转换器相连接，所述触发元件配置为根据所述第一信号调整指令，控制所述电平转换器停止执行电荷共享操作。
  7. 根据权利要求4或6所述的显示驱动电路，其中，所述控制子电路还包括与所述指令生成元件相连接的触发元件；所述触发元件配置为根据第二信号调整指令，控制所述电平转换器执行电荷共享操作。
  8. 根据权利要求5-7任一项所述的显示驱动电路，其中，所述信号判断元件、所述指令生成元件以及所述触发元件集成于时序控制器中。
  9. 一种用于控制如权利要求1-8任一项所述的显示驱动电路的控制方法，包括：
    控制子电路接收有效显示数据选通信号，并根据所述有效显示数据选通信号向栅极驱动子电路提供多个有效时钟信号；
    所述控制子电路判断所述有效显示数据选通信号丢失时，生成第一信号调整指令，并根据所述第一信号调整指令控制所述栅极驱动子电路中的每一级移位寄存器的输出端输出非选通信号。
  10. 根据权利要求9所述的显示驱动电路的控制方法，其中，所述控制子电路包括时序控制器、电平转换器、信号判断元件、指令生成元件和触发元件；
    所述控制子电路判断所述有效显示数据选通信号丢失时，生成第一信号调整指令，并根据所述第一信号调整指令控制所述栅极驱动子电路中的每一级移位寄存器的输出端输出非选通信号，包括：
    所述信号判断元件判断所述有效显示数据选通信号在至少一个周期内是否连续为低电平；
    若所述信号判断元件判断所述有效显示数据选通信号在至少一个周期内连续为低电平，则，所述电平转换器保持电荷共享操作，将所述时序控制器输出的多个初始时钟信号中的每个转换为中间电压，所述中间电压大于有效时钟信号的波谷电压，小于有效时钟信号的波峰电压；
    所述指令生成元件生成所述第一信号调整指令，所述触发元件根据所述第一信号调整指令向所述栅极驱动子电路中的每一级移位寄存器所连接的总复位端提供第一使能信号；
    在来自所述总复位端的所述第一使能信号的控制下，所述移位寄存器的输出端的电压下拉至用于输出低电平的第一电压端。
  11. 根据权利要求10所述的显示驱动电路的控制方法，其中，所述移 位寄存器包括第一复位晶体管；所述第一复位晶体管的栅极连接到所述总复位端，第一极连接到所述移位寄存器的输出端，第二极与所述第一电压端相连接；
    在来自所述总复位端的所述第一使能信号的控制下，所述移位寄存器的输出端的电压下拉至用于输出低电平的第一电压端，包括：在来自所述总复位端的所述第一使能信号的控制下，所述第一复位晶体管导通，所述移位寄存器的输出端与所述第一电压端电连接。
  12. 根据权利要求11所述的显示驱动电路的控制方法，其中，所述移位寄存器还包括第二复位晶体管；所述第二复位晶体管的栅极连接到所述总复位端，第一极连接到所述移位寄存器中的上拉节点，第二极与所述第一电压端相连接；所述方法还包括：在来自所述总复位端的所述第一使能信号的控制下，所述第二复位晶体管导通，所述上拉节点与所述第一电压端电连接。
  13. 根据权利要求9所述的显示驱动电路的控制方法，其中，所述控制子电路包括时序控制器、电平转换器、信号判断元件、指令生成元件和触发元件；
    所述控制子电路判断所述有效显示数据选通信号丢失时，生成第一信号调整指令，并根据所述第一信号调整指令控制所述栅极驱动子电路中的每一级移位寄存器的输出端输出非选通信号，包括：
    所述信号判断元件判断所述有效显示数据选通信号在至少一个周期内是否连续为低电平；
    若所述信号判断元件判断所述有效显示数据选通信号在至少一个周期内连续为低电平，则，所述指令生成元件生成所述第一信号调整指令；
    所述触发元件根据所述第一信号调整指令控制所述电平转换器停止执行电荷共享操作；所述电平转换器向所述栅极驱动子电路提供的所述多个有效时钟信号的每个在至少一个周期内连续为所述非选通信号。
  14. 根据权利要求13所述的显示驱动电路的控制方法，其中，所述方法还包括：若所述信号判断元件判断所述有效显示数据选通信号未在至少一个周期内连续为低电平，则，所述指令生成元件生成第二信号调整指令，所述触发元件根据所述第二信号调整指令控制所述电平转换器执行电荷共享操作。
  15. 根据权利要求13所述的显示驱动电路的控制方法，其中，所述控 制所述电平转换器停止执行电荷共享操作包括：
    所述电平转换器的电荷共享控制端接收第二使能信号，在来自所述电荷共享控制端的所述第二使能信号的控制下，所述电平转换器停止执行电荷共享操作。
  16. 根据权利要求9-15任一项所述的显示驱动电路的控制方法，其中，在所述有效显示数据选通信号在至少一个周期内连续为低电平之后，且当所述有效显示数据选通信号为方波信号时，所述方法还包括：
    所述控制子电路向所述栅极驱动子电路中第一级移位寄存器的输入端输出起始信号。
  17. 根据权利要求10-15任一项所述的显示驱动电路的控制方法，其中，所述显示驱动电路还包括与时序控制器相连接的源极驱动子电路；
    当所述有效显示数据选通信号在至少一个周期内连续为低电平时，所述方法还包括：所述时序控制器向所述源极驱动子电路输出用于显示黑色图像的数据电压。
  18. 一种计算机设备，包括存储器、处理器；所述存储器上存储有可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现如权利要求9-17任一项所述的显示驱动电路的控制方法。
  19. 一种显示装置，包括如权利要求1-8任一项所述的显示驱动电路。
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