WO2019052091A1 - 拼板工艺边及拼板方法 - Google Patents

拼板工艺边及拼板方法 Download PDF

Info

Publication number
WO2019052091A1
WO2019052091A1 PCT/CN2017/120095 CN2017120095W WO2019052091A1 WO 2019052091 A1 WO2019052091 A1 WO 2019052091A1 CN 2017120095 W CN2017120095 W CN 2017120095W WO 2019052091 A1 WO2019052091 A1 WO 2019052091A1
Authority
WO
WIPO (PCT)
Prior art keywords
edge
test
panel
copper
layer
Prior art date
Application number
PCT/CN2017/120095
Other languages
English (en)
French (fr)
Inventor
程柳军
李艳国
陈蓓
Original Assignee
广州兴森快捷电路科技有限公司
深圳市兴森快捷电路科技股份有限公司
宜兴硅谷电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 广州兴森快捷电路科技有限公司, 深圳市兴森快捷电路科技股份有限公司, 宜兴硅谷电子科技有限公司 filed Critical 广州兴森快捷电路科技有限公司
Publication of WO2019052091A1 publication Critical patent/WO2019052091A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits

Definitions

  • the present invention relates to the field of electronics, and more particularly to a method and a method for assembling a panel.
  • the uniformity of the thickness of the dielectric layer of the PCB has certain influence on the performance of the PCB. For example, as the PCB tends to be light, thin and short, the thickness of the dielectric layer in the PCB is getting smaller and smaller, so that the uniformity of the thickness of the dielectric layer is controlled to the impedance. The impact is getting bigger and bigger.
  • impedance test strip or test module it is common practice to design an impedance test strip or test module at the edge of the PCB panel to simulate the impedance within the unit. The impedance of the impedance test strip or test module can be detected quickly and conveniently. Determine the impedance control of the PCB.
  • the thickness of the dielectric layer of the impedance test strip or the test module is greatly different from that of the graphic unit.
  • the presence of factors such as edge overflow during lamination will further increase the difference in dielectric layer thickness between the impedance test strip or the test module and the pattern unit, and the thickness of the dielectric layer has the largest influence on the impedance control, resulting in impedance testing.
  • the strip or test module does not match the impedance value of the graphic unit.
  • the invention overcomes the defects that the thickness of the dielectric layer of the PCB panel is not uniform due to the design of the PCB in the prior art, and further causes the test result of the test strip or the test module to fail to truly reflect the corresponding value of the graphic unit, and provides a jigsaw process. Edge and panel method.
  • a jigsaw process edge disposed on the periphery of the graphic unit of the circuit board, comprises: at least two layers of process edges stacked, each layer has a balanced copper point on the edge of the process, and the residual copper ratio of each layer of the process side and corresponding The residual copper ratio of the graphic unit of the layer is the same.
  • the jigsaw process side of the technical solution has the same lamination as the graphic unit of the jigsaw, and the jigsaw process retains the targets of the conventional plate edge auxiliary holes, such as laminated positioning holes, drilling positioning holes, etc.;
  • Balanced copper points are set at corresponding positions of the process edges of the layer, that is, all layers of the craft side are provided with balanced copper points, and the number of the balanced copper points and the size of the balanced copper points satisfy the process of laying the balanced copper points.
  • the residual copper ratio of each layer is the same as the residual copper ratio of the pattern unit of the corresponding layer.
  • the residual copper ratio of each layer of the jigsaw process is consistent with the residual copper ratio of the graphic unit of the corresponding layer, the consistency of the thickness of the jigsaw process edge and the dielectric layer of the graphic unit after the lamination is ensured, and the jigsaw is improved.
  • the uniformity of the plate thickness ensures that the current density distribution of the jigsaw process side and the graphic unit is more uniform during electroplating, and the test result of the test strip or the test module set in the process edge is improved, which effectively represents the graphic unit of the graphic unit. Relevant real values.
  • the equilibrium copper dots of adjacent layers are misaligned.
  • the center point of the equilibrium copper dots of the adjacent layers is misaligned.
  • the balanced copper dots are circular, rectangular, triangular or polygonal.
  • the center distance of the equilibrium copper points of the same layer or the equilibrium copper points of the different layers remains the same, and/or the equilibrium copper points of the same layer or the dimensions of the balanced copper points of the different layers are continuously variable.
  • At least the edge of the inner layer side is provided with a copper strip with a flow tank.
  • the glue grooves of adjacent layers are arranged in a staggered position.
  • the technical solution further provides a splicing method, the stencil includes a slab process edge and at least one graphic unit and a test strip or a test module placed in the edge of the slab process, the jig craft side is any of the above In the edge of the jigsaw process described in the embodiment, the jigsaw method is:
  • test strip or the test module is placed in a direction in which the margin of the pattern unit is larger than the edge of the panel, and the edge of the panel formed by the graphic unit and the test strip or the test module after the panel is assembled.
  • the edge margins of the sides are equal.
  • the jigsaw method of the technical solution complies with the principle of compact center and symmetrical margin of the board edge, improves the accuracy of the test result of the test strip or the test module, and effectively represents the relevant true value of the graphic unit.
  • the test strip or test module is placed between the graphic units.
  • test strips or test modules when the number of the test strips or test modules is at least two, at least two test strips or test modules are placed side by side.
  • the edge of the panel formed by the pattern unit and the test strip or the test module after the panel is not less than 0.5 inch from the edge of the panel side; and/or the test strip or test
  • the module and the graphic unit are spaced apart, and the distance between the test strip or the test module and the graphic unit ranges from 0.05 inches to 0.1 inches.
  • the jigsaw process side of the technical solution has the same lamination as the graphic unit of the jigsaw, and the jigsaw process retains the targets of the conventional plate edge auxiliary holes, such as laminated positioning holes, drilling positioning holes, etc.;
  • Balanced copper points are set on the edge of the layer process, that is, all the layers on the side of the jigsaw process are provided with balanced copper points, and the number of the balanced copper points and the size of the balanced copper points satisfy the edge of the jigsaw process after laying the balanced copper points.
  • the residual copper ratio of the layer is the same as the residual copper ratio of the pattern unit of the corresponding layer.
  • the residual copper ratio of each layer of the jigsaw process is consistent with the residual copper ratio of the graphic unit of the corresponding layer, the consistency of the thickness of the jigsaw process edge and the dielectric layer of the graphic unit after the lamination is ensured, and the jigsaw is improved.
  • the uniformity of the plate thickness ensures that the current density distribution of the jigsaw process edge and the graphic unit is more uniform during electroplating, and improves the accuracy of the test strip or the test module set in the process edge, effectively representing the correlation of the graphic unit. actual value.
  • the method of assembling the technical solution complies with the principle of compact center and symmetrical margin of the board edge, and improves the consistency of the test strip or the test module with the graphic unit, so that the test strip or the test module effectively represents the relevant real value of the graphic unit.
  • FIG. 1 is a schematic structural view of a side of a jigsaw process of the present invention
  • FIG. 2 is a schematic view 1 of an equilibrium copper point of an adjacent layer of the present invention
  • FIG. 3 is a schematic view 2 of an equilibrium copper point of an adjacent layer of the present invention.
  • FIG. 4 is a schematic structural view of a layer of a process side of the present invention.
  • Figure 5 is a schematic structural view of a process side adjacent to the process side of Figure 4.
  • Figure 6 is a schematic view of the puzzle piece of the present invention.
  • Figure 7 is a schematic view 1 of a puzzle piece of the puzzle board of the present invention.
  • Figure 8 is a schematic view 2 of a puzzle piece of the puzzle board of the present invention.
  • Figure 9 is a schematic view of a piece of the puzzle of the present invention.
  • a jigsaw process edge 100 as shown in FIG. 1 is disposed on the periphery of the graphic unit 200 of the circuit board, and includes: at least two layers of process edges 10 stacked on each side, and each layer of the process edge 10 is provided with a balanced copper dot 11 And the residual copper ratio of each process side 10 is the same as the residual copper ratio of the graphic unit 200 of the corresponding layer.
  • the jigsaw process edge 100 of the present embodiment has the same lamination as the graphic unit 200 of the jigsaw, and the jigsaw process 100 retains the targets of the conventional plate edge auxiliary holes, such as laminated positioning holes, drilling positioning holes, and the like;
  • Balanced copper dots 11 are disposed on each process edge 10, that is, all layers of the jigsaw process edge 100 are provided with balanced copper dots, and the number of the balanced copper dots 11 and the size of the balanced copper dots 11 satisfy the laying balance copper point.
  • the residual copper ratio of each layer of the jigsaw process side 100 after 11 is the same as the residual copper ratio of the graphic unit 200 of the corresponding layer.
  • the residual copper ratio of each layer of the jigsaw process edge 100 is consistent with the residual copper ratio of the graphic unit 200 of the corresponding layer, the consistency of the thickness of the dielectric layer 100 of the laminated glue after the lamination process is ensured.
  • the plate thickness consistency of the jigsaw plate is improved, and the current density distribution of the jigsaw process edge and the graphic unit during the electroplating is more uniform, and the test result of the test strip or the test module disposed on the process side 100 is improved, and the representative of the test result is effectively represented.
  • the associated true value of graphics unit 200 is provided.
  • the center distance of the balanced copper dots 11 of the same layer or the balanced copper dots 11 of different layers remains unchanged, and/or the size of the balanced copper dots 11 of the same layer or the balanced copper dots 11 of different layers is continuously variable. That is, the distance between the center points of adjacent balanced copper dots 11 of the same layer remains unchanged, or the distance between the center points of adjacent balanced copper dots 11 on each layer is the same; and the balance copper of different layers
  • the size of the dots 11 may be the same or different, and the size of the balanced copper dots 11 on the same layer may be the same, may be different, and the size of the balanced copper dots 11 may be continuously variable, thereby providing a residual copper ratio of 0%-
  • the 100% continuously variable selection makes the residual copper ratio of the jigsaw process side consistent with the residual copper ratio of the graphic unit.
  • the center distance of the adjacent balanced copper dots 11 on the same layer is 100 mil, and the side length of the balanced copper dots 11 is adjusted to 50 mils or a radius of 0-80 mils according to the actual residual copper ratio of the graphic unit, thereby obtaining 0%-100%.
  • Continuously variable residual copper ratio When the PCB has multiple layers, the residual copper ratio of the process edge 10 of each layer coincides with the residual copper ratio of the graphics unit 200 of the layer.
  • the balanced copper dots 11 of the adjacent layers are arranged in a staggered position. As shown in FIGS. 1 and 2, the balanced copper dots 11 of adjacent layers are arranged offset, for example, the balanced copper dots 111 on the first layer and the balanced copper dots 112 on the second layer adjacent to the first layer are misaligned and Without overlapping, the thickness uniformity of the jigsaw process edge 100 is improved.
  • the center point of the balanced copper dots 11 of the adjacent layers is dislocated. As shown in FIG. 3, for example, the center point of the balance copper point 113 on the third layer and the balance copper point 114 on the fourth layer adjacent to the third layer is misaligned, and the balance copper point 113 on the third layer is There is a partial overlap of the equilibrium copper dots 114 on the fourth layer.
  • the size of the balanced copper dots 11 on each process side 10 is inconsistent, and when the residual copper ratio of a certain layer or a certain adjacent two layer of the graphic unit is large, in order to satisfy the residual copper ratio and the graphic unit, the jigsaw process
  • the size of the balanced copper dots 11 of the corresponding layers on the side 100 is also large, so that the overlapping copper dots 11 of the adjacent layers may overlap, and the balanced copper dots 11 of the adjacent layers cannot be completely misaligned within the size range thereof; At the same time, it is only necessary to satisfy the center point misalignment setting of the equilibrium copper dots 11 of the adjacent layers, thereby maximizing the thickness uniformity of the jigsaw process side 100.
  • the position of the center point of each balanced copper point 11 on the odd-numbered layer on the edge of the jigsaw process 100 can be set to the same position on each odd-numbered layer, and the balance copper point 11 on the even-numbered layer on the side of the jigsaw process 100 The position of the center point is set to the same position on each even layer of each layer, which simplifies the operation process and improves the efficiency of laying the balance copper point 11.
  • balance copper dots 11 are plural, and a plurality of balance copper dots 11 are uniformly disposed on the process edge 10 to further improve the thickness uniformity of the jigsaw process edge 100.
  • the balance copper dots 11 are circular, rectangular, triangular or polygonal. As shown in FIG. 1 to FIG. 3, the balance copper dot 11 of the present embodiment adopts a circular shape, and the radius of the circular balance copper dot 11 is continuously variable from 0 to 80, and in other embodiments, a square or the like may be used. A simple and convenient graphic serves as the shape of the balance copper spot 11.
  • the edge of the inner layer side 10 is provided with a copper skin 12 with a flow glue groove 121.
  • the edge of the process edge 10 is formed on the edge 10 of each layer except the balance copper point 11 is laid.
  • the copper skin 12 with the flow glue groove 121 is designed in a certain size to avoid the phenomenon that the edge of the plate is excessively overflowed, and the uniformity of the thickness of the dielectric layer of the PCB plate is further improved.
  • FIG. 1 is a schematic structural view of a stacked two adjacent process edges 10, that is, a schematic structural view of the stacked layers of FIG. 4 and FIG. 5, as can be seen from the figure, the balanced copper dots 11 and the flow glue grooves 121 of the adjacent layers are all misaligned.
  • the setting increases the thickness uniformity of the jigsaw process edge 100.
  • the embodiment further provides a paneling method, the panel comprising a panel craft edge 100 and at least one graphics unit 200 and a test strip or test placed in the panel process edge 100.
  • the module 300, the jigsing process edge 100 is the jigsaw process edge 100 described in any of the above embodiments, and the jigsaw method is as follows:
  • the test strip or test module 300 is placed in the direction of the margin of the board unit 200 from the edge of the panel process, and the edge of the panel formed by the pattern unit 200 and the test strip or test module 300 after the panel is
  • the test strips or the test modules 300 are placed between the graphic units 200, and the graphics unit 200 and the test strips or the test modules 300 are formed by the posterior panels.
  • the edge of the board is equal to the margin of the edge of the panel 100. As shown in FIG.
  • the present embodiment takes a spelling two as an example.
  • the panel method of the present embodiment complies with the principle of center compactness and symmetry of the margin of the board edge, and improves the accuracy of the test result of the test strip or the test module 300, and effectively represents the relevant true value of the graphic unit 200.
  • FIG. 9 when one is three, the principle that the center is compact and the margin of the board edge is symmetrical is adhered to, and the edge of the panel formed by the graphic unit 200 and the test strip or the test module 300 after the panel is required to be ensured.
  • the number of the test strips or test modules 300 may exceed one, that is, when at least two test strips or test modules 300 are disposed in the same panel, preferably at least two test strips or test modules 300 are placed side by side. .
  • test strip or the test module 300 used in the embodiment is an impedance test strip or a test module.
  • the present embodiment optimizes the PCB board assembly method, thereby reducing the test strip or the test module and the graphic unit in the panel. The difference is that the test result of the test strip or the test module is more representative of the true value of the graphic unit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

一种拼板工艺边及拼板方法。拼板工艺边（100）设于电路板的图形单元（200）的***，包括：至少两层层叠设置的工艺边（10），每层工艺边上设有平衡铜点（11），且每层工艺边的残铜率与相应层的图形单元的残铜率相同。拼板方法的拼板包括拼板工艺边以及置于拼板工艺边内的图形单元和测试条或测试模块（300）。由于拼板工艺边各层的残铜率与相应层的图形单元的残铜率一致，因此保证了层压填胶后的拼板工艺边与图形单元的介质层厚度的一致性，提高拼板的板厚一致性，同时可保证电镀时拼板工艺边与图形单元的电流密度分布更加均匀，提高设置于工艺边内的测试条或测试模块测试结果的准确性，有效代表图形单元的相关真实值。

Description

拼板工艺边及拼板方法 技术领域
本发明涉及电子领域，更具体地，涉及一种拼板工艺边及拼板方法。
背景技术
PCB介质层厚度的均匀性对PCB的各项性能均有一定影响，例如，随着PCB趋于轻薄短小发展，PCB中介质层厚度越来越小，使得介质层厚度均匀性的控制对阻抗的影响越来越大。对于有阻抗控制要求的PCB，目前常见的做法是在PCB拼板板边位置设计阻抗测试条或测试模块，用于模拟单元内的阻抗，可通过检测阻抗测试条或测试模块的阻抗快速、方便地判断PCB的阻抗控制情况。但是，由于阻抗测试条或测试模块的图形、残铜率和所处的拼板位置等与实际图形存在较大的差异，使得阻抗测试条或测试模块的介质层厚度与图形单元差异较大，同时，在层压时板边溢胶等因素的存在会进一步增大阻抗测试条或测试模块与图形单元的介质层厚度差异，而介质层厚度对阻抗控制的影响占比最大，从而导致阻抗测试条或测试模块与图形单元的阻抗值不一致的情况。
因此，改善PCB电路板的介质层厚度均匀性是各PCB企业急需解决的问题。
发明内容
基于此，本发明在于克服现有技术中PCB因设计导致PCB拼板介质层厚度不均匀，进一步导致测试条或测试模块的检测结果无法真实反映图形单元相应值的缺陷，提供一种拼板工艺边及拼板方法。
其技术方案如下：
一种拼板工艺边，设于电路板的图形单元的***，包括：至少两层层叠设置的工艺边，每层工艺边上设有平衡铜点，且每层工艺边的残铜率与相应层的图形单元的残铜率相同。
本技术方案的拼板工艺边与拼板的图形单元有相同的叠层，且拼板工艺边 保留常规的板边辅助孔的靶标，例如层压定位孔、钻孔定位孔等；在PCB各层的工艺边对应位置设置平衡铜点，即拼板工艺边的所有层均设置平衡铜点，且所述平衡铜点设置的数量以及平衡铜点的尺寸满足铺设平衡铜点后的拼板工艺边各层的残铜率与相应层的图形单元的残铜率相同。由于拼板工艺边各层的残铜率与相应层的图形单元的残铜率一致，因此保证了层压填胶后的拼板工艺边与图形单元的介质层厚度的一致性，提高拼板的板厚一致性，同时可保证电镀时拼板工艺边与图形单元的电流密度分布更加均匀，提高设置于工艺边内的测试条或测试模块测试结果的准确性，有效代表图形单元图形单元的相关真实值。
在其中一个实施例中，相邻层的平衡铜点呈错位设置。
在其中一个实施例中，所述相邻层的平衡铜点的中心点呈错位设置。
在其中一个实施例中，所述平衡铜点为圆形、矩形、三角形或多边形。
在其中一个实施例中，同一层的平衡铜点或不同层的平衡铜点的中心距保持不变，和/或同一层的平衡铜点或不同层的平衡铜点的尺寸连续可变。
在其中一个实施例中，至少内层工艺边的边缘设有带流胶槽的铜皮。
在其中一个实施例中，相邻层的流胶槽呈错位设置。
本技术方案还提供一种拼板方法，所述拼板包括拼板工艺边以及置于拼板工艺边内的至少一个图形单元和测试条或测试模块，所述拼板工艺边为上述任一实施例所述的拼板工艺边，所述拼板方法为：
所述测试条或测试模块置于图形单元距拼板工艺边的板边余量较多的方向上，且拼板后图形单元和测试条或测试模块形成的拼板的边沿，距离拼板工艺边的板边余量相等。
本技术方案的拼板方法遵守中心紧凑、板边余量对称的原则，提高测试条或测试模块测试结果的准确性，有效地代表图形单元的相关真实值。
在其中一个实施例中，当所述图形单元的数量为多个时，优选地，所述测试条或测试模块置于图形单元之间。
在其中一个实施例中，当所述测试条或测试模块的数量为至少两个时，至少两个测试条或测试模块并排放置。
在其中一个实施例中，拼板后图形单元和测试条或测试模块形成的拼板的边沿，距离拼板工艺边的板边余量不少于0.5英寸；和/或所述测试条或测试模块与图形单元之间间隔设置，且测试条或测试模块与图形单元的间距范围为0.05英寸-0.1英寸之间。
本发明的有益效果在于：
本技术方案的拼板工艺边与拼板的图形单元有相同的叠层，且拼板工艺边保留常规的板边辅助孔的靶标，例如层压定位孔、钻孔定位孔等；在PCB各层工艺边上设置平衡铜点，即拼板工艺边的所有层均设置平衡铜点，且所述平衡铜点设置的数量以及平衡铜点的尺寸满足铺设平衡铜点后的拼板工艺边各层的残铜率与相应层的图形单元的残铜率相同。由于拼板工艺边各层的残铜率与相应层的图形单元的残铜率一致，因此保证了层压填胶后的拼板工艺边与图形单元的介质层厚度的一致性，提高拼板的板厚一致性，同时可保证电镀时拼板工艺边与图形单元的电流密度分布更加均匀，提高设置于工艺边内的测试条或测试模块测试结果的准确性，有效地代表图形单元的相关真实值。
本技术方案的拼板方法遵守中心紧凑、板边余量对称的原则，提高测试条或测试模块与图形单元的一致性，使测试条或测试模块有效地代表图形单元的相关真实值。
附图说明
图1为本发明的拼板工艺边的结构示意图；
图2为本发明的相邻层的平衡铜点的示意图一；
图3为本发明的相邻层的平衡铜点的示意图二；
图4为本发明的某层工艺边的结构示意图；
图5为与图4工艺边相邻层的工艺边的结构示意图；
图6为本发明的拼板的一拼一的示意图；
图7为本发明的拼板的一拼二的示意图一；
图8为本发明的拼板的一拼二的示意图二；
图9为本发明的拼板的一拼三的示意图。
附图标记说明：
100、拼板工艺边；10、工艺边；11、平衡铜点；111、第一层上的平衡铜点；112、第二层上的平衡铜点；12、铜皮；121、流胶槽；200、图形单元；300、测试条或测试模块。
具体实施方式
为使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施方式，对本发明进行进一步的详细说明。应当理解的是，此处所描述的具体实施方式仅用以解释本发明，并不限定本发明的保护范围。
如图1所示的一种拼板工艺边100，设于电路板的图形单元200的***，包括：至少两层层叠设置的工艺边10，每层工艺边10上设有平衡铜点11，且每层工艺边10的残铜率与相应层的图形单元200的残铜率相同。
本实施方式的拼板工艺边100与拼板的图形单元200有相同的叠层，且拼板工艺100边保留常规的板边辅助孔的靶标，例如层压定位孔、钻孔定位孔等；在每层工艺边10上设置平衡铜点11，即拼板工艺边100的所有层均设置平衡铜点，且所述平衡铜点11设置的数量以及平衡铜点11的尺寸满足铺设平衡铜点11后的拼板工艺边100各层的残铜率与相应层的图形单元200的残铜率相同。由于拼板工艺边100各层的残铜率与相应层的图形单元200的残铜率一致，因此保证了层压填胶后的拼板工艺边100与图形单元200的介质层厚度的一致性，提高拼板的板厚一致性，同时可保证电镀时拼板工艺边与图形单元的电流密度分布更加均匀，提高设置于工艺边100的测试条或测试模块测试结果的准确性，有效地代表图形单元200的相关真实值。
进一步地，同一层的平衡铜点11或不同层的平衡铜点11的中心距保持不变，和/或同一层的平衡铜点11或不同层的平衡铜点11的尺寸连续可变。即同一层的相邻的平衡铜点11的中心点之间的距离保持不变，或每一层上相邻的平衡铜点11的中心点之间的距离均相同；而不同层的平衡铜点11的尺寸可以相 同，也可以不同，同一层上的平衡铜点11的尺寸也可以相同，可以不相同，且平衡铜点11的尺寸连续可变，从而可提供残铜率为0％-100％连续可变的选择，使得拼板工艺边的残铜率与图形单元的残铜率一致。优选地，同一层上相邻平衡铜点11的中心距离为100mil，根据图形单元的实际残铜率调整平衡铜点11的边长为50mil或半径为0-80mil，从而获得0％-100％连续可变的残铜率。当PCB有多层时，每层的工艺边10的残铜率与该层的图形单元200的残铜率一致。
进一步地，相邻层的平衡铜点11呈错位设置。如图1和图2所示，相邻层的平衡铜点11错位排布，例如第一层上的平衡铜点111和与第一层相邻的第二层上的平衡铜点112错位且不重叠，提高了拼板工艺边100的厚度均匀性。
进一步地，所述相邻层的平衡铜点11的中心点呈错位设置。如图3所示，例如第三层上的平衡铜点113和与第三层相邻的第四层上的平衡铜点114的中心点错位，且上述第三层上的平衡铜点113和第四层上的平衡铜点114存在部分重叠。由于每层工艺边10上的平衡铜点11的尺寸不一致，且当某层或某相邻两层的图形单元的残铜率较大时，为了满足残铜率与图形单元一致，拼板工艺边100上相应层的平衡铜点11的尺寸也较大，从而使得相邻层的平衡铜点11可能存在重叠现象，无法满足相邻层的平衡铜点11在其尺寸范围内完全错位；此时，只需满足相邻层的平衡铜点11的中心点错位设置，最大限度地提高拼板工艺边100的厚度均匀性。
进一步地，可将拼板工艺边100上奇数层上各平衡铜点11的中心点所在位置设为每层奇数层上的同一位置，拼板工艺边100上偶数层上各平衡铜点11的中心点所在位置设为每层偶数层上的同一位置，简化操作工艺，提高铺设平衡铜点11的效率。
进一步地，所述平衡铜点11有多个，且多个平衡铜点11均匀设置于工艺边10上，进一步提高拼板工艺边100的厚度均匀性。
进一步地，所述平衡铜点11为圆形、矩形、三角形或多边形。如图1至图3所示，本实施方式的平衡铜点11采用圆形，圆形平衡铜点11的半径范围为0-80之间连续可变，在其他实施方式中还可采用方形等简单且方便的图形作为 平衡铜点11的形状。
进一步地，至少内层工艺边10的边缘设有带流胶槽121的铜皮12。图4和图5所示，为减弱PCB板板边溢胶过大对介质层厚度的影响，在每层的工艺边10上除铺设有平衡铜点11外，在工艺边10的边缘即板边一定尺寸设计带有流胶槽121的铜皮12，避免板边溢胶过大的现象，进一步提升PCB板介质层厚度的均匀性。
进一步地，如图1所示，相邻层的流胶槽121呈错位设置。图1为相邻两层工艺边10层叠后的结构示意图，即图4和图5层叠后的结构示意图，从图中可看出，相邻层的平衡铜点11以及流胶槽121均错位设置，提高了拼板工艺边100的厚度均匀性。
如图6至图9所示，本实施方式还提供一种拼板方法，所述拼板包括拼板工艺边100以及置于拼板工艺边100内的至少一个图形单元200和测试条或测试模块300，所述拼板工艺边100为上述任一实施例所述的拼板工艺边100，所述拼板方法如下：
所述测试条或测试模块300置于图形单元200距拼板工艺边的板边余量较多的方向上，且拼板后图形单元200和测试条或测试模块300形成的拼板的边沿，距离拼板工艺边100的板边余量相等。如图6所示，保证D1＝D2,D3＝D4，进一步地，D1＝D2>0.75,D3＝D4>0.75英寸为最佳实施方案；如若不能满足，至少需保证同一方向上的图形单元200和测试条或测试模块300形成的拼板的边沿，距离拼板工艺边100的板边余量相等；即D1＝D2，D3＝D4。
进一步地，当所述图形单元200的数量为多个时，所述测试条或测试模块300置于图形单元200之间，且拼板后图形单元200和测试条或测试模块300形成的拼板的边沿，距离拼板工艺边100的板边余量相等；如图7所示，本实施方式以一拼二为例，所述测试条或测试模块300设于两图形单元200之间，且拼板后图形单元200和测试条或测试模块300形成的拼板的边沿，距离拼板工艺边100的板边余量相等；即保证D5＝D6，D7＝D8，进一步地，D5＝D6>0.75,D7＝D8>0.75英寸为最佳实施方案；如若不能满足，至少需保证同一 方向上的图形单元200和测试条或测试模块300形成的拼板的边沿，即图形单元200和测试条或测试模块300形成的拼板的左侧与右侧、上侧与下侧的边沿分别距离拼板工艺边100的板边余量相等；即D5＝D6，D7＝D8。
进一步地，如果测试条或测试模块300置于图形单元200之间后，导致相应的两侧距拼板工艺边100的板边余量较小，而另一方向的板边余量足够大时，调整测试条或测试模块300位置，将测试条或测试模块300置于余量较多方向上的图形单元200边缘或图形单元200之间，遵守中心紧凑、板边余量对称的原则。如图7和图8所示，本实施方式以一拼二为例，当按照图7的方法布置测试条或测试模块300的位置后，导致D5＝D6<0.50英寸，而D7＝D8又足够大时，需调整测试条或测试模块300的位置，改为图8所示的拼板形式，需保证D5＝D6，D7＝D8。另外，若改为图8所示的拼板形式，D5＝D6>0.50英寸，但D7＝D8<0.50英寸时，优先考虑上述四边距板边余量更加接近0.50英寸的拼板形式，或考虑更换拼板尺寸。
本实施方式的拼板方法遵守中心紧凑、板边余量对称的原则，提高测试条或测试模块300测试结果的准确性，有效代表图形单元200的相关真实值。如图9所示，当一拼三时，遵守中心紧凑、板边余量对称的原则，需保证拼板后图形单元200和测试条或测试模块300形成的拼板的边沿，距离拼板工艺边100的板边余量相等；即保证D9＝D10，D11＝D12，D13＝D14。
进一步地，所述测试条或测试模块300的数量可超过一个，即当至少两个测试条或测试模块300设于同一拼板内时，优选地，至少两个测试条或测试模块300并排放置。
进一步地，所述测试条或测试模块300与图形单元200之间间隔设置，且测试条或测试模块300与图形单元200的间距L1的范围为0.05英寸-0.1英寸之间。本实施方式中L1＝0.1英寸。另外，当相邻两图形单元200之间未设置测试条或测试模块300时，相邻两图形单元200也需间隔设置，且相邻两图形单元200之间的间距L2的范围为0.05英寸-0.1英寸之间。本实施方式中L2＝0.1英寸。
进一步地，本实施方式所采用的测试条或测试模块300为阻抗测试条或测试模块，本实施方式对PCB板的拼板方法进行优化，从而降低了测试条或测试模块与拼板内图形单元的差异，使测试条或测试模块的测试结果更能代表图形单元的真实值。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种拼板工艺边，设于电路板的图形单元的***，其特征在于，包括：至少两层层叠设置的工艺边，每层工艺边上设有平衡铜点，且每层工艺边的残铜率与相应层的图形单元的残铜率相同。
  2. 根据权利要求1所述的拼板工艺边，其特征在于，相邻层的平衡铜点呈错位设置。
  3. 根据权利要求1所述的拼板工艺边，其特征在于，所述平衡铜点为圆形、矩形、三角形或多边形。
  4. 根据权利要求1所述的拼板工艺边，其特征在于，同一层的平衡铜点或不同层的平衡铜点的中心距保持不变，和/或同一层的平衡铜点或不同层的平衡铜点的尺寸连续可变。
  5. 根据权利要求1-4任一项所述的拼板工艺边，其特征在于，至少内层工艺边的边缘设有带流胶槽的铜皮。
  6. 根据权利要求5所述的拼板工艺边，其特征在于，相邻层的流胶槽呈错位设置。
  7. 一种拼板方法，其特征在于，所述拼板包括拼板工艺边以及置于拼板工艺边内的至少一个图形单元和测试条或测试模块，所述拼板工艺边为权利要求1-6任一项所述的拼板工艺边，所述拼板方法为：所述测试条或测试模块置于图形单元距拼板工艺边的板边余量较多的方向上，且拼板后图形单元和测试条或测试模块形成的拼板的边沿，距离拼板工艺边的板边余量相等。
  8. 根据权利要求7所述的拼板方法，其特征在于，当所述图形单元的数量为多个时，所述测试条或测试模块置于图形单元之间。
  9. 根据权利要求7所述的拼板方法，其特征在于，所述当所述测试条或测试模块的数量为至少两个时，至少两个测试条或测试模块并排放置。
  10. 根据权利要求7-9任一项所述的拼板方法，其特征在于，拼板后图形单元和测试条或测试模块形成的拼板的边沿，距离拼板工艺边的板边余量不少于0.5英寸；和/或所述测试条或测试模块与图形单元之间间隔设置，且测试条 或测试模块与图形单元的间距范围为0.05英寸-0.1英寸之间。
PCT/CN2017/120095 2017-09-14 2017-12-29 拼板工艺边及拼板方法 WO2019052091A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710828881.X 2017-09-14
CN201710828881.XA CN107567182B (zh) 2017-09-14 2017-09-14 拼板工艺边及拼板方法

Publications (1)

Publication Number Publication Date
WO2019052091A1 true WO2019052091A1 (zh) 2019-03-21

Family

ID=60979980

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/120095 WO2019052091A1 (zh) 2017-09-14 2017-12-29 拼板工艺边及拼板方法

Country Status (2)

Country Link
CN (1) CN107567182B (zh)
WO (1) WO2019052091A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108322996A (zh) * 2018-03-07 2018-07-24 汕头超声印制板（二厂）有限公司 一种高拼板利用率的电路板及其制作方法
CN108650808B (zh) * 2018-04-16 2022-08-19 惠州市纬德电路有限公司 一种多层盲埋孔结构pcb板的生产工艺
CN109121302B (zh) * 2018-09-28 2020-03-06 广州兴森快捷电路科技有限公司 线路板的板边设计方法及线路板的设计方法
CN111491447B (zh) * 2019-01-29 2023-01-03 胜宏科技（惠州）股份有限公司 一种射频模块转接pcb板的制作方法
CN110519929A (zh) * 2019-08-26 2019-11-29 广州兴森快捷电路科技有限公司 线路板的板边图形设计方法及线路板
CN114980514A (zh) * 2022-05-19 2022-08-30 深圳崇达多层线路板有限公司 一种改善电路板板边压合空洞的方法、电路板及电子设备
CN117241505B (zh) * 2023-11-14 2024-04-05 圆周率半导体(南通)有限公司 一种提升多层有机基板c4-pad铜厚均匀性的方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0312996A (ja) * 1989-06-12 1991-01-21 Ibiden Co Ltd 多層プリント配線板
JPH05211392A (ja) * 1992-01-30 1993-08-20 Nec Corp 多層印刷配線板の製造方法
JPH0783179B2 (ja) * 1989-12-14 1995-09-06 日本電気株式会社 多層印刷配線板の製造方法
CN201491385U (zh) * 2009-08-19 2010-05-26 广东依顿电子科技股份有限公司 电路拼板
CN102711370A (zh) * 2012-06-08 2012-10-03 镇江华印电路板有限公司 防翘曲刚性印刷线路板
CN106231799A (zh) * 2016-08-09 2016-12-14 上海斐讯数据通信技术有限公司 一种pcb板及其制造方法
CN205946335U (zh) * 2016-08-17 2017-02-08 东莞市五株电子科技有限公司 高可靠性的pcb板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201509361U (zh) * 2009-09-22 2010-06-16 深圳崇达多层线路板有限公司 一种印刷线路板
JP2011171473A (ja) * 2010-02-18 2011-09-01 Fujikura Ltd プリント配線板
CN203722932U (zh) * 2014-01-26 2014-07-16 长沙牧泰莱电路技术有限公司 一种pcb工艺边
CN205305222U (zh) * 2016-01-13 2016-06-08 深圳市迅捷兴电路技术有限公司 阻抗布置结构
CN105916301A (zh) * 2016-04-06 2016-08-31 上海斐讯数据通信技术有限公司 一种pcb阻抗验证匹配方法及***

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0312996A (ja) * 1989-06-12 1991-01-21 Ibiden Co Ltd 多層プリント配線板
JPH0783179B2 (ja) * 1989-12-14 1995-09-06 日本電気株式会社 多層印刷配線板の製造方法
JPH05211392A (ja) * 1992-01-30 1993-08-20 Nec Corp 多層印刷配線板の製造方法
CN201491385U (zh) * 2009-08-19 2010-05-26 广东依顿电子科技股份有限公司 电路拼板
CN102711370A (zh) * 2012-06-08 2012-10-03 镇江华印电路板有限公司 防翘曲刚性印刷线路板
CN106231799A (zh) * 2016-08-09 2016-12-14 上海斐讯数据通信技术有限公司 一种pcb板及其制造方法
CN205946335U (zh) * 2016-08-17 2017-02-08 东莞市五株电子科技有限公司 高可靠性的pcb板

Also Published As

Publication number Publication date
CN107567182A (zh) 2018-01-09
CN107567182B (zh) 2020-04-14

Similar Documents

Publication Publication Date Title
WO2019052091A1 (zh) 拼板工艺边及拼板方法
CN102291949B (zh) 多层电路板制作方法
WO2015096667A1 (zh) 线路板的钻孔方法
CN101668389B (zh) 高对准度印制线路板的制作方法
CN104470265B (zh) 一种多层线路板的制作方法
CN102056414A (zh) 印刷电路板的制作方法
US20140208286A1 (en) System and method for designing via of printed circuit board
CN102711395B (zh) 多层印刷电路板的图形转移处理方法
CN108495486A (zh) 一种高速背板的制作方法及高速背板
CN108650790A (zh) 一种线路板镭射大孔的加工方法
CN110708873A (zh) 一种实现埋入式铜块定位的制作方法
CN203708620U (zh) 一种带有多重对位***的pcb板
WO2021068400A1 (zh) 一种超长多层板钻孔定位制作方法
CN105934091A (zh) 一种电路板拼板
CN110708893A (zh) 一种多层pcb板内层图形的制作方法
CN208128627U (zh) 一种便于裁切的多单元线路板
CN105916315A (zh) 一种hdi印刷电路板的制作方法
CN102036486B (zh) 一种假双面板制作方法
CN105307388A (zh) Fpc柔性线路板线路pin对位的操作方法
CN110708896B (zh) 一种hdi板的制作方法
CN206611633U (zh) 具有对位标靶的pcb板
US3369293A (en) Method of manufacturing etched circuitry
TWI386126B (zh) 覆銅基板裁切方法
CN110708894B (zh) 一种hdi板的制作方法
CN108633193B (zh) 多层电路板的制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17924832

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 14.09.2020)

122 Ep: pct application non-entry in european phase

Ref document number: 17924832

Country of ref document: EP

Kind code of ref document: A1