Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
  • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
  • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
  • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
  • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
  • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
  • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
  • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
  • H01L29/0623—Buried supplementary region, e.g. buried guard ring
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
  • H01L29/1608—Silicon carbide

Definitions

• the invention relates to a vertical power transistor with a
• Trench structure wherein diode junctions and / or heterojunction transitions between the trenches and at least one epitaxial layer form.
• the shielding of the gate oxide from high field strengths at high positive voltage between drain and source is problematic both in the blocking operation and in the case of short circuits. Furthermore, limiting the short-circuit current is difficult.
• the object of the invention is the performance of a vertical
• the vertical power transistor has at least one epitaxial layer comprising a first semiconductor material doped with first carriers and a plurality of trenches.
• the trenches extend from a surface of the epitaxial layer into the interior of the epitaxial layer.
• each trench has one
• the area that extends from a trench bottom to a certain height.
• the area is at least partially with a second
• Filled semiconductor material which is doped with second charge carriers.
• the region is electrically connected to a source region.
• the first charge carriers are different from the second charge carriers.
• the advantage here is that direct p / n transitions or n / p transitions are generated between each trench and the epitaxial layer, so that the MOS head is shielded from high field strengths in the case of blocking.
• the first semiconductor material has a larger bandgap than the second semiconductor material.
• hetero-junction transitions are formed which reduce the conduction losses in the Reduce reverse operation of the transistor as they reduce the forward voltage of the integrated freewheeling diode.
• the term reverse operation is understood to mean the operating mode of the transistor as freewheeling diode, ie the current flow of the transistor is inversely to the normal current flow direction. In other words, the reverse conductivity is increased.
• the heterojunction junctions can be placed directly below the MOS head without a further epitaxial layer. As a result, a good shielding of the MOS head can be produced with comparably low production costs.
• a layer comprising a third semiconductor material which is doped with the second charge carriers is arranged between a trench surface of the region, wherein the trench surface comprises the trench bottom and side walls of the respective trench, and the epitaxial layer.
• the layer forms a kind of well between the trench surface and the epitaxial layer.
• Semiconductor material and the first semiconductor material is located so that the transistor can be exposed to higher field strengths. As a result, higher reverse voltages can be applied to the transistor or at the same
• the layer below the trench bottom of the respective trench has a greater thickness than between the side walls of the respective trench and the epitaxial layer.
• the advantage here is that the MOS head can be shielded even more.
• the height of the region comprises ten to ninety percent of a depth of the respective trench.
• the first charge carriers are n-conducting and the second charge carriers are p-conducting.
• the vertical power transistor has lower conductivities due to a higher mobility of the electrons.
• the first semiconductor material SiC and the second semiconductor material comprises polycrystalline silicon.
• the third semiconductor material comprises SiC.
• the epitaxial layer is on a
• Semiconductor substrate arranged comprising SiC.
• the vertical power transistor is a MOSFET.
• Blocking resistance for example, compared to bipolar solutions such as IGBTs occur.
• FIG. 1 shows an example of a vertical power transistor
• FIG. 2 shows another example of the vertical power transistor
• FIG. 3 shows a method for producing the vertical power transistor according to FIG. 2 and
• FIG Figure 4 shows an alternative method for producing the vertical
• FIG. 1 shows an example of a vertical power transistor 100.
• the vertical power transistor 100 includes a semiconductor substrate 101 on the same
• Front side at least one epitaxial layer 103 is applied or arranged.
• the epitaxial layer 103 comprises a first semiconductor material which is doped with first charge carriers.
• the epitaxial layer 103 preferably comprises n-doped SiC.
• p-doped ions are implanted, for example of Al.
• a channel layer 104 which functions as a channel region, is formed in the upper region of the epitaxial layer 103.
• a p-doped epitaxial layer may be arranged on the epitaxial layer 103, which forms the channel region.
• the vertical power transistor 100 has a trench structure, i. H. a plurality or plurality of trenches. Each trench 107 has a region 108 that extends from the trench bottom to a certain height of the trench. This region 108 is completely filled with a second semiconductor material 109.
• the second semiconductor material 109 is completely filled with a second semiconductor material 109.
• Semiconductor material 109 is electrically conductively connected to at least one source region 105. Above the region 108 within the trench structure, a gate dielectric 110 and a gate electrode 111 are arranged. On each ditch 107, d. H. above the trench structure is a textured
• Insulation layer 112 is arranged, which electrically isolates the gate electrode 111 from the source region 105.
• a structured insulation layer 112 On the structured insulation layer 112 is a
• Metal layer 113 is arranged. On the back side of the semiconductor substrate 101, a drain metallization 114 is disposed.
• the trench structure has, for example, 0.5 ⁇ m to 10 ⁇ m deep trenches.
• the trenches 107 have the same depth except for manufacturing tolerances.
• the distances between the trenches 107 are substantially the same size and are in the range between 0.1 ⁇ and 10 ⁇ , the lower limit is process-related and the upper limit by otherwise poor shielding of the MOS complex is conditional.
• the area laterally between the areas 108 and the horizontal area between the areas 108, ie a part of the epitaxial layer 103, may have a different doping from the remaining part of the epitaxial layer 103. As a result, the conductivity between the regions 108 can be increased so that the current flows off faster.
• a further epitaxial layer can be arranged between the at least one epitaxial layer 103 and the MOS head or MOS complex.
• the first semiconductor material and the second semiconductor material are different.
• the second semiconductor material comprises
• the gate dielectric 110 comprises S1O2 and the gate electrode 111 poly-silicon.
• the semiconductor substrate 101 and the epitaxial layer 103 comprise GaN.
• FIG. 1 shows another example of the vertical power transistor 200.
• the vertical power transistor 200 comprises the structure of the vertical
• the vertical power transistor 200 has a layer 215 interposed between the
• the layer 215 comprises a third semiconductor material, which with second
• the third semiconductor material is in particular p-doped, for example by ion implantation.
• the effective dopant dose is usually more than 1 E13 cm A -3.
• the high effective dopant dose improves the shielding of the MOS head.
• the third semiconductor material includes, for example, SiC.
• the thickness of the layer 215 is in the range between 0.01 ⁇ and 4 ⁇ .
• the vertical power transistors 100 and 200 are preferably MOSFETs. However, they can also be designed or realized as HEMT.
• the vertical power transistors 100 and 200 are, for example, in
• Vehicle inverters photovoltaic inverters, traction drives or
• High voltage rectifiers can be used.
• FIG. 3 describes a method 300 for producing the vertical
• the method 300 starts with a step 310, in which at least one epitaxial layer is applied to a semiconductor substrate.
• the epitaxial layer has first charge carriers.
• a subsequent step 320 functional layers of the vertical
• Implantations source regions, p-channel regions and p + regions are generated.
• step 330 by dry etching a
• Post-treatment of the trench sidewalls for example a high temperature rounding or sacrificial oxidation to improve the surface.
• a subsequent step 350 by ion implantation, a layer is created between the trench surface comprising the trench bottom and portions of the sidewalls of the respective trench and the epitaxial layer.
• Trench bottom and the parts of the side walls of the respective trench are, for example, highly p-doped.
• each trench is filled up to a certain height with a second semiconductor material.
• the second semiconductor material comprises, for example, p-doped polycrystalline silicon.
• an insulating layer is arranged on the filled area of the respective trench, around the second
• Insulate semiconductor material from the MOS head In a following step 380, the MOS head, a patterned isolation layer, a metal layer, and the backside metallization are generated according to the prior art.
• FIG. 4 describes an alternative method 400 for producing the vertical power transistor according to FIG. 2.
• Steps 410 to 430, as well as 470 and 480 correspond to steps 310 to 330, and 370 and 380 from FIG. 3.
• a step 440 following step 430 becomes by means of ion implantation a Layer between the trench surface, which include the trench bottom and the entire side walls of the respective trench, and the
• each trench is filled up to the determined height with an etch mask or a hard mask, for example, of S1O2.
• each trench is widened by dry etching so that the layer created in step 440 on the sidewalls of the remaining unfilled trench is removed.
• the hard mask is removed.
• the after-treatment of the trench side walls for example a rounding by high temperature or a sacrificial oxidation to improve the surface.
• the trenches are filled to a certain height with a second semiconductor material, for example by means of deposition methods in combination with a dry etching step.
• the second semiconductor material is, for example, poly-Si.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Ceramic Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Junction Field-Effect Transistors (AREA)
• Electrodes Of Semiconductors (AREA)

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Citations (3)

• 2017
  • 2017-05-10 DE DE102017207848.0A patent/DE102017207848A1/de not_active Withdrawn
• 2018
  • 2018-02-09 WO PCT/EP2018/053282 patent/WO2018206165A1/de unknown
  • 2018-02-09 EP EP18708342.3A patent/EP3646387A1/de not_active Withdrawn
  • 2018-05-09 TW TW107115786A patent/TW201907564A/zh unknown

Patent Citations (3)

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