WO2017219658A1 - 移位寄存器、栅极驱动电路以及显示设备 - Google Patents

移位寄存器、栅极驱动电路以及显示设备 Download PDF

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Publication number
WO2017219658A1
WO2017219658A1 PCT/CN2017/070259 CN2017070259W WO2017219658A1 WO 2017219658 A1 WO2017219658 A1 WO 2017219658A1 CN 2017070259 W CN2017070259 W CN 2017070259W WO 2017219658 A1 WO2017219658 A1 WO 2017219658A1
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WIPO (PCT)
Prior art keywords
transistor
node
clock signal
shift register
unit
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PCT/CN2017/070259
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English (en)
French (fr)
Inventor
冯思林
李红敏
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/542,239 priority Critical patent/US10236073B2/en
Publication of WO2017219658A1 publication Critical patent/WO2017219658A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and more particularly to a shift register, a gate drive circuit, and a display device.
  • the gate drive circuit is an important factor affecting the size of the bezel of the display device.
  • Existing gate drive circuits typically include a plurality of cascaded shift registers, each shift register outputting a row of scan signals for driving the pixel switches.
  • such a gate drive circuit generally includes a relatively large number of shift registers, and accordingly, the total number of included switching devices and the total number of signal lines are also large, which is disadvantageous for narrowing the frame of the display device.
  • Embodiments of the present invention provide a shift register, a gate driving circuit including the shift register, and a display device including the same, to facilitate narrowing of a bezel of the display device.
  • the shift register includes: an input unit, the input unit is respectively connected to the input end and the first node, and the input unit controls the potential of the first node by an input signal of the input end; the first control unit, the first The control unit is respectively connected to the second node and the first reference voltage, and the first control unit is configured to output the first reference voltage to the second node;
  • a second control unit wherein the second control unit is respectively connected to the first node, the second node, and the second reference voltage, and is configured to control the second node based on the potential of the first node a voltage gating unit, wherein the voltage gating unit is respectively connected to the first reference voltage, the second reference voltage, the first node, the second node, and the output unit, and the voltage gating unit is based on the potential of the first node.
  • the output unit is further connected to the first clock signal input end, the second clock signal input end, the first output end and the second output end, respectively, the output unit respectively from the first output based on the first clock signal and the second clock signal
  • the second output terminal outputs the first pulse signal and the second pulse signal
  • the input unit may include a first transistor, a gate of the first transistor is configured to receive the input signal, a first end of the first transistor is coupled to the first node, and a second end of the first transistor is used to Receiving a third voltage signal.
  • the reset unit may include a second transistor, a gate of the second transistor is configured to receive the reset signal, a first end of the second transistor is configured to receive the fourth voltage signal, and a second end of the second transistor is coupled to The first node.
  • the voltage gating unit may include a third transistor connected to the first reference voltage, and a fourth transistor connected to the first node, the fourth transistor The gate is connected to the second node, the first end of the fourth transistor is connected to the second reference voltage, and the first end of the third transistor and the second end of the fourth transistor are connected to the output unit.
  • the energy storage unit can include a first capacitor having a first end coupled to the first node and a second end of the first capacitor coupled to the output of the voltage gating unit.
  • the first control unit can include a fifth transistor, the first end of the fifth transistor is coupled to the second node, and the second end of the fifth transistor and the gate are coupled to the first reference voltage.
  • the second control unit may include a sixth transistor and a second capacitor, the first ends of the second capacitor and the first end of the sixth transistor being connected to the second reference voltage, and the second end of the second capacitor and A second end of the sixth transistor is coupled to the second node, and a gate of the sixth transistor is coupled to the first node.
  • the second control unit may further include a seventh transistor, a gate of the seventh transistor is connected to the second node, and a first end of the seventh transistor is connected to the second reference voltage, A second end of the seventh transistor is coupled to the first node.
  • the output unit may include an eighth transistor connected to the first clock signal input terminal and a ninth transistor connected to the second clock signal input terminal, the eighth a first end of the transistor, a first end of the ninth transistor is coupled to an output of the voltage gating cell, and a second end of the eighth transistor and a second end of the ninth transistor are respectively configured to output the first pulse signal and the Second pulse signal.
  • a further embodiment of the present invention provides a gate drive circuit that can include a plurality of cascaded shift registers provided in accordance with any of the above embodiments.
  • the gate driving circuit may include a first clock signal line, a second clock signal line, and a third clock that respectively provide the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal.
  • the signal line and the fourth clock signal line, the phases of the pulse signals of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially different by 90 degrees, and the kth shift register in the gate driving circuit
  • the first clock signal input end and the second clock signal input end are respectively connected to the first clock signal line and the third clock signal line, the first clock signal input end and the second clock signal input of the k+1th shift register
  • the terminals are respectively connected to the second clock signal line and the fourth clock signal line, and k is an integer greater than or equal to 1.
  • the reset end of the kth shift register is coupled to the second output of the k+1th shift register, the first of the kth shift register An output is coupled to the input of the k+1th shift register, the input of the first shift register for receiving a vertical sync signal indicative of the beginning of a new one frame of image.
  • a further embodiment of the present invention also provides a display device that can include a gate drive circuit provided by any of the above-described embodiments of the present invention.
  • the shift register proposed by the embodiment of the present invention can provide two driving signals with fewer switching devices.
  • the shift register When the shift register is applied to the gate driving circuit of the display device, the total number of switching devices in the gate driving circuit and the total number of required signal lines can be reduced, the structure of the gate driving circuit is simplified, and the gate is saved.
  • the footprint of the pole drive circuit can make the frame of the display device narrower.
  • FIG. 1 is a block diagram showing the structure of a shift register according to an embodiment of the present invention
  • FIG. 2 shows a circuit diagram of a shift register provided in accordance with one embodiment of the present invention
  • FIG. 3 is a timing diagram showing operation of a shift register according to an embodiment of the present invention.
  • Figure 4 shows a circuit diagram of a conventional shift register
  • FIG. 5 is a block diagram showing the structure of a gate driving circuit according to another embodiment of the present invention.
  • first end and the second end of the transistor mentioned herein are used to distinguish the two ends of the transistor except the gate, and one end is referred to as a first end, and the other end is referred to as a second end.
  • the first end and the second end of the transistor are symmetrical, so the first end and the second end are interchangeable.
  • connection as used herein may be used to mean that the two elements are directly connected, or that the two elements are indirectly connected (ie, other elements may be present between the two elements).
  • FIG. 1 schematically shows a structural block diagram of a shift register according to an embodiment of the present invention.
  • a shift register according to an embodiment of the present invention includes: an input unit 10 connected to an input terminal input and a first node PU, respectively, and an input unit 10 controls a potential of the first node PU through an input signal of the input terminal input
  • the first control unit 20 is respectively connected to the second node PD and the first reference voltage GCH, and the first control unit 20 is configured to use the first reference
  • the voltage GCH is output to the second node PD;
  • the second control unit 30 is connected to the first node PU, the second node PD, and the second reference voltage VGL, respectively, for the potential based on the first node PU.
  • the pass unit 40 outputs a first reference voltage GCH to the output unit 50 based on the potential of the first node PU; an energy storage unit 70 that is respectively connected to the output of the voltage gating unit 40 and the first node PU; and a reset unit 60.
  • the reset unit 60 is respectively connected to the reset end reset and the first node PU, and the reset unit 60 controls the potential of the first node PU by the reset signal of the reset end reset.
  • the output unit 50 is further connected to the first clock signal input terminal CLKA, the second clock signal input terminal CLKB, the first output terminal Output_K and the second output terminal Output_K+2, and the output unit 50 is based on the first clock.
  • the signal and the second clock signal respectively output the first pulse signal and the second pulse signal from the first output terminal Output_K and the second output terminal Output_K+2.
  • the shift register proposed by the embodiment of the present invention can be used as a unit circuit in a gate drive circuit (GOA), which can simultaneously output two signals for driving the pixel switch.
  • GOA gate drive circuit
  • the number of shift registers in the gate drive circuit can be reduced, thereby reducing the overall number of switching devices in the gate drive circuit and the total number of signal lines required, simplifying the gate
  • the structure of the pole drive circuit saves the footprint of the gate drive circuit, thereby making the frame of the display device narrower.
  • the total number of switching devices is deliberately reduced, it is also advantageous to reduce the power consumption of the gate driving circuit, thereby reducing the power consumption of the display device.
  • FIG. 2 exemplarily shows a specific circuit configuration of a shift register proposed according to an embodiment of the present invention.
  • the various elements of the register are schematically shifted by dashed boxes in FIG.
  • the input unit 10 may include a first transistor M1 whose gate is for receiving an input signal, and a first end (eg, a source) of the first transistor M1 is connected to the first node PU, The second end (eg, the drain) of the first transistor M1 is for receiving the third voltage signal FW.
  • the third voltage signal may be a constant voltage having a high voltage level or a constant voltage having a low voltage level.
  • the high voltage level may also be referred to as a logic "1” and the low voltage level may also be referred to as a logic "0".
  • the first transistor M1 can control the first node PU based on the input signal of the input terminal input Potential.
  • the first transistor M1 may be an N-type thin film transistor (TFT), in which case it can receive an input signal of a high voltage level and be turned on such that the potential of the first node PU is equal to the voltage level of the third voltage signal FW.
  • TFT N-type thin film transistor
  • the reset unit may include a second transistor M2, the gate of the second transistor M2 is configured to receive a reset signal, and the first end of the second transistor M2 is configured to receive the fourth voltage signal BW.
  • the second end of the second transistor M2 is connected to the first node PU.
  • the gate of the second transistor M2 receives the reset signal and is turned on, the potential of the first node PU is equal to the voltage level of the fourth voltage signal BW.
  • the fourth voltage signal BW may also be a constant voltage signal, but its voltage level is different from the third voltage signal FW.
  • the fourth voltage signal BW is a low voltage level (logic "0") and vice versa.
  • the voltage levels of the third voltage signal FW and the fourth voltage signal BW may be set or changed.
  • the second reference voltage VGL may have a low voltage level
  • the first reference voltage GCH may have a high voltage level.
  • the voltage gating unit 40 includes a third transistor M3 and a fourth transistor M4.
  • the second terminal of the third transistor M3 is connected to the first reference voltage GCH, and the gate of the third transistor M3 is connected to the a node PU, the gate of the fourth transistor M4 is connected to the second node PD, the first end of the fourth transistor M4 is connected to the second reference voltage VGL, the first end of the third transistor M3 and the second end of the fourth transistor M4 The end is connected to the output unit 50.
  • the second end of the fourth transistor M4 and the first end of the third transistor M3 are interconnected to the node PU.
  • the energy storage unit may include a first capacitor C1, the first end of the first capacitor C1 is connected to the first node PU, and the second end of the first capacitor C1 is connected to the output of the voltage gating unit 40. .
  • the first control unit 20 may include a fifth transistor M5, the first end of which is connected to the second node PD, and the second end of the fifth transistor M5 and the gate are connected to the first reference voltage GCH.
  • the second control unit 30 may include a sixth transistor M6 and a second capacitor C2, the first end of the second capacitor C2 and the first end of the sixth transistor M6 being connected to the second reference voltage VGL, and the second end of the second capacitor C2 And the second end of the sixth transistor M6 is connected to the second node PD, and the gate of the sixth transistor M6 is connected to the first node PU. That is, the second capacitor C2 can be connected in parallel to the sixth transistor M6.
  • the second control unit 30 may further include a seventh transistor M7, The gate of the seventh transistor M7 is connected to the second node PD, the first end of the seventh transistor M7 is connected to the second reference voltage VGL, and the second end of the seventh transistor M7 is connected to the first node PU.
  • the output unit 50 may include an eighth transistor M8 having a gate connected to the first clock signal input terminal CLKA and a ninth transistor M9 having a gate connected to the second clock signal input terminal CLKB,
  • the first end of the eight transistor M8, the first end of the ninth transistor M9 is connected to the output of the voltage gating unit 40, and the second end of the eighth transistor M8 and the second end of the ninth transistor M9 are respectively used to output the first pulse Signal and second pulse signal.
  • the working process of the mobile register provided by the implementation of the present invention for the gate driving circuit to provide the scan signal will be specifically described below with reference to FIG. 2 and FIG. 3.
  • each transistor in the shift register may be an N-type thin film transistor.
  • each transistor in the shift register can also be other types of switching devices, such as P-type field effect transistors, N-type field effect transistors, P-type thin film transistors, etc., implementation of the present invention. This example does not limit this.
  • the transistor M1 is turned on, and at this time, the reset signal of the reset terminal Reset is kept at a low level.
  • the transistor M1 Since the transistor M1 is turned on, the potential of the first node PU becomes a high level, thereby charging the energy storage unit (first capacitor C1). The first end of the first capacitor C1 accumulates charges such that the third transistor M3 and the sixth transistor M6 are turned on. Since the third transistor M3 is turned on, the potential of the second terminal PU of the first capacitor C1 is equal to the first reference voltage GCH; since the sixth transistor M6 is turned on, the second capacitor C2 is discharged via the sixth transistor M6, the second The potential of the node PD is equal to the second reference voltage VGL.
  • the fourth transistor M4 and the seventh transistor M7 are both turned off. If the eighth transistor M8 Or the ninth transistor M9 receives the corresponding clock signal and is turned on, and the shift register can output the first pulse signal or the second pulse signal from the second ends of the eighth transistor M8 and the ninth transistor M9, respectively. When the input signal of the input terminal becomes a low level, the first transistor M1 is turned off. However, since the potential of the energy storage unit (first capacitor C1) remains, the first node PU can maintain a high voltage level, thereby causing the node PU to maintain a high voltage level.
  • the shift register can maintain the previous operating state. At this time, if the clock signal of the first clock signal input terminal CLKA or the second clock signal input terminal CLKB turns on the eighth transistor M8 or the ninth transistor M9, the continuation can be continued.
  • the first pulse signal or the second pulse signal is output.
  • the fourth transistor M4 and the seventh transistor M7 are turned on, and the voltage level of the output terminal of the voltage gating unit 40 (ie, the node PU between the third transistor M3 and the fourth transistor M4) is equal to the second reference voltage. VGL. Since the voltage level of the node PU is logic "0", at this time, the output unit 50 does not output the first pulse signal or the second pulse signal.
  • the operation of the shift register may include four periods of a, b, c, and d.
  • the four clock signals CLK1, CLK2, CLK3, and CLK4 in FIG. 3 are periodic clock signals generated by the clock signal generating circuit.
  • the clock signals CLK1, CLK3 may be respectively supplied to the gates of the eighth transistor M8 and the ninth transistor M9, or the eighth transistor M8 and the ninth transistor M9 may also receive the clock signals respectively.
  • the eighth transistor M8 is turned on by receiving the clock signal CLK1, the first pulse signal can be output from the first output terminal Output_K.
  • the ninth transistor M9 receives the clock signal CLK3 and is turned on, the second pulse signal can be output from the second output terminal Output_K+2.
  • the first capacitor C1 can maintain the potential of the first node PU at a high voltage level, thereby causing the shift register to remain in an operational state for a period of time.
  • the shift register causes the potential of the first node PU to become a low voltage level due to receiving a valid reset signal, and the shift register no longer outputs a valid scan signal at this time.
  • the shift register remains in the previous operating state and cannot provide a valid scan signal until a valid input signal is received again.
  • FIG. 4 shows a circuit diagram of a conventional shift register for a gate drive circuit.
  • the conventional shift register includes seven switching devices, but only one driving signal can be provided. If two drive signals are to be provided, at least 14 switching devices are required.
  • the shift register provided by the embodiment of the present invention can provide two driving signals only by 9 switching devices. Therefore, the circuit structure and wiring are simplified, which is advantageous for the display device to realize a narrow bezel.
  • Another embodiment of the present invention provides a gate drive circuit that can include a plurality of cascaded shift registers as described in any of the preceding embodiments. As described above, since each shift register can output two driving signals with fewer switching devices, the total number of switching devices included in the gate driver is reduced, and the footprint of the gate driver is reduced, further promoting The border of the display device is narrowed.
  • FIG. 5 is a block diagram showing the structure of a gate driving circuit according to an embodiment of the present invention.
  • the gate driving circuit may include a first clock signal line and a second clock signal line respectively providing the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4.
  • the third clock signal line and the fourth clock signal line, the phases of the pulse signals of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 are sequentially different by 90 degrees, and the gate driving circuit
  • the first clock signal input terminal CLKA and the second clock signal input terminal CLKB of the kth shift register may be respectively connected to the first clock signal line and the third clock signal line, and the k+1th shift register
  • a clock signal input terminal CLKA and a second clock signal input terminal CLKB may be respectively connected to the second clock signal line and the fourth clock signal line, and k is an integer greater than or equal to 1.
  • the phases of the pulse signals of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 are sequentially different by 90 degrees. Therefore, the four clock signals CLK1-CLK4 are in time.
  • a high-level pulse signal appears successively, that is, the pulse signals of the first clock signals CLK1 and CLK3 are in phase
  • the difference may be 180 degrees
  • the pulse signals of the second clock signals CLK2 and CLK4 may be 180 degrees out of phase.
  • each shift register may receive the first clock signal CLK1 and the third clock signal CLK3, or the second clock signal CLK2 and the fourth clock signal CLK4, respectively, such that The eighth transistor and the ninth transistor in the output unit of the bit register provide dead time, ensuring that the eighth transistor and the ninth transistor are not turned on at the same time, so that the gate driving circuit provides the driving signal in a row-by-row manner, that is, Line scan.
  • the reset end of the kth shift register may be connected to the second output of the k+1th shift register, the first of the kth shift register
  • An output terminal is connectable to an input of the k+1th shift register
  • an input of the first shift register is for receiving a vertical sync signal STV indicating the start of a new one frame image.
  • the reset end of the previous shift register can be connected to the next shift adjacent thereto a second output of the bit register, the first output of the previous shift register being connectable to an input of a subsequent shift register adjacent thereto, the input of the first shift register being capable of receiving an indication of a new one frame image
  • the first shift register can provide gate drive signals for the first row and the third row of pixels
  • the second shift register can provide gate drive for the second row and the fourth row of pixels.
  • the kth shift register can provide gate drive signals for the kth row and the k+2th row of pixels. In this manner, drive signals can be sequentially provided for each row of pixels to implement progressive scan driving of the pixel switches.
  • the display device can include a gate drive circuit as provided in any of the preceding embodiments.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the invention.

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Abstract

一种移位寄存器、栅极驱动电路以及显示设备。该移位寄存器包括输入单元（10）、第一控制单元（20）、第二控制单元（30）、电压选通单元（40）、输出单元（50）、储能单元（70）以及复位单元（60）。该移位寄存器可以较少的开关器件输出双路驱动信号，当其应用于栅极驱动电路时，可以减少栅极驱动电路所包括的开关器件的总数目并简化布线，降低栅极驱动电路的占用面积，有利于显示设备的边框窄化。

Description

移位寄存器、栅极驱动电路以及显示设备
相关申请的交叉引用
本申请要求于2016年6月23日向中国专利局提交的专利申请201610454724.2的优先权利益，并且在此通过引用的方式将该在先申请的内容并入本文。
技术领域
本发明涉及显示技术领域，更具体地，涉及一种移位寄存器、栅极驱动电路和显示设备。
背景技术
随着技术的发展，为了满足人们对诸如LCD的各类显示设备的审美和使用方面的要求，对这些显示设备的边框进行窄化设计已经成为一种潮流。对于诸如LCD之类的显示设备而言，栅极驱动电路(GOA)是影响显示设备的边框的大小的重要因素。现有的栅极驱动电路通常包括多个级联的移位寄存器，每个移位寄存器输出一行用于驱动像素开关的扫描信号。然而，这样的栅极驱动电路一般包括较大数量的移位寄存器，相应地，所包括的开关器件的总数目以及信号线的总数目也较大，不利于显示设备的边框的窄化。
发明内容
本发明的实施例提供一种移位寄存器、包括该移位寄存器的栅极驱动电路以及包括该栅极驱动电路的显示设备，以促进显示设备的边框的窄化。
本发明的一个实施例提供了一种移位寄存器。该移位寄存器包括：输入单元，所述输入单元分别与输入端和第一节点连接，所述输入单元通过所述输入端的输入信号控制第一节点的电位；第一控制单元，所述第一控制单元分别与第二节点和第一参考电压连接，所述第一控制单元用于将第一参考电压输出至第二节点；
第二控制单元，所述第二控制单元分别与第一节点、第二节点、以及第二参考电压连接，用于基于第一节点的电位而控制第二节点的 电位；电压选通单元，所述电压选通单元分别与第一参考电压、第二参考电压、第一节点、第二节点和输出单元连接，所述电压选通单元基于第一节点的电位而向所述输出单元输出所述第一参考电压；储能单元，所述储能单元分别与电压选通单元的输出和第一节点连接；以及复位单元，所述复位单元分别与复位端和第一节点连接，所述复位单元通过复位端的复位信号而控制第一节点的电位。输出单元还分别与第一时钟信号输入端、第二时钟信号输入端、第一输出端和第二输出端连接，所述输出单元基于第一时钟信号和第二时钟信号而分别从第一输出端和第二输出端输出第一脉冲信号以及第二脉冲信号，
在一些实施例中，输入单元可包括第一晶体管，第一晶体管的栅极用于接收所述输入信号，第一晶体管的第一端连接至第一节点，第一晶体管的第二端用于接收第三电压信号。
在一些实施例中，复位单元可包括第二晶体管，第二晶体管的栅极用于接收复位信号，第二晶体管的第一端用于接收第四电压信号，第二晶体管的第二端连接至第一节点。
在一些实施例中，电压选通单元可包括第三晶体管和第四晶体管，第三晶体管的第二端连接至第一参考电压，第三晶体管的栅极连接至第一节点，第四晶体管的栅极连接至第二节点，第四晶体管的第一端连接至第二参考电压，第三晶体管的第一端和第四晶体管的第二端连接至所述输出单元。
在一些实施例中，储能单元可包括第一电容器，所述第一电容器的第一端连接至第一节点，所述第一电容器的第二端连接至电压选通单元的输出。
在一些实施例中，第一控制单元可包括第五晶体管，第五晶体管的第一端连接至第二节点，第五晶体管的第二端和栅极连接至第一参考电压。
在一些实施例中，第二控制单元可包括第六晶体管以及第二电容器，第二电容器的第一端以及第六晶体管的第一端连接至第二参考电压，第二电容器的第二端以及第六晶体管的第二端连接至第二节点，第六晶体管的栅极连接至第一节点。
在一些实施例中，第二控制单元还可包括第七晶体管，第七晶体管的栅极连接至第二节点，第七晶体管的第一端连接至第二参考电压， 第七晶体管的第二端连接至第一节点。
在一些实施例中，输出单元可包括第八晶体管和第九晶体管，第八晶体管的栅极连接至第一时钟信号输入端，第九晶体管的栅极连接至第二时钟信号输入端，第八晶体管的第一端、第九晶体管的第一端连接至电压选通单元的输出，第八晶体管的第二端和第九晶体管的第二端分别用于输出所述第一脉冲信号和所述第二脉冲信号。
本发明的另外的实施例提供了一种栅极驱动电路，该栅极驱动电路可包括多个级联的根据以上实施例中的任一实施例提供的移位寄存器。
在一些实施例中，该栅极驱动电路可包括分别提供第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的第一时钟信号线、第二时钟信号线、第三时钟信号线和第四时钟信号线，第一时钟信号、第二时钟信号、第三时钟信号以及第四时钟信号的脉冲信号的相位依次相差90度，栅极驱动电路中的第k个移位寄存器的第一时钟信号输入端和第二时钟信号输入端分别连接至第一时钟信号线、第三时钟信号线，第k+1个移位寄存器的第一时钟信号输入端和第二时钟信号输入端分别连接至第二时钟信号线和第四时钟信号线，k为大于等于1的整数。
在一些实施例中，在级联的多个移位寄存器中，第k个移位寄存器的复位端连接至第k+1个移位寄存器的第二输出端，第k个移位寄存器的第一输出端连接至第k+1个移位寄存器的输入端，第一移位寄存器的输入端用于接收指示新的一帧图像的开始的垂直同步信号。
本发明的另外的实施例还提供了一种显示设备，该显示设备可包括本发明的上述实施例中的任一实施例提供的栅极驱动电路。
本发明实施例提出的移位寄存器能够以较少的开关器件而实现提供两路驱动信号。当该移位寄存器应用于显示设备的栅极驱动电路时,可以减小栅极驱动电路中的开关器件的总体数量以及所需的信号线的总体数量，简化栅极驱动电路的结构，节省栅极驱动电路的占用面积，从而可以使得显示设备的边框变得更窄。
附图说明
下面，参考附图更详细地并且通过非限制性的示例方式描述本发 明的实施例，以提供对本发明的原理和精神的透彻理解。
图1示出了根据本发明的一个实施例提供的移位寄存器的结构框图；
图2示出了根据本发明的一个实施例提供的移位寄存器的电路图；
图3示出了根据本发明的实施例提供的移位寄存器工作时的时序图；
图4示出了一种常规的移位寄存器的电路图；
图5示意性地示出了本发明的另一实施例提供的栅极驱动电路的结构框图。
具体实施方式
下面，通过示例的方式来详细说明本发明的具体实施例。应当理解的是，本发明的实施例不局限于以下所列举的示例，本领域技术人员利用本发明的原理或精神可以对所描述的各实施例进行修改和变型，得到形式不同的其它实施例，显然，这些实施例都落入本发明要求保护的范围。
此外，需要说明的是，本文所参考的附图是为了说明和解释本发明的实施例的需要，附图所体现的每个单元并不一定与实际的电路结构完全相同，不同单元之间的连接仅仅用于示意性地说明本发明的实施例，这些都不构成对本发明的保护范围的限制。在不冲突的情况下，本发明的各实施例中的技术特征可以相互组合。
另外，本文提到的晶体管的第一端和第二端是用于区分晶体管除栅极之外的两端，将其中一端称为第一端，另一端称为第二端。晶体管的第一端和第二端是对称的，所以第一端、第二端是可以互换的。还应理解的是，本文提到的“连接”可用于表示两个元件直接连接，或者，也可表示这两个元件间接连接(即，这两个元件之间可能存在其它元件)。
图1示意性地示出了根据本发明的实施例的移位寄存器的结构框图。如图1所示，根据本发明实施例的移位寄存器包括：输入单元10，分别与输入端input和第一节点PU连接，输入单元10通过输入端input的输入信号控制第一节点PU的电位；第一控制单元20，分别与第二节点PD和第一参考电压GCH连接，第一控制单元20用于将第一参考 电压GCH输出至第二节点PD；第二控制单元30，第二控制单元30分别与第一节点PU、第二节点PD、以及第二参考电压VGL连接，用于基于第一节点PU的电位而控制第二节点PD的电位；电压选通单元40，电压选通单元40分别与第一参考电压GCH、第二参考电压VGL、第一节点PU、第二节点PD和输出单元50连接，电压选通单元40基于第一节点PU的电位而向输出单元50输出第一参考电压GCH；储能单元70，储能单元70分别与电压选通单元40的输出和第一节点PU连接；以及复位单元60，复位单元60分别与复位端reset和第一节点PU连接，复位单元60通过复位端reset的复位信号而控制第一节点PU的电位。在该实施例中，输出单元50还分别与第一时钟信号输入端CLKA、第二时钟信号输入端CLKB、第一输出端Output_K和第二输出端连接Output_K+2，输出单元50基于第一时钟信号和第二时钟信号而分别从第一输出端Output_K和第二输出端Output_K+2输出第一脉冲信号以及第二脉冲信号。
本发明实施例提出的移位寄存器可用作栅极驱动电路(GOA)中的一个单元电路,其可以同时输出两路用于驱动像素开关的信号。因而，对于同一显示设备，可以减小其中的栅极驱动电路中的移位寄存器的数量，进而减小栅极驱动电路中的开关器件的总体数量以及所需的信号线的总体数量，简化栅极驱动电路的结构，节省栅极驱动电路的占用面积，从而可以使得显示设备的边框变得更窄。同时，由于开关器件的总体数目得意减小，所以还有利于降低栅极驱动电路的功耗，进而降低显示设备的功耗。
图2示例性地示出了根据本发明实施例提出的移位寄存器的具体电路结构。为了便于对照图1来理解图2的实施例，图2中用虚线框示意性地移位寄存器的各个单元。
如图2所示，输入单元10可包括第一晶体管M1，第一晶体管M1的栅极用于接收输入信号，第一晶体管M1的第一端(例如，源极)连接至第一节点PU，第一晶体管M1的第二端(例如，漏极)用于接收第三电压信号FW。在该实施例中，第三电压信号可以是具有高电压水平的恒定电压，也可以是具有低电压水平的恒定电压。在本文中，高电压水平也可以被称为逻辑“1”，低电压水平也可以被称为逻辑“0”。第一晶体管M1可以基于输入端input的输入信号而控制第一节点PU 的电位。例如，第一晶体管M1可以是N型薄膜晶体管(TFT)，此时，其可以接收高电压水平的输入信号而导通，使得第一节点PU的电位等于第三电压信号FW的电压水平。
在一个实施例中，如图2所示，复位单元可包括第二晶体管M2，第二晶体管M2的栅极用于接收复位信号，第二晶体管M2的第一端用于接收第四电压信号BW，第二晶体管M2的第二端连接至第一节点PU。当第二晶体管M2的栅极接收到复位信号而导通时，第一节点PU的电位等于第四电压信号BW的电压水平。在本发明的实施例中，第四电压信号BW也可以是恒定的电压信号，但是其电压水平与第三电压信号FW不同。例如，如果第三电压信号FW是高电压水平(逻辑“1”)，则第四电压信号BW是低电压水平(逻辑“0”)，反之亦然。第三电压信号FW和第四电压信号BW的电压水平可以被设定或改变。在本发明的实施例中，第二参考电压VGL可以具有低电压水平，第一参考电压GCH可以具有高电压水平。
在本发明的实施例中，电压选通单元40包括第三晶体管M3和第四晶体管M4，第三晶体管M3的第二端连接至第一参考电压GCH，第三晶体管M3的栅极连接至第一节点PU，第四晶体管M4的栅极连接至第二节点PD，第四晶体管M4的第一端连接至第二参考电压VGL，第三晶体管M3的第一端和第四晶体管M4的第二端连接至输出单元50。如图2所示，在该实施例中，第四晶体管M4的第二端和第三晶体管M3的第一端互连于节点PU,。
在本发明的实施例中，储能单元可包括第一电容器C1，第一电容器C1的第一端连接至第一节点PU，第一电容器C1的第二端连接至电压选通单元40的输出。
第一控制单元20可包括第五晶体管M5，第五晶体管M5的第一端连接至第二节点PD，第五晶体管M5的第二端和栅极连接至第一参考电压GCH。第二控制单元30可包括第六晶体管M6以及第二电容器C2，第二电容器C2的第一端以及第六晶体管M6的第一端连接至第二参考电压VGL，第二电容器C2的第二端以及第六晶体管M6的第二端连接至第二节点PD，第六晶体管M6的栅极连接至第一节点PU。也就是说，第二电容器C2可以并联连接至第六晶体管M6。
在本发明的实施例中，第二控制单元30还可包括第七晶体管M7， 第七晶体管M7的栅极连接至第二节点PD，第七晶体管M7的第一端连接至第二参考电压VGL，第七晶体管M7的第二端连接至第一节点PU。
输出单元50可包括第八晶体管M8和第九晶体管M9，第八晶体管M8的栅极连接至第一时钟信号输入端CLKA，第九晶体管M9的栅极连接至第二时钟信号输入端CLKB，第八晶体管M8的第一端、第九晶体管M9的第一端连接至电压选通单元40的输出，第八晶体管M8的第二端和第九晶体管M9的第二端分别用于输出第一脉冲信号和第二脉冲信号。
图2所示的实施例提供的移位寄存器可用作栅极驱动电路中的单元电路，即多个这样的级联的移位寄存器可形成栅极驱动电路，每个移位寄存器输出的第一脉冲信号和第二脉冲信号可以用作两行像素的扫描信号。此外，通过设置第三电压信号FW和第四电压信号BW的电压水平，可以实现不同的扫描方式。例如，通过使得FW＝1、BW＝0可以实现正向扫描，通过使得FW＝0、BW＝1可以实现反向扫描。下面结合图2和图3来具体说明本发明实施提供的移动寄存器用于栅极驱动电路而提供扫描信号的工作过程。
如图2所示，该移位寄存器中的各个晶体管可以为N型薄膜晶体管。当然，在其它的实施例中，移位寄存器中的各个晶体管也可以为其它类型的开关器件，例如，P型场效应晶体管，N型场效应晶体管，P型薄膜晶体管等等，本发明的实施例对此不作限定。下面，以晶体管M1-M9为N型薄膜晶体管、且扫描方式为正向扫描(FW＝1,BW＝0)为例来说明移位寄存器的工作过程。当提供给输入单元10的输入信号变为高电平时，晶体管M1导通，此时，复位端Reset的复位信号保持低电平。由于晶体管M1导通，所以第一节点PU的电位变为高电平，从而对储能单元(第一电容器C1)充电。第一电容器C1的第一端积累电荷，使得第三晶体管M3和第六晶体管M6导通。由于第三晶体管M3导通，所以第一电容器C1的第二端PU,的电位等于第一参考电压GCH；由于第六晶体管M6导通，使得第二电容器C2经由第六晶体管M6放电，第二节点PD的电位等于第二参考电压VGL。即，可以认为此时第二节点PD的电位为逻辑“0”，节点PU,的电位为逻辑“1”，因此，第四晶体管M4和第七晶体管M7均关断。如果第八晶体管M8 或第九晶体管M9接收到相应的时钟信号而导通，则移位寄存器可分别从第八晶体管M8和第九晶体管M9的第二端输出第一脉冲信号或第二脉冲信号。当输入端Input的输入信号变为低电平时，第一晶体管M1将关断。但是，由于储能单元(第一电容器C1)的电位保持作用，第一节点PU可保持高电压水平，从而使得节点PU,保持高电压水平。因此，移位寄存器可保持之前的工作状态，此时，如果第一时钟信号输入端CLKA或第二时钟信号输入端CLKB的时钟信号使得第八晶体管M8或第九晶体管M9导通，则可继续输出第一脉冲信号或第二脉冲信号。当移位寄存器从复位端Reset接收到有效的复位信号(即，Reset＝1)时，第二晶体管M2导通，使得第一节点PU的电位等于第四电压信号BW，即节点PU的电位为逻辑“0”。因此，第三晶体管M3和第六晶体管M6断开，第二节点PD的电位变为高电压水平，即PD的电位为逻辑“1”。这样，导致第四晶体管M4和第七晶体管M7导通，电压选通单元40的输出端(即，第三晶体管M3和第四晶体管M4之间的节点PU,)的电压水平等于第二参考电压VGL。由于节点PU,的电压水平为逻辑“0”，所以，此时，输出单元50不输出第一脉冲信号或第二脉冲信号。当复位信号失效(Reset＝0)时，由于第五晶体管M5保持导通，因此，第二节点PD的电位为高电压水平，这样，使得第七晶体管M7和第四晶体管M4导通，从而使得第一节点PU和节点PU,的电位为低电压水平，即，PU＝PU,＝0。此时，移位寄存器仍不输出第一脉冲信号或第二脉冲信号。
如图3所示，移位寄存器的工作过程可包括a、b、c和d四个时段。图3中的四个时钟信号CLK1、CLK2、CLK3和CLK4是由时钟信号生成电路产生的周期性时钟信号。当移位寄存器用于提供扫描信号时，时钟信号CLK1、CLK3可以分别提供给第八晶体管M8、第九晶体管M9的栅极，或者，第八晶体管M8和第九晶体管M9也可以分别接收时钟信号CLK2、CLK4。在a时段的起始，移位寄存器接收到有效的输入信号(Input＝1)，使得第一节点PU的电位变化至高电压水平，即PU＝1，从而使得PU,＝1。当第八晶体管M8接收到时钟信号CLK1而导通时，可以从第一输出端Output_K输出第一脉冲信号。当第九晶体管M9接收到时钟信号CLK3而导通时，可以从第二输出端Output_K+2输出第二脉冲信号。在b时段期间，虽然输入信号变为低 电压水平，但是，第一电容器C1可保持第一节点PU的电位处于高电压水平，从而使得移位寄存器保持a时段的工作状态。在时段c的起始，移位寄存器由于接收到有效的复位信号而使得第一节点PU的电位变为低电压水平，移位寄存器此时不再输出有效的扫描信号。在时段d期间，尽管有效的复位信号缺失，移位寄存器仍保持之前的工作状态，不能提供有效的扫描信号，直到再次接收到有效的输入信号。
因此，本发明的实施例以较少的电子器件实现了让一个移位寄存器同时提供两路驱动信号。图4示出了用于栅极驱动电路的常规的移位寄存器的电路图。如图4所示，常规的移位寄存器包括7个开关器件，但只能提供一路驱动信号。如果要提供两路驱动信号，则至少需要14个开关器件。如图2所示，本发明实施例提供的移位寄存器只需9个开关器件即能提供两路驱动信号。因此，电路结构和布线得到简化，有利于显示设备实现窄边框。
本发明的另一实施例提供了一种栅极驱动电路，该栅极驱动电路可包括多个级联的前述实施例中的任一实施例所描述的移位寄存器。如前所述，由于每个移位寄存器能够以较少的开关器件输出两路驱动信号，所以栅极驱动器所包括的开关器件的总数目得以减少，栅极驱动器的占用面积得以降低，进一步促进显示设备的边框窄化。
图5示意性地示出了本发明实施例提供的栅极驱动电路的结构框图。如图5所示，该栅极驱动电路可包括分别提供第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3和第四时钟信号CLK4的第一时钟信号线、第二时钟信号线、第三时钟信号线和第四时钟信号线，第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3以及第四时钟信号CLK4的脉冲信号的相位依次相差90度，栅极驱动电路中的第k个移位寄存器的第一时钟信号输入端CLKA和第二时钟信号输入端CLKB可分别连接至第一时钟信号线、第三时钟信号线，第k+1个移位寄存器的第一时钟信号输入端CLKA和第二时钟信号输入端CLKB可分别连接至第二时钟信号线和第四时钟信号线，k为大于等于1的整数。再次参照图3，第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3以及第四时钟信号CLK4的脉冲信号的相位依次相差90度，因此，四个时钟信号CLK1-CLK4在时间上相继出现高电平的脉冲信号，即，第一时钟信号CLK1和CLK3的脉冲信号在相位 上可以相差180度，第二时钟信号CLK2和CLK4的脉冲信号在相位上可以相差180度。在图5所示的实施例中，每个移位寄存器可分别接收第一时钟信号CLK1和第三时钟信号CLK3，或者第二时钟信号CLK2和第四时钟信号CLK4，这样，可以为每个移位寄存器的输出单元中的第八晶体管和第九晶体管提供死区时间，确保第八晶体管和第九晶体管不会同时导通，让栅极驱动电路以逐行的方式提供驱动信号，即实现逐行扫描。如图5所示，栅极驱动电路中的每个移位寄存器还可接收第三电压信号FW和第四电压信号BW，可以通过调整第三电压信号FW和第四电压信号BW的电压水平而实现以不同的方式提供驱动信号。在本发明的一个实施例中，当FW＝1,BW＝0时，以正向扫描方式提供驱动信号，当FW＝0,BW＝1时，以反向扫描方式提供驱动信号。
再次参照图5，在级联的多个移位寄存器中，第k个移位寄存器的复位端可连接至第k+1个移位寄存器的第二输出端，第k个移位寄存器的第一输出端可连接至第k+1个移位寄存器的输入端，第一移位寄存器的输入端用于接收指示新的一帧图像的开始的垂直同步信号STV。换句话说，在图5的实施例中，对于级联的多个移位寄存器中的两个相邻的移位寄存器，前一个移位寄存器的复位端可连接至与其相邻的后一个移位寄存器的第二输出端，前一个移位寄存器的第一输出端可连接至与其相邻的后一个移位寄存器的输入端，第一移位寄存器的输入端可接收指示新的一帧图像的开始的垂直同步信号STV。如图5所示，第一移位寄存器可提供用于第一行和第三行像素的栅极驱动信号，第二移位寄存器可提供用于第二行和第四行像素的栅极驱动信号，第k个移位寄存器可提供用于第k行和第k+2行像素的栅极驱动信号以此方式，可以为各行像素相继提供驱动信号，实现对像素开关的逐行扫描驱动。
本发明的另一实施例提供了一种显示设备，该显示设备可包括如前述实施例中任一实施例提供的栅极驱动电路。该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
以上已经参照附图详细描述了本发明的实施例，但是，应该注意的是，上述实施例用来举例说明而不是限制本发明，并且本领域技术人员将能够设计许多替代性实施例而并未脱离所附权利要求的范围。在权利要求中，词语“包括”并未排除除了权利要求中所列举的那些之外的元件或步骤的存在。元件之前的词语“一”或“一个”并未排除多个这样的元件的存在。某些特征被记载在相互不同从属权利要求中这一纯粹事实并不意味着这些特征的组合不能被有利地使用。

Claims (13)

  1. 一种移位寄存器，包括：
    输入单元，所述输入单元分别与输入端和第一节点(PU)连接，所述输入单元通过所述输入端的输入信号控制第一节点(PU)的电位；
    第一控制单元，所述第一控制单元分别与第二节点(PD)和第一参考电压(GCH)连接，所述第一控制单元用于将第一参考电压输出至第二节点(PD)；
    第二控制单元，所述第二控制单元分别与第一节点(PU)、第二节点(PD)、以及第二参考电压(VGL)连接，用于基于第一节点(PU)的电位而控制第二节点(PD)的电位；
    电压选通单元，所述电压选通单元分别与第一参考电压(GCH)、第二参考电压(VGL)、第一节点(PU)、第二节点(PD)和输出单元连接，所述电压选通单元基于第一节点(PU)的电位而向所述输出单元输出所述第一参考电压；
    储能单元，所述储能单元分别与电压选通单元的输出和第一节点(PU)连接；以及
    复位单元，所述复位单元分别与复位端和第一节点(PU)连接，所述复位单元通过复位端的复位信号而控制第一节点(PU)的电位，
    其中所述输出单元还分别与第一时钟信号输入端、第二时钟信号输入端、第一输出端和第二输出端连接，所述输出单元基于第一时钟信号和第二时钟信号而分别从第一输出端和第二输出端输出第一脉冲信号以及第二脉冲信号。
  2. 如权利要求1所述的移位寄存器，其中所述输入单元包括第一晶体管，第一晶体管的栅极用于接收所述输入信号，第一晶体管的第一端连接至第一节点，第一晶体管的第二端用于接收第三电压信号。
  3. 如权利要求1所述的移位寄存器，其中所述复位单元包括第二晶体管，第二晶体管的栅极用于接收复位信号，第二晶体管的第一端用于接收第四电压信号，第二晶体管的第二端连接至第一节点。
  4. 如权利要求1所述的移位寄存器，其中所述电压选通单元包括第三晶体管和第四晶体管，第三晶体管的第二端连接至第一参考电压，第三晶体管的栅极连接至第一节点，第四晶体管的栅极连接至第二节 点，第四晶体管的第一端连接至第二参考电压，第三晶体管的第一端和第四晶体管的第二端连接至所述输出单元。
  5. 如权利要求1所述的移位寄存器，其中所述储能单元包括第一电容器，所述第一电容器的第一端连接至第一节点，所述第一电容器的第二端连接至电压选通单元的输出。
  6. 如权利要求1所述的移位寄存器，其中第一控制单元包括第五晶体管，第五晶体管的第一端连接至第二节点，第五晶体管的第二端和栅极连接至第一参考电压。
  7. 如权利要求1所述的移位寄存器，其中所述第二控制单元包括第六晶体管以及第二电容器，第二电容器的第一端以及第六晶体管的第一端连接至第二参考电压，第二电容器的第二端以及第六晶体管的第二端连接至第二节点，第六晶体管的栅极连接至第一节点。
  8. 如权利要求7所述的移位寄存器，其中所述第二控制单元还包括第七晶体管，第七晶体管的栅极连接至第二节点，第七晶体管的第一端连接至第二参考电压，第七晶体管的第二端连接至第一节点。
  9. 如权利要求1所述的移位寄存器，其中输出单元包括第八晶体管和第九晶体管，第八晶体管的栅极连接至第一时钟信号输入端，第九晶体管的栅极连接至第二时钟信号输入端，第八晶体管的第一端、第九晶体管的第一端连接至电压选通单元的输出，第八晶体管的第二端和第九晶体管的第二端分别用于输出所述第一脉冲信号和所述第二脉冲信号。
  10. 一种栅极驱动电路，包括多个级联的根据权利要求1-9中任一项所述的移位寄存器。
  11. 如权利要求10所述的栅极驱动电路，其中该栅极驱动电路包括分别提供第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的第一时钟信号线、第二时钟信号线、第三时钟信号线和第四时钟信号线，第一时钟信号、第二时钟信号、第三时钟信号以及第四时钟信号的脉冲信号的相位依次相差90度，栅极驱动电路中的第k个移位寄存器的第一时钟信号输入端和第二时钟信号输入端分别连接至第一时钟信号线、第三时钟信号线，第k+1个移位寄存器的第一时钟信号输入端和第二时钟信号输入端分别连接至第二时钟信号线和第四时钟信号线，k为大于等于1的整数。
  12. 如权利要求11所述的栅极驱动电路，其中在级联的多个移位寄存器中，第k个移位寄存器的复位端连接至第k+1个移位寄存器的第二输出端，
    第k个移位寄存器的第一输出端连接至第k+1个移位寄存器的输入端，第一移位寄存器的输入端用于接收指示新的一帧图像的开始的垂直同步信号。
  13. 一种显示设备，包括如权利要求10-12中任一项所述的栅极驱动电路。
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