WO2016206240A1 - 移位寄存器单元及其驱动方法、移位寄存器和显示装置 - Google Patents

移位寄存器单元及其驱动方法、移位寄存器和显示装置 Download PDF

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Publication number
WO2016206240A1
WO2016206240A1 PCT/CN2015/092003 CN2015092003W WO2016206240A1 WO 2016206240 A1 WO2016206240 A1 WO 2016206240A1 CN 2015092003 W CN2015092003 W CN 2015092003W WO 2016206240 A1 WO2016206240 A1 WO 2016206240A1
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Prior art keywords
transistor
signal
output
shift register
gate
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PCT/CN2015/092003
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English (en)
French (fr)
Inventor
张玉婷
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/517,587 priority Critical patent/US9965986B2/en
Publication of WO2016206240A1 publication Critical patent/WO2016206240A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/007—Use of pixel shift techniques, e.g. by mechanical shift of the physical pixels or by optical shift of the perceived pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of display technologies, and more particularly to a shift register unit and a driving method thereof, a shift register circuit, and a display device.
  • a pixel array includes horizontally interleaved gate scan lines and data lines.
  • a gate driving circuit is generally used to drive the pixel unit in the pixel array.
  • a gate drive circuit (GOA) is used to integrate a TFT (Thin Film Transistor) gate switch circuit on an array substrate of a display panel to form a gate drive circuit.
  • the gate driving circuit integrated on the array substrate by the GOA technology is also called a shift register, and the shift register needs to provide a plurality of control signals to drive a row of pixel units.
  • the shift register includes a multi-stage shift register unit.
  • the first-stage shift register unit can only provide one control signal.
  • a multi-stage shift register unit needs to be cascaded.
  • the structure of the shift register is complicated, and the space occupied by the shift register is too large.
  • the present invention provides the following technical solutions:
  • the present invention provides a shift register unit comprising:
  • An input module wherein the control end is connected to the input signal end, the input end is connected to the high level end, and the output end is connected to the pull-up control node, and the input module is configured to pull up the control node under the control of the signal of the input signal end Output pull-up control signal;
  • the reset module has a control terminal connected to the fifth stage output terminal, and the first input terminal and the shift register The output terminal of the unit is connected, the second input terminal is connected to the pull-up control node, the output terminal is connected to the low-level terminal, and the output terminal of the fifth-stage is the shift register unit as the first-stage shift register unit.
  • the pull-down module has a control terminal connected to the pull-down control node, a first input terminal connected to the output terminal of the shift register unit, a second input terminal connected to the pull-up control node, and an output terminal connected to the low-level terminal, the pull-down The module is configured to discharge the pull-up control node and the output terminal of the shift register unit;
  • the output pull-down control module has a first control end connected to the pull-up control node, a first input end connected to the pull-down control node, a first output end connected to the low level end, a second control end connected to an intermediate node, and a second input
  • the terminal is connected to the high level end, the second output end is connected to the pull-down control node, the third control end and the third input end are connected to the high level end, the third output end is connected to the intermediate node, and the fourth control end is connected to the The intermediate node is connected, the fourth input end is connected to the high level end, the fourth output end is connected to the output control node, the fifth control end is connected to the output end of the shift register unit, and the fifth input end is connected to the output control node.
  • the fifth output terminal is connected to the low level end, and the output pull-down control module is configured to generate a power enable signal and a power supply signal;
  • An output control module wherein the first control end is connected to the pull-up control node, the first input end is connected to the first clock signal end, the first output end is connected to the output end of the shift register unit, and the second control end is moved
  • the output terminal of the bit register unit is connected, the second input terminal is connected to the high level end, the second output end is connected to the gate drive signal end, the third control end is connected to the fourth stage output end, and the third input end is connected to the gate.
  • the pole drive signal end is connected, the third output end is connected to the low level end, the fourth control end is connected to the second clock signal end, the fourth input end is connected to the output control node, and the fourth output end is connected to the power supply power supply signal end,
  • the fifth control end is connected to the third clock signal end, the fifth input end is connected to the output control node, the fifth output end is connected to the output power supply enable signal end, and the fourth stage output end is the shift register unit a first stage shift register unit corresponding to an output of the fourth stage shift register unit, the output control module is configured to generate a gate driving signal, output the power enable signal, Said power supply providing power signal and the gate driving signal.
  • the present invention provides a driving method of a shift register unit, including:
  • the input module receives a high level signal of the input signal terminal, and uses the high level end
  • the high level signal is for charging the pull-up control node
  • the output control module receives the high level signal of the pull-up control node and the signal of the first clock signal end, and provides a signal for the output end of the shift register unit, according to the a signal of the output terminal of the shift register unit and a signal of the output of the fourth stage output a gate drive signal at the gate drive signal end
  • the output pull-down control module receives the signal of the output terminal of the shift register unit and the a high level signal at the high level end, generating a power enable signal and a power supply signal at the output control node
  • the output control module receiving the signal at the second clock signal end and the signal at the third clock signal end, at the power supply enable signal end And outputting the power enable signal and the power supply signal respectively to the power supply signal terminal;
  • the reset module receives a high level signal of the output of the fifth stage, resetting the output terminal of the shift register unit and the pull-up control node to a low level signal; and outputting the pull-down control module to receive the Pulling up a low level signal of the control node to provide a high level signal for the pull-down control node; the pull-down module receiving a high level signal of the pull-down control node, for the pull-up control node and the shift register unit
  • the output of the current stage is discharged;
  • the output control module receives a low level signal of the pull-up control node and a signal of the output of the fourth stage, and outputs a low level signal at the gate drive signal end;
  • the output pull-down control module receives a signal of the output terminal of the shift register unit and a high level signal of the high level end, and generates a high level signal at the output control node; the output control module receives the second a signal of the clock signal end and a signal of the third clock signal end
  • the present invention provides a shift register including a cascaded multi-stage shift register unit in the above technical solution, wherein a first stage shift of the current stage output of the previous stage shift register unit is connected The input signal terminal of the register unit.
  • the present invention provides a display device comprising the shift register in the above technical solution, wherein an output power enable signal, a power supply signal, and a gate provided by a shift register unit in the shift register
  • the pole drive signal is used to drive a pixel unit in the display device.
  • the shift register unit includes an input module, a reset module, a pull-down module, and an output pull-down control a module and an output control module, wherein the output pull-down control module is capable of generating a power enable signal and a power supply signal, and the output control module is capable of generating a gate enable signal, and receiving a power enable signal and a power supply signal generated by the pull-down control module And outputting three control signals of a power enable signal, a power supply signal, and a gate drive signal at the output thereof, compared with the shift register unit in the prior art that can only output one control signal, the shift in the present invention
  • the bit register unit can provide three control signals for simultaneously providing a power enable signal, a power supply signal, and a gate drive signal to drive the pixel unit, thereby reducing the shift required in the shift register while driving the pixel unit.
  • the number of bit register units simplifies the structure of the shift register and reduces the space occupied
  • FIG. 1 is a schematic structural diagram of a shift register unit in Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural diagram of a shift register unit in Embodiment 2 of the present invention.
  • FIG. 3 is a signal timing diagram corresponding to the shift register unit of FIG. 2;
  • FIG. 4 is a schematic structural diagram of a shift register in Embodiment 3 of the present invention.
  • Figure 5 is a timing diagram of signals corresponding to the shift register of Figure 4.
  • FIG. 6 is a schematic structural diagram of a shift register according to another embodiment of the present invention.
  • Fig. 7 is a timing chart of signals corresponding to the shift register of Fig. 6.
  • a shift register unit provided by an embodiment of the present invention includes an input module P1 , a reset module P2 , a pull-down module P3 , an output pull-down control module P4 , and an output control module P5 .
  • the following description will be made with the Nth stage shift register unit in the shift register.
  • the control terminal of the input module P1 is connected to the input signal terminal Input N, and the input terminal and the high level terminal
  • the VGH is connected, the output end is connected to the pull-up control node PU, and the pull-up control node PU is the intersection of the input module P1, the reset module P2, the pull-down module P3, the output pull-down control module P4, and the output control module P5.
  • the input module P1 is configured to output a pull-up control signal at the pull-up control node under the control of the signal of the input signal terminal Input N.
  • the control terminal of the reset module P2 is connected to the fifth-stage output terminal OUT N+4, the first input terminal is connected to the output terminal OUT N of the shift register unit, and the second input terminal is connected to the pull-up control node PU, and the output terminal is connected.
  • Connected to the low-level terminal VGL, wherein the fifth-stage output terminal OUT N+4 is a cascade-level shift register unit, and the fifth-order shift register corresponding to the shift register unit as the first-stage shift register unit The output of the unit.
  • the reset module P2 is configured to reset the local output terminal OUT N of the shift register unit and the pull-up control node PU.
  • the control terminal of the pull-down module P3 is connected to the pull-down control node PD, the first input terminal is connected to the output terminal OUT N of the shift register unit, the second input terminal is connected to the pull-up control node PU, and the output terminal and the low-level terminal VGL are connected.
  • the connection pull-down control node PD is the intersection of the pull-down module P3 and the output pull-down control module P4.
  • the pull-down module P3 is used to discharge the pull-up control node PU and the output terminal OUT N of the shift register unit.
  • the first control end of the output pull-down control module P4 is connected to the pull-up control node PU, the first input end is connected to the pull-down control node PD, the first output end is connected to the low-level end VGL, and the second control end is connected to an intermediate node.
  • the second input terminal is connected to the high-level terminal VGH, the second output terminal is connected to the pull-down control node PD, the third control terminal and the third input terminal are connected to the high-level terminal VGH, and the third output terminal is connected to the intermediate node,
  • the fourth control terminal is connected to the intermediate node, the fourth input terminal is connected to the high level terminal VGH, the fourth output terminal is connected to the output control node PB, and the fifth control terminal is connected to the output terminal OUT N of the shift register unit.
  • the fifth input terminal is connected to the output control node PB, the fifth output terminal is connected to the low level terminal VGL, and the output control node PB is the intersection of the output pull-down control module P4 and the output control module P5.
  • the output pull-down control module P4 is configured to generate and output a power enable signal and a power supply signal at the output control node PB.
  • the first control end of the output control module P5 is connected to the pull-up control node PU, the first input end is connected to the first clock signal terminal CL1, and the first output end is connected to the local output terminal OUT N of the shift register unit, and the second The control terminal is connected to the output terminal OUT N of the shift register unit, the second input terminal is connected to the high level terminal VGH, and the second output terminal is connected to the gate drive signal terminal GATE.
  • the third control terminal is connected to the fourth-stage output terminal OUT N+3, the third input terminal is connected to the gate drive signal terminal GATE, the third output terminal is connected to the low-level terminal VGL, and the fourth control terminal and the second clock are connected.
  • the signal terminal CL2 is connected, the fourth input terminal is connected to the output control node PB, the fourth output terminal is connected to the power supply power supply signal terminal Elvdd, the fifth control terminal is connected to the third clock signal terminal CL3, and the fifth input terminal and the output control node are connected.
  • PB connection the fifth output is connected to the output power enable signal terminal EM, wherein the fourth stage output terminal OUT N+3 is in the cascaded shift register unit, and the shift register unit is used as the first stage shift register
  • the output of the fourth stage shift register unit corresponding to the unit, the output control module P5 is used to generate the gate drive signal, and the power enable signal is outputted at the power enable signal terminal EM, and the power supply is output at the power supply signal end Elvdd.
  • the power supply signal and the gate drive signal are output at the gate drive signal terminal GATE.
  • the shift register unit provided by the embodiment of the invention comprises an input module P1, a reset module P2, a pull-down module P3, an output pull-down control module P4 and an output control module P5, wherein the output pull-down control module P4 can generate power at the output control node PB.
  • the enable signal and the power supply provide signals, and the output control module P5 can generate a gate drive signal, receive the power enable signal and the power supply signal generated by the pull-down control module, and output the power enable signal and the power at the output thereof.
  • the signal and the gate drive signal are provided with three control signals. Compared with the prior art shift register unit which can only output one control signal, the shift register unit of the present invention can simultaneously provide a power enable signal and a power supply.
  • Three control signals of the signal and the gate drive signal drive the pixel unit, thereby reducing the number of shift register units required in the shift register under the premise of being able to drive the pixel unit, thereby simplifying the structure of the shift register , reducing the space occupied by the shift register.
  • the input module P1 receives the high level signal of the input signal terminal Input N, and uses the high level signal of the high level terminal VGH to charge the pull-up control node PU; the output control module P5 receives the high power of the pull-up control node PU.
  • the flat signal and the signal of the first clock signal terminal CL1 provide a signal for the output terminal OUT N of the shift register unit, according to the signal of the output terminal OUT N of the shift register unit and the fourth stage output terminal OUT N+
  • the signal of 3 outputs a gate driving signal at the gate driving signal end GATE;
  • the output pull-down control module P4 receives the signal of the output terminal OUT N of the shift register unit and the high level signal of the high level terminal VGH, and outputs the control
  • the node PB generates a power enable signal and a power supply signal;
  • the output control module P5 receives the signal of the second clock signal terminal CL2 and the signal of the third clock signal terminal CL3, and provides a signal terminal at the power supply enable signal terminal EM and the power supply power terminal.
  • Elvdd outputs a power enable signal and a power supply to provide signals, respectively.
  • the reset module P2 receives the high level signal of the output terminal OUT N+4 of the fifth stage, and resets the output terminal OUT N of the shift register unit and the pull-up control node PU to a low level signal;
  • the control module P4 receives the low level signal of the pull-up control node PU, and provides a high level signal for the pull-down control node PD;
  • the pull-down module P3 receives the high level signal of the pull-down control node PD, and pulls up the control node PU and the shift register.
  • the output terminal OUT N of the unit is discharged; the output control module P5 receives the low-level signal of the pull-up control node PU and the signal of the fourth-stage output terminal OUT N+3, and outputs a low level at the gate drive signal end GATE
  • the output pull-down control module P4 receives the signal of the output terminal OUT N of the shift register unit and the high-level signal of the high-level terminal VGH, generates a high-level signal at the output control node PB, and the output control module P5 receives the second signal.
  • the signal of the clock signal terminal CL2 and the signal of the third clock signal terminal CL3, the output power enable signal and the power source at the power supply enable signal terminal EM and the power supply power supply signal terminal Elvdd output are both high level signals. Rate provided signal.
  • the above driving method is applied to the shift register unit in the first embodiment, and the driving method of the shift register unit has the same advantages as those of the shift register unit, and details are not described herein again.
  • the specific structure of the input module P1, the reset module P2, the pull-down module P3, the output pull-down control module P4, and the output control module P5 in the first embodiment will be described in detail below.
  • the configuration of the input module P1, the reset module P2, the pull-down module P3, the output pull-down control module P4, and the output control module P5 according to the present invention is not limited to the embodiment shown in FIG. 2. This embodiment is provided by way of example only.
  • the input module P1 includes a first transistor T1 having a gate connected to the input signal terminal Input N, a source connected to the high level terminal VGH, and a drain connected to the pull-up control node PU.
  • the gate of the first transistor T1 corresponds to the control terminal of the input module
  • the source corresponds to the input of the input module
  • the drain corresponds to the output of the input module.
  • the reset module P2 includes a second transistor T2 and a third transistor T3; wherein, the second crystal
  • the tube T2 has a gate connected to the fifth-stage output terminal OUT N+4, a source connected to the output terminal OUT N of the shift register unit, a drain connected to the low-level terminal VGL, and a third transistor T3 whose gate Connect to the fifth-stage output terminal OUT++4, the source of which is connected to the pull-up control node PU, and the drain of which is connected to the low-level terminal VGL.
  • the gate of the second transistor T2 and the gate of the third transistor T3 correspond to the control terminal of the reset module
  • the source of the second transistor T2 corresponds to the first input terminal of the reset module
  • the third transistor T3 The source corresponds to the second input of the reset module
  • the drain of the second transistor T2 and the drain of the third transistor T3 correspond to the output of the reset module.
  • the pull-down module P3 includes a fourth transistor T4 and a fifth transistor T5.
  • the fourth transistor T4 has a gate connected to the pull-down control node PD, and a source connected to the output terminal OUT N of the shift register unit, and a drain connection thereof.
  • the fifth transistor T5 has a gate connected to the pull-down control node PD, a source connected to the pull-up control node PU, and a drain connected to the low-level terminal VGL.
  • the gate of the fourth transistor T4 and the gate of the fifth transistor T5 correspond to the control terminal of the pull-down module
  • the source of the fourth transistor T4 corresponds to the first input terminal of the pull-down module
  • the fifth transistor T5 The source corresponds to the second input of the pull-down module
  • the drain of the fourth transistor T4 and the drain of the fifth transistor T5 correspond to the output of the pull-down module.
  • the output pull-down control module P4 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10; wherein the sixth transistor T6 has a gate connected to the pull-up control node PU, the source thereof The pole is connected to the pull-down control node PD, and the drain thereof is connected to the low-level terminal VGL; the seventh transistor T7 has a gate connected to the drain of the eighth transistor T8 and the gate of the ninth transistor T9, and the source thereof is connected to the high-level terminal VGH, The drain is connected to the pull-down control node PD; the eighth transistor T8 has a gate connected to the high-level terminal VGH, a source connected to the high-level terminal VGH, a drain connected to the gate of the ninth transistor T9, and a ninth transistor T9.
  • the gate is connected to the gate of the seventh transistor, the source is connected to the high level terminal VGH, the drain thereof is connected to the output control node PB, and the tenth transistor T10 is connected to the output terminal OUT N of the shift register unit.
  • the source is connected to the output control node PB, and its drain is connected to the low-level terminal VGL.
  • the gate of the sixth transistor T6 corresponds to the first control terminal of the output pull-down control module P4, and the source of the sixth transistor T6 corresponds to the first input terminal of the output pull-down control module P4, the sixth transistor The drain corresponds to the first output of the output pull-down control module P4; the gate of the seventh transistor corresponds to the second control terminal of the output pull-down control module P4, and the source of the seventh transistor corresponds to the second of the output pull-down control module P4 At the input end, the drain of the seventh transistor corresponds to the output pull-down control module P4 The second output terminal; the gate of the eighth transistor corresponds to the third control terminal of the output pull-down control module P4, the source of the eighth transistor corresponds to the third input terminal of the output pull-down control module P4, and the drain of the eighth transistor Corresponding to the output end of the output pull-down control module P4; the gate of the ninth transistor corresponds to the fourth control end of the output pull-down control module P4, and the source of the ninth transistor corresponds to the
  • the output control module P5 includes a first output control sub-module for outputting a gate drive signal, and a second output control sub-module for outputting a power enable signal and a power supply signal.
  • the first output control sub-module includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13
  • the second output control sub-module includes a fourteenth transistor T14 and a fifteenth transistor T15;
  • the eleven transistor T11 has a gate connected to the pull-up control node PU, a source connected to the first clock signal terminal CL1, a drain connected to the output terminal OUT N of the shift register unit, and a twelfth transistor T12.
  • the terminal is connected to the output terminal OUT N of the shift register unit, the source thereof is connected to the high level terminal VGH, the drain thereof is connected to the gate driving signal terminal GATE, and the thirteenth transistor T13 is connected to the fourth stage output terminal OUT.
  • N+3 the source is connected to the gate driving signal terminal GATE, the drain thereof is connected to the low-level terminal VGL;
  • the fourteenth transistor T14 has a gate connected to the second clock signal terminal CL2, and a source thereof is connected to the output control node PB, The drain is connected to the power supply signal terminal Elvdd;
  • the fifteenth transistor T15 has a gate connected to the third clock signal terminal CL3, a source connected to the output control node PB, and a drain connected to the output power enable signal terminal EM.
  • the gate of the eleventh transistor corresponds to the first control terminal of the output control module P5, and the source of the eleventh transistor corresponds to the first input terminal of the output control module P5, and the drain of the eleventh transistor
  • the pole corresponds to the first output of the output control module P5;
  • the gate of the twelfth transistor corresponds to the second control terminal of the output control module P5, and the source of the twelfth transistor corresponds to the second input of the output control module P5
  • the drain of the twelfth transistor corresponds to the second output of the output control module P5;
  • the gate of the thirteenth transistor corresponds to the third control terminal of the output control module P5, and the source of the thirteenth transistor corresponds to the output control
  • the third input of the module P5, the drain of the thirteenth transistor corresponds to the third output of the output control module P5;
  • the gate of the fourteenth transistor corresponds to the output control module a fourth control terminal of P5, a source of the fourteenth transistor corresponds to a fourth input terminal of
  • the specific connection between the specific structure of the input module P1, the reset module P2, the pull-down module P3, the output pull-down control module P4, and the output control module P5 is as follows: the first transistor T1 whose source is connected to the twelfth transistor T12 a source whose drain is connected to a gate of the eleventh transistor T11, a source of the third transistor T3, a source of the fifth transistor T5, and a gate of the sixth transistor T6; and a second transistor T2 whose source is connected a drain of the eleven transistor T11, a gate of the twelfth transistor T12, a source of the fourth transistor T4, and a gate of the tenth transistor T10, the drain of which is connected to the drain of the fourth transistor T4 and the fifth transistor T5
  • the drain is connected to the drain of the sixth transistor T6, the drain of the tenth transistor T10, and the drain of the thirteenth transistor T13;
  • the fifth transistor T5 has a gate connected to the source of the sixth transistor T6 and the seventh transistor T7.
  • a drain whose source is connected to the gate of the eleventh transistor T11 and the gate of the sixth transistor T6, the drain of which is connected to the drain of the sixth transistor T6, the drain of the tenth transistor T10, and the thirteenth transistor T13 a drain;
  • a sixth transistor T6 having a gate connected to the gate of the eleventh transistor T11, a drain connected to the drain of the thirteenth transistor T13, and a ninth transistor T9 having a drain connected to the source of the fourteenth transistor T14 a terminal of the fifteenth transistor T15;
  • a tenth transistor T10 having a gate connected to the gate of the twelfth transistor T12 and a source connected to the source of the fourteenth transistor T14 and the source of the fifteenth transistor T15
  • the pull-up control node PU may specifically be a connection intersection of the drain of the first transistor T1 and the gate of the eleventh transistor T11, and the pull-down control node PD may specifically be the source and the seventh of the sixth transistor T6.
  • the gate of transistor T7 The connection control point PB may specifically be a connection point of the drain of the ninth transistor T9 and the source of the tenth transistor T10.
  • each transistor is a P-type transistor.
  • the circuit design in which each transistor may be an N-type transistor and the transistor is an N-type transistor is also within the scope of the present application.
  • the connections of the individual transistors are the same as in the previous embodiment, except that the connections of the respective inputs and outputs are switched.
  • the gate of the first transistor corresponds to the control terminal of the input module
  • the drain corresponds to the input of the input module
  • the source corresponds to the output of the input module.
  • FIG. 3 is a timing diagram of signals corresponding to the shift register unit shown in FIG. 2.
  • the shift register unit in the second embodiment will be described below with reference to FIG. 3 and taking each transistor as a P-type transistor as an example.
  • the driving method is explained.
  • the first phase in the first embodiment includes an A-B phase, a B-C phase, a C-D phase, a D-E phase, and an E-F phase
  • the second phase includes an F-G phase and a G-H phase:
  • the signal of the input signal terminal Input N is a high level signal
  • the gate of the first transistor T1 receives the high level signal of the input signal terminal Input N
  • the first transistor T1 is turned on to charge the pull-up control node PU.
  • the signal of the pull-up control node PU is a high level signal; the gate of the eleventh transistor T11 receives the high level signal of the pull-up control node PU, the eleventh transistor T11 is turned on, and the signal of the first clock signal terminal CL1 is The low level signal, the signal of the output terminal OUT N of the shift register unit is a low level signal, the twelfth transistor T12 is turned off, the signal of the gate drive signal end GATE is a low level signal; the pull-up control node PU The signal is a high level signal, the sixth transistor T6 is turned on, the signal of the pull-down control node PD is a low level signal, the fourth transistor T4 and the fifth transistor T5 are both turned off; the gate of the tenth transistor T10 receives the shift register unit The low level signal of the output terminal OUT N of the current stage, the tenth transistor T10 is turned off, so the signal of the output control node PB is a high level signal; the signal of the second clock signal end
  • the signal of the input signal terminal Input N is a low level signal
  • the first transistor T1 is turned off, the pull-up control node PU maintains a high level signal in the AB phase;
  • the eleventh transistor T11 is turned on, and the first clock signal terminal is turned on.
  • the signal of CL1 is a high level signal
  • shift register The signal of the output terminal OUT of the current stage of the element is a high level signal
  • the gate of the twelfth transistor T12 receives the high level signal of the output terminal OUT N of the shift register unit, and the twelfth transistor T12 is turned on.
  • the pole drive signal terminal GATE receives the high level signal of the high level terminal VGH through the twelfth transistor T12, and outputs the gate driving signal, the gate driving signal is a high level signal; the signal of the pull-up control node PU is a high level The signal, the sixth transistor T6 is turned on, the signal of the pull-down control node PD is a low level signal, the fourth transistor T4 and the fifth transistor T5 remain closed; the gate of the tenth transistor T10 receives the output of the shift register unit
  • the signal terminal Elvdd output power supply signal is provided, the power supply power supply signal is a low level signal; the third clock signal end CL3 signal is a low level signal, and the fifteenth transistor
  • the signal of the input signal terminal Input N is a high level signal
  • the first transistor T1 is turned on, the pull-up control node PU is charged, and the signal of the pull-up control node PU is a high level signal
  • the eleventh transistor T11 When the signal of the first clock signal terminal CL1 is a low level signal, the signal of the output terminal OUT N of the shift register unit is a low level signal, the twelfth transistor T12 is turned off, and the signal of the gate driving signal terminal GATE is turned on.
  • Maintaining a high level signal for the BC phase that is, the gate drive signal terminal GATE continues to output the gate drive signal;
  • the signal of the pull-up control node PU is a high level signal, the sixth transistor T6 is turned on, and the signal of the pull-down control node PD is The low level signal, the fourth transistor T4 and the fifth transistor T5 are both turned off;
  • the gate of the tenth transistor T10 receives the low level signal of the output terminal OUT N of the shift register unit, and the tenth transistor T10 is turned off, so the output
  • the signal of the control node PB is a high level signal;
  • the signal of the second clock signal terminal CL2 is a high level signal, the fourteenth transistor T14 is turned on, and the signal of the power supply power supply signal end Elvdd is a high level signal.
  • End of the third clock signal CL3 is the signal for the low level signal, a fifteenth transistor T15 off, the power signal so that the signal remains high end of the EM signal.
  • the signal of the input signal terminal Input N is a low level signal
  • the first transistor T1 is turned off
  • the pull-up control node PU maintains a high level signal of the CD phase
  • the eleventh transistor T11 is turned on
  • the first clock signal terminal CL1 The signal is a high level signal
  • the signal of the output terminal OUT N of the shift register unit is a high level signal
  • the gate of the twelfth transistor T12 receives
  • the high-level signal of the output terminal OUT N of the shift register unit is turned on
  • the twelfth transistor T12 is turned on
  • the gate drive signal terminal GATE receives the high-level signal of the high-level terminal VGH through the twelfth transistor T12, and outputs the gate.
  • the pole drive signal, the gate drive signal is a high level signal; the signal of the pull-up control node PU is a high level signal, the sixth transistor T6 is turned on, the signal of the pull-down control node PD is a low level signal, and the fourth transistor T4 and The fifth transistor T5 remains in the off state; the gate of the tenth transistor T10 receives the high level signal of the output terminal OUT N of the shift register unit, the tenth transistor T10 is turned on, and the signal of the output control node PB is low.
  • the signal of the second clock signal terminal CL2 is a low level signal
  • the fourteenth transistor T14 is turned off
  • the signal of the power supply power supply signal terminal Elvdd is a high level signal
  • the signal of the third clock signal terminal CL3 is a high level signal.
  • the fifteenth transistor T15 is turned on, the power enable signal terminal EM outputs a power enable signal, and the power enable signal is a low level signal.
  • the signal of the input signal terminal Input N is a low level signal
  • the first transistor T1 is turned off
  • the pull-up control node PU maintains a high level signal of the DE phase
  • the eleventh transistor T11 is turned on
  • the first clock signal terminal CL1 The signal is a low level signal
  • the signal of the output terminal OUT N of the shift register unit is a low level signal
  • the twelfth transistor T12 is turned off
  • the signal of the fourth stage output terminal OUT N+3 is a high level signal.
  • the thirteenth transistor T13 is turned on, the signal of the gate driving signal terminal GATE is a low level signal; the signal of the pull-up control node PU is a high level signal, the sixth transistor T6 is turned on, and the signal of the pull-down control node PD is low.
  • the flat signal, the fourth transistor T4 and the fifth transistor T5 are both turned off; the gate of the tenth transistor T10 receives the low level signal of the output terminal OUT N of the shift register unit, and the tenth transistor T10 is turned off, so the output control node
  • the signal of PB is a high level signal; the signal of the second clock signal end CL2 is a low level signal, the fourteenth transistor T14 is turned off, the signal of the power supply power supply signal end Elvdd is a high level signal; the third clock signal Signal is a high level signal CL3, fifteenth transistor T15 is turned on, the power supply so that the signal EM signal terminal of a high level signal.
  • the signal of the input signal terminal Input N is a low level signal
  • the first transistor T1 is turned off
  • the signal of the fifth stage output terminal OUT N+4 is a high level signal
  • the second transistor T2 and the third transistor T3 are both Turning on, discharging the current output terminal OUT N of the shift register unit through the second transistor T2, resetting the output terminal OUT N of the shift register unit to a low level signal, and pulling up the control node through the third transistor T3
  • the PU discharges, the pull-up control node PU resets to a low level signal;
  • the gate of the sixth transistor T6 receives the pull-up control node PU
  • the low level signal, the sixth transistor T6 is turned off, so the pull-down control node PD is a high level signal;
  • the gate of the fourth transistor T4 and the gate of the fifth transistor T5 receive the high level signal of the pull-down control node PD, fourth The transistor T4 and the fifth transistor T5 are both turned on, the fourth
  • the signal of the power supply power supply signal terminal Elvdd is a high level signal; the signal of the third clock signal terminal CL3 is a low level signal, the fifteenth transistor T15 is turned off, and the signal of the power supply enable signal terminal EM is a high level signal.
  • the signal of the input signal terminal Input N is a low level signal
  • the first transistor T1 is turned off
  • the signal of the fifth stage output terminal OUT N+4 is a low level signal
  • the second transistor T2 and the third transistor T3 are both Off
  • the output terminal OUT N of the shift register unit maintains a low level signal of the FG phase
  • the pull-up control node PU maintains a low level signal of the FG phase
  • the gate of the sixth transistor T6 receives the pull-up control node PU
  • the low level signal, the sixth transistor T6 is turned off, so the pull-down control node PD is a high level signal
  • the gate of the fourth transistor T4 and the gate of the fifth transistor T5 receive the high level signal of the pull-down control node PD
  • fourth The transistor T4 and the fifth transistor T5 are both turned on, the fourth transistor T4 further discharges the output terminal OUT N of the shift register unit, and the fifth transistor T5 further discharges the pull-up control node PU
  • the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are both turned on, wherein the output of the eighth transistor T8 is high, and the seventh transistor T7 and the ninth transistor T9 are controlled to be turned on, thereby being PD point and PB, respectively. Click to write a high level signal.
  • the gate and the source of the eighth transistor T8 are both connected to the high-level terminal VGH in FIG. 2, it may be connected to the inverted signal of the first clock signal CL1, thereby ensuring that the PU point is in the PU. The point is high before, so that the PD point can be discharged when the PU point is high.
  • the signal of the second clock signal terminal CL2 and the signal of the third clock signal terminal CL3 are mutually inverted signals; the frequency of the signal of the first clock signal terminal CL1 is different from the frequency of the signal of the second clock signal terminal CL2.
  • the frequency of the signal of the first clock signal terminal CL1 is twice the frequency of the signal of the second clock signal terminal CL2.
  • the present invention further provides a shift register including a plurality of shift register units in the first embodiment and the second embodiment, wherein the output terminal of the previous stage shift register unit Connect the input signal terminal of the next stage shift register unit.
  • the output terminal OUT1 of the first stage shift register unit UNIT1 is connected to the input signal terminal Input2 of the second stage shift register unit UNIT2.
  • the shift register includes N stages of shift register units in the first embodiment and the second embodiment, and N is an integer greater than or equal to 4; wherein the first clock signal terminal CL1 of the i-th stage shift register unit is The first clock signal terminal CL1 of the i+2th stage shift register unit inputs a first clock signal, and the first clock signal terminal CL1 of the i+1th stage shift register unit and the i+3th stage shift register unit The first clock signal terminal CL1 inputs an inverted signal of the first clock signal; the second clock signal terminal CL2 of the i-th stage shift register unit and the second clock signal terminal CL2 of the i+1th-order shift register unit are both input.
  • a second clock signal, a second clock signal terminal CL2 of the i+2th stage shift register unit and a second clock signal terminal CL2 of the i+3th stage shift register unit are both input with a reverse signal of the second clock signal;
  • the third clock signal terminal CL3 of the i-stage shift register unit and the third clock signal terminal CL3 of the i+1th-order shift register unit respectively input an inverted signal of the second clock signal, and the i+2th stage shift register unit
  • the first clock signal terminal CL1 of the first stage shift register unit UNIT1 inputs the first clock signal CLK1, the second clock signal terminal CL2 inputs the second clock signal CLK2, and the third clock signal terminal CL3 inputs.
  • the inverted signal CLK2B of the second clock signal, the first reset terminal Reset 11 is connected to the output terminal OUT 4 of the fourth stage shift register, and the second reset terminal Reset 12 is connected to the output terminal OUT 5 of the fifth stage register;
  • the first clock signal terminal CL1 of the bit register unit UNIT 2 inputs the inverted signal CLK1B of the first clock signal
  • the second clock signal terminal CL2 inputs the second clock signal CLK2
  • the third clock signal terminal CL3 inputs the inversion of the second clock signal.
  • first reset terminal Reset 21 is connected The output terminal OUT 5 of the five-stage shift register, the second reset terminal Reset 22 is connected to the output terminal OUT 6 of the sixth-stage register; the first clock signal terminal CL1 of the third-stage shift register unit UNIT 3 inputs the first clock signal CLK1
  • the second clock signal terminal CL2 inputs the inverted signal CLK2B of the second clock signal, the third clock signal terminal CL3 inputs the second clock signal CLK2, and the first reset terminal Reset 31 is connected to the output terminal OUT6 of the sixth stage shift register.
  • the second reset terminal Reset 32 is connected to the output terminal OUT 7 of the seventh-stage register; the first clock signal terminal CL1 of the fourth-stage shift register unit UNIT 4 inputs the inverted signal CLK1B of the first clock signal, and the second clock signal terminal CL2 Inputting the inverted signal CLK2B of the second clock signal, the third clock signal terminal CL3 is input to the second clock signal CLK2, and the first reset terminal Reset 41 is connected to the output terminal OUT7 of the seventh-stage shift register, and the second reset terminal Reset 42 is connected.
  • the output terminal OUT 8 of the eighth-stage register the first clock signal terminal CL1 of the fifth-stage shift register unit UNIT 5 inputs the first clock signal CLK1, and the second clock signal terminal CL2 inputs the second clock signal CLK2, the third clock signal terminal CL3 inputs the inverted signal CLK2B of the second clock signal, the first reset terminal Reset 51 is connected to the output terminal OUT8 of the eighth stage shift register, and the second reset terminal Reset 52 is connected to the ninth stage register.
  • the output terminal OUT 9 the connection of the remaining more stages of the shift register unit and so on.
  • each stage shift register unit The connection of the gate drive signal output terminal of each stage shift register unit, the power supply enable signal output terminal, and the power supply power supply signal output terminal is not shown in FIG. Obviously, the gate drive signal, the power enable signal and the power supply signal provided by the shift register units of each stage are used to drive the corresponding row of pixel units. That is, the gate drive signal output end of each stage shift register unit, the power supply enable signal output end, and the power supply power supply signal output end are connected to the terminals of the corresponding pixel unit.
  • shift register unit in the shift register has the same advantages as the shift register unit in the first embodiment and the second embodiment, and details are not described herein again.
  • FIG. 5 is a signal timing diagram corresponding to the shift register in the third embodiment.
  • the specific driving method of the shift register refer to the driving method of the shift register unit constituting the shift register, and the signal timing description of FIG.
  • the signal timing description corresponding to FIG. 3 can also be referred to.
  • a third clock signal may be provided which is delayed with respect to the second clock signal, for example, by half a clock period with respect to the second clock signal.
  • the ith stage shift register unit The first clock signal terminal CL1 and the first clock signal terminal CL1 of the i+2th stage shift register unit respectively input the first clock signal, and the first clock signal terminal CL1 and the i+th of the i+1th stage shift register unit
  • the first clock signal terminal CL1 of the 3-stage shift register unit inputs an inverted signal of the first clock signal
  • the second clock signal terminal CL2 of the i-th shift register unit inputs the second clock signal
  • the second clock signal terminal CL2 of the bit register unit inputs a third clock signal
  • the second clock signal terminal CL2 of the i+2th stage shift register unit inputs the reverse signal of the second clock signal, the i+3th stage shift register
  • the second clock signal terminal CL2 of the unit inputs the reverse signal of the third clock signal
  • the third clock signal terminal CL3 of the i-th stage shift register unit inputs the reverse signal of the second clock signal
  • the first clock signal terminal CL1 of the first stage shift register unit UNIT 1 inputs the first clock signal CLK1, the second clock signal terminal CL2 inputs the second clock signal CLK2, and the third clock signal terminal CL3.
  • the first reset terminal Reset 11 is connected to the output terminal OUT 4 of the fourth stage shift register
  • the second reset terminal Reset 12 is connected to the output terminal OUT 5 of the fifth stage register;
  • the first clock signal terminal CL1 of the shift register unit UNIT 2 inputs the inverted signal CLK1B of the first clock signal
  • the second clock signal terminal CL2 inputs the third clock signal CLK3,
  • the third clock signal terminal CL3 inputs the inverse of the third clock signal.
  • the phase signal CLK3B, the first reset terminal Reset 21 is connected to the output terminal OUT 5 of the fifth stage shift register, the second reset terminal Reset 22 is connected to the output terminal OUT 6 of the sixth stage register; the third stage shift register unit UNIT 3
  • the first clock signal terminal CL1 inputs the first clock signal CLK1, the second clock signal terminal CL2 inputs the inverted signal CLK2B of the second clock signal, and the third clock signal terminal CL3 inputs the second clock signal CLK2,
  • the first The bit end Reset 31 is connected to the output terminal OUT6 of the sixth stage shift register, and the second reset end Reset 32 is connected to the output terminal OUT7 of the seventh stage register;
  • the first clock signal terminal CL1 of the fourth stage shift register unit UNIT4 Inputting the inverted signal CLK1B of the first clock signal, the second clock signal terminal CL2 inputs the inverted signal CLK3B of the third clock signal, the third clock signal terminal CL3 inputs the third clock signal CLK3, and the first reset terminal Reset 41 is connected to
  • the clock signal CLK1, the second clock signal terminal CL2 inputs the second clock signal CLK2, the third clock signal terminal CL3 inputs the inverted signal CLK2B of the second clock signal, and the first reset terminal Reset 51 is connected to the output terminal of the eighth stage shift register.
  • the second reset terminal Reset 52 is connected to the output terminal OUT of the ninth stage register, and the connection of the remaining stages of the shift register unit is deduced by analogy.
  • FIG. 7 is a signal timing diagram corresponding to the shift register in the embodiment.
  • the specific driving method of the shift register refer to the driving method of the shift register unit constituting the shift register, and the signal timing description of FIG. 7 can also refer to FIG. Corresponding signal timing description.
  • the present invention also provides a display device comprising the shift register of the above third embodiment, wherein the output power enable signal, the power supply signal and the gate provided by the shift register unit in the shift register
  • the drive signal is used to drive a pixel unit in the display device.
  • the shift register in the display device has the same advantages as the shift register in the above embodiment, and details are not described herein again.
  • the display device may be any product or component having an display function such as an organic light emitting diode display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种移位寄存器单元及其驱动方法、移位寄存器和显示装置。移位寄存器单元包括用于接收输入信号端（Input N）的信号和高电平端（VGH）的信号的输入模块（P1），用于对移位寄存器单元的本级输出端（OUT N）和上拉控制节点（PU）进行复位的复位模块（P2），用于对上拉控制节点（PU）和移位寄存器单元的本级输出端（OUT N）进行放电的下拉模块（P3），用于生成电源使能信号和电源功率提供信号的输出下拉控制模块（P4），以及用于生成栅极驱动信号，输出电源使能信号、电源功率提供信号和栅极驱动信号的输出控制模块（P5）。移位寄存器单元应用于显示装置中，能够解决移位寄存器结构复杂，且占用空间过大的问题。

Description

移位寄存器单元及其驱动方法、移位寄存器和显示装置 技术领域
本发明涉及显示技术领域，更具体地，涉及移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置。
背景技术
在显示装置中，像素阵列包括横纵交错的栅极扫描线和数据线。其中，为了实现像素阵列的逐行扫描，通常采用栅极驱动电路驱动像素阵列中的像素单元。现有技术中，栅极驱动电路常采用GOA(Gate Driver on Array，阵列基板行驱动)设计将TFT(Thin Film Transistor，薄膜场效应晶体管)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，这种利用GOA技术集成在阵列基板上的栅极驱动电路也称为移位寄存器，移位寄存器需要提供多个控制信号来驱动一行像素单元。
在现有技术中，移位寄存器包括多级移位寄存器单元，但是，一级移位寄存器单元只能提供一个控制信号，想要驱动一行像素单元，需要将多级移位寄存器单元级联，使得移位寄存器的结构复杂，且移位寄存器占用的空间过大。
发明内容
本发明的目的在于提供一种移位寄存器单元及其驱动方法、移位寄存器和显示装置，用于简化移位寄存器的结构，减小移位寄存器占用的空间。
为了实现上述目的，本发明提供如下技术方案：
第一方面，本发明提供了一种移位寄存器单元，包括：
输入模块，其控制端与输入信号端连接，输入端与高电平端连接，输出端与上拉控制节点连接，所述输入模块用于在所述输入信号端的信号的控制下在上拉控制节点输出上拉控制信号；
复位模块，其控制端与第五级输出端连接，第一输入端与移位寄存器 单元的本级输出端连接，第二输入端与上拉控制节点连接，输出端与低电平端连接，所述第五级输出端为移位寄存器单元作为第一级移位寄存器单元时对应的第五级移位寄存器单元的输出端，所述复位模块用于对所述移位寄存器单元的本级输出端和所述上拉控制节点进行复位；
下拉模块，其控制端与下拉控制节点连接，第一输入端与移位寄存器单元的本级输出端连接，第二输入端与上拉控制节点连接，输出端与低电平端连接，所述下拉模块用于对所述上拉控制节点和所述移位寄存器单元的本级输出端进行放电；
输出下拉控制模块，其第一控制端与上拉控制节点连接，第一输入端与下拉控制节点连接，第一输出端与低电平端连接，第二控制端与一中间节点连接，第二输入端与高电平端连接，第二输出端与下拉控制节点连接，第三控制端和第三输入端与高电平端连接，第三输出端与所述中间节点连接，第四控制端与所述中间节点连接，第四输入端与高电平端连接，第四输出端与输出控制节点连接，第五控制端与移位寄存器单元的本级输出端连接，第五输入端与输出控制节点连接，第五输出端与低电平端连接，所述输出下拉控制模块用于生成电源使能信号和电源功率提供信号；
输出控制模块，其第一控制端与上拉控制节点连接，第一输入端与第一时钟信号端连接，第一输出端与移位寄存器单元的本级输出端连接，第二控制端与移位寄存器单元的本级输出端连接，第二输入端与高电平端连接，第二输出端与栅极驱动信号端连接，第三控制端与第四级输出端连接，第三输入端与栅极驱动信号端连接，第三输出端与低电平端连接，第四控制端与第二时钟信号端连接，第四输入端与输出控制节点连接，第四输出端与电源功率提供信号端连接，第五控制端与第三时钟信号端连接，第五输入端与输出控制节点连接，第五输出端与输出电源使能信号端连接，所述第四级输出端为所述移位寄存器单元作为第一级移位寄存器单元时对应的第四级移位寄存器单元的输出端，所述输出控制模块用于生成栅极驱动信号，输出所述电源使能信号、所述电源功率提供信号和所述栅极驱动信号。
第二方面，本发明提供了一种移位寄存器单元的驱动方法，包括：
第一阶段，输入模块接收输入信号端的高电平信号，利用高电平端的 高电平信号为上拉控制节点充电；输出控制模块接收所述上拉控制节点的高电平信号和第一时钟信号端的信号，为移位寄存器单元的本级输出端提供信号，根据所述移位寄存器单元的本级输出端的信号和第四级输出端的信号，在栅极驱动信号端输出栅极驱动信号；输出下拉控制模块接收所述移位寄存器单元的本级输出端的信号和所述高电平端的高电平信号，在输出控制节点生成电源使能信号和电源功率提供信号；输出控制模块接收第二时钟信号端的信号和第三时钟信号端的信号，在所述电源使能信号端和所述电源功率提供信号端分别输出所述电源使能信号和所述电源功率提供信号；
第二阶段，复位模块接收第五级输出端的高电平信号，将所述移位寄存器单元的本级输出端和所述上拉控制节点复位至低电平信号；输出下拉控制模块接收所述上拉控制节点的低电平信号，为下拉控制节点提供高电平信号；所述下拉模块接收所述下拉控制节点的高电平信号，对所述上拉控制节点和所述移位寄存器单元的本级输出端进行放电；所述输出控制模块接收所述上拉控制节点的低电平信号和所述第四级输出端的信号，在所述栅极驱动信号端输出低电平信号；所述输出下拉控制模块接收所述移位寄存器单元的本级输出端的信号和所述高电平端的高电平信号，在输出控制节点生成高电平信号；所述输出控制模块接收所述第二时钟信号端的信号和所述第三时钟信号端的信号，在所述电源使能信号端和所述电源功率提供信号端输出均为高电平信号的输出电源使能信号和电源功率提供信号。
第三方面，本发明提供了一种移位寄存器，包括级联的多级上述技术方案中的移位寄存器单元，其中，前一级移位寄存器单元的本级输出端连接后一级移位寄存器单元的输入信号端。
第四方面，本发明提供了一种显示装置，包括上述技术方案中的移位寄存器，其中，所述移位寄存器中的移位寄存器单元提供的输出电源使能信号、电源功率提供信号和栅极驱动信号用于驱动所述显示装置中的像素单元。
本发明提供的移位寄存器单元及其驱动方法、移位寄存器和显示装置中，移位寄存器单元包括输入模块、复位模块、下拉模块、输出下拉控制 模块和输出控制模块，其中，输出下拉控制模块能够生成电源使能信号和电源功率提供信号，输出控制模块能够生成栅极启动信号，接收输出下拉控制模块生成的电源使能信号和电源功率提供信号，并在其输出处输出电源使能信号、电源功率提供信号和栅极驱动信号三个控制信号，与现有技术中只能输出一个控制信号的移位寄存器单元相比，本发明中的移位寄存器单元能够提供同时提供电源使能信号、电源功率提供信号和栅极驱动信号三个控制信号，来驱动像素单元，从而在能够驱动像素单元的前提下，减少了移位寄存器中所需移位寄存器单元的数目，从而简化了移位寄存器的结构，减小了移位寄存器占用的空间。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本发明的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1为本发明实施例一中的移位寄存器单元的结构示意图；
图2为本发明实施例二中的移位寄存器单元的结构示意图；
图3为与图2中移位寄存器单元对应的信号时序图；
图4为本发明实施例三中的移位寄存器的结构示意图；
图5为与图4中移位寄存器对应的信号时序图；
图6为本发明另一实施例中的移位寄存器的结构示意图；
图7为与图6中移位寄存器对应的信号时序图。
具体实施方式
为了进一步说明本发明实施例提供的移位寄存器单元及其驱动方法、移位寄存器和显示装置，下面结合说明书附图进行详细描述。
实施例一
请参阅图1，本发明实施例提供的移位寄存器单元包括输入模块P1、复位模块P2、下拉模块P3、输出下拉控制模块P4和输出控制模块P5。下面以移位寄存器中的第N级移位寄存器单元进行说明。
输入模块P1的控制端与输入信号端Input N连接，输入端与高电平端 VGH连接，输出端与上拉控制节点PU连接，上拉控制节点PU为输入模块P1、复位模块P2、下拉模块P3、输出下拉控制模块P4和输出控制模块P5的交点。输入模块P1用于在输入信号端Input N的信号的控制下，在上拉控制节点输出上拉控制信号。
复位模块P2的控制端与第五级输出端OUT N+4连接，第一输入端与移位寄存器单元的本级输出端OUT N连接，第二输入端与上拉控制节点PU连接，输出端与低电平端VGL连接，其中第五级输出端OUT N+4为级联的移位寄存器单元中、以本移位寄存器单元作为第一级移位寄存器单元时对应的第五级移位寄存器单元的输出端。复位模块P2用于对所述移位寄存器单元的本级输出端OUT N和所述上拉控制节点PU进行复位。
下拉模块P3的控制端与下拉控制节点PD连接，第一输入端与移位寄存器单元的本级输出端OUT N连接，第二输入端与上拉控制节点PU连接，输出端与低电平端VGL连接，下拉控制节点PD为下拉模块P3与输出下拉控制模块P4的交点。下拉模块P3用于对上拉控制节点PU和移位寄存器单元的本级输出端OUT N进行放电。
输出下拉控制模块P4的第一控制端与上拉控制节点PU连接，第一输入端与下拉控制节点PD连接，第一输出端与低电平端VGL连接，第二控制端与一中间节点连接，第二输入端与高电平端VGH连接，第二输出端与下拉控制节点PD连接，第三控制端和第三输入端与高电平端VGH连接，第三输出端与所述中间节点连接，第四控制端与所述中间节点连接，第四输入端与高电平端VGH连接，第四输出端与输出控制节点PB连接，第五控制端与移位寄存器单元的本级输出端OUT N连接，第五输入端与输出控制节点PB连接，第五输出端与低电平端VGL连接，输出控制节点PB为输出下拉控制模块P4与输出控制模块P5的交点。输出下拉控制模块P4用于生成并在输出控制节点PB处输出电源使能信号和电源功率提供信号。
输出控制模块P5的第一控制端与上拉控制节点PU连接，第一输入端与第一时钟信号端CL1连接，第一输出端与移位寄存器单元的本级输出端OUT N连接，第二控制端与移位寄存器单元的本级输出端OUT N连接，第二输入端与高电平端VGH连接，第二输出端与栅极驱动信号端GATE 连接，第三控制端与第四级输出端OUT N+3连接，第三输入端与栅极驱动信号端GATE连接，第三输出端与低电平端VGL连接，第四控制端与第二时钟信号端CL2连接，第四输入端与输出控制节点PB连接，第四输出端与电源功率提供信号端Elvdd连接，第五控制端与第三时钟信号端CL3连接，第五输入端与输出控制节点PB连接，第五输出端与输出电源使能信号端EM连接，其中第四级输出端OUT N+3为级联的移位寄存器单元中、以本移位寄存器单元作为第一级移位寄存器单元时对应的第四级移位寄存器单元的输出端，输出控制模块P5用于生成栅极驱动信号，并在电源使能信号端EM输出电源使能信号、在电源功率提供信号端Elvdd输出电源功率提供信号和在栅极驱动信号端GATE输出栅极驱动信号。
本发明实施例提供的移位寄存器单元包括输入模块P1、复位模块P2、下拉模块P3、输出下拉控制模块P4和输出控制模块P5，其中，输出下拉控制模块P4能够在输出控制节点PB处生成电源使能信号和电源功率提供信号，输出控制模块P5能够生成栅极驱动信号，接收输出下拉控制模块生成的电源使能信号和电源功率提供信号，并在其输出处输出电源使能信号、电源功率提供信号和栅极驱动信号三个控制信号，与现有技术中只能输出一个控制信号的移位寄存器单元相比，本发明中的移位寄存器单元能够同时提供电源使能信号、电源功率提供信号和栅极驱动信号三个控制信号，来驱动像素单元，从而在能够驱动像素单元的前提下，减少了移位寄存器中所需移位寄存器单元的个数，从而简化了移位寄存器的结构，减小了移位寄存器占用的空间。
下面将说明上述移位寄存器单元的驱动方法，其中，上述移位寄存器单元的驱动方法包括两个阶段：
第一阶段，输入模块P1接收输入信号端Input N的高电平信号，利用高电平端VGH的高电平信号为上拉控制节点PU充电；输出控制模块P5接收上拉控制节点PU的高电平信号和第一时钟信号端CL1的信号，为移位寄存器单元的本级输出端OUT N提供信号，根据移位寄存器单元的本级输出端OUT N的信号和第四级输出端OUT N+3的信号，在栅极驱动信号端GATE输出栅极驱动信号；输出下拉控制模块P4接收移位寄存器单元的本级输出端OUT N的信号和高电平端VGH的高电平信号，在输出控 制节点PB生成电源使能信号和电源功率提供信号；输出控制模块P5接收第二时钟信号端CL2的信号和第三时钟信号端CL3的信号，在电源使能信号端EM和电源功率提供信号端Elvdd分别输出电源使能信号和电源功率提供信号。
第二阶段，复位模块P2接收第五级输出端OUT N+4的高电平信号，将移位寄存器单元的本级输出端OUT N和上拉控制节点PU复位至低电平信号；输出下拉控制模块P4接收上拉控制节点PU的低电平信号，为下拉控制节点PD提供高电平信号；下拉模块P3接收下拉控制节点PD的高电平信号，对上拉控制节点PU和移位寄存器单元的本级输出端OUT N进行放电；输出控制模块P5接收上拉控制节点PU的低电平信号和第四级输出端OUT N+3的信号，在栅极驱动信号端GATE输出低电平信号；输出下拉控制模块P4接收移位寄存器单元的本级输出端OUT N的信号和高电平端VGH的高电平信号，在输出控制节点PB生成高电平信号；输出控制模块P5接收第二时钟信号端CL2的信号和第三时钟信号端CL3的信号，在电源使能信号端EM和电源功率提供信号端Elvdd输出均为高电平信号的输出电源使能信号和电源功率提供信号。
上述驱动方法应用于实施例一中的移位寄存器单元，所述移位寄存器单元的驱动方法具有的优势与移位寄存器单元具有的优势相同，此处不再赘述。
实施例二
请参阅图2，下面将详细说明实施例一中的输入模块P1、复位模块P2、下拉模块P3、输出下拉控制模块P4和输出控制模块P5的具体结构。当然，根据本发明的输入模块P1、复位模块P2、下拉模块P3、输出下拉控制模块P4和输出控制模块P5的结构不局限于图2所示的实施例。该实施例仅作为示例提供。
输入模块P1包括第一晶体管T1，其栅极连接输入信号端Input N，其源极连接高电平端VGH，其漏极连接上拉控制节点PU。在该实施例中，第一晶体管T1的栅极对应于输入模块的控制端，源极对应于输入模块的输入端，漏极对应于输入模块的输出端。
复位模块P2包括第二晶体管T2和第三晶体管T3；其中，第二晶体 管T2，其栅极连接第五级输出端OUT N+4，其源极连接移位寄存器单元的本级输出端OUT N，其漏极连接低电平端VGL；第三晶体管T3，其栅极连接第五级输出端OUT N+4，其源极连接上拉控制节点PU，其漏极连接低电平端VGL。在该实施例中，第二晶体管T2的栅极和第三晶体管T3的栅极对应于复位模块的控制端，第二晶体管T2的源极对应于复位模块的第一输入端，第三晶体管T3的源极对应于复位模块的第二输入端第二晶体管T2的漏极和第三晶体管T3的漏极对应于复位模块的输出端。
下拉模块P3包括第四晶体管T4和第五晶体管T5；其中，第四晶体管T4，其栅极连接下拉控制节点PD，其源极连接移位寄存器单元的本级输出端OUT N，其漏极连接低电平端VGL；第五晶体管T5，其栅极连接下拉控制节点PD，其源极连接上拉控制节点PU，其漏极连接低电平端VGL。在该实施例中，第四晶体管T4的栅极和第五晶体管T5的栅极对应于下拉模块的控制端，第四晶体管T4的源极对应于下拉模块的第一输入端，第五晶体管T5的源极对应于下拉模块的第二输入端，第四晶体管T4的漏极和第五晶体管T5的漏极对应于下拉模块的输出端。
输出下拉控制模块P4包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10；其中，第六晶体管T6，其栅极连接上拉控制节点PU，其源极连接下拉控制节点PD，其漏极连接低电平端VGL；第七晶体管T7，其栅极连接第八晶体管T8的漏极和第九晶体管T9的栅极，其源极连接高电平端VGH，其漏极连接下拉控制节点PD；第八晶体管T8，其栅极连接高电平端VGH、其源极连接高电平端VGH，其漏极连接第九晶体管T9的栅极；第九晶体管T9，其栅极连接第七晶体管的栅极，其源极连接高电平端VGH，其漏极连接输出控制节点PB；第十晶体管T10，其栅极连接移位寄存器单元的本级输出端OUT N，其源极连接输出控制节点PB，其漏极连接低电平端VGL。在该实施例中，第六晶体管T6的栅极对应于输出下拉控制模块P4的第一控制端，第六晶体管T6的源极对应于输出下拉控制模块P4的第一输入端，第六晶体管的漏极对应于输出下拉控制模块P4的第一输出端；第七晶体管的栅极对应于输出下拉控制模块P4的第二控制端，第七晶体管的源极对应于输出下拉控制模块P4的第二输入端，第七晶体管的漏极对应于输出下拉控制模块P4 的第二输出端；第八晶体管的栅极对应于输出下拉控制模块P4的第三控制端，第八晶体管的源极对应于输出下拉控制模块P4的第三输入端，第八晶体管的漏极对应于输出下拉控制模块P4的输出端；第九晶体管的栅极对应于输出下拉控制模块P4的第四控制端，第九晶体管的源极对应于输出下拉控制模块P4的第四输入端，第九晶体管的漏极对应于输出下拉控制模块P4的第四输出端；第十晶体管的栅极对应于输出下拉控制模块P4的第五控制端，第十晶体管的源极对应于输出下拉控制模块P4的第五输入端，第十晶体管的漏极对应于输出下拉控制模块P4的第五输出端。
输出控制模块P5包括第一输出控制子模块和第二输出控制子模块，第一输出控制子模块用于输出栅极驱动信号，第二输出控制子模块用于输出电源使能信号和电源功率提供信号。具体的，第一输出控制子模块包括第十一晶体管T11、第十二晶体管T12和第十三晶体管T13，第二输出控制子模块包括第十四晶体管T14和第十五晶体管T15；其中，第十一晶体管T11，其栅极连接上拉控制节点PU，其源极连接第一时钟信号端CL1，其漏极连接移位寄存器单元的本级输出端OUT N；第十二晶体管T12，其栅极连接移位寄存器单元的本级输出端OUT N，其源极连接高电平端VGH，其漏极连接栅极驱动信号端GATE；第十三晶体管T13，其栅极连接第四级输出端OUT N+3，其源极连接栅极驱动信号端GATE，其漏极连接低电平端VGL；第十四晶体管T14，其栅极连接第二时钟信号端CL2，其源极连接输出控制节点PB，其漏极连接电源功率提供信号端Elvdd；第十五晶体管T15，其栅极连接第三时钟信号端CL3，其源极连接输出控制节点PB，其漏极连接输出电源使能信号端EM。在该实施例中，第十一晶体管的栅极对应于输出控制模块P5的第一控制端，第十一晶体管的源极对应于输出控制模块P5的第一输入端，第十一晶体管的漏极对应于输出控制模块P5的第一输出端；第十二晶体管的栅极对应于输出控制模块P5的第二控制端，第十二晶体管的源极对应于输出控制模块P5的第二输入端，第十二晶体管的漏极对应于输出控制模块P5的第二输出端；第十三晶体管的栅极对应于输出控制模块P5的第三控制端，第十三晶体管的源极对应于输出控制模块P5的第三输入端，第十三晶体管的漏极对应于输出控制模块P5的第三输出端；第十四晶体管的栅极对应于输出控制模块 P5的第四控制端，第十四晶体管的源极对应于输出控制模块P5的第四输入端，第十四晶体管的漏极对应于输出控制模块P5的第四输出端；第十五晶体管的栅极对应于输出控制模块P5的第五控制端，第十五晶体管的源极对应于输出控制模块P5的第五输入端，第十五晶体管的漏极对应于输出控制模块P5的第五输出端。
其中，输入模块P1、复位模块P2、下拉模块P3、输出下拉控制模块P4和输出控制模块P5的具体结构之间的具体连接情况如下：第一晶体管T1，其源极连接第十二晶体管T12的源极，其漏极连接第十一晶体管T11的栅极、第三晶体管T3的源极、第五晶体管T5的源极和第六晶体管T6的栅极；第二晶体管T2，其源极连接第十一晶体管T11的漏极、第十二晶体管T12的栅极、第四晶体管T4的源极和第十晶体管T10的栅极，其漏极连接第四晶体管T4的漏极、第五晶体管T5的漏极、第六晶体管T6的漏极、第十晶体管T10的漏极和第十三晶体管T13的漏极；第三晶体管T3，其源极连接第五晶体管T5的源极、第十一晶体管T11的栅极和第六晶体管T6的栅极，其漏极连接第五晶体管T5的漏极、第四晶体管T4的漏极、第六晶体管T6的漏极、第十晶体管T10的漏极和第十三晶体管T13的漏极；第四晶体管T4，其栅极连接第六晶体管T6的源极和第七晶体管T7的漏极，其源极连接第十一晶体管T11的漏极、第十二晶体管T12的栅极和第十晶体管T10的栅极，其漏极连接第六晶体管T6的漏极、第十晶体管T10的漏极和第十三晶体管T13的漏极；第五晶体管T5，其栅极连接第六晶体管T6的源极和第七晶体管T7的漏极，其源极连接第十一晶体管T11的栅极和第六晶体管T6的栅极，其漏极连接第六晶体管T6的漏极、第十晶体管T10的漏极和第十三晶体管T13的漏极；第六晶体管T6，其栅极连接第十一晶体管T11的栅极，其漏极连接第十三晶体管T13的漏极；第九晶体管T9，其漏极连接第十四晶体管T14的源极和第十五晶体管T15的源极；第十晶体管T10，其栅极连接第十二晶体管T12的栅极，其源极连接第十四晶体管T14的源极和第十五晶体管T15的源极，其漏极连接第十三晶体管T13的漏极。需要说明的是，上拉控制节点PU具体可以为第一晶体管T1的漏极和第十一晶体管T11的栅极的连接交点，下拉控制节点PD具体可以为第六晶体管T6的源极和第七晶体管T7的栅极的 连接交点，输出控制节点PB具体可以是第九晶体管T9的漏极和第十晶体管T10的源极的连接交点。
本实施例中以各个晶体管为P型晶体管为例进行说明，但需要说明的是，各个晶体管也可以为N型晶体管，晶体管为N型晶体管的电路设计也在本申请的保护范围之内。在该备选实施例中，各个晶体管的连接与上述实施例相同，只是相应输入端和输出端的连接交换。例如，第一晶体管的栅极对应于输入模块的控制端，漏极对应于输入模块的输入端，源极对应于输入模块的输出端。
请参阅图3，图3为与图2所示的移位寄存器单元对应的信号时序图，下面将结合图3并以各个晶体管为P型晶体管为例，对实施例二中的移位寄存器单元的驱动方法进行说明。需要说明的是，实施例一中的第一阶段包括A-B阶段、B-C阶段、C-D阶段、D-E阶段和E-F阶段，第二阶段包括F-G阶段和G-H阶段：
在A-B阶段，输入信号端Input N的信号为高电平信号，第一晶体管T1的栅极接收输入信号端Input N的高电平信号，第一晶体管T1开启，对上拉控制节点PU进行充电，上拉控制节点PU的信号为高电平信号；第十一晶体管T11的栅极接收上拉控制节点PU的高电平信号，第十一晶体管T11开启，第一时钟信号端CL1的信号为低电平信号，移位寄存器单元的本级输出端OUT N的信号为低电平信号，第十二晶体管T12关闭，栅极驱动信号端GATE的信号为低电平信号；上拉控制节点PU的信号为高电平信号，第六晶体管T6开启，下拉控制节点PD的信号为低电平信号，第四晶体管T4和第五晶体管T5均关闭；第十晶体管T10的栅极接收移位寄存器单元的本级输出端OUT N的低电平信号，第十晶体管T10关闭，故输出控制节点PB的信号为高电平信号；第二时钟信号端CL2的信号为低电平信号，第十四晶体管T14关闭，电源功率提供信号端Elvdd的信号为高电平信号；第三时钟信号端CL3的信号为高电平信号，第十五晶体管T15开启，电源使能信号端EM的信号为高电平信号。
在B-C阶段，输入信号端Input N的信号为低电平信号，第一晶体管T1关闭，上拉控制节点PU保持A-B阶段时的高电平信号；第十一晶体管T11开启，第一时钟信号端CL1的信号为高电平信号，移位寄存器单 元的本级输出端OUT N的信号为高电平信号，第十二晶体管T12的栅极接收移位寄存器单元的本级输出端OUT N的高电平信号，第十二晶体管T12开启，栅极驱动信号端GATE通过第十二晶体管T12接收高电平端VGH的高电平信号，并输出栅极驱动信号，栅极驱动信号为高电平信号；上拉控制节点PU的信号为高电平信号，第六晶体管T6开启，下拉控制节点PD的信号为低电平信号，第四晶体管T4和第五晶体管T5仍保持关闭状态；第十晶体管T10的栅极接收移位寄存器单元的本级输出端OUT N的高电平信号，第十晶体管T10开启，输出控制节点PB的信号为低电平信号；第二时钟信号端CL2的信号为高电平信号，第十四晶体管T14开启，电源功率提供信号端Elvdd输出电源功率提供信号，电源功率提供信号为低电平信号；第三时钟信号端CL3的信号为低电平信号，第十五晶体管T15关闭，电源使能信号端EM的信号保持为高电平信号。
在C-D阶段，输入信号端Input N的信号为高电平信号，第一晶体管T1开启，对上拉控制节点PU进行充电，上拉控制节点PU的信号为高电平信号；第十一晶体管T11开启，第一时钟信号端CL1的信号为低电平信号，移位寄存器单元的本级输出端OUT N的信号为低电平信号，第十二晶体管T12关闭，栅极驱动信号端GATE的信号保持为B-C阶段的高电平信号，即栅极驱动信号端GATE继续输出栅极驱动信号；上拉控制节点PU的信号为高电平信号，第六晶体管T6开启，下拉控制节点PD的信号为低电平信号，第四晶体管T4和第五晶体管T5均关闭；第十晶体管T10的栅极接收移位寄存器单元的本级输出端OUT N的低电平信号，第十晶体管T10关闭，故输出控制节点PB的信号为高电平信号；第二时钟信号端CL2的信号为高电平信号，第十四晶体管T14开启，电源功率提供信号端Elvdd的信号为高电平信号；第三时钟信号端CL3的信号为低电平信号，第十五晶体管T15关闭，电源使能信号端EM的信号保持为高电平信号。
在D-E阶段，输入信号端Input N的信号为低电平信号，第一晶体管T1关闭，上拉控制节点PU保持C-D阶段的高电平信号，第十一晶体管T11开启，第一时钟信号端CL1的信号为高电平信号，移位寄存器单元的本级输出端OUT N的信号为高电平信号，第十二晶体管T12的栅极接收 移位寄存器单元的本级输出端OUT N的高电平信号，第十二晶体管T12开启，栅极驱动信号端GATE通过第十二晶体管T12接收高电平端VGH的高电平信号，并输出栅极驱动信号，栅极驱动信号为高电平信号；上拉控制节点PU的信号为高电平信号，第六晶体管T6开启，下拉控制节点PD的信号为低电平信号，第四晶体管T4和第五晶体管T5仍保持关闭状态；第十晶体管T10的栅极接收移位寄存器单元的本级输出端OUT N的高电平信号，第十晶体管T10开启，输出控制节点PB的信号为低电平信号；第二时钟信号端CL2的信号为低电平信号，第十四晶体管T14关闭，电源功率提供信号端Elvdd的信号为高电平信号；第三时钟信号端CL3的信号为高电平信号，第十五晶体管T15开启，电源使能信号端EM输出电源使能信号，电源使能信号为低电平信号。
在E-F阶段，输入信号端Input N的信号为低电平信号，第一晶体管T1关闭，上拉控制节点PU保持D-E阶段的高电平信号，第十一晶体管T11开启，第一时钟信号端CL1的信号为低电平信号，移位寄存器单元的本级输出端OUT N的信号为低电平信号，第十二晶体管T12关闭；第四级输出端OUT N+3的信号为高电平信号，第十三晶体管T13开启，栅极驱动信号端GATE的信号为低电平信号；上拉控制节点PU的信号为高电平信号，第六晶体管T6开启，下拉控制节点PD的信号为低电平信号，第四晶体管T4和第五晶体管T5均关闭；第十晶体管T10的栅极接收移位寄存器单元的本级输出端OUT N的低电平信号，第十晶体管T10关闭，故输出控制节点PB的信号为高电平信号；第二时钟信号端CL2的信号为低电平信号，第十四晶体管T14关闭，电源功率提供信号端Elvdd的信号为高电平信号；第三时钟信号端CL3的信号为高电平信号，第十五晶体管T15开启，电源使能信号端EM的信号为高电平信号。
在F-G阶段，输入信号端Input N的信号为低电平信号，第一晶体管T1关闭；第五级输出端OUT N+4的信号为高电平信号，第二晶体管T2和第三晶体管T3均开启，通过第二晶体管T2对移位寄存器单元的本级输出端OUT N进行放电，移位寄存器单元的本级输出端OUT N复位至低电平信号，通过第三晶体管T3对上拉控制节点PU进行放电，上拉控制节点PU复位至低电平信号；第六晶体管T6的栅极接收上拉控制节点PU的 低电平信号，第六晶体管T6关闭，故下拉控制节点PD为高电平信号；第四晶体管T4的栅极和第五晶体管T5的栅极接收下拉控制节点PD的高电平信号，第四晶体管T4和第五晶体管T5均开启，第四晶体管T4进一步对移位寄存器单元的本级输出端OUT N进行放电，第五晶体管T5进一步对上拉控制节点PU进行放电；移位寄存器单元的本级输出端OUT N的信号为低电平信号，第十晶体管T10关闭，输出控制节点PB为高电平信号；第二时钟信号端CL2的信号为高电平信号，第十四晶体管T14开启，电源功率提供信号端Elvdd的信号为高电平信号；第三时钟信号端CL3的信号为低电平信号，第十五晶体管T15关闭，电源使能信号端EM的信号为高电平信号。
在G-H阶段，输入信号端Input N的信号为低电平信号，第一晶体管T1关闭；第五级输出端OUT N+4的信号为低电平信号，第二晶体管T2和第三晶体管T3均关闭，移位寄存器单元的本级输出端OUT N保持F-G阶段的低电平信号，上拉控制节点PU保持F-G阶段的低电平信号；第六晶体管T6的栅极接收上拉控制节点PU的低电平信号，第六晶体管T6关闭，故下拉控制节点PD为高电平信号；第四晶体管T4的栅极和第五晶体管T5的栅极接收下拉控制节点PD的高电平信号，第四晶体管T4和第五晶体管T5均开启，第四晶体管T4进一步对移位寄存器单元的本级输出端OUT N进行放电，第五晶体管T5进一步对上拉控制节点PU进行放电；移位寄存器单元的本级输出端OUT N的信号为低电平信号，第十晶体管T10关闭，输出控制节点PB为高电平信号；第二时钟信号端CL2的信号为高电平信号，第十四晶体管T14开启，电源功率提供信号端Elvdd的信号为高电平信号；第三时钟信号端CL3的信号为低电平信号，第十五晶体管T15关闭，电源使能信号端EM的信号为高电平信号。
在A-H阶段，第七晶体管T7、第八晶体管T8和第九晶体管T9均保持开启，其中第八晶体管T8输出为高，控制第七晶体管T7和第九晶体管T9开启，从而分别为PD点和PB点写入高电平信号。
虽然在图2中示出了第八晶体管T8的栅极和源极均与高电平端VGH连接，但是，也可以将其与第一时钟信号CL1的反向信号相连，从而确保PU点在PU点之前为高电平，使得PU点为高电平时能对PD点进行放电。
需要说明的是，第二时钟信号端CL2的信号与第三时钟信号端CL3的信号互为反相信号；第一时钟信号端CL1的信号的频率与第二时钟信号端CL2的信号的频率不同，优选的，第一时钟信号端CL1的信号的频率为第二时钟信号端CL2的信号的频率的2倍。
实施例三
请参阅图4，本发明还提供了一种移位寄存器，该移位寄存器包括多级上述实施例一、二中的移位寄存器单元，其中，前一级移位寄存器单元的本级输出端连接后一级移位寄存器单元的输入信号端。比如，如图4所示，第一级移位寄存器单元UNIT1的本级输出端OUT 1连接第二级移位寄存器单元UNIT2的输入信号端Input 2。
进一步地，所述移位寄存器包括N级上述实施例一、二中的移位寄存器单元，N为大于或等于4的整数；其中，第i级移位寄存器单元的第一时钟信号端CL1与第i+2级移位寄存器单元的第一时钟信号端CL1均输入第一时钟信号，第i+1级移位寄存器单元的第一时钟信号端CL1与第i+3级移位寄存器单元的第一时钟信号端CL1均输入第一时钟信号的反相信号；第i级移位寄存器单元的第二时钟信号端CL2与第i+1级移位寄存器单元的第二时钟信号端CL2均输入第二时钟信号，第i+2级移位寄存器单元的第二时钟信号端CL2与第i+3级移位寄存器单元的第二时钟信号端CL2均输入第二时钟信号的反向信号；第i级移位寄存器单元的第三时钟信号端CL3与第i+1级移位寄存器单元的第三时钟信号端CL3均输入第二时钟信号的反向信号，第i+2级移位寄存器单元的第三时钟信号端CL3与第i+3级移位寄存器单元的第三时钟信号端CL3均输入第二时钟信号，i为整数，i≥1且i+3≤N。比如：如图4所示，第一级移位寄存器单元UNIT1的第一时钟信号端CL1输入第一时钟信号CLK1，第二时钟信号端CL2输入第二时钟信号CLK2，第三时钟信号端CL3输入第二时钟信号的反相信号CLK2B，第一复位端Reset 11连接第四级移位寄存器的输出端OUT 4，第二复位端Reset 12连接第五级寄存器的输出端OUT 5；第二级移位寄存器单元UNIT 2的第一时钟信号端CL1输入第一时钟信号的反相信号CLK1B，第二时钟信号端CL2输入第二时钟信号CLK2，第三时钟信号端CL3输入第二时钟信号的反相信号CLK2B，第一复位端Reset 21连接第 五级移位寄存器的输出端OUT 5，第二复位端Reset 22连接第六级寄存器的输出端OUT 6；第三级移位寄存器单元UNIT 3的第一时钟信号端CL1输入第一时钟信号CLK1，第二时钟信号端CL2输入第二时钟信号的反相信号CLK2B，第三时钟信号端CL3输入第二时钟信号CLK2，第一复位端Reset 31连接第六级移位寄存器的输出端OUT 6，第二复位端Reset 32连接第七级寄存器的输出端OUT 7；第四级移位寄存器单元UNIT 4的第一时钟信号端CL1输入第一时钟信号的反相信号CLK1B，第二时钟信号端CL2输入第二时钟信号的反相信号CLK2B，第三时钟信号端CL3输入第二时钟信号CLK2，第一复位端Reset 41连接第七级移位寄存器的输出端OUT 7，第二复位端Reset 42连接第八级寄存器的输出端OUT 8；第五级移位寄存器单元UNIT 5的第一时钟信号端CL1输入第一时钟信号CLK1，第二时钟信号端CL2输入第二时钟信号CLK2，第三时钟信号端CL3输入第二时钟信号的反相信号CLK2B，第一复位端Reset 51连接第八级移位寄存器的输出端OUT 8，第二复位端Reset 52连接第九级寄存器的输出端OUT 9，其余更多级的移位寄存器单元的连接情况以此类推。
在图4中未示出各级移位寄存器单元的栅极驱动信号输出端、电源使能信号输出端和电源功率提供信号输出端的连接。显然，各级移位寄存器单元输出的栅极驱动信号、电源使能信号和电源功率提供信号用于驱动相应的一行像素单元。即，各级移位寄存器单元的栅极驱动信号输出端、电源使能信号输出端和电源功率提供信号输出端与相应的像素单元的端子相连。
需要说明的是，所述移位寄存器中的移位寄存器单元与上述实施例一、二中的移位寄存器单元具有的优势相同，此处不再赘述。
请参阅图5，图5为与实施例三中的移位寄存器对应的信号时序图，移位寄存器的具体驱动方法参见组成移位寄存器的移位寄存器单元的驱动方法，图5的信号时序说明也可以参照图3对应的信号时序说明。
当然，考虑到晶体管的充放电，为了确保各个移位寄存器单元的驱动时序，可以提供第三时钟信号，其相对于第二时钟信号滞后，例如，相对于第二时钟信号滞后半个时钟周期。在移位寄存器包括N级移位寄存器单元，其中N为大于或等于4的整数的实施例中，第i级移位寄存器单元的 第一时钟信号端CL1与第i+2级移位寄存器单元的第一时钟信号端CL1均输入第一时钟信号，第i+1级移位寄存器单元的第一时钟信号端CL1与第i+3级移位寄存器单元的第一时钟信号端CL1均输入第一时钟信号的反相信号；第i级移位寄存器单元的第二时钟信号端CL2输入第二时钟信号，第i+1级移位寄存器单元的第二时钟信号端CL2输入第三时钟信号，第i+2级移位寄存器单元的第二时钟信号端CL2输入第二时钟信号的反向信号，第i+3级移位寄存器单元的第二时钟信号端CL2输入第三时钟信号的反向信号；第i级移位寄存器单元的第三时钟信号端CL3输入第二时钟信号的反向信号，第i+1级移位寄存器单元的第三时钟信号端CL3输入第三时钟信号的反向信号，第i+2级移位寄存器单元的第三时钟信号端CL3输入第二时钟信号，第i+3级移位寄存器单元的第三时钟信号端CL3输入第三时钟信号，i为整数，i≥1且i+3≤N。比如：如图6所示，第一级移位寄存器单元UNIT 1的第一时钟信号端CL1输入第一时钟信号CLK1，第二时钟信号端CL2输入第二时钟信号CLK2，第三时钟信号端CL3输入第二时钟信号的反相信号CLK2B，第一复位端Reset 11连接第四级移位寄存器的输出端OUT 4，第二复位端Reset 12连接第五级寄存器的输出端OUT 5；第二级移位寄存器单元UNIT 2的第一时钟信号端CL1输入第一时钟信号的反相信号CLK1B，第二时钟信号端CL2输入第三时钟信号CLK3，第三时钟信号端CL3输入第三时钟信号的反相信号CLK3B，第一复位端Reset 21连接第五级移位寄存器的输出端OUT 5，第二复位端Reset 22连接第六级寄存器的输出端OUT 6；第三级移位寄存器单元UNIT 3的第一时钟信号端CL1输入第一时钟信号CLK1，第二时钟信号端CL2输入第二时钟信号的反相信号CLK2B，第三时钟信号端CL3输入第二时钟信号CLK2，第一复位端Reset 31连接第六级移位寄存器的输出端OUT 6，第二复位端Reset 32连接第七级寄存器的输出端OUT 7；第四级移位寄存器单元UNIT 4的第一时钟信号端CL1输入第一时钟信号的反相信号CLK1B，第二时钟信号端CL2输入第三时钟信号的反相信号CLK3B，第三时钟信号端CL3输入第三时钟信号CLK3，第一复位端Reset 41连接第七级移位寄存器的输出端OUT 7，第二复位端Reset 42连接第八级寄存器的输出端OUT 8；第五级移位寄存器单元UNIT 5的第一时钟信号端CL1输入第一 时钟信号CLK1，第二时钟信号端CL2输入第二时钟信号CLK2，第三时钟信号端CL3输入第二时钟信号的反相信号CLK2B，第一复位端Reset 51连接第八级移位寄存器的输出端OUT 8，第二复位端Reset 52连接第九级寄存器的输出端OUT 9，其余更多级的移位寄存器单元的连接情况以此类推。
图7为与该实施例中的移位寄存器对应的信号时序图，移位寄存器的具体驱动方法参见组成移位寄存器的移位寄存器单元的驱动方法，图7的信号时序说明也可以参照图3对应的信号时序说明。
实施例四
本发明还提供了一种显示装置，该显示装置包括上述实施例三中的移位寄存器，其中，移位寄存器中的移位寄存器单元提供的输出电源使能信号、电源功率提供信号和栅极驱动信号用于驱动显示装置中的像素单元。所述显示装置中的移位寄存器与上述实施例中的移位寄存器具有的优势相同，此处不再赘述。具体的，显示装置可以为有机发光二极管显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。对于驱动方法实施例而言，由于其应用于装置实施例，相关之处参见装置实施例的部分说明即可。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种移位寄存器单元，其特征在于，包括：
    输入模块，其控制端与输入信号端连接，输入端与高电平端连接，输出端与上拉控制节点连接，所述输入模块用于在所述输入信号端的信号的控制下在上拉控制节点输出上拉控制信号；
    复位模块，其控制端与第五级输出端连接，第一输入端与移位寄存器单元的本级输出端连接，第二输入端与上拉控制节点连接，输出端与低电平端连接，所述第五级输出端为移位寄存器单元作为第一级移位寄存器单元时对应的第五级移位寄存器单元的输出端，所述复位模块用于对所述移位寄存器单元的本级输出端和所述上拉控制节点进行复位；
    下拉模块，其控制端与下拉控制节点连接，第一输入端与移位寄存器单元的本级输出端连接，第二输入端与上拉控制节点连接，输出端与低电平端连接，所述下拉模块用于对所述上拉控制节点和所述移位寄存器单元的本级输出端进行放电；
    输出下拉控制模块，其第一控制端与上拉控制节点连接，第一输入端与下拉控制节点连接，第一输出端与低电平端连接，第二控制端与一中间节点连接，第二输入端与高电平端连接，第二输出端与下拉控制节点连接，第三控制端和第三输入端与高电平端连接，第三输出端与所述中间节点连接，第四控制端与所述中间节点连接，第四输入端与高电平端连接，第四输出端与输出控制节点连接，第五控制端与移位寄存器单元的本级输出端连接，第五输入端与输出控制节点连接，第五输出端与低电平端连接；所述输出下拉控制模块用于生成电源使能信号和电源功率提供信号；
    输出控制模块，其第一控制端与上拉控制节点连接，第一输入端与第一时钟信号端连接，第一输出端与移位寄存器单元的本级输出端连接，第二控制端与移位寄存器单元的本级输出端连接，第二输入端与高电平端连接，第二输出端与栅极驱动信号端连接，第三控制端与第四级输出端连接，第三输入端与栅极驱动信号端连接，第三输出端与低电平端连接，第四控制端与第二时钟信号端连接，第四输入端与输出控制节点连接，第四输出端与电源功率提供信号端连接，第五控制端与第三时钟信号端连接，第五 输入端与输出控制节点连接，第五输出端与输出电源使能信号端连接，所述第四级输出端为所述移位寄存器单元作为第一级移位寄存器单元时对应的第四级移位寄存器单元的输出端，所述输出控制模块用于生成栅极驱动信号，并输出所述电源使能信号、所述电源功率提供信号和所述栅极驱动信号。
  2. 根据权利要求1所述的移位寄存器单元，其特征在于，所述输出控制模块包括第一输出控制子模块和第二输出控制子模块，所述第一输出控制子模块用于输出所述栅极驱动信号，所述第二输出控制子模块用于输出所述输出电源使能信号和所述电源功率提供信号。
  3. 根据权利要求1或2所述的移位寄存器单元，其特征在于，所述输入模块包括第一晶体管，其栅极连接所述输入信号端，其源极连接所述高电平端和所述输出控制模块，其漏极连接所述上拉控制节点。
  4. 根据权利要求1-3之一所述的移位寄存器单元，其特征在于，所述复位模块包括第二晶体管和第三晶体管；
    其中，所述第二晶体管，其栅极连接所述第三晶体管的栅极，其源极连接所述移位寄存器单元的本级输出端，其漏极连接所述低电平端；
    所述第三晶体管，其栅极连接所述第五级输出端，其源极连接所述上拉控制节点，其漏极连接所述低电平端。
  5. 根据权利要求1-4之一所述的移位寄存器单元，其特征在于，所述下拉模块包括第四晶体管和第五晶体管；
    其中，所述第四晶体管，其栅极连接所述下拉控制节点，其源极连接所述移位寄存器单元的本级输出端，其漏极连接所述低电平端；
    所述第五晶体管，其栅极连接所述下拉控制节点，其源极连接所述上拉控制节点，其漏极连接所述低电平端。
  6. 根据权利要求1-5之一所述的移位寄存器单元，其特征在于，所述输出下拉控制模块包括第六晶体管、第七晶体管、第八晶体管、第九晶体管和第十晶体管；
    其中，所述第六晶体管，其栅极连接所述上拉控制节点，其源极连接所述下拉控制节点，其漏极连接所述低电平端；
    所述第七晶体管，其栅极连接所述第八晶体管的漏极和第九晶体管的 栅极，其源极连接所述高电平端，其漏极连接所述下拉控制节点；
    所述第八晶体管，其栅极连接所述高电平端，其源极连接所述高电平端，其漏极连接所述第九晶体管的栅极；
    所述第九晶体管，其栅极连接第七晶体管的栅极，其源极连接高电平端VGH，其漏极连接所述输出控制节点；
    所述第十晶体管，其栅极连接所述移位寄存器单元的本级输出端，其源极连接所述输出控制节点，其漏极连接所述低电平端。
  7. 根据权利要求2-6之一所述的移位寄存器单元，其特征在于，所述第一输出控制子模块包括第十一晶体管、第十二晶体管和第十三晶体管，所述第二输出控制子模块包括第十四晶体管和第十五晶体管；
    其中，所述第十一晶体管，其栅极连接所述上拉控制节点，其源极连接所述第一时钟信号端，其漏极连接所述移位寄存器单元的本级输出端；
    所述第十二晶体管，其栅极连接所述移位寄存器单元的本级输出端，其源极连接所述高电平端，其漏极连接所述栅极驱动信号端；
    所述第十三晶体管，其栅极连接所述第四级输出端，其源极连接所述栅极驱动信号端，其漏极连接所述低电平端；
    所述第十四晶体管，其栅极连接所述第二时钟信号端，其源极连接所述输出控制节点，其漏极连接所述电源功率提供信号端；
    所述第十五晶体管，其栅极连接所述第三时钟信号端，其源极连接所述输出控制节点，其漏极连接所述输出电源使能信号端。
  8. 根据权利要求7所述的移位寄存器单元，其特征在于，所述第一晶体管，其源极连接所述第十二晶体管的源极，其漏极连接所述第十一晶体管的栅极、所述第三晶体管的源极、所述第五晶体管的源极和所述第六晶体管的栅极；
    所述第二晶体管，其源极连接所述第十一晶体管的漏极、第十二晶体管的栅极、所述第四晶体管的源极和所述第十晶体管的栅极，其漏极连接所述第四晶体管的漏极、所述第五晶体管的漏极、所述第六晶体管的漏极、所述第十晶体管的漏极和所述第十三晶体管的漏极；
    所述第三晶体管，其源极连接所述第五晶体管的源极、所述第十一晶体管的栅极和所述第六晶体管的栅极，其漏极连接所述第五晶体管的漏极、 所述第四晶体管的漏极、所述第六晶体管的漏极、所述第十晶体管的漏极和所述第十三晶体管的漏极；
    所述第四晶体管，其栅极连接所述第六晶体管的源极和所述第七晶体管的漏极，其源极连接所述第十一晶体管的漏极、所述第十二晶体管的栅极和所述第十晶体管的栅极，其漏极连接所述第六晶体管的漏极、所述第十晶体管的漏极和所述第十三晶体管的漏极；
    所述第五晶体管，其栅极连接所述第六晶体管的源极和所述第七晶体管的漏极，其源极连接所述第十一晶体管的栅极和所述第六晶体管的栅极，其漏极连接所述第六晶体管的漏极、所述第十晶体管的漏极和所述第十三晶体管的漏极；
    所述第六晶体管，其栅极连接所述第十一晶体管的栅极，其漏极连接所述第十三晶体管的漏极；
    所述第九晶体管，其漏极连接所述第十四晶体管的源极和所述第十五晶体管的源极；
    所述第十晶体管，其栅极连接所述第十二晶体管的栅极，其源极连接所述第十四晶体管的源极和所述第十五晶体管的源极，其漏极连接所述第十三晶体管的漏极。
  9. 根据权利要求1-8之一所述的移位寄存器单元，其特征在于，所述第一时钟信号端的信号的频率与所述第二时钟信号端的信号的频率不同；所述第二时钟信号端的信号与所述第三时钟信号端的信号互为反相信号。
  10. 一种根据权利要求1所述的移位寄存器单元的驱动方法，其特征在于，包括：
    第一阶段，输入模块接收输入信号端的高电平信号，利用高电平端的高电平信号为上拉控制节点充电；输出控制模块接收所述上拉控制节点的高电平信号和第一时钟信号端的信号，为移位寄存器单元的本级输出端提供信号，根据所述移位寄存器单元的本级输出端的信号和第四级输出端的信号，在栅极驱动信号端输出栅极驱动信号；输出下拉控制模块接收所述移位寄存器单元的本级输出端的信号和所述高电平端的高电平信号，在输出控制节点生成电源使能信号和电源功率提供信号；输出控制模块接收第二时钟信号端的信号和第三时钟信号端的信号，在所述电源使能信号端和 所述电源功率提供信号端分别输出所述电源使能信号和所述电源功率提供信号；
    第二阶段，复位模块接收第五级输出端的高电平信号，将所述移位寄存器单元的本级输出端和所述上拉控制节点复位至低电平信号；输出下拉控制模块接收所述上拉控制节点的低电平信号，为下拉控制节点提供高电平信号；所述下拉模块接收所述下拉控制节点的高电平信号，对所述上拉控制节点和所述移位寄存器单元的本级输出端进行放电；所述输出控制模块接收所述上拉控制节点的低电平信号和所述第四级输出端的信号，在所述栅极驱动信号端输出低电平信号；所述输出下拉控制模块接收所述移位寄存器单元的本级输出端的信号和所述高电平端的高电平信号，在输出控制节点生成高电平信号；所述输出控制模块接收所述第二时钟信号端的信号和所述第三时钟信号端的信号，在所述电源使能信号端和所述电源功率提供信号端输出均为高电平信号的输出电源使能信号和电源功率提供信号。
  11. 根据权利要求10所述的移位寄存器单元的驱动方法，其特征在于，当应用于根据权利要求9所述的移位寄存器单元时，所述第一阶段具体包括：
    第一晶体管的栅极接收输入信号端的高电平信号时，所述第一晶体管开启，利用高电平端的高电平信号为上拉控制节点充电；所述第一晶体管的栅极接收输入信号端的低电平信号时，所述第一晶体管关闭，所述上拉控制节点的信号保持为高电平信号；
    第十一晶体管的栅极接收所述上拉控制节点的高电平信号，所述第十一晶体管开启，所述第十一晶体管接收第一时钟信号端的信号，将所述第一时钟信号端的信号传输至移位寄存器单元的本级输出端，作为所述移位寄存器单元的本级输出端的信号；
    第十二晶体管的栅极接收所述移位寄存器单元的本级输出端的信号，所述第十二晶体管开启或关闭，所述栅极驱动信号端输出栅极驱动信号或低电平信号；
    第十晶体管的栅极接收所述移位寄存器单元的本级输出端的信号和高电平端的高电平信号，输出控制节点生成所述电源使能信号和所述电源 功率提供信号；
    第十四晶体管的栅极接收第二时钟信号端的高电平信号，所述第十四晶体管开启，所述电源功率提供信号端输出所述电源功率提供信号或高电平信号；
    第十五晶体管的栅极接收第三时钟信号端的高电平信号，所述第十五晶体管开启，所述电源使能信号端输出所述电源使能信号或高电平信号；
    其中，第二时钟信号端的信号与第三时钟信号端的信号互为反相信号。
  12. 根据权利要求10所述的移位寄存器单元的驱动方法，其特征在于，当应用于根据权利要求9所述的移位寄存器单元时，所述第二阶段具体包括：
    第二晶体管的栅极接收第五级输出端的高电平信号，所述第二晶体管开启，将所述移位寄存器单元的本级输出端复位至低电平信号；
    第三晶体管的栅极接收第五级输出端的高电平信号，所述第二晶体管开启，将所述上拉控制节点复位至低电平信号；
    第六晶体管的栅极接收所述上拉控制节点的低电平信号，第六晶体管关闭；
    第八晶体管的栅极接收所述高电平端的高电平信号，所述第八晶体管开启；
    第七晶体管的栅极通过所述第八晶体管接收所述高电平端的高电平信号，所述第七晶体管开启，为所述下拉控制节点提供高电平信号；
    第四晶体管的栅极接收所述下拉控制节点的高电平信号，所述第四晶体管开启，对所述移位寄存器单元的本级输出端进行放电；
    第五晶体管的栅极接收所述下拉控制节点的高电平信号，所述第五晶体管开启，对所述上拉控制节点进行放电；
    所述第十晶体管的栅极接收所述移位寄存器单元的本级输出端的低电平信号，所述第十晶体管关闭；
    第九晶体管的栅极通过第八晶体管接收所述高电平端的高电平信号，所述第九晶体管开启，为所述输出控制节点提供高电平信号；
    第十四晶体管的栅极接收第二时钟信号端的高电平信号，所述第十四晶体管开启，所述电源功率提供信号端输出高电平信号；
    第十五晶体管的栅极接收第三时钟信号端的高电平信号，所述第十五晶体管开启，所述电源使能信号端输出高电平信号；
    其中，第二时钟信号端的信号与第三时钟信号端的信号互为反相信号。
  13. 一种移位寄存器，其特征在于，包括级联的多级上述权利要求1-9中任意一项所述的移位寄存器单元，其中，前一级移位寄存器单元的本级输出端连接后一级移位寄存器单元的输入信号端。
  14. 根据权利要求13所述的移位寄存器，其特征在于，所述移位寄存器包括N级所述移位寄存器单元，N为大于或等于4的整数；
    其中，第i级移位寄存器单元的第一时钟信号端与第i+2级移位寄存器单元的第一时钟信号端均输入第一时钟信号，第i+1级移位寄存器单元的第一时钟信号端与第i+3级移位寄存器单元的第一时钟信号端均输入第一时钟信号的反相信号；第i级移位寄存器单元的第二时钟信号端与第i+1级移位寄存器单元的第二时钟信号端均输入第二时钟信号，第i+2级移位寄存器单元的第二时钟信号端与第i+3级移位寄存器单元的第二时钟信号端均输入第二时钟信号的反向信号；第i级移位寄存器单元的第三时钟信号端与第i+1级移位寄存器单元的第三时钟信号端均输入第二时钟信号的反向信号，第i+2级移位寄存器单元的第三时钟信号端与第i+3级移位寄存器单元的第三时钟信号端均输入第二时钟信号，i为整数，i≥1且i+3≤N。
  15. 一种显示装置，其特征在于，包括如权利要求13或14所述的移位寄存器，其中，所述移位寄存器中的移位寄存器单元提供的输出电源使能信号、电源功率提供信号和栅极驱动信号用于驱动所述显示装置中的像素单元。
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