WO2020192340A1 - 移位寄存器、栅极驱动电路及其驱动方法、显示装置 - Google Patents

移位寄存器、栅极驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2020192340A1
WO2020192340A1 PCT/CN2020/076669 CN2020076669W WO2020192340A1 WO 2020192340 A1 WO2020192340 A1 WO 2020192340A1 CN 2020076669 W CN2020076669 W CN 2020076669W WO 2020192340 A1 WO2020192340 A1 WO 2020192340A1
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Prior art keywords
signal
terminal
coupled
node
shift register
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PCT/CN2020/076669
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English (en)
French (fr)
Inventor
刘鹏
刘白灵
李付强
王志冲
冯京
栾兴龙
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2020192340A1 publication Critical patent/WO2020192340A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit and a driving method thereof, and a display device.
  • a gate driving device is usually used to provide a gate driving signal to the gate of each thin film transistor (TFT, Thin Film Transistor) in the pixel area.
  • the gate driving device can be formed on the array substrate of the display through an array process, that is, an array substrate line drive (Gate Driver on Array, GOA) process.
  • GOA array substrate line drive
  • This integrated process not only saves costs, but also can be achieved on both sides of the liquid crystal panel (Panel)
  • the symmetrical and beautiful design also eliminates the bonding area of the gate integrated circuit (IC) and the fan-out wiring space, so that a narrow frame design can be realized; and, This integrated process can also omit the bonding process in the gate scan line direction, thereby improving productivity and yield.
  • the embodiment of the present disclosure provides a shift register, including:
  • the input control circuit is configured to provide the signal of the first reference signal terminal to the first node in response to the effective signal of the signal input terminal;
  • the reset control circuit is configured to provide the signal of the second reference signal terminal to the first node in response to the effective signal of the reset signal terminal;
  • the first output control circuit is configured to control the signal output of the gate signal output terminal in response to the potential of the first node
  • the signal output termination circuit is configured to terminate the conduction state between the first reference signal terminal and the input control circuit in response to the effective signal of the signal output termination terminal in the partial scan mode, and terminate the second reference The conduction state between the signal terminal and the reset control circuit;
  • the signal output selection circuit is configured to output the valid signal of the selection terminal in response to the valid signal output from the gate signal output terminal when it is determined that the shift register is designated as the scanning start line in the partial scanning mode.
  • the signal is provided to the second node;
  • the signal output trigger circuit is configured to respond to the potential of the second node and provide the signal of the trigger signal terminal to all the signals in the partial scanning mode and when the shift register is designated as the scanning start line.
  • the signal output reset circuit is configured to provide the signal of the third reference signal terminal to the second node in response to the effective signal of the output reset signal terminal when it is determined that the full-screen scanning mode is restored.
  • the signal output termination circuit specifically includes: a first signal output termination circuit and a second signal output termination circuit; the first signal output termination circuit includes a first switching transistor, and The second signal output termination circuit includes a second switch transistor; wherein,
  • the gate of the first switch transistor is coupled to the signal output termination terminal, the first pole is coupled to the first reference signal terminal, and the second pole is coupled to the input control circuit;
  • the gate of the second switch transistor is coupled to the signal output termination terminal, the first pole is coupled to the second reference signal terminal, and the second pole is coupled to the reset control circuit.
  • the signal output selection circuit specifically includes: a third switch transistor; wherein,
  • the gate of the third switch transistor is coupled to the gate signal output terminal, the first pole is coupled to the signal output selection terminal, and the second pole is coupled to the second node.
  • the signal output reset circuit specifically includes: a fourth switch transistor; wherein,
  • the gate of the fourth switch transistor is coupled to the output reset signal terminal, the first pole is coupled to the third reference signal terminal, and the second pole is coupled to the second node.
  • the signal output trigger circuit specifically includes: a fifth switch transistor and a first capacitor; wherein,
  • the gate of the fifth switch transistor is coupled to the second node, the first pole is coupled to the trigger signal terminal, and the second pole is coupled to the first node;
  • the first capacitor has a first terminal coupled with the second node, and a second terminal coupled with the first node.
  • the signal output trigger circuit further includes: a sixth switch transistor; wherein,
  • the gate of the sixth switch transistor is coupled to the second terminal of the first capacitor, the first pole is coupled to the fourth reference signal terminal, and the second pole is coupled to the first node.
  • the input control circuit specifically includes: a seventh switch transistor; wherein,
  • a seventh switching transistor has its gate coupled to the signal input terminal, a first pole coupled to the second pole of the first switching transistor, and a second pole coupled to the first node.
  • the reset control circuit specifically includes: an eighth switch transistor; wherein,
  • the eighth switch transistor has its gate coupled to the reset signal terminal, the first pole is coupled to the second pole of the second switch transistor, and the second pole is coupled to the first node.
  • the above shift register further includes: a node control circuit configured to control the potential of the third node in response to the potential of the first node and the gate signal output terminal.
  • the node control circuit specifically includes: a ninth switch transistor, an eleventh switch transistor, a twelfth switch transistor, and a second capacitor; wherein,
  • a ninth switch transistor the gate and first pole of which are both coupled to the first clock signal terminal, and the second pole is coupled to the third node;
  • An eleventh switching transistor the gate of which is coupled to the first node, the first pole is coupled to the third node, and the second pole is coupled to the third reference signal terminal;
  • a twelfth switching transistor a gate of which is coupled to the gate signal output terminal, a first pole is coupled to the third node, and a second pole is coupled to the third reference signal terminal;
  • the first terminal of the second capacitor is coupled to the third node, and the second terminal is coupled to the third reference signal terminal.
  • the first output control circuit specifically includes: a thirteenth switching transistor and a third capacitor; wherein,
  • a thirteenth switching transistor the gate of which is coupled to the first node, the first pole is coupled to the second clock signal terminal, and the second pole is coupled to the gate signal output terminal;
  • the first terminal of the third capacitor is coupled to the first node, and the second terminal is coupled to the gate signal output terminal.
  • shift register further comprising: a second output control circuit configured to provide the signal of the third reference signal terminal to the gate signal output in response to the potential of the third node End and the first node.
  • the second output control circuit specifically includes: a tenth switching transistor and a fourteenth switching transistor; wherein,
  • a tenth switching transistor the gate of which is coupled to the third node, the first pole is coupled to the first node, and the second pole is coupled to the third reference signal terminal;
  • the fourteenth switching transistor has its gate coupled with the third node, a first pole coupled with the gate signal output terminal, and a second pole coupled with the third reference signal terminal.
  • shift register further includes: an initialization circuit configured to initialize the third node in response to the signal of the initialization signal terminal.
  • the initialization circuit specifically includes: a fifteenth switch transistor; wherein,
  • the gate and first pole of the fifteenth switch transistor are both coupled to the initialization signal terminal, and the second pole is coupled to the third node.
  • all switch transistors included in the shift register are N-type transistors.
  • the present disclosure also provides a gate drive circuit, including a plurality of cascaded shift registers of any of the above; wherein,
  • each stage of shift register is coupled to the signal input terminal of its adjacent next stage of shift register;
  • the gate signal output terminal of each stage of shift register is coupled to the reset signal terminal of the adjacent previous stage of shift register.
  • the present disclosure also provides a display device including the above-mentioned gate drive circuit.
  • the present disclosure also provides a driving method of the above-mentioned gate driving circuit, including:
  • FIG. 1 is a schematic diagram of a structure of a shift register provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of another structure of a shift register provided by an embodiment of the disclosure.
  • FIG. 3 is an input and output timing diagram corresponding to the shift register shown in FIG. 2;
  • FIG. 4 is another input and output timing diagram corresponding to the shift register shown in FIG. 2;
  • FIG. 5 is an input and output timing diagram corresponding to the gate driving circuit provided by the embodiments of the disclosure.
  • FIG. 6 is another input and output timing diagram corresponding to the gate driving circuit provided by the embodiments of the disclosure.
  • FIG. 7 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the disclosure.
  • the resolution of the traditional GOA circuit After the resolution of the traditional GOA circuit is determined, it can only scan from the first row of gate lines to the end of the last row of gate lines. Regardless of the specific actual needs of the display, all scanning and display must be performed from the start line to the end line. As the resolution of our mobile products is getting higher and higher, the power consumption also increases with the increase in resolution, resulting in a greatly reduced standby time for display products. Therefore, how to increase the standby time of a display product is a technical problem urgently needed to be solved by those skilled in the art.
  • a shift register provided by an embodiment of the present disclosure, as shown in FIG. 1, includes:
  • the input control circuit 1 which is coupled between the first node A, the signal input terminal Out N-1, and the first reference signal terminal CN, is configured to respond to the effective signal of the signal input terminal Out N-1 to set the first reference
  • the signal of the signal terminal CN is provided to the first node A;
  • the reset control circuit 2 which is coupled between the first node A, the reset signal terminal Out N+1, and the second reference signal terminal CNB, is configured to respond to the effective signal of the reset signal terminal Out N+1 to set the second reference
  • the signal of the signal terminal CNB is provided to the first node A;
  • the first output control circuit 3 which is coupled between the first node A and the gate signal output terminal Out N , is configured to control the signal output of the gate signal output terminal Out N in response to the potential of the first node A;
  • the first signal output termination circuit 4 is configured to terminate the connection between the first reference signal terminal CN and the first input control circuit 1 under the control of the signal output termination terminal CGE signal in the partial scan mode;
  • the second signal output The termination circuit 5 is configured to terminate the connection between the second reference signal terminal CNB and the second input control circuit 2 under the control of the signal output termination terminal CGE signal in the partial scan mode;
  • the signal output switching circuit includes: a signal output selection circuit 6, a signal output trigger circuit 7 and a signal output reset circuit 8; among them,
  • the signal output selection circuit 6 is configured to provide the signal of the signal output selection terminal CGI under the control of the gate signal output terminal Out N signal when it is determined that the shift register is designated as the scanning start line in the partial scanning mode To the second node B;
  • the signal output trigger circuit 7 is configured to provide the signal of the trigger signal terminal CGS to the first node under the control of the potential of the second node B in the partial scanning mode and when the shift register is designated as the scanning start line A;
  • the signal output reset circuit 8 is configured to provide the signal of the third reference signal terminal VGL to the second node B under the control of the output reset signal terminal CGR signal when it is determined to resume the full-screen scanning mode.
  • the above-mentioned shift register addeds a signal output switching circuit at the first node between the input control circuit 1 and the reset control circuit 2, wherein the signal output selection circuit 6 determines the shift register When it is designated as the scanning start line in the partial scanning mode, under the control of the gate signal output terminal Out N signal, the signal of the signal output selection terminal CGI is provided to the second node B, and the signal output trigger circuit 7 is configured as In the partial scan mode and when the shift register is designated as the scan start line, under the potential control of the second node B, the signal of the trigger signal terminal CGS is provided to the first node A instead of the input control circuit 1
  • the first node A is provided with a signal for controlling the output control circuit 3 to realize the function of any row shift register as the scanning start row.
  • a first signal output termination circuit is added between the first reference signal terminal CN and the input control circuit 1, and a second signal output termination circuit between the reset control circuit 2 and the second reference signal terminal CNB can realize any line
  • the shift register functions as the scanning end line.
  • the signal input terminal of the shift register N of the current stage may be coupled to the gate signal output terminal OUT N-1 of the shift register N-1 of the previous stage.
  • the reset signal terminal of the bit register N may be coupled to the gate signal output terminal OUT N+1 of the shift register N+1 of the next stage, or vice versa.
  • the signal of the first reference signal terminal CN is a high potential signal, and the signal of the second reference signal terminal CNB It is a low-level signal; when the reverse scan mode is adopted, the signal at the first reference signal terminal CN is a low-level signal, and the signal at the second reference signal terminal CNB is a high-level signal.
  • the signal output from the gate signal output terminal OUT N+1 of the next stage of shift register N+1 resets the current stage of shift register N; when using reverse scanning, the previous stage shifts The signal output from the gate signal output terminal OUT N-1 of the register N-1 resets the shift register N of this stage.
  • the first signal output termination circuit 4 specifically includes: a first switching transistor M1; ,
  • the gate of the first switch transistor M1 is coupled to the signal output termination terminal CGE, the first pole is coupled to the first reference signal terminal CN, and the second pole is coupled to the input control circuit 1.
  • the channel length L of the first switching transistor M1 may be designed to be 8 ⁇ m, and the channel width may be designed to be 15 ⁇ m.
  • the specific structure of the first signal output termination circuit 4 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be Other structures known to those skilled in the art are not limited here.
  • the second signal output termination circuit 5 specifically includes: a second switching transistor M2; ,
  • the gate of the second switch transistor M2 is coupled to the signal output termination terminal CGE, the first pole is coupled to the second reference signal terminal CNB, and the second pole is coupled to the reset control circuit 2.
  • the channel length L of the second switching transistor M2 may be designed to be 8 ⁇ m, and the channel width may be designed to be 15 ⁇ m.
  • the specific structure of the second signal output termination circuit 5 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be the present invention. Other structures known to those skilled in the art are not limited here.
  • the signal output selection circuit 6 specifically includes: a third switch transistor M3; wherein,
  • the gate of the third switch transistor M3 is coupled to the gate signal output terminal Out N , the first pole is coupled to the signal output selection terminal CGI, and the second pole is coupled to the second node B.
  • the channel length L of the third switching transistor M3 can be designed to be 8 ⁇ m, and the channel width can be designed to be 30 ⁇ m.
  • the resolution of the traditional shift register circuit can only scan from the first row of gate lines to the end of the last row of gate lines. Regardless of the specific actual needs of the display, it must be from the start line to the end line. Perform full scan display, as our mobile products have higher resolution, power consumption also increases with the increase in resolution, resulting in a greatly reduced standby time of display products.
  • the signal output selection circuit 6 in the signal output switching circuit in the shift register can scan the third row in the full-screen scan mode through the signal output selection terminal
  • the high potential signal input by CGI charges the second node B. Due to the bootstrap effect of the first capacitor C1, the potential of the second node B remains high until the third line scan of the next frame, so that it can be switched to the second node B. Partial scan mode from 3 lines to 8th line.
  • the specific structure of the signal output selection circuit 6 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may be known to those skilled in the art. Other structures of, are not limited here.
  • the signal output reset circuit 8 specifically includes: a fourth switch transistor M4; wherein,
  • the fourth switch transistor M4 has its gate and the output reset signal terminal coupled to the CGR, the first pole is coupled to the third reference signal terminal VGL, and the second pole is coupled to the second node B.
  • the channel length L of the fourth switching transistor M4 can be designed to be 8 ⁇ m, and the channel width can be designed to be 5 ⁇ m.
  • the shift register resumes the full-screen scan mode from the first line to the last line.
  • the shift of the partial scan The potential of the second node B of the register is reset, that is, the fourth switch transistor M4 is turned on under the control of the high potential signal of the output reset signal terminal CGR, and the low potential signal of the third reference signal terminal VGL is input to the second node B to ensure the first
  • the signal of the two node B is a low potential signal, which does not affect the operation of each shift register in the subsequent full-screen scan mode.
  • the specific structure of the signal output reset circuit 8 in the shift register is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be known to those skilled in the art. Other structures of, are not limited here.
  • the signal output trigger circuit 7 specifically includes: a fifth switch transistor M5 and a first capacitor C1;
  • the fifth switch transistor M5 has its gate coupled to the second node B, the first pole is coupled to the trigger signal terminal CGS, and the second pole is coupled to the first node A;
  • the first capacitor C1 has a first end coupled to the second node B, and a second end coupled to the first node A.
  • the channel length L of the fifth switching transistor M5 can be designed to be 8 ⁇ m, and the channel width can be designed to be 30 ⁇ m.
  • the first capacitor C1 can be designed to be 200f.
  • the trigger signal terminal CGS inputs a high potential signal to the first node A to charge the first node A to perform Scanning of the shift register.
  • the specific structure of the signal output trigger circuit 7 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may be known to those skilled in the art. Other structures of, are not limited here.
  • the signal output trigger circuit 7 may further include: a sixth switch transistor M6;
  • the sixth switch transistor M6 has its gate coupled to the second terminal of the first capacitor C1, the first pole is coupled to the fourth reference signal terminal VGH, and the second pole is coupled to the first node A; The signal of the fourth reference signal terminal VGH is provided to the first node A under the control of the node B.
  • the channel length L of the sixth switching transistor M6 can be designed to be 8 ⁇ m, and the channel width can be designed to be 30 ⁇ m.
  • the input control circuit 1 specifically includes: a seventh switch transistor M7; wherein,
  • the gate of the seventh switch transistor M7 is coupled to the signal input terminal OUT N-1 , the first pole is coupled to the second pole of the first switch transistor M1, and the second pole is coupled to the first node A.
  • the channel length L of the seventh switching transistor M7 can be designed to be 8 ⁇ m, and the channel width can be designed to be 30 ⁇ m.
  • the above is only an example to illustrate the specific structure of the input control circuit 1 in the shift register.
  • the specific structure of the input control circuit 1 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other known to those skilled in the art. The structure is not limited here.
  • the reset control circuit 2 specifically includes: an eighth switch transistor M8; wherein,
  • the eighth switch transistor M8 has its gate coupled to the reset signal terminal OUT N+1 , the first pole is coupled to the second pole of the second switch transistor M2, and the second pole is coupled to the first node A.
  • the channel length L of the eighth switching transistor M8 may be designed to be 8 ⁇ m, and the channel width may be designed to be 15 ⁇ m.
  • the specific structure of the reset control circuit 2 in the shift register is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may be other known to those skilled in the art. The structure is not limited here.
  • the shift register may further include: a node control circuit 9 configured to respond to the first node A and the gate signal output terminal Out N
  • the second output control circuit 10 is configured to respond to the potential of the third node D and provide the signal of the third reference signal terminal VGL to the gate signal output terminal Out N and the first A node A
  • the initialization circuit 11 is configured to initialize the third node D in response to the signal of the initialization signal terminal RST.
  • the node control circuit 9 specifically includes: a ninth switch transistor M9, an eleventh switch The transistor M11, the twelfth switching transistor M12 and the second capacitor C2; among them,
  • the ninth switch transistor M9 has its gate and first pole both coupled to the first clock signal terminal CK, and the second pole is coupled to the third node D;
  • the gate of the eleventh switching transistor M11 is coupled to the first node A, the first pole is coupled to the third node D, and the second pole is coupled to the third reference signal terminal VGL;
  • the twelfth switching transistor M12 has its gate coupled to the gate signal output terminal Out N of the shift register of the current stage, the first pole is coupled to the third node D, and the second pole is coupled to the third reference signal terminal VGL ;
  • the first terminal of the second capacitor C2 is coupled to the third node D, and the second terminal is coupled to the third reference signal terminal VGL.
  • the size of the eleventh switch transistor M11 is generally set larger than that of the ninth switch transistor M9 during process preparation, so that the size of the When the potential of A is high, the eleventh switch transistor M11 provides the signal of the third reference signal terminal VGL to the third node D at a rate greater than that of the ninth switch transistor M9 under the control of the signal of the first node A.
  • the channel length L of the ninth switching transistor M9 can be designed to be 8 ⁇ m, and the channel width can be designed to be 10 ⁇ m.
  • the channel length L of the eleventh switching transistor M11 may be designed to be 8 ⁇ m, and the channel width may be designed to be 18 ⁇ m.
  • the channel length L of the twelfth switching transistor M12 can be designed to be 8 ⁇ m, and the channel width can be designed to be 5 ⁇ m.
  • the second capacitor C2 can be designed to be 200f.
  • the above is only an example to illustrate the specific structure of the node control circuit 9 in the shift register.
  • the specific structure of the node control circuit 9 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other known to those skilled in the art. The structure is not limited here.
  • the first output control circuit 3 specifically includes: a thirteenth switching transistor M13 and a Three capacitors C3; among them,
  • the thirteenth switching transistor M13 has its gate coupled to the first node A, the first pole is coupled to the second clock signal terminal CKB, and the second pole is coupled to the gate signal output terminal Out N of the shift register of this stage ;
  • the first terminal of the third capacitor C3 is coupled to the first node A, and the second terminal is coupled to the gate signal output terminal Out N of the shift register of this stage.
  • the channel length L of the thirteenth switching transistor M12 can be designed to be 8 ⁇ m, and the channel width can be designed to be 150 ⁇ m.
  • the third capacitor C3 can be designed to be 200f.
  • the above is only an example to illustrate the specific structure of the first output control circuit 3 in the shift register.
  • the specific structure of the first output control circuit 3 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may also be a technology in the art. Other structures known to the personnel are not limited here.
  • the second output control circuit 10 specifically includes: a tenth switch transistor M10 and a tenth switch transistor M10. Four-switch transistor M14; among them,
  • the tenth switch transistor M10 has its gate coupled to the third node D, the first pole is coupled to the first node A, and the second pole is coupled to the third reference signal terminal VGL;
  • the fourteenth switching transistor M14 has its gate coupled to the third node D, the first pole is coupled to the gate signal output terminal Out N of the shift register of this stage, and the second pole is coupled to the third reference signal terminal VGL .
  • the channel length L of the tenth switching transistor M10 can be designed to be 8 ⁇ m, and the channel width can be designed to be 15 ⁇ m.
  • the channel length L of the fourteenth switching transistor M14 can be designed to be 8 ⁇ m, and the channel width can be designed to be 60 ⁇ m.
  • the specific structure of the second output control circuit 10 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may also be technical in the art. Other structures known to the personnel are not limited here.
  • the initialization circuit 11 specifically includes: a fifteenth switching transistor M15; wherein,
  • the gate and first pole of the fifteenth switching transistor M15 are both coupled to the initialization signal terminal RST, and the second pole is coupled to the third node D.
  • the channel length L of the fifteenth switching transistor M15 can be designed to be 8 ⁇ m, and the channel width can be designed to be 5 ⁇ m.
  • the function of the initialization circuit 11 is to initialize all the shift registers before the shift registers in the first row of the cascaded shift registers start scanning.
  • the fifteenth switch transistor M15 is high at the initialization signal terminal RST. Is turned on under the control of RST, the high potential signal of the initialization signal terminal RST is input to the third node D to charge the third node D, the fourteenth switch transistor M14 is turned on, and the low potential signal of the third reference signal terminal VGL is input to the gate signal
  • the output terminal Out N initializes the gate signal output terminal Out N so as not to affect the progressive scan of the cascaded multiple shift registers.
  • the specific structure of the initialization circuit 11 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may also be other structures known to those skilled in the art. It is not limited here.
  • the switching transistor mentioned in the foregoing embodiments of the present disclosure may be a thin film transistor (TFT, Thin Film Transistor), or may be a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Scmiconductor), which is not limited herein.
  • TFT Thin Film Transistor
  • MOS metal oxide semiconductor field effect transistor
  • all the switching transistors may be N-type transistors; the potential of the third reference signal terminal VGL is a low potential, and the fourth reference signal The potential of the terminal VGH is high.
  • all the switch transistors may also be P-type transistors, which is not limited herein.
  • the N-type transistor is turned on under the action of a high potential, and is turned off under the action of a low potential;
  • the P-type transistor is turned off under the action of a high potential, and is turned on under the action of a low potential.
  • the first electrode of the switching transistor mentioned in the above-mentioned embodiments of the present disclosure can be a source electrode and the second electrode can be a drain electrode, or the first electrode can be a drain electrode and the second electrode is a source electrode. distinguish.
  • a forward scan is taken as an example to describe the working process of the shift register provided in the embodiment of the present disclosure from full-screen scan to designated line scan.
  • 1 represents a high-level signal
  • 0 represents a low-level signal.
  • RST in Figure 3 and Figure 4 indicates that before the first row of shift registers is triggered (that is, before STV is high, STV is the initial trigger signal of the shift register), the gate signal output terminal of each shift register is initialized ,
  • double-sided driving means that the shift register on the left drives odd rows Gate lines, the shift register on the right drives the even-numbered gate lines, CKL and CKBL represent the clock signal terminals on the left, CKR and CKBR represent the clock signal terminals on the right, and the connections between CK and CKB and shift registers in different rows are mutually switched
  • CKL is connected to the second clock signal terminal CKB of the shift register connected to the gate line of the first row
  • the first clock signal terminal CK of the shift register connected to the gate line of the third row is connected
  • CKBL is connected to the first The first clock signal terminal
  • the embodiment of the present disclosure takes forward scanning as an example to illustrate the working principle of the design switching from the full-screen scanning mode to the partial scanning mode from the third line to the eighth line.
  • the next frame is the partial scan mode from line 3 to line 8, that is, the shift register in line 3 from the next frame is the starting line, and the shift register in line 8 is At the end of the line, the scanning from the shift register in the third row to the shift register in the eighth row is one cycle, and several cycles are continuously scanned according to display needs.
  • the resolution ie, partial
  • the work of the shift register that specifies the specific initial line and the end line is divided into two stages.
  • the first stage: the resolution switching trigger stage T1 is the full-screen scanning stage, which is a normal frame. Scanning (from the first line to the last line), because the next frame will start from the third line for partial scanning, so the resolution switching trigger stage T1 needs to coordinate with the signal output selection terminal CGI signal to specify the third frame of the next frame
  • the row shift register is the initial row
  • the second stage: the resolution switching display stage T2 is the partial scanning stage, which can be realized with the signal output selection terminal CGI, signal output trigger terminal CGS, signal output termination CGE and reset signal terminal CGR. Switch the resolution display, and display the start line and end line progressively according to the specified line.
  • the timing of Figure 3 is the input and output timing of the second stage shift register Out 2 and the input and output timing of the third stage shift register Out 3.
  • the timing of Figure 4 is the eighth The input and output timing of the shift register Out 8 stage and the input and output timing of the ninth stage shift register Out 9 .
  • the signal of the initialization signal terminal Rst is a high-level signal, and the other signals are low-level signals.
  • the fifteenth switch transistor M15 of each shift register is turned on and the first row is pulled up.
  • the potential of the three nodes D pulls down the potential of the first node A to reset the gate signal output terminal of the shift register.
  • each shift register scans in full screen, that is, scans step by step from the first row to the last row, and the signal at the signal output termination terminal CGE is always a high potential signal.
  • the gate signal output terminal Out 2 of the shift register in row 2 is output at a high level (the output of Out 2 in Figure 3 is a high stage)
  • the first switching transistor M1 and the seventh The switching transistor M7 is turned on to charge the first node A.
  • the signal of the first node A is a high-potential signal
  • the eleventh switching transistor M11 is turned on
  • the low-potential signal of the third reference signal terminal VGL pulls down the third
  • the potential of node D and the signal of the third node D are low potential signals.
  • the signal output selection terminal CGI will input a high-level signal when the gate signal output terminal of the shift register of the third line is a high-level signal during full-screen scan.
  • the third switch transistor M3 of the 3-row shift register is turned on, and the second node B is pulled up to a high potential.
  • the progressive scan time period after Out 3 is output, in the third row shift register
  • the signal of the second node B always remains a high potential signal.
  • the resolution switching display phase T2 starts.
  • the signal at the trigger signal terminal CGS is a high potential signal
  • the signal at the signal output termination terminal CGE is a low potential signal.
  • the second node B is raised due to the bootstrap action of the first capacitor C1, the fifth switch transistor M5 is turned on, and the sixth switch transistor M6 is also turned on, and the signal of the first node A is a high potential signal.
  • the signal of the second clock signal terminal CKB is a high-level signal.
  • the signal of the first node A further rises, the thirteenth switching transistor M13 is turned on, and Out 3 outputs a high-level signal ,
  • the twelfth switch transistor M12 is turned on, and the low potential signal of the third reference signal terminal VGL continues to pull down the signal of the third node D through the twelfth switch transistor M12.
  • the signal input at the second clock signal terminal CKB is the CKBL in FIG. 3, that is, the low potential signal
  • the potential of the first node A is restored to the high potential at the time when the output of Out 3 is low
  • the thirteenth switching transistor M13 is still on, and Out 3 outputs a low-level signal.
  • the high-potential signal output by Out 3 is input to the signal input terminal of the shift register in the fourth row, so that the subsequent shift register cascaded in the shift register in the third row outputs the signal row by row.
  • the signal of the signal output selection terminal CGI is at a high level during the output phase of Out 3 , the signal of the second node B in the shift register of the third row is always maintained at a high level during the line-by-line scanning period after Out 3 is output.
  • Out 8 outputs a high-level signal
  • the signal at the signal output trigger terminal CGS of each shift register is a high-level signal, causing the third row to shift
  • the first node in the bit register can be charged again, so that in the next frame, the shift register from row 3 is the initial scan line, that is, from row 3 to row 8, scanning for several cycles.
  • the signal at the signal output termination terminal CGE is a low level signal, so that the first line of the shift register in the 9th row
  • the switching transistor M1 is turned off and does not charge the shift register of the 9th row, that is, the scanning line ends in the 8th row.
  • a high potential signal is input to the output reset signal terminal CGR of each shift register, the fourth switch transistor is turned on, and the third reference signal terminal VGL discharges the second node B.
  • the third row of shift registers will not be used as the starting row to scan.
  • the embodiments of the present disclosure also provide a gate driving circuit, including a plurality of cascaded shift registers as provided in the embodiments of the present disclosure; wherein,
  • each stage of shift register is coupled to the signal input terminal of its adjacent next stage of shift register;
  • the gate signal output terminal of each stage of shift register is coupled to the reset signal terminal of the adjacent previous stage of shift register.
  • a frame start signal is loaded to the signal input end of the shift register of the first row to realize progressive scanning from top to bottom.
  • load the frame start signal to the signal input end of the shift register of the last row to realize progressive scanning from bottom to top.
  • embodiments of the present disclosure also provide a display device, including the gate driving circuit provided by the embodiments of the present disclosure.
  • the display device can be a display device of any product with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display device for the implementation of the display device, reference may be made to the embodiment of the gate drive circuit described above, and the repetition is not repeated here.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be a liquid crystal display device or an organic electroluminescence display device, which is not limited herein.
  • the embodiments of the present disclosure also provide a driving method of a gate driving circuit, including:
  • n and m are positive integers, and n is greater than m; that is, the gate of the m-th row shift register in the full-screen scan mode and the partial scan mode
  • the signal output terminal outputs a valid signal to the gate signal output terminal of the shift register in the n-1th row to output a valid signal
  • the valid signal is continuously input to the signal output termination terminal;
  • the following provides two embodiments to illustrate the input and output timing diagrams of the gate driving circuit provided by the embodiments of the present disclosure for switching from full-screen scanning to specified line scanning.
  • the resolution switching trigger frame T1 is a full-screen scan, and the next frame is matched with the signals output by the CGI, CGS, and CGE signal terminals of the signal output switching circuit to switch from line 3 to line 9.
  • the specific gate driving circuit please refer to the working principle of the above-mentioned shift register provided in the embodiment of the present disclosure, which will not be repeated here.
  • the resolution switching trigger frame T1 is a full-screen scan, and the next frame is matched with the signals output by the CGI, CGS, and CGE signal terminals of the signal output switching circuit to switch from the 5th line to the 12th line.
  • the specific gate driving circuit please refer to the working principle of the above-mentioned shift register provided in the embodiment of the present disclosure, which will not be repeated here.
  • the embodiment of the present disclosure provides a shift register, a gate driving circuit and a driving method thereof, and a display device.
  • a signal output switching circuit is added through the first node between the input control circuit 1 and the reset control circuit 2, wherein
  • the signal output selection circuit 6 determines that the shift register is designated as the scanning start line in the partial scanning mode, under the control of the gate signal output terminal Out N signal, it provides the signal output selection terminal CGI signal to the second
  • the signal output trigger circuit 7 is configured to provide the signal of the trigger signal terminal CGS to the trigger signal terminal CGS under the control of the potential of the second node B in the partial scan mode and when the shift register is designated as the scan start line
  • the first node A replaces the input control circuit 1 to provide the first node A with a signal for controlling the output control circuit 3 to realize the function of any row shift register as the scanning start row.
  • a first signal output termination circuit is added between the first reference signal terminal CN and the input control circuit 1, and a second signal output termination circuit between the reset control circuit 2 and the second reference signal terminal CNb can realize any line
  • the shift register functions as the scanning end line.

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Abstract

一种移位寄存器、栅极驱动电路及其驱动方法、显示装置。移位寄存器包括：通过增加信号输出切换电路，其中的信号输出选择电路（6）在确定本移位寄存器被指定为局部扫描模式下的扫描起始行时，在栅极信号输出端信号的控制下，将信号输出选择端的信号提供给第二节点（B），信号输出触发电路（7）在局部扫描模式下且在本移位寄存器被指定为扫描起始行时，在第二节点（B）的电位控制下，将触发信号端的信号提供给第一节点（A），以代替输入控制电路为第一节点（A）提供控制输出控制电路的信号，实现任意行移位寄存器作为扫描起始行的功能。同时，增加信号输出终止电路可以实现任意行移位寄存器作为扫描结束行的功能。

Description

移位寄存器、栅极驱动电路及其驱动方法、显示装置
相关申请的交叉引用
本公开要求在2019年03月25日提交中国专利局、申请号为201910225344.5、申请名称为“移位寄存器、栅极驱动电路及其驱动方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器、栅极驱动电路及其驱动方法、显示装置。
背景技术
在薄膜晶体管显示器中，通常通过栅极驱动装置向像素区域的各个薄膜晶体管(TFT，Thin Film Transistor)的栅极提供栅极驱动信号。栅极驱动装置可以通过阵列工艺形成在显示器的阵列基板上，即阵列基板行驱动(Gate Driver on Array,GOA)工艺，这种集成工艺不仅节省了成本，而且可以做到液晶面板(Panel)两边对称的美观设计，同时，也省去了栅极集成电路(IC，Integrated Circuit)的绑定(Bonding)区域以及扇出(Fan-out)的布线空间，从而可以实现窄边框的设计；并且，这种集成工艺还可以省去栅极扫描线方向的Bonding工艺，从而提高了产能和良率。
发明内容
本公开实施例提供了一种移位寄存器，包括：
输入控制电路，被配置为响应于信号输入端的有效信号，将第一参考信号端的信号提供给第一节点；
复位控制电路，被配置为响应于复位信号端的有效信号，将第二参考信号端的信号提供给所述第一节点；
第一输出控制电路，被配置为响应于所述第一节点的电位，控制栅极信号输出端的信号输出；
信号输出终止电路，被配置为在局部扫描模式下，响应于信号输出终止端的有效信号，终止所述第一参考信号端与所述输入控制电路之间的导通状态，终止所述第二参考信号端与所述复位控制电路之间的导通状态；
信号输出选择电路，被配置为在确定本移位寄存器被指定为所述局部扫描模式下的扫描起始行时，响应于所述栅极信号输出端输出的有效信号，将信号输出选择端的有效信号提供给第二节点；
信号输出触发电路，被配置为在所述局部扫描模式下且在本移位寄存器被指定为所述扫描起始行时，响应于所述第二节点的电位，将触发信号端的信号提供给所述第一节点；
信号输出复位电路，被配置为在确定恢复全屏扫描模式时，响应于输出复位信号端的有效信号，将第三参考信号端的信号提供给所述第二节点。
可选地，在上述移位寄存器中，所述信号输出终止电路具体包括：第一信号输出终止电路和第二信号输出终止电路；所述第一信号输出终止电路包括第一开关晶体管，所述第二信号输出终止电路包括第二开关晶体管；其中，
所述第一开关晶体管，其栅极与所述信号输出终止端耦接，第一极与所述第一参考信号端耦接，第二极与所述输入控制电路耦接；
所述第二开关晶体管，其栅极与所述信号输出终止端耦接，第一极与所述第二参考信号端耦接，第二极与所述复位控制电路耦接。
可选地，在上述移位寄存器中，所述信号输出选择电路具体包括：第三开关晶体管；其中，
所述第三开关晶体管，其栅极与所述栅极信号输出端耦接，第一极与所述信号输出选择端耦接，第二极与所述第二节点耦接。
可选地，在上述移位寄存器中，所述信号输出复位电路具体包括：第四开关晶体管；其中，
所述第四开关晶体管，其栅极与所述输出复位信号端耦接，第一极与所 述第三参考信号端耦接，第二极与所述第二节点耦接。
可选地，在上述移位寄存器中，所述信号输出触发电路具体包括：第五开关晶体管和第一电容；其中，
所述第五开关晶体管，其栅极与所述第二节点耦接，第一极与所述触发信号端耦接，第二极与所述第一节点耦接；
所述第一电容，其第一端与所述第二节点耦接，第二端与所述第一节点耦接。
可选地，在上述移位寄存器中，所述信号输出触发电路还包括：第六开关晶体管；其中，
所述第六开关晶体管，其栅极与所述第一电容的第二端耦接，第一极与第四参考信号端耦接，第二极与所述第一节点耦接。
可选地，在上述移位寄存器中，所述输入控制电路具体包括：第七开关晶体管；其中，
第七开关晶体管，其栅极与所述信号输入端耦接，第一极与所述第一开关晶体管的第二极耦接，第二极与所述第一节点耦接。
可选地，在上述移位寄存器中，所述复位控制电路具体包括：第八开关晶体管；其中，
第八开关晶体管，其栅极与所述复位信号端耦接，第一极与所述第二开关晶体管的第二极耦接，第二极与所述第一节点耦接。
可选地，在上述移位寄存器中，还包括：节点控制电路，被配置为响应于所述第一节点和所述栅极信号输出端的电位，控制所述第三节点的电位。
可选地，在上述移位寄存器中，所述节点控制电路具体包括：第九开关晶体管、第十一开关晶体管、第十二开关晶体管和第二电容；其中，
第九开关晶体管，其栅极和第一极均与第一时钟信号端耦接，第二极与第三节点耦接；
第十一开关晶体管，其栅极与所述第一节点耦接，第一极与所述第三节点耦接，第二极与所述第三参考信号端耦接；
第十二开关晶体管，其栅极与所述栅极信号输出端耦接，第一极与所述第三节点耦接，第二极与所述第三参考信号端耦接；
第二电容，其第一端与所述第三节点耦接，第二端与所述第三参考信号端耦接。
可选地，在上述移位寄存器中，所述第一输出控制电路具体包括：第十三开关晶体管和第三电容；其中，
第十三开关晶体管，其栅极与所述第一节点耦接，第一极与第二时钟信号端耦接，第二极与所述栅极信号输出端耦接；
第三电容，其第一端与所述第一节点耦接，第二端与所述栅极信号输出端耦接。
可选地，在上述移位寄存器中，还包括：第二输出控制电路，被配置为响应于所述第三节点的电位，将所述第三参考信号端的信号提供给所述栅极信号输出端和所述第一节点。
可选地，在上述移位寄存器中，所述第二输出控制电路具体包括：第十开关晶体管和第十四开关晶体管；其中，
第十开关晶体管，其栅极与所述第三节点耦接，第一极与所述第一节点耦接，第二极与所述第三参考信号端耦接；
第十四开关晶体管，其栅极与所述第三节点耦接，第一极与所述栅极信号输出端耦接，第二极与所述第三参考信号端耦接。
可选地，在上述移位寄存器中，还包括：初始化电路，被配置为响应于初始化信号端的信号，对所述第三节点进行初始化。
可选地，在上述移位寄存器中，所述初始化电路具体包括：第十五开关晶体管；其中，
所述第十五开关晶体管，其栅极和第一极均与初始化信号端耦接，第二极与所述第三节点耦接。
可选地，在上述移位寄存器中，所述移位寄存器所包含的全部开关晶体管为N型晶体管。
本公开还提供了一种栅极驱动电路，包括级联的多个上述任一的移位寄存器；其中，
除最后一级移位寄存器之外，每一级移位寄存器的栅极信号输出端与其相邻的下一级移位寄存器的信号输入端耦接；
除第一级移位寄存器之外，每一级移位寄存器的栅极信号输出端与其相邻的上一级移位寄存器的复位信号端耦接。
本公开还提供了一种显示装置，包括上述栅极驱动电路。
本公开还提供了一种上述栅极驱动电路的驱动方法，包括：
在全屏扫描模式下，在确定第m行移位寄存器被指定为局部扫描模式下的扫描起始行时，在所述第m行移位寄存器的栅极信号输出端输出有效信号时，对所述信号输出选择端输入有效信号；
在局部扫描模式的起始时刻，对所述触发信号端输入有效电位信号，同时对所述信号输出终止端输入有效信号；在第n行移位寄存器的栅极信号输出端输出关断信号时，对所述触发信号端输入有效电位信号，同时对所述信号输出终止端输入关断信号；其中，n大于m；
在恢复所述全屏扫描模式之前，对所述输出复位信号端输入有效电位信号。
附图说明
图1为本公开实施例提供的移位寄存器的一种结构示意图；
图2为本公开实施例提供的移位寄存器的另一种结构示意图；
图3为图2所示的移位寄存器对应的一种输入输出时序图；
图4为图2所示的移位寄存器对应的另一种输入输出时序图；
图5为本公开实施例提供的栅极驱动电路对应的一种输入输出时序图；
图6为本公开实施例提供的栅极驱动电路对应的另一种输入输出时序图；
图7为本公开实施例提供的栅极驱动电路的一种结构示意图。
具体实施方式
目前，移动产品更新换代极快，产品朝着轻薄化、精细化和超长待机的趋势发展，从客户体验角度，对屏幕的边框要求越来越窄，待机时间更长。因此，开发出驱动能力强、功耗更低、待机时间更长的panel设计，对于提升显示器件性能的竞争力有极大的作用。
传统的GOA电路在分辨率确定后，只能从第一行栅线开始扫描到最后一行栅线结束，无论显示的具体实际需求是多少，都必须从起始行到终止行进行全部扫描显示。由于我们的移动产品分辨率越来越高，功耗也随着分辨率的增大而增大，导致显示产品的待机时间大大减小。因此，如何提高显示产品的待机时间是本领域技术人员亟需解决的技术问题。
下面结合附图，对本公开实施例提供的移位寄存器、栅极驱动电路及其驱动方法、显示装置的具体实施方式进行详细地说明。
本公开实施例提供的一种移位寄存器，如图1所示，包括：
耦接于第一节点A、信号输入端Out N-1和第一参考信号端CN之间的输入控制电路1，被配置为响应于信号输入端Out N-1的有效信号，将第一参考信号端CN的信号提供给第一节点A；
耦接于第一节点A、复位信号端Out N+1和第二参考信号端CNB之间的复位控制电路2，被配置为响应于复位信号端Out N+1的有效信号，将第二参考信号端CNB的信号提供给第一节点A；
耦接于第一节点A与栅极信号输出端Out N之间的第一输出控制电路3，被配置为响应于第一节点A的电位，控制栅极信号输出端Out N的信号输出；
位于输入控制电路1与第一参考信号端CN之间的第一信号输出终止电路4，位于第二输入控制电路2与第二参考信号端CNB之间的第二信号输出终止电路5，以及与第一节点A耦接的信号输出切换电路；其中，第一信号输出终止电路4和第二信号输出终止电路5可以组成信号输出终止电路0；
第一信号输出终止电路4被配置为在局部扫描模式下，在信号输出终止端CGE信号的控制下，终止第一参考信号端CN与第一输入控制电路1之间 的连接；第二信号输出终止电路5被配置为在局部扫描模式下，在信号输出终止端CGE信号的控制下，终止第二参考信号端CNB与第二输入控制电路2之间的连接；
信号输出切换电路包括：信号输出选择电路6，信号输出触发电路7和信号输出复位电路8；其中，
信号输出选择电路6被配置为在确定本移位寄存器被指定为局部扫描模式下的扫描起始行时，在栅极信号输出端Out N信号的控制下，将信号输出选择端CGI的信号提供给第二节点B；
信号输出触发电路7被配置为在局部扫描模式下且在本移位寄存器被指定为扫描起始行时，在第二节点B的电位控制下，将触发信号端CGS的信号提供给第一节点A；
信号输出复位电路8被配置为在确定恢复全屏扫描模式时，在输出复位信号端CGR信号的控制下，将第三参考信号端VGL的信号提供给第二节点B。
具体地，本公开实施例提供的上述移位寄存器通过在输入控制电路1和复位控制电路2之间的第一节点，增加信号输出切换电路，其中的信号输出选择电路6在确定本移位寄存器被指定为局部扫描模式下的扫描起始行时，在栅极信号输出端Out N信号的控制下，将信号输出选择端CGI的信号提供给第二节点B，信号输出触发电路7被配置为在局部扫描模式下且在本移位寄存器被指定为扫描起始行时，在第二节点B的电位控制下，将触发信号端CGS的信号提供给第一节点A，以代替输入控制电路1为第一节点A提供控制输出控制电路3的信号，实现任意行移位寄存器作为扫描起始行的功能。同时，在第一参考信号端CN与输入控制电路1之间增加第一信号输出终止电路，在复位控制电路2与第二参考信号端CNB之间的第二信号输出终止电路，可以实现任意行移位寄存器作为扫描结束行的功能。通过上述几个电路的相互配合，可以实现对移位寄存器的起始行到结束行之间任意行进行选择输出扫描信号，从而实现对panel分辨率的选择，降低功耗，延长待机时间。
在具体实施时，如图1所示，本级移位寄存器N的信号输入端可以是与 上一级的移位寄存器N-1的栅极信号输出端OUT N-1耦接，本级移位寄存器N的复位信号端可以是与下一级的移位寄存器N+1的栅极信号输出端OUT N+1耦接，或者反之亦可。本公开实施例提供的上述移位寄存器可以实现正向扫描和反向扫描模式，当采用正向扫描模式时，第一参考信号端CN的信号为高电位信号，第二参考信号端CNB的信号为低电位信号；当采用反向扫描模式时，第一参考信号端CN的信号为低电位信号，第二参考信号端CNB的信号为高电位信号。在采用正向扫描时，下一级移位寄存器N+1的栅极信号输出端OUT N+1输出的信号对本级移位寄存器N进行复位；在采用反向扫描时，上一级移位寄存器N-1的栅极信号输出端OUT N-1输出的信号对本级移位寄存器N进行复位。
下面结合具体实施例，对本公开进行详细说明。需要说明的是，本实施例是为了更好的解释本公开，但不限制本公开。
在一种可能的实施方式中，在具体实施时，在本公开实施例提供的上述移位寄存器中，如图2所示，第一信号输出终止电路4具体包括：第一开关晶体管M1；其中，
第一开关晶体管M1，其栅极与信号输出终止端CGE耦接，第一极与第一参考信号端CN耦接，第二极与输入控制电路1耦接。
具体地，第一开关晶体管M1的沟道长度L可以设计为8μm，沟道宽度可以设计为15μm。
以上仅是举例说明移位寄存器中第一信号输出终止电路4的具体结构，在具体实施时，第一信号输出终止电路4的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在一种可能的实施方式中，在具体实施时，在本公开实施例提供的上述移位寄存器中，如图2所示，第二信号输出终止电路5具体包括：第二开关晶体管M2；其中，
第二开关晶体管M2，其栅极与信号输出终止端CGE耦接，第一极与第二参考信号端CNB耦接，第二极与复位控制电路2耦接。
具体地，第二开关晶体管M2的沟道长度L可以设计为8μm，沟道宽度可以设计为15μm。
以上仅是举例说明移位寄存器中第二信号输出终止电路5的具体结构，在具体实施时，第二信号输出终止电路5的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在一种可能的实施方式中，在具体实施时，在本公开实施例提供的上述移位寄存器中，如图2所示，信号输出选择电路6具体包括：第三开关晶体管M3；其中，
第三开关晶体管M3，其栅极与栅极信号输出端Out N耦接，第一极与信号输出选择端CGI耦接，第二极与第二节点B耦接。
具体地，第三开关晶体管M3的沟道长度L可以设计为8μm，沟道宽度可以设计为30μm。
具体地，传统的移位寄存器电路在分辨率确定后，只能从第一行栅线开始扫描到最后一行栅线结束，无论显示的具体实际需求是多少，都必须从起始行到终止行进行全部扫描显示，由于我们的移动产品分辨率越来越高，功耗也随着分辨率的增大而增大，导致显示产品的待机时间大大减小。比如，我们仅需要长时间观看屏幕上的时间和天气信息，其它地方不需要显示，而传统的屏幕就是全屏显示，耗电量较大；例如屏幕上的时间和天气信息只需显示某几行，如第3行至第8行，本公开实施例提供的移位寄存器中的信号输出切换电路中的信号输出选择电路6就可以在全屏扫描模式下扫描第3行时，通过信号输出选择端CGI输入的高电位信号给第二节点B充电，由于第一电容C1的自举作用，在下一帧的第三行扫描之前，第二节点B的电位一直保持高电位，从而可以切换至从第3行扫描至第8行的局部扫描模式。
以上仅是举例说明移位寄存器中信号输出选择电路6的具体结构，在具体实施时，信号输出选择电路6的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在一种可能的实施方式中，在具体实施时，在本公开实施例提供的上述 移位寄存器中，如图2所示，信号输出复位电路8具体包括：第四开关晶体管M4；其中，
第四开关晶体管M4，其栅极与输出复位信号端耦接CGR，第一极与第三参考信号端VGL耦接，第二极与第二节点B耦接。
具体地，第四开关晶体管M4的沟道长度L可以设计为8μm，沟道宽度可以设计为5μm。
具体地，在局部扫描模式下仅选择级联的多个移位寄存器中的某几行进行扫描输出栅极信号时，比如从第3行扫到第8行，即第3行到第8行为一个周期，在扫描若干个周期之后结束局部扫描模式时，移位寄存器又恢复从第一行扫到最后一行的全屏扫描模式，那么在恢复全屏扫描模式之前，要对进行局部扫描的各移位寄存器的第二节点B的电位进行复位，即第四开关晶体管M4在输出复位信号端CGR高电位信号的控制下开启，第三参考信号端VGL的低电位信号输入至第二节点B，保证第二节点B的信号为低电位信号，不影响后续全屏扫描模式下各移位寄存器的工作。
以上仅是举例说明移位寄存器中信号输出复位电路8的具体结构，在具体实施时，信号输出复位电路8的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在一种可能的实施方式中，在具体实施时，在本公开实施例提供的上述移位寄存器中，如图2所示，信号输出触发电路7具体包括：第五开关晶体管M5和第一电容C1；其中，
第五开关晶体管M5，其栅极与第二节点B耦接，第一极与触发信号端CGS耦接，第二极与第一节点A耦接；
第一电容C1，其第一端与第二节点B耦接，第二端与第一节点A耦接。
具体地，第五开关晶体管M5的沟道长度L可以设计为8μm，沟道宽度可以设计为30μm。第一电容C1可以设计为200f。
具体地，本公开实施例中信号输出触发电路7在信号输出选择电路6选择从某一行扫描时，触发信号端CGS输入高电位信号至第一节点A，对第一 节点A进行充电，以进行移位寄存器的扫描。
以上仅是举例说明移位寄存器中信号输出触发电路7的具体结构，在具体实施时，信号输出触发电路7的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在一种可能的实施方式中，在具体实施时，由于第一电容C1的第二端是与各开关晶体管的源漏极耦接，这样会影响第一电容C1存储电荷的功能，因此为了提高第一电容C1存储电荷的能力，在本公开实施例提供的上述移位寄存器中，如图2所示，信号输出触发电路7还可以包括：第六开关晶体管M6；其中，
第六开关晶体管M6，其栅极与第一电容C1的第二端耦接，第一极与第四参考信号端VGH耦接，第二极与第一节点A耦接；用于在第二节点B的控制下将第四参考信号端VGH的信号提供给第一节点A。
具体地，第六开关晶体管M6的沟道长度L可以设计为8μm，沟道宽度可以设计为30μm。
在一种可能的实施方式中，在具体实施时，在本公开实施例提供的上述移位寄存器中，如图2所示，输入控制电路1具体包括：第七开关晶体管M7；其中，
第七开关晶体管M7，其栅极与信号输入端OUT N-1耦接，第一极与第一开关晶体管M1的第二极耦接，第二极与第一节点A耦接。
具体地，第七开关晶体管M7的沟道长度L可以设计为8μm，沟道宽度可以设计为30μm。
以上仅是举例说明移位寄存器中输入控制电路1的具体结构，在具体实施时，输入控制电路1的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在一种可能的实施方式中，在具体实施时，在本公开实施例提供的上述移位寄存器中，如图2所示，复位控制电路2具体包括：第八开关晶体管M8；其中，
第八开关晶体管M8，其栅极与复位信号端OUT N+1耦接，第一极与第二开关晶体管M2的第二极耦接，第二极与第一节点A耦接。
具体地，第八开关晶体管M8的沟道长度L可以设计为8μm，沟道宽度可以设计为15μm。
以上仅是举例说明移位寄存器中复位控制电路2的具体结构，在具体实施时，复位控制电路2的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在具体实施时，在本公开实施例提供的上述移位寄存器中，如图1所示，还可以包括：节点控制电路9，被配置为响应于第一节点A和栅极信号输出端Out N的电位，控制第三节点D的电位；第二输出控制电路10，被配置为响应于第三节点D的电位，将第三参考信号端VGL的信号提供给栅极信号输出端Out N和第一节点A；初始化电路11，被配置为响应于初始化信号端RST的信号，对第三节点D进行初始化。
在一种可能的实施方式中，在具体实施时，在本公开实施例提供的上述移位寄存器中，如图2所示，节点控制电路9具体包括：第九开关晶体管M9、第十一开关晶体管M11、第十二开关晶体管M12和第二电容C2；其中，
第九开关晶体管M9，其栅极和第一极均与第一时钟信号端CK耦接，第二极与第三节点D耦接；
第十一开关晶体管M11，其栅极与第一节点A耦接，第一极与第三节点D耦接，第二极与第三参考信号端VGL耦接；
第十二开关晶体管M12，其栅极与本级移位寄存器的栅极信号输出端Out N耦接，第一极与第三节点D耦接，第二极与第三参考信号端VGL耦接；
第二电容C2，其第一端与第三节点D耦接，第二端与第三参考信号端VGL耦接。
在具体实施时，在本公开实施例提供的上述移位寄存器中，一般在工艺制备时第十一开关晶体管M11的尺寸设置的比第九开关晶体管M9的尺寸大，这样设置使得当第一节点A的电位为高电位时，第十一开关晶体管M11在第 一节点A的信号的控制下将第三参考信号端VGL的信号提供给第三节点D的速率大于第九开关晶体管M9在第一时钟信号端CK的控制下将第一时钟信号端CK的信号提供给第三节点D的速率，从而保证第三节点D的电位为低电位。
具体地，第九开关晶体管M9的沟道长度L可以设计为8μm，沟道宽度可以设计为10μm。
具体地，第十一开关晶体管M11的沟道长度L可以设计为8μm，沟道宽度可以设计为18μm。
具体地，第十二开关晶体管M12的沟道长度L可以设计为8μm，沟道宽度可以设计为5μm。
具体地，第二电容C2可以设计为200f。
以上仅是举例说明移位寄存器中节点控制电路9的具体结构，在具体实施时，节点控制电路9的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在一种可能的实施方式中，在具体实施时，在本公开实施例提供的上述移位寄存器中，如图2所示，第一输出控制电路3具体包括：第十三开关晶体管M13和第三电容C3；其中，
第十三开关晶体管M13，其栅极与第一节点A耦接，第一极与第二时钟信号端CKB耦接，第二极与本级移位寄存器的栅极信号输出端Out N耦接；
第三电容C3，其第一端与第一节点A耦接，第二端与本级移位寄存器的栅极信号输出端Out N耦接。
具体地，第十三开关晶体管M12的沟道长度L可以设计为8μm，沟道宽度可以设计为150μm。第三电容C3可以设计为200f。
以上仅是举例说明移位寄存器中第一输出控制电路3的具体结构，在具体实施时，第一输出控制电路3的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在一种可能的实施方式中，在具体实施时，在本公开实施例提供的上述 移位寄存器中，如图2所示，第二输出控制电路10具体包括：第十开关晶体管M10和第十四开关晶体管M14；其中，
第十开关晶体管M10，其栅极与第三节点D耦接，第一极与第一节点A耦接，第二极与第三参考信号端VGL耦接；
第十四开关晶体管M14，其栅极与第三节点D耦接，第一极与本级移位寄存器的栅极信号输出端Out N耦接，第二极与第三参考信号端VGL耦接。
具体地，第十开关晶体管M10的沟道长度L可以设计为8μm，沟道宽度可以设计为15μm。
具体地，第十四开关晶体管M14的沟道长度L可以设计为8μm，沟道宽度可以设计为60μm。
以上仅是举例说明移位寄存器中第二输出控制电路10的具体结构，在具体实施时，第二输出控制电路10的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在一种可能的实施方式中，在具体实施时，在本公开实施例提供的上述移位寄存器中，如图2所示，初始化电路11具体包括：第十五开关晶体管M15；其中，
第十五开关晶体管M15，其栅极和第一极均与初始化信号端RST耦接，第二极与第三节点D耦接。
具体地，第十五开关晶体管M15的沟道长度L可以设计为8μm，沟道宽度可以设计为5μm。
具体地，初始化电路11的作用是级联的多个移位寄存器的第一行移位寄存器开始扫描之前，对全部移位寄存器进行初始化，第十五开关晶体管M15在初始化信号端RST高电位信号的控制下开启，初始化信号端RST的高电位信号输入至第三节点D，给第三节点D充电，第十四开关晶体管M14开启，第三参考信号端VGL的低电位信号输入至栅极信号输出端Out N，对栅极信号输出端Out N进行初始化，以不影响级联的多个移位寄存器的逐行扫描。
以上仅是举例说明移位寄存器中初始化电路11的具体结构，在具体实施 时，初始化电路11的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
需要说明的是本公开上述实施例中提到的开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不作限定。
在具体实施时，在本公开实施例提供的上述移位寄存器中，如图2所示，所有开关晶体管可以均为N型晶体管；第三参考信号端VGL的电位为低电位，第四参考信号端VGH的电位为高电位。
当然，在具体实施时，在本公开实施例提供的上述移位寄存器中，所有开关晶体管也可以均为P型晶体管，在此不做限定。
进一步地，在具体实施时，N型晶体管在高电位作用下导通，在低电位作用下截止；P型晶体管在高电位作用下截止，在低电位作用下导通。
需要说明的是本公开上述实施例中提到的开关晶体管的第一极可以为源极，第二极为漏极，或者第一极可以为漏极，第二极为源极，在此不做具体区分。
下面结合电路时序图，以正向扫描为例对本公开实施例提供的上述移位寄存器从全屏扫描切换到指定行扫描的工作过程作以描述。下述描述中以1表示高电位信号，0表示低电位信号。
以图2所示的移位寄存器为例，其中，在图2中，所有开关晶体管均为N型晶体管。详细描述从对全屏栅线扫描切换至从第3行扫描至第8行栅线的输入输出时序过程，对应的输入输出时序如图3和图4所示。图3和图4中的RST表示在第一行移位寄存器被触发之前(即STV为高之前，STV为移位寄存器的初始触发信号)，对各移位寄存器的栅极信号输出端进行初始化，以保证各移位寄存器的正常输出；本公开实施例提供的图3和图4的输入输出时序是针对双边驱动的，如图7所示，双边驱动是指左边的移位寄存器驱动奇数行栅线，右边的移位寄存器驱动偶数行栅线，CKL和CKBL表示左边的时钟信号端，CKR和CKBR表示右边的时钟信号端，CK和CKB与不同行的 移位寄存器的连接是相互切换的，例如CKL和第一行的栅线连接的移位寄存器的第二时钟信号端CKB相连，以及与第三行的栅线连接的移位寄存器的第一时钟信号端CK相连；CKBL和第一行的栅线连接的移位寄存器的第一时钟信号端CK相连，以及第三行的栅线连接的移位寄存器的第二时钟信号端CKB相连；一参考信号端CN的信号为高电位信号，第二参考信号端CNB的信号为低电位信号，第三参考信号端VGL的电位为低电位，第四参考信号端VGH的电位为高电位。
本公开实施例以正向扫描为例说明本设计从对全屏扫描模式切换到从第3行扫描到第8行的局部扫描模式的工作原理。在当前帧为全屏扫描模式时，下一帧为从第3行扫描到第8行的局部扫描模式，即下一帧开始第3行移位寄存器为起始行，第8行移位寄存器为结束行，第3行移位寄存器至第8行移位寄存器的扫描为一周期，根据显示需要连续扫描若干周期。在切换分辨率(即局部)扫描时指定具体初始行和结束行的移位寄存器的工作分为两个阶段，第一阶段：分辨率切换触发阶段T1即全屏扫描阶段，该阶段为正常一帧的扫描(从第一行扫描到最后一行)，由于下一帧要从第3行开始进行局部扫描，因此分辨率切换触发阶段T1需要配合信号输出选择端CGI的信号指定下一帧的第3行移位寄存器为初始行；第二阶段：分辨率切换显示阶段T2即局部扫描阶段，配合信号输出选择端CGI、信号输出触发端CGS、信号输出终止CGE和复位信号端CGR的信号，可以实现切换分辨率显示，按指定行为起始行和结束行逐行扫描显示。
如图2、图3和图4所示，图3的时序为第2级移位寄存器Out 2的输入输出时序和第3级移位寄存器Out 3的输入输出时序，图4的时序为第8级移位寄存器Out 8的输入输出时序和第9级移位寄存器Out 9的输入输出时序。
如图3和图4所示，指定第3行为起始行、第8行为终止行，即对第3-8行栅线逐行扫描的切换分辨率显示为例，用第2、3、8、9行的工作状态说明本公开实施例提供的移位寄存器切换分辨率显示的电路工作原理。
具体地，在触发第一行移位寄存器工作之前，初始化信号端Rst的信号为 高电位信号，其它信号均为低电位信号，各移位寄存器的第十五开关晶体管M15导通，拉高第三节点D的电位，拉低第一节点A的电位、对移位寄存器的栅极信号输出端进行复位。
对切换至第3行移位寄存器为初始行的原理进行说明：
在切换至第3行移位寄存器为初始行之前，各移位寄存器是全屏扫描即从第一行逐级扫描至最后一行，信号输出终止端CGE的信号始终为高电位信号。在第2行移位寄存器的栅极信号输出端Out 2输出为高电位阶段(图3中的Out 2输出为高阶段)时，第3行移位寄存器中：第一开关晶体管M1和第七开关晶体管M7管导通，对第一节点A进行充电，第一节点A的信号为高电位信号，第十一开关晶体管M11管导通，第三参考信号端VGL的低电位信号拉低第三节点D的电位，第三节点D的信号为低电位信号。之后，在第二时钟信号端CKB输入的信号为图3中的CKBL即高电位信号时，第3行移位寄存器中：由于第三电容C3的自举作用，第一节点A的电位进一步升高，第十三开关晶体管M13导通，Out 3输出高电平，第十二开关晶体管M12导通，第三参考信号端VGL的低电位信号继续拉低第三节点D的电位。接着，在第二时钟信号端CKB输入的信号为图3中的CKBL即低电位信号时，第3行移位寄存器中：第一节点A的电位恢复到Out 3输出为低时刻的高电位，第十三开关晶体管M13依然导通，Out 3输出低电位信号。
若想全屏扫描的下一帧从第3行开始扫描，则全屏扫描时，信号输出选择端CGI在第3行移位寄存器的栅极信号输出端输出为高电位信号时输入高电位信号，第3行移位寄存器的第三开关晶体管M3导通，第二节点B拉高为高电位，在切换分辨率触发阶段T1内，Out 3输出之后逐行扫描时间段，第3行移位寄存器中的第二节点B的信号始终保持为高电位信号。
切换分辨率触发阶段T1结束后，分辨率切换显示阶段T2开始，首先，触发信号端CGS的信号为高电位信号，信号输出终止端CGE的信号为低电位信号，第3行移位寄存器中的第二节点B由于第一电容C1的自举作用被抬高，第五开关晶体管M5导通，第六开关晶体管M6也导通，第一节点A的 信号为高电位信号。之后，第二时钟信号端CKB的信号为高电位信号，由于第三电容C3的自举作用，第一节点A的信号进一步升高，第十三开关晶体管M13导通，Out 3输出高电位信号，第十二开关晶体管M12导通，第三参考信号端VGL的低电位信号通过第十二开关晶体管M12继续拉低第三节点D的信号。接着，在第二时钟信号端CKB输入的信号为图3中的CKBL即低电位信号时，第3行移位寄存器中：第一节点A的电位恢复到Out 3输出为低时刻的高电位，第十三开关晶体管M13依然导通，Out 3输出低电位信号。Out 3输出的高电位信号输入至第4行移位寄存器的信号输入端，使第3行移位寄存器级联的后续移位寄存器逐行输出信号。
如图4所示，分辨率切换显示阶段T2中，若以第8行作为终止行，则在Out 8输出高电位信号时，对各移位寄存器的信号输出终止端CGE输入低电位信号，使得第9行移位寄存器中的第一开关晶体管M1截止，Out 8输出的高电位信号无法对第9行移位寄存器中的第一节点A充电，使得扫描行终止于第8行移位寄存器。
由于Out 3输出阶段，信号输出选择端CGI的信号为高电位，则Out 3输出之后逐行扫描时间段，第3行移位寄存器中的第二节点B的信号始终保持为高电位信号，以持续到局部扫描的下一帧。在Out 8输出高电位信号时，对各移位寄存器的信号输出终止端CGE输入低电位信号的同时，对各移位寄存器的信号输出触发端CGS的信号为高电位信号，使得第3行移位寄存器中的第一节点可以再次充电，以实现在下一帧从第3行移位寄存器为初始扫描行，即从第3行扫描至第8行，扫描若干周期。
若在扫描若干周期后，终止局部扫描模式，恢复全屏扫描模式之前，在Out 8输出为高电位信号时，信号输出终止端CGE的信号为低电位信号，使得第9行移位寄存器的第一开关晶体管M1截止，不对第9行移位寄存器进行充电，即扫描行终止于第8行。同时，对各移位寄存器的输出复位信号端CGR输入高电位信号，第四开关晶体管导通，第三参考信号端VGL对第二节点B放电。保证下一帧的全屏扫描模式下，第3行移位寄存器不会作为起始行扫 描。在恢复全屏扫描模式后，对第1行移位寄存器的信号输入端重新输入帧起始信号，实现从第1行移位寄存器作为起始行开始扫描。
通过上述描述可以看出，在本公开实施例提供的移位寄存器中增加的几个电路相互配合，可以实现对移位寄存器的起始行到结束行之间任意行进行选择输出扫描信号，从而实现对panel分辨率的选择，降低功耗，延长待机时间。
基于同一发明构思，本公开实施例还提供了一种栅极驱动电路，包括级联的多个如本公开实施例提供的移位寄存器；其中，
除最后一级移位寄存器之外，每一级移位寄存器的栅极信号输出端与其相邻的下一级移位寄存器的信号输入端耦接；
除第一级移位寄存器之外，每一级移位寄存器的栅极信号输出端与其相邻的上一级移位寄存器的复位信号端耦接。
具体地，在进行正向扫描时，对第1行移位寄存器的信号输入端加载帧起始信号，实现从上到下的逐行扫描。在进行反向扫描时，对最后1行移位寄存器的信号输入端加载帧起始信号，实现从下到上的逐行扫描。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的栅极驱动电路。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品的显示装置。该显示装置的实施可以参见上述栅极驱动电路的实施例，重复之处不再赘述。
在具体实施时，本公开实施例提供的上述显示装置可以是液晶显示装置，也可以是有机电致发光显示装置，在此不作限定。
基于同一发明构思，本公开实施例还提供了一种栅极驱动电路的驱动方法，包括：
在全屏扫描模式下，在确定第m行移位寄存器被指定为局部扫描模式下的扫描起始行时，在第m行移位寄存器的栅极信号输出端输出有效信号时，对信号输出选择端输入有效信号；
在局部扫描模式的起始时刻，对触发信号端输入有效电位信号，同时对信号输出终止端输入关断信号；在第n行移位寄存器的栅极信号输出端输出有效信号时，对触发信号端输入有效电位信号，同时对信号输出终止端输入关断信号；其中，n和m为正整数，n大于m；即在全屏扫描模式下和局部扫描模式的第m行移位寄存器的栅极信号输出端输出有效信号至第n-1行移位寄存器的栅极信号输出端输出有效信号时，对信号输出终止端持续输入有效信号；
在恢复全屏扫描模式之前，对输出复位信号端输入有效电位信号。
下面通过提供两个实施例说明本公开实施例提供的上述栅极驱动电路从全屏扫描切换至指定行扫描的输入输出时序图。
如图5所示，分辨率切换触发帧T1示意出从第1行至第13行的移位寄存器中各信号的输入输出时序图，分辨率切换显示阶段T2示意出切换至从第m＝3行输出至第n＝9行截止。从图5可以看出，分辨率切换触发帧T1是全屏扫描，下一帧配合信号输出切换电路的CGI、CGS、CGE各信号端输出的信号来实现切换从第3行扫描至第9行，具体的栅极驱动电路的详细工作原理参见本公开实施例提供的上述移位寄存器的工作原理，在此不做赘述。
如图6所示，分辨率切换触发帧T1示意出从第1行至第15行的移位寄存器中各信号的输入输出时序图，分辨率切换显示阶段T2示意出切换至从第m＝5行输出至第n＝12行截止。从图6可以看出，分辨率切换触发帧T1是全屏扫描，下一帧配合信号输出切换电路的CGI、CGS、CGE各信号端输出的信号来实现切换从第5行扫描至第12行，具体的栅极驱动电路的详细工作原理参见本公开实施例提供的上述移位寄存器的工作原理，在此不做赘述。
本公开实施例提供的一种移位寄存器、栅极驱动电路及其驱动方法、显示装置，通过在输入控制电路1和复位控制电路2之间的第一节点，增加信号输出切换电路，其中的信号输出选择电路6在确定本移位寄存器被指定为局部扫描模式下的扫描起始行时，在栅极信号输出端Out N信号的控制下，将信号输出选择端CGI的信号提供给第二节点B，信号输出触发电路7被配置 为在局部扫描模式下且在本移位寄存器被指定为扫描起始行时，在第二节点B的电位控制下，将触发信号端CGS的信号提供给第一节点A，以代替输入控制电路1为第一节点A提供控制输出控制电路3的信号，实现任意行移位寄存器作为扫描起始行的功能。同时，在第一参考信号端CN与输入控制电路1之间增加第一信号输出终止电路，在复位控制电路2与第二参考信号端CNb之间的第二信号输出终止电路，可以实现任意行移位寄存器作为扫描结束行的功能。通过上述几个电路的相互配合，可以实现对移位寄存器的起始行到结束行之间任意行进行选择输出扫描信号，从而实现对panel分辨率的选择，降低功耗，延长待机时间。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

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  1. 一种移位寄存器，其中，包括：
    输入控制电路，被配置为响应于信号输入端的有效信号，将第一参考信号端的信号提供给第一节点；
    复位控制电路，被配置为响应于复位信号端的有效信号，将第二参考信号端的信号提供给所述第一节点；
    第一输出控制电路，被配置为响应于所述第一节点的电位，控制栅极信号输出端的信号输出；
    信号输出终止电路，被配置为在局部扫描模式下，响应于信号输出终止端的有效信号，终止所述第一参考信号端与所述输入控制电路之间的导通状态，终止所述第二参考信号端与所述复位控制电路之间的导通状态；
    信号输出选择电路，被配置为在确定本移位寄存器被指定为所述局部扫描模式下的扫描起始行时，响应于所述栅极信号输出端输出的有效信号，将信号输出选择端的有效信号提供给第二节点；
    信号输出触发电路，被配置为在所述局部扫描模式下且在本移位寄存器被指定为所述扫描起始行时，响应于所述第二节点的电位，将触发信号端的信号提供给所述第一节点；
    信号输出复位电路，被配置为在确定恢复全屏扫描模式时，响应于输出复位信号端的有效信号，将第三参考信号端的信号提供给所述第二节点。
  2. 如权利要求1所述的移位寄存器，其中，所述信号输出终止电路包括：第一信号输出终止电路和第二信号输出终止电路；所述第一信号输出终止电路包括第一开关晶体管，所述第二信号输出终止电路包括第二开关晶体管；其中，
    所述第一开关晶体管，其栅极与所述信号输出终止端耦接，第一极与所述第一参考信号端耦接，第二极与所述输入控制电路耦接；
    所述第二开关晶体管，其栅极与所述信号输出终止端耦接，第一极与所 述第二参考信号端耦接，第二极与所述复位控制电路耦接。
  3. 如权利要求1所述的移位寄存器，其中，所述信号输出选择电路包括：第三开关晶体管；其中，
    所述第三开关晶体管，其栅极与所述栅极信号输出端耦接，第一极与所述信号输出选择端耦接，第二极与所述第二节点耦接。
  4. 如权利要求1所述的移位寄存器，其中，所述信号输出复位电路包括：第四开关晶体管；其中，
    所述第四开关晶体管，其栅极与所述输出复位信号端耦接，第一极与所述第三参考信号端耦接，第二极与所述第二节点耦接。
  5. 如权利要求1所述的移位寄存器，其中，所述信号输出触发电路包括：第五开关晶体管和第一电容；其中，
    所述第五开关晶体管，其栅极与所述第二节点耦接，第一极与所述触发信号端耦接，第二极与所述第一节点耦接；
    所述第一电容，其第一端与所述第二节点耦接，第二端与所述第一节点耦接。
  6. 如权利要求5所述的移位寄存器，其中，所述信号输出触发电路还包括：第六开关晶体管；其中，
    所述第六开关晶体管，其栅极与所述第一电容的第二端耦接，第一极与第四参考信号端耦接，第二极与所述第一节点耦接。
  7. 如权利要求2所述的移位寄存器，其中，所述输入控制电路包括：第七开关晶体管；其中，
    第七开关晶体管，其栅极与所述信号输入端耦接，第一极与所述第一开关晶体管的第二极耦接，第二极与所述第一节点耦接。
  8. 如权利要求2所述的移位寄存器，其中，所述复位控制电路包括：第八开关晶体管；其中，
    第八开关晶体管，其栅极与所述复位信号端耦接，第一极与所述第二开关晶体管的第二极耦接，第二极与所述第一节点耦接。
  9. 如权利要求1所述的移位寄存器，其中，还包括：节点控制电路，被配置为响应于所述第一节点和所述栅极信号输出端的电位，控制第三节点的电位。
  10. 如权利要求9所述的移位寄存器，其中，所述节点控制电路包括：第九开关晶体管、第十一开关晶体管、第十二开关晶体管和第二电容；其中，
    第九开关晶体管，其栅极和第一极均与第一时钟信号端耦接，第二极与第三节点耦接；第十一开关晶体管，其栅极与所述第一节点耦接，第一极与所述第三节点耦接，第二极与所述第三参考信号端耦接；
    第十二开关晶体管，其栅极与所述栅极信号输出端耦接，第一极与所述第三节点耦接，第二极与所述第三参考信号端耦接；
    第二电容，其第一端与所述第三节点耦接，第二端与所述第三参考信号端耦接。
  11. 如权利要求1所述的移位寄存器，其中，所述第一输出控制电路包括：第十三开关晶体管和第三电容；其中，
    第十三开关晶体管，其栅极与所述第一节点耦接，第一极与第二时钟信号端耦接，第二极与所述栅极信号输出端耦接；
    第三电容，其第一端与所述第一节点耦接，第二端与所述栅极信号输出端耦接。
  12. 如权利要求9所述的移位寄存器，其中，还包括：第二输出控制电路，被配置为响应于所述第三节点的电位，将所述第三参考信号端的信号提供给所述栅极信号输出端和所述第一节点。
  13. 如权利要求12所述的移位寄存器，其中，所述第二输出控制电路包括：第十开关晶体管和第十四开关晶体管；其中，
    第十开关晶体管，其栅极与所述第三节点耦接，第一极与所述第一节点耦接，第二极与所述第三参考信号端耦接；
    第十四开关晶体管，其栅极与所述第三节点耦接，第一极与所述栅极信号输出端耦接，第二极与所述第三参考信号端耦接。
  14. 如权利要求9所述的移位寄存器，其中，还包括：初始化电路，被配置为响应于初始化信号端的信号，对所述第三节点进行初始化。
  15. 如权利要求14所述的移位寄存器，其中，所述初始化电路包括：第十五开关晶体管；其中，
    所述第十五开关晶体管，其栅极和第一极均与初始化信号端耦接，第二极与所述第三节点耦接。
  16. 如权利要求1-15任一项所述的移位寄存器，其中，所述移位寄存器所包含的全部开关晶体管为N型晶体管。
  17. 一种栅极驱动电路，其中，包括级联的多个如权利要求1-16任一项所述的移位寄存器；其中，
    除最后一级移位寄存器之外，每一级移位寄存器的栅极信号输出端与其相邻的下一级移位寄存器的信号输入端耦接；
    除第一级移位寄存器之外，每一级移位寄存器的栅极信号输出端与其相邻的上一级移位寄存器的复位信号端耦接。
  18. 一种显示装置，其中，包括如权利要求17所述的栅极驱动电路。
  19. 一种如权利要求17所述的栅极驱动电路的驱动方法，其中，包括：
    在全屏扫描模式下，在确定第m行移位寄存器被指定为局部扫描模式下的扫描起始行时，在所述第m行移位寄存器的栅极信号输出端输出有效信号时，对所述信号输出选择端输入有效信号；
    在局部扫描模式的起始时刻，对所述触发信号端输入有效电位信号，同时对所述信号输出终止端输入关断信号；在作为扫描终止行的第n行移位寄存器的栅极信号输出端输出有效信号时，对所述触发信号端输入有效电位信号，同时对所述信号输出终止端输入关断信号；其中，n和m为正整数，n大于m；
    在恢复所述全屏扫描模式之前，对所述输出复位信号端输入有效电位信号。
PCT/CN2020/076669 2019-03-25 2020-02-25 移位寄存器、栅极驱动电路及其驱动方法、显示装置 WO2020192340A1 (zh)

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