WO2015180420A1 - 移位寄存器、栅极集成驱动电路及显示屏 - Google Patents

移位寄存器、栅极集成驱动电路及显示屏 Download PDF

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Publication number
WO2015180420A1
WO2015180420A1 PCT/CN2014/090747 CN2014090747W WO2015180420A1 WO 2015180420 A1 WO2015180420 A1 WO 2015180420A1 CN 2014090747 W CN2014090747 W CN 2014090747W WO 2015180420 A1 WO2015180420 A1 WO 2015180420A1
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Prior art keywords
pull
node
thin film
signal
shift register
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PCT/CN2014/090747
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English (en)
French (fr)
Inventor
赵卫杰
董学
王海生
杨盛际
刘英明
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/443,589 priority Critical patent/US9766741B2/en
Priority to EP14861121.3A priority patent/EP3151235B1/en
Publication of WO2015180420A1 publication Critical patent/WO2015180420A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of liquid crystal display technologies, and in particular, to a shift register, a gate integrated driving circuit, and a display screen.
  • a gate driving signal is generally supplied to a gate of each thin film transistor (TFT) of a pixel region by a gate driving device.
  • the gate driving device can be formed on the array substrate of the liquid crystal display by an array process, that is, a Gate Driver on Array (GOA) process, which not only saves cost, but also can realize a liquid crystal panel (Panel).
  • GOA Gate Driver on Array
  • the symmetrical aesthetic design of both sides, at the same time, the bonding area of the integrated circuit of the integrated circuit (IC) and the fan-out wiring space are omitted, so that the design of the narrow bezel can be realized; This integrated process also eliminates the Bonding process in the gate direction, which increases throughput and yield.
  • the embodiment of the invention provides a shift register, a gate integrated driving circuit and a display screen, which can solve the problem that the existing GOA circuit cannot be normally displayed when applied to a touch screen with a high rate of dot rate.
  • a shift register comprising:
  • a first thin film transistor having a gate connected to the signal input end, a drain connected to the first reference signal end, and a source connected to the first pull-up node;
  • a second thin film transistor having a gate connected to the reset signal end, a drain connected to the first pull-up node, and a source connected to the second reference signal end;
  • a third thin film transistor having a gate connected to the second pull-up node, a drain connected to the clock signal end, and a source connected to the signal output end;
  • a fourth thin film transistor having a gate connected to the touch control signal end, a drain connected to the signal output end, a source connected to the low voltage signal end, and the touch control signal end being used for guiding the touch period Passing the fourth thin film transistor, disconnecting the fourth thin film transistor during a display period;
  • a leakage prevention module connected between the display control signal end, the first pull-up node and the second pull-up node, for conducting the display period during the display period under the control of the display control signal end
  • the first pull-up node and the second pull-up node disconnect the connection of the first pull-up node and the second pull-up node during a touch time period.
  • the shift register provided by the embodiment of the present invention sets a connection point of a source of the first thin film transistor and a drain of the second thin film transistor as a first pull-up node, and connects the capacitor to the gate of the third thin film transistor.
  • the point is set as a second pull-up node, and an anti-leakage module is added between the first pull-up node and the second pull-up node, and the module is turned on first during the display period of one frame under the control of the display control signal end.
  • the pull-up node and the second pull-up node enable the shift register to achieve a normal gate-on signal output; the connection of the first pull-up node and the second pull-up node is disconnected during a touch period of one frame, which is equivalent to the capacitor
  • a resistor with a large resistance value is connected in series in the discharge path, which can greatly reduce the discharge of the capacitor, effectively reduce the leakage speed of the capacitor, and avoid dividing the frame time of the touch screen into multiple display time periods and touch time periods. In order to improve the touch report rate, there may be problems that cannot be displayed properly.
  • the anti-leakage module specifically includes: a fifth thin film transistor having a gate connected to the display control signal end and a drain Connected to the first pull-up node and connected to the second pull-up node.
  • all the thin film transistors included in the shift register are N-type thin film transistors
  • the display control signal end provides a high level signal, and the touch control signal end provides a low level signal;
  • the display control signal end provides a low level signal, and the touch control signal end provides a high level signal.
  • the first reference signal end when the forward scan is started, provides a high level signal during the display period, and the second The reference signal terminal provides a low level signal;
  • the first reference signal end and the second reference signal end simultaneously provide a high level signal.
  • the first reference signal end when the reverse scan is started, provides a low level signal during the display period.
  • the second reference signal terminal provides a high level signal;
  • the first reference signal end and the second reference signal end simultaneously provide a high level signal.
  • the shift register provided by the embodiment of the present invention further includes: a pull-down module connected to the display control signal end, the first pull-up node, the second pull-up node, The signal output terminal and the low voltage signal terminal are configured to maintain the first pull-up node, the second pull-up node, and the signal output terminal at a low level during the non-working time of the shift register.
  • the pull-down module specifically includes:
  • a sixth thin film transistor having a drain connected to the display control signal end and a source connected to the pull-down node;
  • a seventh thin film transistor having a drain connected to the pull-down node, a gate connected to the second pull-up node, and a source connected to the low-voltage signal terminal;
  • An eighth thin film transistor having a gate and a drain connected to the display control signal end and a source connected to a gate of the sixth thin film transistor;
  • a ninth thin film transistor having a drain connected to a source of the eighth thin film transistor, a gate connected to the second pull-up node, and a source connected to the low voltage signal terminal;
  • a tenth thin film transistor having a drain connected to the first pull-up node, a gate connected to the pull-down node, and a source connected to the low voltage signal end;
  • the eleventh thin film transistor has a drain connected to the signal output terminal, a gate connected to the pull-down node, and a source connected to the low voltage signal terminal.
  • An embodiment of the present invention provides a gate integrated driving circuit, including any one of the above-mentioned shift registers provided by the example of the present invention
  • each of the shift registers inputs a trigger signal to the signal input of the next shift register adjacent thereto and moves to the adjacent one adjacent thereto.
  • the embodiment of the invention provides a display screen comprising the above-mentioned gate integrated driving circuit provided by the embodiment of the invention.
  • 1a is a schematic structural view of a GOA circuit
  • Figure 1b is a schematic structural diagram of a shift register
  • FIG. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention.
  • FIG. 3 is a second schematic structural diagram of a shift register according to an embodiment of the present disclosure.
  • 4a and 4b are timing diagrams of forward scan and reverse scan of a shift register according to an embodiment of the present invention.
  • 4c is a specific input and output timing diagram of a shift register according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a shift register with a pull-down module according to an embodiment of the present disclosure
  • FIG. 6 is a second schematic structural diagram of a shift register with a pull-down module according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a gate integrated driving circuit according to an embodiment of the present invention.
  • FIG. 1a shows a gate integrated drive circuit composed of a plurality of shift registers for providing a gate scan signal to a gate line connected to a signal output terminal of the shift register, and A reset signal is input to the reset signal terminal of the previous shift register adjacent thereto, and a trigger signal is input to the signal input terminal of the next shift register adjacent thereto.
  • Figure 1b shows a schematic diagram of a shift register.
  • the four basic thin-film transistors M1-M4 and a capacitor C1 can be used to implement the most basic shift register function.
  • the specific working principle is as follows: Input high level at the signal input terminal Input During the signal, the first thin film transistor M1 is turned on to charge the pull-up node, that is, the PU node, and the third thin film transistor M3 is turned on; when the clock signal terminal CLK inputs a high level signal, the turned-on third thin film transistor M3 enables The signal output terminal Output outputs a high level signal provided by the clock signal terminal CLK, and the PU node is further pulled up due to the bootstrap action of the capacitor C1; after that, when the reset signal terminal Reset inputs a high level signal, the second thin film transistor M2 and The fourth thin film transistor M4 is turned on to discharge the PU node and the signal output terminal Output.
  • one frame time of the liquid crystal screen may be divided into multiple Display time period and touch time period.
  • the GOA circuit outputs the gate-on signal from the original continuous sequence to the gate signal line connected thereto, and becomes the operation only in the display period, that is, the GOA circuit stops working for a plurality of touch periods in one frame time. For example, in the GOA shown in FIG.
  • a touch period is set between the N-1th shift register and the Nth shift register output timing, and after the N-1th shift register is operated, the Nth
  • the trigger signal input from the signal output terminal of the -1 shift register to the signal input terminal of the Nth shift register has caused the potential of the PU node in the Nth shift register to be pulled high, but in the Nth shift register
  • the third thin film transistor M3 needs to be turned on after a touch period. At this time, the PU node is in a floating state, the capacitor C1 starts to discharge, and its discharge path (shown by a broken line in FIG.
  • the second thin film transistor M2 is connected to the low voltage signal terminal VSS, and the other is passed through the first thin film transistor M1 to the high voltage signal terminal VDD, causing leakage phenomenon of the PU node.
  • the second thin film transistor M2 is formed in the non-display area of the display screen. Its large size results in a large leakage current, which accelerates the charge flow of the PU node to the low voltage signal terminal VSS at a low potential.
  • the third thin film transistor M3 in the Nth stage shift register is turned on, but the voltage of the PU node is lowered, causing the gate turn signal on the gate signal line connected to the signal output terminal to be too low. Finally, the display does not display properly.
  • a shift register provided by an embodiment of the present invention, as shown in FIG. 2, includes:
  • the first thin film transistor T1 has a gate connected to the signal input terminal Input, a drain connected to the first reference signal terminal Ref1, and a source connected to the first pull-up node PU1;
  • the second thin film transistor T2 has a gate connected to the reset signal terminal Reset, a drain connected to the first pull-up node PU1, and a source connected to the second reference signal terminal Ref2;
  • the third thin film transistor T3 has a gate connected to the second pull-up node PU2, a drain connected to the clock signal terminal CLK, and a source connected to the signal output terminal Output;
  • the fourth thin film transistor T4 has a gate connected to the touch control signal terminal CT2, a drain connected to the signal output terminal Output, a source connected to the low voltage signal terminal VSS, and a touch control signal terminal CT2 for the touch time period. Turning on the fourth thin film transistor T4, disconnecting the fourth thin film transistor T4 during the display period;
  • the anti-leakage module is connected between the display control signal terminal CT1, the first pull-up node PU1 and the second pull-up node PU2, and is used to turn on the first time during the display period under the control of the display control signal terminal CT1.
  • the connection between the pull-up node PU1 and the second pull-up node PU2 disconnects the connection between the first pull-up node PU1 and the second pull-up node PU2 during the touch time period.
  • the shift register provided by the embodiment of the present invention sets the connection point of the source of the first thin film transistor T1 and the drain of the second thin film transistor T2 as the first pull-up node PU1, and the capacitor C1 and the third thin film transistor T3.
  • the connection point of the gate is set as the second pull-up node PU2, and an anti-leakage module is added between the first pull-up node PU1 and the second pull-up node PU2.
  • the module is under the control of the display control signal end CT1.
  • the display period of one frame turns on the first pull-up node PU1 and the second pull-up node PU2, so that the shift register realizes the normal gate-on signal output; the first pull-up node PU1 is disconnected in the touch period of one frame.
  • connection with the second pull-up node PU2 is equivalent to connecting a resistor having a large resistance value in the discharge path of the capacitor C1, which can greatly slow down the discharge of the capacitor C1, effectively reduce the leakage speed of the capacitor C1, and avoid the one of the touch screen.
  • the frame time is divided into a plurality of display time periods and a touch time period which are alternately performed to improve the problem that the touch report rate may not be displayed normally.
  • the source and the drain of the thin film transistor may be interchanged according to the type of the transistor and the input signal, and no specific distinction is made herein.
  • the anti-leakage module may specifically include: a fifth thin film transistor T5 having a gate and a display control signal end CT1 The connection and the drain are connected to the first pull-up node PU1, and the source is connected to the second pull-up node PU2.
  • the fifth thin film transistor T5 as the anti-leakage module and the other thin film transistors in the shift register which are added in the above-mentioned shift register provided by the embodiment of the present invention generally adopt the same type of thin film transistor, in specific implementation, N-type thin film transistors are generally used.
  • the display control signal end CT1 in order to ensure that the signal output end of the shift register provided by the embodiment of the present invention can normally output the gate turn-on signal during each display period of one frame, the display control signal end CT1 will always provide stability during the display period.
  • the high-level signal causes the fifth thin film transistor T5 to be in an on state, that is, in a conducting state between the first pull-up node PU1 and the second pull-up node PU2; correspondingly, the touch control signal CT2 end is always provided
  • a stable low level signal ensures that the fourth thin film transistor T4 is in an off state.
  • the display control signal terminal always provides a stable low level signal, so that the fifth thin film transistor T5 is in an off state, that is, the first pull-up node PU1 and the second pull-up node PU2 are in an off state;
  • the touch control signal terminal CT2 always provides a stable high level signal to ensure that the fourth thin film transistor T4 is in an on state, so as to lower the voltage of the signal output terminal to ensure no signal output.
  • the reset signal terminal has a symmetrical design, and functions can be interchanged. Therefore, the above shift register provided by the embodiment of the present invention can implement bidirectional scanning.
  • the first reference signal terminal Ref1 provides a high level signal
  • the second reference signal terminal Ref2 provides a low level signal.
  • the second reference signal end Ref2 may be set to a high level, that is, the second reference signal end Ref2 and the first reference signal end Ref1 during the touch period (Touch).
  • a high level signal is also provided, which further slows the flow of current.
  • the first reference signal terminal Ref1 provides a low level signal
  • the second reference signal terminal Ref2 provides a high level signal.
  • the first reference signal end Ref1 may be set to a high level, that is, the first reference signal end Ref1 and the second reference signal end Ref2 during the touch period (Touch).
  • a high level signal is also provided, which further slows the flow of current.
  • the first reference signal terminal Ref1 pulls the second pull-up node PU2 high through the first thin film transistor T1 and charges the capacitor C1.
  • the T1 phase is the charging phase of capacitor C1 in the shift register.
  • the T2 phase is the touch time period.
  • the T3 phase is the phase in which the shift register is turned on.
  • the T4 phase is the discharge phase of the capacitor C1 in the shift register.
  • the method further includes: a pull-down module connected to the display control signal.
  • the terminal CT1, the first pull-up node PU1, the second pull-up node PU2, the signal output terminal Output and the low voltage signal terminal VSS are used to maintain the first pull-up node PU1 in the non-working time of the shift register.
  • the two pull-up nodes PU2 and the signal output terminal are low level to reduce the noise output.
  • the pull-down module in the foregoing shift register provided by the embodiment of the present invention, as shown in FIG. 6, may specifically include:
  • a sixth thin film transistor T6 having a drain connected to the display control signal terminal CT1 and a source connected to the pull-down node PD;
  • a seventh thin film transistor T7 having a drain connected to the pull-down node PD, a gate connected to the second pull-up node PU2, and a source connected to the low voltage signal terminal VSS;
  • the eighth thin film transistor T8 has a gate and a drain connected to the display control signal terminal CT1 and a source connected to the gate of the sixth thin film transistor T6;
  • a ninth thin film transistor T9 having a drain connected to a source of the eighth thin film transistor T8, a gate connected to the second pull-up node PU2, and a source connected to the low voltage signal terminal VSS;
  • the tenth thin film transistor T10 has a drain connected to the first pull-up node PU1, a gate and a pull-down section Point PD is connected, and the source is connected to the low voltage signal terminal VSS;
  • the eleventh thin film transistor T11 has a drain connected to the signal output terminal Output, a gate connected to the pull-down node PD, and a source connected to the low voltage signal terminal VSS.
  • the eighth thin film transistor T8 is turned on to turn on the sixth thin film transistor T6, and the voltage of the pull-down node PD is pulled high, so that the tenth thin film transistor T10 and the eleventh thin film transistor T11 are turned on. It is in an on state, thereby deriving the noise of the first pull-up node PU1 and the second pull-up node PU2 and the signal output terminal Output to the low voltage signal terminal VSS.
  • the second pull-up node PU2 is further pulled up due to the bootstrap action of the capacitor C1, so that the seventh thin film transistor T7 and the ninth thin film transistor T9 are in an on state, and the voltage of the pull-down node PD is pulled down to make the tenth
  • the thin film transistor T10 and the eleventh thin film transistor T11 are in an off state to ensure a normal output of the signal output terminal Output.
  • the second pull-up node PU2 is pulled low after the second thin film crystal T2 is turned on, the seventh thin film transistor T7 and the ninth thin film transistor T9 are turned off, CT1 is high, T8, T6 are turned on, and the pull-down is performed.
  • the voltage of the node PD is gradually pulled high, so that the tenth thin film transistor T10 and the eleventh thin film transistor T11 are in an on state, thereby deriving the noise of the first pull-up node PU1 and the second pull-up node PU2 and the signal output terminal Output to The second reference signal terminal Ref2 or the low voltage signal terminal VSS.
  • the above is only a specific structure of the pull-down module in the shift register.
  • the specific structure of the pull-down module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art. Not limited.
  • an embodiment of the present invention further provides a gate integrated driving circuit, as shown in FIG. 7, including a plurality of shift registers connected in series, except for the first shift register and the last shift register.
  • the signal output terminal Output of each of the remaining shift registers inputs a trigger signal to the signal input end of the next shift register adjacent thereto, and inputs a reset signal to the reset signal end of the previous shift register adjacent thereto;
  • the signal output terminal Output of the first shift register inputs a trigger signal to the signal input end of the second shift register;
  • the signal output terminal Output of the last shift register inputs a reset to itself and the reset signal terminal of the previous shift register. signal.
  • shift registers For convenience of explanation, only five shift registers are shown in FIG. 7, which are an N-2th shift register, an N-1th shift register, an Nth shift register, and an N+1th shift.
  • Bit register The N+2th shift register.
  • the signal output terminal Output(n) of the Nth stage shift register not only outputs a gate turn-on signal to the gate signal line connected thereto, but also outputs a reset signal to the N-1th shift register, and also to the N+th
  • the 1-stage shift register outputs a trigger signal.
  • each shift register in the above-mentioned gate integrated driving circuit is the same as the above-mentioned shift register of the present invention, and the details are not repeated herein.
  • an embodiment of the present invention further provides a display screen, including the above-described gate integrated driving circuit.
  • a display screen including the above-described gate integrated driving circuit.
  • the shift register, the gate integrated driving circuit and the display screen provided by the embodiment of the invention provide a connection point of a source of the first thin film transistor and a drain of the second thin film transistor as a first pull-up node, and a capacitance
  • the connection point of the gate of the third thin film transistor is set as a second pull-up node, and a leakage preventing module is added between the first pull-up node and the second pull-up node, and the module is under the control of the display control signal end,
  • the display period of the frame turns on the first pull-up node and the second pull-up node, so that the shift register realizes normal gate-on signal output; disconnects the first pull-up node and the second on a touch period of one frame
  • the connection of the pull node is equivalent to connecting a resistor with a large resistance value in the discharge path of the capacitor, which can greatly reduce the discharge of the capacitor, effectively reduce the leakage speed of the capacitor, and avoid dividing the frame time of the touch screen into multiple alternates

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

公开了一种移位寄存器、栅极集成驱动电路及显示屏。该移位寄存器将第一薄膜晶体管（T1）的源极和第二薄膜晶体管（T2）的漏极的连接点设置为第一上拉节点（PU1），将电容（C1）和第三薄膜晶体管（T3）的栅极的连接点设置为第二上拉节点（PU2），在第一上拉节点（PU1）和第二上拉节点（PU2）之间增加一防漏电模块。该模块在显示控制信号端的控制下，在一帧的显示时间段导通第一上拉节点（PU1）和第二上拉节点（PU2），使移位寄存器实现正常的栅开启信号输出；在一帧的触控时间段断开第一上拉节点（PU1）和第二上拉节点（PU2）的连接，相当于在电容（C1）的放电路径中串联一个阻值较大的电阻，能够大大减缓电容放电的时间，有效降低电容的漏电速度，避免了应用于高报点率的触摸屏时可能出现的无法正常显示的问题。

Description

移位寄存器、栅极集成驱动电路及显示屏 技术领域
本公开涉及液晶显示技术领域，尤其涉及一种移位寄存器、栅极集成驱动电路及显示屏。
背景技术
在薄膜晶体管液晶显示器(TFT-LCD，Thin Film Transistor Liquid Crystal Display)中，通常通过栅极驱动装置向像素区域的各个薄膜晶体管(TFT，Thin Film Transistor)的栅极提供栅极驱动信号。栅极驱动装置可以通过阵列工艺形成在液晶显示器的阵列基板上，即阵列基板行驱动(Gate Driver on Array,GOA)工艺，这种集成工艺不仅节省了成本，而且可以做到液晶面板(Panel)两边对称的美观设计，同时，也省去了栅极集成电路(IC，Integrated Circuit)的绑定(Bonding)区域以及扇出(Fan-out)的布线空间，从而可以实现窄边框的设计；并且，这种集成工艺还可以省去栅线方向的Bonding工艺，从而提高了产能和良率。
发明内容
本发明实施例提供了一种移位寄存器、栅极集成驱动电路及显示屏，可以解决现有GOA电路在应用于高报点率的触摸屏时出现的无法正常显示的问题。
根据本发明的实施例，提供了一种移位寄存器，包括：
第一薄膜晶体管，其栅极与信号输入端相连、漏极与第一参考信号端相连，源极与第一上拉节点相连；
第二薄膜晶体管，其栅极与复位信号端相连、漏极与所述第一上拉节点相连、源极与第二参考信号端相连；
第三薄膜晶体管，其栅极与第二上拉节点相连、漏极与时钟信号端相连、源极与信号输出端相连；
第四薄膜晶体管，其栅极与触控控制信号端相连、漏极与所述信号输出端相连、源极与低电压信号端相连，所述触控控制信号端用于在触控时间段导通所述第四薄膜晶体管，在显示时间段断开所述第四薄膜晶体管；
电容，其连接在所述第二上拉节点和所述信号输出端之间；
防漏电模块，其连接在显示控制信号端、所述第一上拉节点和所述第二上拉节点之间，用于在所述显示控制信号端的控制下，在显示时间段导通所述第一上拉节点和所述第二上拉节点，在触控时间段断开所述第一上拉节点和所述第二上拉节点的连接。
本发明实施例提供的上述移位寄存器，将第一薄膜晶体管的源极和第二薄膜晶体管的漏极的连接点设置为第一上拉节点，将电容和第三薄膜晶体管的栅极的连接点设置为第二上拉节点，在第一上拉节点和第二上拉节点之间增加一个防漏电模块，该模块在显示控制信号端的控制下，在一帧的显示时间段导通第一上拉节点和第二上拉节点，使移位寄存器实现正常的栅开启信号输出；在一帧的触控时间段断开第一上拉节点和第二上拉节点的连接，相当于在电容的放电路径中串联一个阻值较大的电阻，能够大大减缓电容的放电，有效降低电容的漏电速度，避免了将触摸屏的一帧时间分为交替进行的多个显示时间段和触控时间段以提高触控报点率时可能出现的无法正常显示的问题。
在一种可能的实施方式中，在本发明实施例提供的上述移位寄存器中，所述防漏电模块，具体包括：第五薄膜晶体管，其栅极与所述显示控制信号端相连、漏极与第一上拉节点相连、源极与第二上拉节点相连。
在一种可能的实施方式中，在本发明实施例提供的上述移位寄存器中，所述移位寄存器中包含的所有薄膜晶体管均为N型薄膜晶体管；
在显示时间段，所述显示控制信号端提供高电平信号，所述触控控制信号端提供低电平信号；
在触控时间段，所述显示控制信号端提供低电平信号，所述触控控制信号端提供高电平信号。
在一种可能的实施方式中，在本发明实施例提供的上述移位寄存器中，启动正向扫描时，在显示时间段，所述第一参考信号端提供高电平信号，所述第二参考信号端提供低电平信号；
在触控时间段，所述第一参考信号端和所述第二参考信号端同时提供高电平信号。
在一种可能的实施方式中，在本发明实施例提供的上述移位寄存器中，启动反向扫描时，在显示时间段，所述第一参考信号端提供低电平信号，所 述第二参考信号端提供高电平信号；
在触控时间段，所述第一参考信号端和所述第二参考信号端同时提供高电平信号。
在一种可能的实施方式中，在本发明实施例提供的上述移位寄存器中，还包括：下拉模块，其连接在所述显示控制信号端、第一上拉节点、第二上拉节点、信号输出端以及低电压信号端之间，用于在所述移位寄存器的非工作时间内维持所述第一上拉节点、第二上拉节点和信号输出端为低电平。
在一种可能的实施方式中，在本发明实施例提供的上述移位寄存器中，所述下拉模块，具体包括：
第六薄膜晶体管，其漏极与所述显示控制信号端相连、源极与下拉节点相连；
第七薄膜晶体管，其漏极与所述下拉节点相连、栅极与所述第二上拉节点相连、源极与所述低电压信号端相连；
第八薄膜晶体管，其栅极和漏极分别与所述显示控制信号端相连、源极与第六薄膜晶体管的栅极相连；
第九薄膜晶体管，其漏极与第八薄膜晶体管的源极相连、栅极与所述第二上拉节点相连、源极与所述低电压信号端相连；
第十薄膜晶体管，其漏极与所述第一上拉节点相连、栅极与所述下拉节点相连、源极与所述低电压信号端相连；
第十一薄膜晶体管，其漏极与所述信号输出端相连、栅极与所述下拉节点相连、源极与所述低电压信号端相连。
本发明实施例提供了一种栅极集成驱动电路，包括串联的多个本发明实例例提供的上述任一种移位寄存器；
除第一个移位寄存器和最后一个移位寄存器之外，其余每个移位寄存器均向与其相邻的下一个移位寄存器的信号输入端输入触发信号，并向与其相邻的上一个移位寄存器的复位信号端输入复位信号；第一个移位寄存器向第二个移位寄存器的信号输入端输入触发信号；最后一个移位寄存器向自身以及上一个移位寄存器的复位信号端输入复位信号。
本发明实施例提供了一种显示屏，包括本发明实施例提供的上述栅极集成驱动电路。
附图说明
图1a为一种的GOA电路的结构示意图；
图1b为一种的移位寄存器的结构示意图；
图2为本发明实施例提供的移位寄存器的结构示意图之一；
图3为本发明实施例提供的移位寄存器的结构示意图之二；
图4a和图4b分别为本发明实施例提供的移位寄存器的正向扫描和反向扫描的时序图；
图4c为本发明实施例提供的一个移位寄存器的具体输入输出时序图；
图5为本发明实施例提供的具有下拉模块的移位寄存器的结构示意图之一；
图6为本发明实施例提供的具有下拉模块的移位寄存器的结构示意图之二；
图7为本发明实施例提供的栅极集成驱动电路的结构示意图。
具体实施方式
下面结合附图，对本发明实施例提供的移位寄存器、栅极集成驱动电路及显示屏的具体实施方式进行详细地说明。
图1a示出了一种栅极集成驱动电路，其由多个移位寄存器组成，各个移位寄存器用于向与该移位寄存器的信号输出端相连的栅线提供栅极扫描信号，并向与其相邻的上一个移位寄存器的复位信号端输入复位信号，向与其相邻的下一个移位寄存器的信号输入端输入触发信号。图1b示出了一种移位寄存器的结构示意图，使用4个薄膜晶体管M1-M4和一个电容C1可以实现最基本的移位寄存器功能，具体工作原理如下：在信号输入端Input输入高电平信号时，第一薄膜晶体管M1导通对上拉节点即PU节点充电，此时第三薄膜晶体管M3导通；当时钟信号端CLK输入高电平信号时，导通的第三薄膜晶体管M3使信号输出端Output输出时钟信号端CLK提供的高电平信号，同时由于电容C1的自举作用将PU节点进一步拉高；之后，复位信号端Reset输入高电平信号时，第二薄膜晶体管M2和第四薄膜晶体管M4导通，对PU节点和信号输出端Output放电。
在使用具有上述GOA电路的阵列基板制作内嵌式触摸屏时，为了提高触控的报点率以提高触控效果，可以将液晶屏的一帧时间分为交替进行的多个 显示时间段和触控时间段。这样，GOA电路从原来的连续依次向与其连接的栅极信号线输出栅开启信号，变为仅在显示时间段工作，即GOA电路在一帧时间的多个触控时间段都停止工作。例如图1a所示的GOA中在第N-1级移位寄存器和第N级移位寄存器输出时序之间设置有触控时间段，在第N-1级移位寄存器工作后，由第N-1级移位寄存器的信号输出端向第N级移位寄存器的信号输入端输入的触发信号已使第N级移位寄存器内的PU节点的电位拉高，但第N级移位寄存器内的第三薄膜晶体管M3需要经过一触控时间段才会导通，此时，PU节点处于浮动(Floating)状态，电容C1开始放电，其放电路径(图1b中虚线所示)一个是通过第二薄膜晶体管M2到低电压信号端VSS，另一个是通过第一薄膜晶体管M1到高电压信号端VDD，致使PU节点出现漏电现象，尤其第二薄膜晶体管M2是制作在显示屏的非显示区域，其尺寸较大导致其漏电流较大，会加速PU节点的电荷流向处于低电位的低电压信号端VSS。在经过触控时间段之后，第N级移位寄存器内的第三薄膜晶体管M3导通，但PU节点的电压已降低，导致与信号输出端连接的栅极信号线上的栅开启信号过低，最终导致显示屏不能正常显示。
本发明实施例提供的一种移位寄存器，如图2所示，包括：
第一薄膜晶体管T1，其栅极与信号输入端Input相连、漏极与第一参考信号端Ref1相连，源极与第一上拉节点PU1相连；
第二薄膜晶体管T2，其栅极与复位信号端Reset相连、漏极与第一上拉节点PU1相连、源极与第二参考信号端Ref2相连；
第三薄膜晶体管T3，其栅极与第二上拉节点PU2相连、漏极与时钟信号端CLK相连、源极与信号输出端Output相连；
第四薄膜晶体管T4，其栅极与触控控制信号端CT2相连、漏极与信号输出端Output相连、源极与低电压信号端VSS相连，触控控制信号端CT2用于在触控时间段导通第四薄膜晶体管T4，在显示时间段断开第四薄膜晶体管T4；
电容C1，其连接在第二上拉节点PU2和信号输出端Output之间；
防漏电模块，其连接在显示控制信号端CT1、第一上拉节点PU1和第二上拉节点PU2之间，用于在显示控制信号端CT1的控制下，在显示时间段导通第一上拉节点PU1和第二上拉节点PU2的连接，在触控时间段断开第一上拉节点PU1和第二上拉节点PU2的连接。
本发明实施例提供的上述移位寄存器，将第一薄膜晶体管T1的源极和第二薄膜晶体管T2的漏极的连接点设置为第一上拉节点PU1，将电容C1和第三薄膜晶体管T3的栅极的连接点设置为第二上拉节点PU2，在第一上拉节点PU1和第二上拉节点PU2之间增加一个防漏电模块，该模块在显示控制信号端CT1的控制下，在一帧的显示时间段导通第一上拉节点PU1和第二上拉节点PU2，使移位寄存器实现正常的栅开启信号输出；在一帧的触控时间段断开第一上拉节点PU1和第二上拉节点PU2的连接，相当于在电容C1的放电路径中串联一个阻值较大的电阻，能够大大减缓电容C1的放电，有效降低电容C1的漏电速度，避免了将触摸屏的一帧时间分为交替进行的多个显示时间段和触控时间段以提高触控报点率时可能出现的无法正常显示的问题。
需要说明的是，在本发明实施例提供的移位寄存器中，薄膜晶体管的源极和漏极根据晶体管类型以及输入信号的不同，其功能可以互换，在此不做具体区分。
可选地，为了便于实施，在本发明实施例提供的上述移位寄存器中，防漏电模块，如图3所示，可以具体包括：第五薄膜晶体管T5，其栅极与显示控制信号端CT1相连、漏极与第一上拉节点PU1相连、源极与第二上拉节点PU2相连。
具体地，在本发明实施例提供的上述移位寄存器中增加的作为防漏电模块的第五薄膜晶体管T5和移位寄存器中其他的薄膜晶体管一般均采用相同类型的薄膜晶体管，在具体实施时，一般均采用N型薄膜晶体管。
在具体实施时，为了保证本发明实施例提供的上述移位寄存器的信号输出端在一帧的各显示时间段能正常输出栅开启信号，在显示时间段，显示控制信号端CT1会一直提供稳定的高电平信号，使第五薄膜晶体管T5处于导通状态，即在第一上拉节点PU1和第二上拉节点PU2之间处于导通状态；对应地，触控控制信号CT2端一直提供稳定的低电平信号，保证第四薄膜晶体管T4处于截止状态。在触控时间段，显示控制信号端一直提供稳定的低电平信号，使第五薄膜晶体管T5处于截止状态，即第一上拉节点PU1和第二上拉节点PU2之间处于断开状态；对应地，触控控制信号端CT2一直提供稳定的高电平信号，保证第四薄膜晶体管T4处于导通状态，以拉低信号输出端Output的电压，保证无信号输出。
进一步地，由于在本发明实施例提供的上述移位寄存器中信号输入端和 复位信号端为对称设计，可以实现功能互换，因此本发明实施例提供的上述移位寄存器可以实现双向扫描。
一般地，在启动正向扫描时，如图4a所示，在显示时间段(Display)，第一参考信号端Ref1提供高电平信号，第二参考信号端Ref2提供低电平信号。可选地，为了进一步减缓电容C1的漏电速度，在触控时间段(Touch)，可以将第二参考信号端Ref2置为高电平，即第二参考信号端Ref2和第一参考信号端Ref1同时提供高电平信号，这样可以进一步减缓电流的流动。
一般地，在反向扫描时，如图4b所示，在显示时间段(Display)，第一参考信号端Ref1提供低电平信号，第二参考信号端Ref2提供高电平信号。可选地，为了进一步减缓电容C1的漏电速度，在触控时间段(Touch)，可以将第一参考信号端Ref1置为高电平，即第一参考信号端Ref1和第二参考信号端Ref2同时提供高电平信号，这样可以进一步减缓电流的流动。
下面结合图3所示的移位寄存器以及图4c所示的图3的输入输出时序图，以正向扫描为例对本发明实施例移位寄存器的工作过程作以描述。具体地，选取如图4c所示的输入输出时序图中的T1～T4四个阶段。下述描述中以1表示高电平信号，0表示低电平信号。
在T1阶段，Input＝1，CLK＝0，Reset＝0，Ref1＝1，Ref2＝0，CT1＝1，CT2＝0。由于CT1＝1，因此第五薄膜晶体管T5导通，第一上拉节点PU1和第二上拉节点PU2导通；由于Input＝1，因此第一薄膜晶体管T1导通并控制移位寄存器开始工作，第一参考信号端Ref1通过第一薄膜晶体管T1将第二上拉节点PU2拉高并为电容C1充电。在第二上拉节点PU2为高电平时，第三薄膜晶体管T3导通，但由于CLK＝0，因此信号输出端Output输出低电平信号。T1阶段为该移位寄存器中电容C1的充电阶段。
T2阶段，Input＝0，CLK＝0，Reset＝0，Ref1＝1，Ref2＝1，CT1＝0，CT2＝1。此时，第一薄膜晶体管T1、第二薄膜晶体管T2以及第五薄膜晶体管T5截止，第二上拉节点PU2保持高电平，且在第二上拉节点PU2为高电平时，第三薄膜晶体管T3导通，但由于CLK＝0，因此信号输出端Output输出低电平信号，且CT2＝1，第四薄膜晶体管T4处于导通状态，可以将信号输出端Output的噪声及时拉低。T2阶段为触控时间段。
T3阶段，Input＝0，CLK＝1，Reset＝0，Ref1＝1，Ref2＝0，CT1＝1，CT2＝0。由于Input＝0，因此第一薄膜晶体管T1截止；第三薄膜晶体管T3保持导通， 由于CLK＝1，因此第三薄膜晶体管T3将时钟信号端CLK上的高电平输出到信号输出端Output，电容C1的自举作用将第二上拉节点PU2进一步拉高；由信号输出端Output将CLK的高电平输出到与移位寄存器对应的一行栅线上，使液晶面板的显示区域内位于该行栅极信号线上的所有薄膜晶体管开启，数据信号线开始写入信号。T3阶段为该移位寄存器打开的阶段。
T4阶段，Input＝0，CLK＝0，Reset＝1，Ref1＝1，Ref2＝0，CT1＝1，CT2＝0。由于Reset＝1，因此第二薄膜晶体管T2导通。理论上第二薄膜晶体T2导通后将第二上拉节点PU2拉低至第二参考信号端Ref2的低电平。并且，在第二上拉节点PU2从高电平变为低电平时，第三薄膜晶体管T3由导通状态变为截止状态，信号输出端Output输出低电平信号。T4阶段为该移位寄存器中电容C1的放电阶段。
在实际工作中，在T4阶段，第二上拉节点PU2的电压是逐步从高到低，第三薄膜晶体管T3是逐步从导通到截止，在此过程中，不能保证信号输出端Output无噪声输出(信号输出端Output的噪声一般会随着第二上拉节点PU2的噪声产生而产生)。因此，在本发明实施例提供的上述移位寄存器中，为了降低第二上拉节点PU2和信号输出端Output的噪声，如图5所示，一般还包括：下拉模块，其连接在显示控制信号端CT1、第一上拉节点PU1、第二上拉节点PU2、信号输出端Output以及低电压信号端VSS之间，用于在移位寄存器的非工作时间内维持第一上拉节点PU1、第二上拉节点PU2和信号输出端Output为低电平，以降低噪声的输出。
在具体实施时，本发明实施例提供的上述移位寄存器中的下拉模块，如图6所示，可以具体包括：
第六薄膜晶体管T6，其漏极与显示控制信号端CT1相连、源极与下拉节点PD相连；
第七薄膜晶体管T7，其漏极与下拉节点PD相连、栅极与第二上拉节点PU2相连、源极与低电压信号端VSS相连；
第八薄膜晶体管T8，其栅极和漏极分别与显示控制信号端CT1相连、源极与第六薄膜晶体管T6的栅极相连；
第九薄膜晶体管T9，其漏极与第八薄膜晶体管T8的源极相连、栅极与第二上拉节点PU2相连、源极与低电压信号端VSS相连；
第十薄膜晶体管T10，其漏极与第一上拉节点PU1相连、栅极与下拉节 点PD相连、源极与低电压信号端VSS相连；
第十一薄膜晶体管T11，其漏极与信号输出端Output相连、栅极与下拉节点PD相连、源极与低电压信号端VSS相连。
下面结合图6所示的移位寄存器以及图4c所示的输入输出时序图，以正向扫描为例对本发明实施例移位寄存器中的下拉模块的工作过程作以描述。
在T1和T2阶段，由于CT1＝10，因此第八薄膜晶体管T8导通使第六薄膜晶体管T6导通，将下拉节点PD的电压拉高，使第十薄膜晶体管T10和第十一薄膜晶体管T11处于导通状态，从而将第一上拉节点PU1和第二上拉节点PU2以及信号输出端Output的噪声导出至低电压信号端VSS。
T3阶段，由于电容C1的自举作用将第二上拉节点PU2进一步拉高，使第七薄膜晶体管T7和第九薄膜晶体管T9处于导通状态，将下拉节点PD的电压拉低，使第十薄膜晶体管T10和第十一薄膜晶体管T11处于截止状态，保证信号输出端Output的正常输出。
T4阶段，由于第二薄膜晶体T2导通后将第二上拉节点PU2拉低，使第七薄膜晶体管T7和第九薄膜晶体管T9处于截止状态，CT1为高，T8,T6导通，将下拉节点PD的电压逐渐拉高，使第十薄膜晶体管T10和第十一薄膜晶体管T11处于导通状态，从而将第一上拉节点PU1和第二上拉节点PU2以及信号输出端Output的噪声导出至第二参考信号端Ref2或低电压信号端VSS。
以上仅是举例说明移位寄存器中下拉模块的具体结构，在具体实施时，下拉模块的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
基于同一发明构思，本发明实施例还提供了一种栅极集成驱动电路，如图7所示，包括串联的多个移位寄存器，除第一个移位寄存器和最后一个移位寄存器之外，其余每个移位寄存器的信号输出端Output均向与其相邻的下一个移位寄存器的信号输入端输入触发信号，并向与其相邻的上一个移位寄存器的复位信号端输入复位信号；第一个移位寄存器的信号输出端Output向第二个移位寄存器的信号输入端输入触发信号；最后一个移位寄存器的信号输出端Output向自身以及上一个移位寄存器的复位信号端输入复位信号。
为了方便说明，图7中仅示出了五个移位寄存器，分别为第N-2级移位寄存器、第N-1级移位寄存器、第N级移位寄存器、第N+1级移位寄存器、 第N+2级移位寄存器。其中，第N级移位寄存器的信号输出端Output(n)不仅向与其连接的栅极信号线输出栅开启信号，还向第N-1级移位寄存器输出复位信号，同时还向第N+1级移位寄存器输出触发信号。
具体地，上述栅极集成驱动电路中的每个移位寄存器的具体结构与本发明上述移位寄存器在功能和结构上均相同，重复之处不再赘述。
基于同一发明构思，本发明实施例还提供了一种显示屏，包括上述的栅极集成驱动电路，其具体实施可参见上述栅极集成驱动电路的描述，相同之处不再赘述。
本发明实施例提供的上述移位寄存器、栅极集成驱动电路及显示屏，将第一薄膜晶体管的源极和第二薄膜晶体管的漏极的连接点设置为第一上拉节点，将电容和第三薄膜晶体管的栅极的连接点设置为第二上拉节点，在第一上拉节点和第二上拉节点之间增加一个防漏电模块，该模块在显示控制信号端的控制下，在一帧的显示时间段导通第一上拉节点和第二上拉节点，使移位寄存器实现正常的栅开启信号输出；在一帧的触控时间段断开第一上拉节点和第二上拉节点的连接，相当于在电容的放电路径中串联一个阻值较大的电阻，能够大大减缓电容的放电，有效降低电容的漏电速度，避免了将触摸屏的一帧时间分为交替进行的多个显示时间段和触控时间段以提高触控报点率时可能出现的无法正常显示的问题。
显然，本领域的技术人员可以对本发明的实施例进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
本申请要求于2014年5月30日递交的中国专利申请第201410240531.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (9)

  1. 一种移位寄存器，包括：
    第一薄膜晶体管，其栅极与信号输入端相连、漏极与第一参考信号端相连，源极与第一上拉节点相连；
    第二薄膜晶体管，其栅极与复位信号端相连、漏极与所述第一上拉节点相连、源极与第二参考信号端相连；
    第三薄膜晶体管，其栅极与第二上拉节点相连、漏极与时钟信号端相连、源极与信号输出端相连；
    第四薄膜晶体管，其栅极与触控控制信号端相连、漏极与所述信号输出端相连、源极与低电压信号端相连，所述触控控制信号端用于在触控时间段导通所述第四薄膜晶体管，在显示时间段断开所述第四薄膜晶体管；
    电容，其连接在所述第二上拉节点和所述信号输出端之间；
    防漏电模块，其连接在显示控制信号端、所述第一上拉节点和所述第二上拉节点之间，用于在所述显示控制信号端的控制下，在显示时间段导通所述第一上拉节点和所述第二上拉节点，在触控时间段断开所述第一上拉节点和所述第二上拉节点的连接。
  2. 如权利要求1所述的移位寄存器，其中，所述防漏电模块，包括：第五薄膜晶体管，其栅极与所述显示控制信号端相连、漏极与第一上拉节点相连、源极与第二上拉节点相连。
  3. 如权利要求1或2所述的移位寄存器，其中，所述移位寄存器中包含的所有薄膜晶体管均为N型薄膜晶体管；
    在显示时间段，所述显示控制信号端提供高电平信号，所述触控控制信号端提供低电平信号；
    在触控时间段，所述显示控制信号端提供低电平信号，所述触控控制信号端提供高电平信号。
  4. 如权利要求3所述的移位寄存器，其中，启动正向扫描时，在显示时间段，所述第一参考信号端提供高电平信号，所述第二参考信号端提供低电平信号；
    在触控时间段，所述第一参考信号端和所述第二参考信号端同时提供高 电平信号。
  5. 如权利要求3所述的移位寄存器，其中，启动反向扫描时，在显示时间段，所述第一参考信号端提供低电平信号，所述第二参考信号端提供高电平信号；
    在触控时间段，所述第一参考信号端和所述第二参考信号端同时提供高电平信号。
  6. 如权利要求1-5任一项所述的移位寄存器，还包括：下拉模块，其连接在所述显示控制信号端、第一上拉节点、第二上拉节点、信号输出端以及低电压信号端之间，用于在所述移位寄存器的非工作时间内维持所述第一上拉节点、第二上拉节点和信号输出端为低电平。
  7. 如权利要求6所述的移位寄存器，其中，所述下拉模块，包括：
    第六薄膜晶体管，其漏极与所述显示控制信号端相连、源极与下拉节点相连；
    第七薄膜晶体管，其漏极与所述下拉节点相连、栅极与所述第二上拉节点相连、源极与所述低电压信号端相连；
    第八薄膜晶体管，其栅极和漏极分别与所述显示控制信号端相连、源极与第六薄膜晶体管的栅极相连；
    第九薄膜晶体管，其漏极与第八薄膜晶体管的源极相连、栅极与所述第二上拉节点相连、源极与所述低电压信号端相连；
    第十薄膜晶体管，其漏极与所述第一上拉节点相连、栅极与所述下拉节点相连、源极与所述低电压信号端相连；
    第十一薄膜晶体管，其漏极与所述信号输出端相连、栅极与所述下拉节点相连、源极与所述低电压信号端相连。
  8. 一种栅极集成驱动电路，包括串联的多个如权利要求1-7任一项所述的移位寄存器；
    除第一个移位寄存器和最后一个移位寄存器之外，其余每个移位寄存器均向与其相邻的下一个移位寄存器的信号输入端输入触发信号，并向与其相邻的上一个移位寄存器的复位信号端输入复位信号；第一个移位寄存器向第二个移位寄存器的信号输入端输入触发信号；最后一个移位寄存器向自身以及上一个移位寄存器的复位信号端输入复位信号。
  9. 一种显示屏，包括如权利要求8所述的栅极集成驱动电路。
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