WO2019153864A1 - 移位寄存器单元及其控制方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器单元及其控制方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2019153864A1
WO2019153864A1 PCT/CN2018/119708 CN2018119708W WO2019153864A1 WO 2019153864 A1 WO2019153864 A1 WO 2019153864A1 CN 2018119708 W CN2018119708 W CN 2018119708W WO 2019153864 A1 WO2019153864 A1 WO 2019153864A1
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WIPO (PCT)
Prior art keywords
pull
transistor
signal
control
circuit
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PCT/CN2018/119708
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English (en)
French (fr)
Inventor
章祯
祝政委
胡文成
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US16/470,144 priority Critical patent/US10872551B2/en
Publication of WO2019153864A1 publication Critical patent/WO2019153864A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a control method thereof, a gate driving circuit, a display substrate, and a display device.
  • the existing display panel (Panel) products increasingly adopt the Gate Driver On Array (GOA) technology on the array substrate, that is, directly to the thin film transistor (Thin Film). Transistor, TFT) gate drive circuit is fabricated on the array substrate, thereby eliminating the space occupation of the Bonding and Fan-Out regions, and achieving cost reduction and display panel in materials and preparation processes. Narrow framed.
  • GOA Gate Driver On Array
  • TFT Transistor
  • GOA chip on glass
  • COF chip on film
  • a shift register unit including: an input circuit, a reset circuit, an output circuit, a first pull-down control circuit, a second pull-down control circuit, a first pull-down circuit, and a second pull-down circuit;
  • the input circuit is coupled to the input terminal, the first voltage terminal, and the pull-up node, for outputting a pre-output signal to the pull-up according to an input signal from the input terminal and a first voltage signal from the first voltage terminal a node;
  • the output circuit is coupled to the output terminal, the clock signal terminal, and the pull-up node, configured to control a potential of the output terminal according to a clock signal from the clock signal end and a potential of the pull-up node;
  • a reset circuit connected to the reset signal terminal, the second voltage terminal, and the pull-up node, for outputting a pre-reset signal to the reset signal according to the reset signal from the reset signal terminal and the second voltage signal from the second voltage terminal a pull-up node;
  • the first control signal and the second control signal are inverted, and the periods of the first control signal and the second control signal are the same.
  • the first pull-down circuit includes a first transistor and a second transistor, a control electrode of the first transistor is connected to the first pull-down control circuit, and a first pole of the first transistor is connected The pull-up node, the second pole of the first transistor is connected to the second control signal end, and the control pole of the second transistor is connected to the first pull-down control circuit, the second transistor One pole is connected to the output end, and the second pole of the second transistor is connected to the second control signal end.
  • the second pull-down circuit includes a third transistor and a fourth transistor, a control electrode of the third transistor is connected to the second pull-down control circuit, and a first pole of the third transistor is connected to the a pull-up node, a second pole of the third transistor is connected to the first control signal end, and a control pole of the fourth transistor is connected to the second pull-down control circuit, and a first pole of the fourth transistor is connected The output end, the second pole of the fourth transistor is connected to the first control signal end.
  • the first pull-down control circuit includes a fifth transistor and a sixth transistor, and a control electrode and a first pole of the fifth transistor are connected to the first control signal end, and the fifth transistor is a second pole is connected to the first pull-down circuit, and a control pole of the sixth transistor is connected to the pull-up node, and a first pole of the sixth transistor is connected to the first pull-down circuit, the sixth A second pole of the transistor is coupled to the pull down signal terminal.
  • the second pull-down control circuit includes a seventh transistor and an eighth transistor, a control electrode of the seventh transistor and a first pole connected to the second control signal terminal, and a seventh transistor a diode is connected to the second pull-down circuit, and a control electrode of the eighth transistor is connected to the pull-up node, and a first pole of the eighth transistor is connected to the second pull-down circuit, and the eighth transistor is The two poles are connected to the pull-down signal terminal.
  • the input circuit includes a ninth transistor, a control electrode of the ninth transistor is connected to the input terminal, and a first pole of the ninth transistor is connected to the first voltage terminal, the ninth A second pole of the transistor is coupled to the pull up node.
  • the output circuit includes a tenth transistor and a capacitor, a control electrode of the tenth transistor is connected to the pull-up node, and a first pole of the tenth transistor is connected to the clock signal end. a second pole of the tenth transistor is connected to the output terminal, and a first end of the capacitor is connected to a control electrode of the tenth transistor, and a second end of the capacitor is opposite to a second pole of the tenth transistor connection.
  • the reset circuit includes an eleventh transistor, a control electrode of the eleventh transistor is connected to the reset signal terminal, and a first pole of the eleventh transistor is connected to the second voltage terminal. The second pole of the eleventh transistor is connected to the pull-up node.
  • the first pull-down circuit includes a first transistor and a second transistor
  • the second pull-down circuit includes a third transistor and a fourth transistor
  • the first pull-down control circuit includes a fifth transistor and a sixth transistor
  • the second pull-down control circuit includes a seventh transistor and an eighth transistor
  • the input circuit includes a ninth transistor
  • the output circuit includes a tenth transistor and a capacitor
  • the reset circuit includes an eleventh transistor a control electrode of the first transistor and a control electrode of the second transistor are connected to a second pole of the fifth transistor and a first pole of the sixth transistor, and a second pole of the first transistor a second pole of the second transistor is connected to the second control signal end, a first pole of the first transistor is connected to the pull-up node, and a first pole of the second transistor is connected to the output end
  • a control electrode of the third transistor and a control electrode of the fourth transistor are connected to a second electrode of the seventh transistor and a first electrode of the eighth transistor, and a second electrode of the third transistor
  • a control method for driving any one of the above shift register units including: a charging phase, an input terminal outputs an input signal, a first voltage terminal outputs a first voltage signal, and an input circuit is The input signal and the first voltage signal output a pre-output signal to the pull-up node; in the output stage, the clock signal end outputs a clock signal, and the output circuit controls the output end according to the clock signal and the potential of the pull-up node a reset phase, the reset signal terminal outputs a reset signal, the second voltage terminal outputs a second voltage signal, and the reset circuit outputs a pre-reset signal to the pull-up node according to the reset signal and the second voltage signal; a first control signal terminal outputs a first control signal, a pull-down signal terminal outputs a pull-down signal, and a second control signal terminal outputs a second control signal, the first pull-down control circuit is configured according to the first control signal and the pull-down signal The potential of the pull-up
  • the first pull-down circuit is turned on under the control of the third control signal, and controls a potential of the pull-up node and the output terminal according to the second control signal; or, the second pull-down circuit is
  • the fourth control signal is turned on under control, and the potentials of the pull-up node and the output terminal are controlled according to the first control signal.
  • the first control signal has a first level
  • the second control signal has a second level
  • the first control signal has a second level
  • the second control signal has a first level, wherein the first level and the second level are periodically alternated to control the third control signal and the fourth control signal to alternate periodically.
  • the polarity of the first control signal and the second control signal alternates by an integer multiple of a driving period of one frame.
  • a gate driving circuit comprising at least three shift register units as described above, the shift register units being cascaded with each other; wherein an input of an Nth stage shift register unit The terminal is connected to the output end of the N-1th shift register unit, and the reset signal end of the Nth shift register unit is connected to the output end of the N+1th shift register unit; or, the Nth shift register unit The input end is connected to the output end of the N+1th stage shift register unit, and the reset signal end of the Nth stage shift register unit is connected to the output end of the N-1th stage shift register unit.
  • a display substrate including a gate drive circuit as described above.
  • a display device comprising the display substrate as described above.
  • a shift register unit and a control method thereof, a gate driving circuit, a display substrate, and a display device are provided with a first pull-down circuit and a second pull-down circuit in a shift register unit, through the first control signal And the control of the second control signal, the alternate operation of the first pull-down circuit and the second pull-down circuit can be implemented, so that the drift of the threshold voltage of the TFT in the first pull-down circuit and the second pull-down circuit can be corrected, thereby improving The leakage characteristics of the TFT.
  • FIG. 1 is a schematic structural diagram of an embodiment of a shift register unit provided by the present disclosure
  • FIG. 2 is a schematic structural diagram of another embodiment of a shift register unit provided by the present disclosure.
  • FIG. 3 is a schematic structural diagram of still another embodiment of a shift register unit provided by the present disclosure.
  • FIG. 4 is a schematic flow chart of an embodiment of a method for controlling a shift register unit according to the present disclosure
  • FIG. 5 is a schematic flowchart diagram of another embodiment of a method for controlling a shift register unit according to the present disclosure
  • FIG. 6 is a timing diagram of control of one embodiment of a shift register unit provided by the present disclosure.
  • FIG. 7 is a schematic structural diagram of an embodiment of a gate driving circuit provided by the present disclosure.
  • first and second used in the various embodiments of the present disclosure are to distinguish two entities having the same name but not the same or non-identical parameters, thus “first” and The “second” is merely for convenience of description and should not be construed as limiting the embodiments of the present disclosure.
  • the pull-down TFT thin film transistor
  • its gate and source are The voltage difference is VGS>0V.
  • a long forward bias can cause a positive drift of the threshold voltage Vth.
  • the Vth drift caused by long-term forward bias is small, but for oxide TFTs (such as a-IGZO TFT), back channel is easy due to process influence.
  • FIG. 1 is a schematic structural diagram of an embodiment of a shift register unit provided by the present disclosure.
  • the shift register unit includes an input circuit 101, an output circuit 102, a reset circuit 103, a first pull-down control circuit 104, a second pull-down control circuit 105, a first pull-down circuit 106, and a second pull-down. Circuit 107.
  • the input circuit 101 is connected to the input terminal G(N-1), the first voltage terminal VDD and the pull-up node PU for inputting an input signal from the input terminal G(N-1) and from the first
  • the first voltage signal of the voltage terminal VDD outputs a pre-output signal to the pull-up node PU to control the potential of the pull-up node PU.
  • the output circuit 102 is connected to the clock signal terminal CLK and the pull-up node PU for controlling the output terminal G(N) according to the clock signal from the clock signal terminal CLK and the potential of the pull-up node PU. Potential.
  • the reset circuit 103 is connected to the reset signal terminal G(N+1), the second voltage terminal VSS, and the pull-up node PU for receiving and resetting signals according to the reset signal terminal G(N+1)
  • the second voltage signal of the second voltage terminal VSS outputs a pre-reset signal to the pull-up node PU to control the potential of the pull-up node PU.
  • the first pull-down control circuit 104 is connected to the first control signal terminal GCL, the pull-down signal terminal VGL, and the pull-up node PU for receiving the first control signal and the source from the first control signal terminal GCL.
  • the pull-down signal of the pull-down signal terminal VGL and the potential of the pull-up node output a third control signal to the first pull-down circuit 106 to control the first pull-down circuit 106 to be turned on or off.
  • the second pull-down control circuit 105 is connected to the second control signal terminal GCH, the pull-down signal terminal VGL, and the pull-up node PU for using the second control signal from the second control signal terminal GCH and from the The pull-down signal of the pull-down signal terminal VGL and the potential of the pull-up node output a fourth control signal to the second pull-down circuit 107 to control the second pull-down circuit 107 to be turned on or off.
  • the first pull-down circuit 106 is connected to the second control signal terminal GCH, the first pull-down control circuit 104, the pull-up node PU, and the output terminal G(N), in response to the The three control signals cause the first pull-down circuit 106 to be turned on, and the potentials of the pull-up node PU and the output terminal G(N) are controlled according to the second control signal.
  • the second pull-down circuit 107 is connected to the first control signal terminal GCL, the second pull-down control circuit 105, the pull-up node PU, and the output terminal G(N) in response to the fourth control
  • the signal causes the second pull-down circuit 107 to be turned on, and the potential of the pull-up node PU and the output terminal G(N) is controlled according to the first control signal.
  • the first pull-down circuit 106 and the second pull-down circuit 107 are alternately turned on.
  • the shift register unit provided by the embodiment of the present disclosure sets the first pull-down circuit and the second pull-down circuit, and the first pull-down circuit can realize the first pull-down by the control of the first control signal and the second control signal.
  • the alternate operation of the circuit and the second pull-down circuit enables the drift of the threshold voltage of the TFTs in the first pull-down circuit and the second pull-down circuit to be corrected, thereby improving the TFT leakage characteristics.
  • the first control signal accessed by the first control signal terminal GCL and the second control signal accessed by the second control signal terminal GCH are inverted, and the periods of the first control signal and the second control signal are the same.
  • the alternating period of the first control signal and the second control signal is an integer multiple of a driving period of one frame, and may be, for example, 2 s.
  • first control signal and the second control signal may also be the same in the case of corresponding to different types of transistors.
  • FIG. 2 is a schematic structural diagram of another embodiment of a shift register unit provided by the present disclosure.
  • the shift register unit includes an input circuit 101, an output circuit 102, a reset circuit 103, a first pull-down control circuit 104, a second pull-down control circuit 105, a first pull-down circuit 106, and a second pull-down. Circuit 107.
  • the input circuit 101 is connected to the input terminal G(N-1), the first voltage terminal VDD and the pull-up node PU for inputting an input signal from the input terminal G(N-1) and from the first
  • the first voltage signal of the voltage terminal VDD outputs a pre-output signal to the pull-up node PU to control the potential of the pull-up node PU.
  • the output circuit 102 is connected to the clock signal terminal CLK and the pull-up node PU for controlling the output terminal G(N) according to the clock signal from the clock signal terminal CLK and the potential of the pull-up node PU. Potential.
  • the reset circuit 103 is connected to the reset signal terminal G(N+1), the second voltage terminal VSS, and the pull-up node PU for receiving and resetting signals according to the reset signal terminal G(N+1)
  • the second voltage signal of the second voltage terminal VSS outputs a pre-reset signal to the pull-up node PU to control the potential of the pull-up node PU.
  • the first pull-down control circuit 104 is connected to the first control signal terminal GCL, the pull-down signal terminal VGL, and the pull-up node PU for receiving the first control signal and the source from the first control signal terminal GCL.
  • the pull-down signal of the pull-down signal terminal VGL and the potential of the pull-up node PU output a third control signal to the first pull-down circuit 106 to control the first pull-down circuit 106 to be turned on or off.
  • the second pull-down control circuit 105 is connected to the second control signal terminal GCH, the pull-down signal terminal VGL, and the pull-up node PU for using the second control signal from the second control signal terminal GCH and from the
  • the pull-down signal of the pull-down signal terminal VGL and the potential of the pull-up node PU output a fourth control signal to the second pull-down circuit 107 to control the second pull-down circuit 107 to be turned on or off.
  • the first pull-down circuit 106 is connected to the second control signal terminal GCH, the first pull-down control circuit 104, the pull-up node PU, and the output terminal G(N), in response to the The three control signals cause the first pull-down circuit 106 to be turned on, and the potentials of the pull-up node PU and the output terminal G(N) are controlled according to the second control signal.
  • the first pull-down circuit 106 may further include a first transistor T1 and a second transistor T2.
  • the control electrode of the first transistor T1 is connected to the first pull-down control circuit 104, the first pole of the first transistor T1 is connected to the pull-up node PU, and the second pole of the first transistor T1 is connected
  • the second control signal terminal GCH is described.
  • the control electrode of the second transistor T2 is connected to the first pull-down control circuit 104, the first pole of the second transistor T2 is connected to the output terminal G(N), and the second pole of the second transistor T2
  • the second control signal terminal GCH is connected.
  • the second pull-down circuit 107 is connected to the first control signal terminal GCL, the second pull-down control circuit 105, the pull-up node PU, and the output terminal G(N) in response to the fourth control
  • the signal causes the second pull-down circuit 107 to be turned on, and the potential of the pull-up node PU and the output terminal G(N) is controlled according to the first control signal.
  • the second pull-down circuit 107 may further include a third transistor T3 and a fourth transistor T4.
  • a control electrode of the third transistor T3 is connected to the second pull-down control circuit 105, a first pole of the third transistor T3 is connected to the pull-up node PU, and a second pole of the third transistor T3 is connected to the The first control signal terminal GCL.
  • the control electrode of the fourth transistor T4 is connected to the second pull-down control circuit 105, the first pole of the fourth transistor T4 is connected to the output terminal G(N), and the second pole of the fourth transistor T4 is connected.
  • the first control signal terminal GCL is connected to the second pull-down control circuit 105.
  • the first pull-down circuit 106 and the second pull-down circuit 107 are alternately turned on under the control of the third control signal and the fourth control signal.
  • the first control signal accessed by the first control signal terminal GCL and the second control signal accessed by the second control signal terminal GCH are inverted, and the first control signal and the second control signal have the same period And controlling the third control signal and the fourth control signal to alternate periodically.
  • the alternating period of the first control signal and the second control signal is an integer multiple of a driving period of one frame picture.
  • the polarity of the gate and source voltage difference VGS is opposite when the two sets of pull-down TFTs operate in the shift register unit, and the time-division driving scheme of the two sets of pull-down TFTs is matched ( That is, the first control signal and the second control signal are periodically alternated, and the Vth drift of the pull-down TFT can be corrected to improve the leakage characteristics of the pull-down TFT.
  • first control signal and the second control signal may also be the same in the case of corresponding to different types of transistors.
  • FIG. 3 is a schematic structural diagram of still another embodiment of a shift register unit provided by the present disclosure.
  • the shift register unit includes an input circuit 101, an output circuit 102, a reset circuit 103, a first pull-down control circuit 104, a second pull-down control circuit 105, a first pull-down circuit 106, and a second Pull down circuit 107.
  • the input circuit 101 is connected to the input terminal G(N-1), the first voltage terminal VDD and the pull-up node PU for inputting an input signal from the input terminal G(N-1) and from the first
  • the first voltage signal of the voltage terminal VDD outputs a pre-output signal to the pull-up node PU to control the potential of the pull-up node PU.
  • the input circuit 101 further includes a ninth transistor T9.
  • a control electrode of the ninth transistor T9 is connected to the input terminal G(N-1), a first pole of the ninth transistor T9 is connected to the first voltage terminal VDD, and a second pole of the ninth transistor T9
  • the pull-up node PU is connected.
  • the output circuit 102 is connected to the clock signal terminal CLK and the pull-up node PU for controlling the output terminal G(N) according to the clock signal from the clock signal terminal CLK and the potential of the pull-up node PU. Potential.
  • the output circuit 102 further includes a tenth transistor T10 and a capacitor C.
  • a control electrode of the tenth transistor T10 is connected to the pull-up node PU, a first pole of the tenth transistor T10 is connected to the clock signal terminal CLK, and a second pole of the tenth transistor T10 outputs the output.
  • the first end of the capacitor C is connected to the control electrode of the tenth transistor T10, and the second end of the capacitor C is connected to the second pole of the tenth transistor T10.
  • the reset circuit 103 is connected to the reset signal terminal G(N+1), the second voltage terminal VSS, and the pull-up node PU for receiving and resetting signals according to the reset signal terminal G(N+1)
  • the second voltage signal of the second voltage terminal VSS outputs a pre-reset signal to the pull-up node PU to control the potential of the pull-up node PU.
  • the reset circuit 103 further includes an eleventh transistor T11. a control electrode of the eleventh transistor T11 is connected to the reset signal terminal G(N+1), a first electrode of the eleventh transistor T11 is connected to the second voltage terminal VSS, and the eleventh transistor T11 The second pole is connected to the pull-up node PU.
  • the first pull-down control circuit 104 is connected to the first control signal terminal GCL, the pull-down signal terminal VGL, and the pull-up node PU for receiving the first control signal and the source from the first control signal terminal GCL.
  • the pull-down signal of the pull-down signal terminal VGL and the potential of the pull-up node PU output a third control signal to the first pull-down circuit 106 to control the first pull-down circuit 106 to be turned on or off.
  • the first pull-down control circuit 104 further includes a fifth transistor T5 and a sixth transistor T6.
  • the control electrode and the first pole of the fifth transistor T5 are both connected to the first control signal terminal GCL, and the second electrode of the fifth transistor T5 is connected to the first pull-down circuit 106.
  • a control electrode of the sixth transistor T6 is connected to the pull-up node PU, a first pole of the sixth transistor T6 is connected to the first pull-down circuit 106, and a second pole of the sixth transistor T6 is connected to the Pull down the signal terminal VGL.
  • the second pull-down control circuit 105 is connected to the second control signal terminal GCH, the pull-down signal terminal VGL, and the pull-up node PU for using the second control signal from the second control signal terminal GCH and from the
  • the pull-down signal of the pull-down signal terminal VGL and the potential of the pull-up node PU output a fourth control signal to the second pull-down circuit 107 to control the second pull-down circuit 107 to be turned on or off.
  • the second pull-down control circuit 105 further includes a seventh transistor T7 and an eighth transistor T8.
  • the control electrode and the first pole of the seventh transistor T7 are both connected to the second control signal terminal GCH, and the second electrode of the seventh transistor T7 is connected to the second pull-down circuit 107.
  • the control electrode of the eighth transistor T8 is connected to the pull-up node PU, the first pole of the eighth transistor T8 is connected to the second pull-down circuit 107, and the second pole of the eighth transistor T8 is connected to the pull-down Signal terminal VGL.
  • the first pull-down circuit 106 is connected to the second control signal terminal GCH, the first pull-down control circuit 104, the pull-up node PU, and the output terminal G(N), in response to the The three control signals cause the first pull-down circuit 106 to be turned on, and the potentials of the pull-up node PU and the output terminal G(N) are controlled according to the second control signal.
  • the first pull-down circuit 106 further includes a first transistor T1 and a second transistor T2.
  • the control electrode of the first transistor T1 is connected to the first pull-down control circuit 104, the first pole of the first transistor T1 is connected to the pull-up node PU, and the second pole of the first transistor T1 is connected
  • the second control signal terminal GCH is described.
  • the control electrode of the second transistor T2 is connected to the first pull-down control circuit 104, the first pole of the second transistor T2 is connected to the output terminal G(N), and the second pole of the second transistor T2
  • the second control signal terminal GCH is connected.
  • the second pull-down circuit 107 is connected to the first control signal terminal GCL, the second pull-down control circuit 105, the pull-up node PU, and the output terminal G(N) in response to the fourth control
  • the signal causes the second pull-down circuit 107 to be turned on, and the potential of the pull-up node PU and the output terminal G(N) is controlled according to the first control signal.
  • the second pull-down circuit 107 further includes a third transistor T3 and a fourth transistor T4.
  • a control electrode of the third transistor T3 is connected to the second pull-down control circuit 105, a first pole of the third transistor T3 is connected to the pull-up node PU, and a second pole of the third transistor T3 is connected to the The first control signal terminal GCL.
  • the control electrode of the fourth transistor T4 is connected to the second pull-down control circuit 105, the first pole of the fourth transistor T4 is connected to the output terminal G(N), and the second pole of the fourth transistor T4 is connected.
  • the first control signal terminal GCL is connected to the second pull-down control circuit 105.
  • the first pull-down circuit 106 and the second pull-down circuit 107 are alternately turned on and off under the control of the third control signal and the fourth control signal.
  • the first transistor T1 and the second transistor T2 form a set of pull-down TFTs
  • the third transistor T3 and the fourth transistor T4 form another set of pull-down TFTs.
  • the turning on and off of the fifth transistor T5 and the sixth transistor T6 can adjust the potential of the Q1 point
  • the turning on and off of the seventh transistor T7 and the eighth transistor T8 can adjust the Q2 point. Potential.
  • the Q1 point potential controls the on and off of the first transistor T1 and the second transistor T2
  • the Q2 point potential controls the turning on and off of the third transistor T3 and the fourth transistor T4.
  • the input circuit 101 and the reset circuit 103 are of a symmetrical structure such that they can be used interchangeably in the case of a drive signal exchange, that is, the input circuit 101 is used as a reset circuit, and the reset circuit 103 is used as an input circuit. To meet more drive requirements.
  • a control method of a shift register unit is proposed.
  • 4 is a schematic flow chart of an embodiment of a method for controlling a shift register unit provided by the present disclosure.
  • control method of the shift register unit is used to drive any of the shift register units as described above, including:
  • Step 201 In the charging phase, the input terminal G(N-1) outputs an input signal, the first voltage terminal VDD outputs a first voltage signal, and the input circuit 101 outputs a pre-output signal according to the input signal and the first voltage signal. Pulling up the node PU to control the potential of the pull-up node PU;
  • Step 202 In the output stage, the clock signal terminal CLK outputs a clock signal, and the output circuit 102 controls the potential of the output terminal G(N) according to the clock signal and the potential of the pull-up node PU;
  • Step 203 In the reset phase, the reset signal terminal G(N+1) outputs a reset signal, the second voltage terminal VSS outputs a second voltage signal, and the reset circuit 103 outputs a pre-reset signal according to the reset signal and the second voltage signal. Go to the pull-up node PU to control the potential of the pull-up node PU;
  • Step 204 In the noise reduction phase, the first control signal terminal GCL outputs a first control signal, the pull-down signal terminal VGL outputs a pull-down signal, and the second control signal terminal GCH outputs a second control signal, and the first pull-down control circuit 104 is configured according to the first a control signal and the pull-down signal and a potential of the pull-up node PU, outputting a third control signal to the first pull-down circuit 106, the second pull-down control circuit 105 according to the second control signal and the pull-down signal The potential of the pull-up node PU outputs a fourth control signal to the second pull-down circuit 107,
  • the first pull-down circuit 106 and the second pull-down circuit 107 are alternately turned on and off under the control of the third control signal and the fourth control signal, wherein
  • the first pull-down circuit 106 is turned on under the control of the third control signal, and controls the potentials of the pull-up node PU and the output terminal G(N) according to the second control signal;
  • the second pull-down circuit 107 is turned on under the control of the fourth control signal, and controls the potential G(N) of the pull-up node PU and the output terminal according to the first control signal.
  • the first voltage signal and the second control signal are first level signals, and the second voltage signal and the first control signal are second level signals; or the first voltage signal and The first control signal is a first level signal, and the second voltage signal and the second control signal are second level signals.
  • the first level signal and the second level signal are different. It should be noted that the first level signal and the second level signal may also be the same depending on different transistor types.
  • control method of the shift register unit sets the first pull-down circuit and the second pull-down circuit in the shift register unit, and passes the first control signal and the second control signal.
  • the control can realize the alternate operation of the first pull-down circuit and the second pull-down circuit, so that the drift of the threshold voltage of the TFT in the first pull-down circuit and the second pull-down circuit can be corrected, thereby improving the TFT leakage characteristics.
  • the first control signal has a first level
  • the second control signal has a second level
  • the first control signal has a second level
  • the second control signal has a first level
  • the first level and the second level are periodically alternated to control periodic alternation of the third control signal and the fourth control signal.
  • the alternating period of the first level and the second level may be an integer multiple of a driving period of one frame of picture.
  • FIG. 5 is a schematic flow chart of another embodiment of a method for controlling a shift register unit according to the present disclosure.
  • the control method of the shift register unit is used to drive any of the shift register units as described above, including: a timing chart referring to the left half of FIG. 6, wherein the first voltage
  • the first voltage signal accessed by the terminal VDD and the second control signal of the second control signal terminal GCH are the first level signal
  • the second voltage signal of the second voltage terminal VSS is connected to the first control signal terminal.
  • the second control signal accessed by the GCL is a second level signal, and the first level signal and the second level signal are different;
  • Step 301 In the input stage, the input signal (which may be the output signal of the shift register unit of the previous stage) accessed by the input terminal G(N-1) is a first level signal, and the reset signal terminal G ( The N+1) access reset signal (which may be the output signal of the next stage shift register unit) is a second level signal, and the input circuit 101 outputs a pre-output signal at the pull-up node PU, the output circuit 102
  • the output signal of the output terminal G(N) is a second level signal; the first pull-down control circuit 104 and the second pull-down control circuit 105 both output a second level signal, the first pull-down circuit 106 and the second pull-down circuit 107 are both turned off; the input signal causes the ninth transistor T9 to be turned on, and the input first level signal charges the capacitor C, so that the potential of the pull-up node PU is pulled high The pull-up node PU is pulled high so that the sixth transistor T6 and the eighth transistor T8 are turned on, the Q1 point and
  • Step 302 In the output stage, the input signal input by the input terminal G(N-1) and the reset signal accessed by the reset signal terminal G(N+1) are both second level signals, and the clock signal end is
  • the clock signal of the CLK access is a first level signal
  • the potential of the pull-up node PU is further raised by the bootstrap effect of the capacitor C, so that the output circuit 102 outputs a first level signal
  • the pull control circuit 104 and the second pull-down control circuit 105 both output a second level signal, the first pull-down circuit 106 and the second pull-down circuit 107 are both turned off; the input signal is low level,
  • the ninth transistor T9 is turned off, the pull-up node PU remains at a high potential, the tenth transistor T10 remains in an on state; the clock signal is at a high potential, and the pull-up node PU is affected by the bootstrapping effect of the capacitor C,
  • the PU voltage of the pull-up node continues to rise, and the tenth transistor
  • Step 303 In the reset phase and the noise reduction phase, the input signal input by the input terminal G(N-1) is a second level signal, and the reset signal of the reset signal terminal G(N+1) is a first level signal, the second voltage signal of the pull-up node PU being accessed by the second voltage terminal VSS is pulled low; the first pull-down control circuit 104 outputs a second level signal, the second The pull-down control circuit 105 outputs a first level signal, the first pull-down circuit 106 is turned off, the second pull-down circuit 107 is turned on, and the potential of the pull-up node PU is continuously pulled down to the pull-down signal end
  • the pull-down signal of the VGL is input, so that the output circuit 102 outputs a second level signal; the reset signal is a first level signal, and the first level signal turns on the eleventh transistor T11, the pull-up node PU The potential is pulled low, the tenth transistor T10 is turned off; the pull-up node PU is at a low
  • the pull-up node PU is continuously pulled down by the first control signal through the third transistor T3 to The low potential of the pull-down signal, the output signal of the output terminal G(N) is continuously pulled down by the fourth transistor T4 to the low potential of the pull-down signal.
  • Step 304 In the continuous phase, the input signal input by the input terminal G(N-1) and the reset signal accessed by the reset signal terminal G(N+1) are both second level signals, and the pull-up node The potential of the PU is maintained as the pull-down signal, so that the output circuit 102 continuously outputs the second level signal; the potentials of the pull-up nodes PU, Q1, and Q2 are the same as the previous period, and the output terminal G ( The output signal of N) remains low until the next shift register unit (GOA) of the row is recharged.
  • GOA shift register unit
  • the first voltage signal accessed by the first voltage terminal VDD and the first control signal accessed by the first control signal terminal GCL are first level signals
  • the second voltage signal of the second voltage terminal VSS access and the second control signal of the second control signal terminal GCH are the second level signal, and the first level signal and the second level signal are different ;
  • Step 305 In the input stage, the input signal of the input terminal G(N-1) is a first level signal, and the reset signal of the reset signal terminal G(N+1) is a second level. a signal, the input circuit 101 outputs a pre-output signal at the pull-up node PU, and the output circuit 102 outputs a second level signal; the first pull-down control circuit 104 and the second pull-down control circuit 105 are both The second level signal is output, and the first pull-down circuit 106 and the second pull-down circuit 107 are both turned off.
  • Step 306 In the output stage, the input signal input by the input terminal G(N-1) and the reset signal accessed by the reset signal terminal G(N+1) are both second level signals, and the clock signal end is The clock signal of the CLK access is a first level signal, and the potential of the pull-up node PU is further raised by the bootstrap effect of the capacitor C, so that the output circuit 102 outputs a first level signal;
  • the pull control circuit 104 and the second pull-down control circuit 105 each output a second level signal, and the first pull-down circuit 106 and the second pull-down circuit 107 are both turned off.
  • Step 307 In the reset phase and the noise reduction phase, the input signal input by the input terminal G(N-1) is a second level signal, and the reset signal of the reset signal terminal G(N+1) is a first level signal, the second voltage signal of the pull-up node PU being accessed by the second voltage terminal VSS is pulled low; the second pull-down control circuit 105 outputs a second level signal, the first The pull control circuit 104 outputs a first level signal, the second pull-down circuit 107 is turned off, the first pull-down circuit 106 is turned on, and the potential of the pull-up node PU is continuously pulled down to the pull-down signal.
  • the output circuit 102 is caused to output a second level signal;
  • Step 308 In the continuous phase, the input signal input by the input terminal G(N-1) and the reset signal accessed by the reset signal terminal G(N+1) are both second level signals, and the pull-up node The potential of the PU is maintained as the pull-down signal, causing the output circuit 102 to continuously output the second level signal.
  • the first level and the second level are periodically alternated, and an alternating period of the first level and the second level is an integer multiple of a driving period of one frame.
  • the TFTs in the two pull-down circuits can be alternately operated, so that the drift of the threshold voltage can be better corrected.
  • the conversion period of the first control signal and the second control signal is 2s, that is, after 120 frames are driven, the levels of GCH and GCL are interchanged. It can be known that the cycle can be set arbitrarily as long as it satisfies an integral multiple of one frame time.
  • the first control signal accessed by the first control signal terminal GCL is at a low potential
  • the second control signal accessed by the second control signal terminal GCH is at a high potential
  • the Q1 point is at a low potential
  • Q2 The point is at a high potential such that the third transistor T3 and the fourth transistor T4 are turned on, and the first transistor T1 and the second transistor T2 are turned off.
  • the pull-up node PU is continuously pulled down to the low potential of the pull-down signal by the third transistor T3, and the output signal of the output terminal G(N) is controlled by the first transistor T4.
  • the signal continues to pull low to the low potential of the pull-down signal.
  • the VGS of the third transistor T3 and the fourth transistor T4 are in a forward bias state
  • the VGS of the first transistor T1 and the second transistor T2 are in a reverse bias state.
  • the first control signal of the first control signal terminal GCL is at a high potential
  • the second control signal of the second control signal terminal GCH is at a low potential
  • the Q1 point is at a high potential
  • Q2 The point is at a low potential such that the first transistor T1 and the second transistor T2 are turned on, and the third transistor T3 and the fourth transistor T4 are turned off.
  • the pull-up node PU is continuously pulled down by the first transistor T1 to a low potential of the pull-down signal
  • the output signal of the output terminal G(N) is controlled by the second transistor T2 by the second control
  • the signal continues to pull low to the low potential of the pull-down signal.
  • the VGS of the third transistor T3 and the fourth transistor T4 are in a reverse bias state
  • the VGSs of the first transistor T1 and the second transistor T2 are in a forward bias state.
  • the first transistor T1 and the second transistor T2 and the third can be realized by periodically alternating the levels of the first control signal and the second control signal.
  • the periodic switching of the VGS bias voltages of the two sets of pull-down TFTs of the transistor T3 and the fourth transistor T4 corrects the Vth drift of the pull-down TFT to improve the leakage characteristics of the pull-down TFT.
  • control method of the shift register unit sets the first pull-down circuit and the second pull-down circuit in the shift register unit, and passes the first control signal and the second control signal.
  • the control can realize the alternate operation of the first pull-down circuit and the second pull-down circuit, so that the drift of the threshold voltage of the TFT in the first pull-down circuit and the second pull-down circuit can be corrected, thereby improving the TFT leakage characteristics.
  • FIG. 7 is a schematic structural diagram of an embodiment of a gate driving circuit provided by the present disclosure.
  • the gate driving circuit includes at least three shift register units as described before, and the shift register units are cascaded with each other.
  • the input end of the Nth stage shift register unit is connected to the output end of the N-1th shift register unit, and the reset signal end of the Nth stage shift register unit is connected to the output end of the N+1th shift register unit.
  • the input end of the Nth stage shift register unit is connected to the output end of the N+1th shift register unit, and the reset signal end of the Nth stage shift register unit is connected to the N-1th shift register unit. Output.
  • the functions of the input circuit and the reset circuit in the shift register unit at this time are reversed compared with the aforementioned cascade method.
  • the gate driving circuit provided by the embodiment of the present disclosure sets the first pull-down circuit and the second pull-down circuit in the shift register unit, and controls the first control signal and the second control signal,
  • the alternate operation of the first pull-down circuit and the second pull-down circuit can be implemented, so that the drift of the threshold voltage of the TFTs in the first pull-down circuit and the second pull-down circuit can be corrected, thereby improving the leakage characteristics of the TFT.
  • an embodiment of a display substrate is presented.
  • the display substrate includes a gate drive circuit as previously described.
  • the display substrate provided by the embodiment of the present disclosure has a first pull-down circuit and a second pull-down circuit disposed in the shift register unit and cooperates with other circuits to pass the first control signal and the second control.
  • the control of the signal can realize the alternate operation of the first pull-down circuit and the second pull-down circuit, so that the drift of the threshold voltage of the TFT in the first pull-down circuit and the second pull-down circuit can be corrected, thereby improving the leakage of the TFT characteristic.
  • an embodiment of a display device is presented.
  • the display device includes a display substrate as described above.
  • the display device in this embodiment may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device provided by the embodiment of the present disclosure sets the first pull-down circuit and the second pull-down circuit in the shift register unit and cooperates with other circuits to pass the first control signal and the second control.
  • the control of the signal can realize the alternate operation of the first pull-down circuit and the second pull-down circuit, so that the drift of the threshold voltage of the TFT in the first pull-down circuit and the second pull-down circuit can be corrected, thereby improving the discharge of the TFT characteristic.
  • the transistors in the above embodiments are independently selected from any one of a polysilicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor.
  • the "control electrode” referred to in various embodiments may specifically refer to the gate or the base of the transistor, and the “first pole” may specifically refer to the source or emitter of the transistor, and the corresponding “second pole” may specifically Refers to the drain or collector of a transistor.
  • first pole and second pole are interchangeable.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other devices having the same characteristics.
  • one of the poles is referred to as a first pole and the other pole is referred to as a second pole.
  • the transistor can be classified into an N-type transistor or a P-type transistor according to the characteristics of the transistor.
  • the driving circuit provided by the embodiments of the present disclosure, all the transistors are described by taking an N-type transistor as an example. It is conceivable that those skilled in the art can perform without creative work when implemented by using a P-type transistor. It is easily conceivable and therefore also within the scope of protection of the various embodiments of the present disclosure.
  • a first extreme source for an N-type transistor, a first extreme source, a second extreme drain, a first extreme drain, and a second extreme source for a P-type transistor.

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Abstract

一种移位寄存器单元，包括输入电路（101）、复位电路（103）、输出电路（102）、第一下拉控制电路（104）、第二下拉控制电路（105）、第一下拉电路（106）以及第二下拉电路（107）。第一下拉控制电路（104）连接至第一控制信号端（GCL）、下拉信号端（VGL）和上拉节点（PU），输出第三控制信号到第一下拉电路（106）；第二下拉控制电路（105）连接至第二控制信号端（GCH）、下拉信号端（VGL）和上拉节点（PU），输出第四控制信号到第二下拉电路（107）；第一下拉电路（106）响应于第三控制信号接通，根据第二控制信号控制上拉节点（PU）和输出端（G(N)）的电位；第二下拉电路（107）响应于第四控制信号接通，根据第一控制信号控制上拉节点（PU）和输出端（G(N)）的电位；其中，第一下拉电路（106）和第二下拉电路（107）交替接通。

Description

移位寄存器单元及其控制方法、栅极驱动电路、显示装置
相关申请
本申请要求享有2018年2月12日提交的中国发明专利申请No.201810147132.5的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，特别涉及一种移位寄存器单元及其控制方法、栅极驱动电路、显示基板以及显示装置。
背景技术
为了追求显示设备的低成本和窄边框化，现有显示面板(Panel)产品越来越多地采用阵列基板上栅极驱动(Gate driver On Array，GOA)技术，即直接将薄膜晶体管(Thin Film Transistor，TFT)栅极驱动电路制作在阵列基板上，从而省去IC绑定(Bonding)及扇出(Fan-Out)区域的空间占用，实现在材料及制备工艺等方面的成本降低与显示面板的窄边框化。
GOA技术与玻璃上芯片封装(chip on glass，COG)及膜上芯片封装(chip on film，COF)技术相比，在窄边框化以及成本上具有无可比拟的优势，目前已经在移动电话(Mobile)，触控个人电脑(Touch PC，TPC)以及笔记本(Notebook，NB)等产品上广泛使用。
发明内容
根据本公开的一个方面，提供一种移位寄存器单元，包括：输入电路、复位电路、输出电路、第一下拉控制电路、第二下拉控制电路、第一下拉电路和第二下拉电路；所述输入电路连接至输入端、第一电压端和上拉节点，用于根据来自所述输入端的输入信号和来自所述第一电压端的第一电压信号，输出预输出信号到所述上拉节点；所述输出电路连接至输出端、时钟信号端和所述上拉节点，用于根据来自所述时钟信号端的时钟信号以及所述上拉节点的电位，控制所述输出端的电位；所述复位电路连接至复位信号端、第二电压端和所述上拉节点，用于根据来自所述复位信号端的复位信号和来自所述第二电压端 的第二电压信号，输出预复位信号到所述上拉节点；所述第一下拉控制电路连接至第一控制信号端、下拉信号端和所述上拉节点，用于根据来自所述第一控制信号端的第一控制信号和来自所述下拉信号端的下拉信号以及所述上拉节点的电位，输出第三控制信号到所述第一下拉电路，以控制所述第一下拉电路接通或关断；所述第二下拉控制电路连接至第二控制信号端、下拉信号端和所述上拉节点，用于根据来自所述第二控制信号端的第二控制信号和来自所述下拉信号端的下拉信号以及所述上拉节点的电位，输出第四控制信号到所述第二下拉电路，以控制所述第二下拉电路接通或关断；所述第一下拉电路连接至所述第二控制信号端、所述第一下拉控制电路、所述上拉节点和所述输出端，响应于所述第三控制信号使得所述第一下拉电路接通，根据所述第二控制信号控制所述上拉节点和所述输出端的电位；所述第二下拉电路连接至所述第一控制信号端、所述第二下拉控制电路、所述上拉节点和所述输出端，响应于所述第四控制信号使得所述第二下拉电路接通，根据所述第一控制信号控制所述上拉节点和所述输出端的电位；其中，所述第一下拉电路和所述第二下拉电路交替接通。
在一个实施例中，所述第一控制信号和所述第二控制信号反相，且所述第一控制信号和所述第二控制信号的周期相同。
在一个实施例中，所述第一下拉电路包括第一晶体管和第二晶体管，所述第一晶体管的控制极连接所述第一下拉控制电路，所述第一晶体管的第一极连接所述上拉节点，所述第一晶体管的第二极连接所述第二控制信号端，并且所述第二晶体管的控制极连接所述第一下拉控制电路，所述第二晶体管的第一极连接所述输出端，所述第二晶体管的第二极连接所述第二控制信号端。
在一个实施例中，所述第二下拉电路包括第三晶体管和第四晶体管，所述第三晶体管的控制极连接所述第二下拉控制电路，所述第三晶体管的第一极连接所述上拉节点，所述第三晶体管的第二极连接所述第一控制信号端，并且所述第四晶体管的控制极连接所述第二下拉控制电路，所述第四晶体管的第一极连接所述输出端，所述第四晶体管的第二极连接所述第一控制信号端。
在一个实施例中，所述第一下拉控制电路包括第五晶体管和第六晶体管，所述第五晶体管的控制极和第一极连接所述第一控制信号端， 所述第五晶体管的第二极连接所述第一下拉电路，并且所述第六晶体管的控制极连接所述上拉节点，所述第六晶体管的第一极连接所述第一下拉电路，所述第六晶体管的第二极连接所述下拉信号端。
在一个实施例中，所述第二下拉控制电路包括第七晶体管和第八晶体管，所述第七晶体管的控制极和第一极连接所述第二控制信号端，所述第七晶体管的第二极连接所述第二下拉电路，并且所述第八晶体管的控制极连接所述上拉节点，所述第八晶体管的第一极连接所述第二下拉电路，所述第八晶体管的第二极连接所述下拉信号端。
在一个实施例中，所述输入电路包括第九晶体管，所述第九晶体管的控制极连接所述输入端，所述第九晶体管的第一极连接所述第一电压端，所述第九晶体管的第二极连接所述上拉节点。
在一个实施例中，所述输出电路包括第十晶体管和电容器，所述第十晶体管的控制极与所述上拉节点连接，所述第十晶体管的第一极连接所述时钟信号端，所述第十晶体管的第二极连接所述输出端，并且所述电容器的第一端与所述第十晶体管的控制极连接，所述电容的第二端与所述第十晶体管的第二极连接。
在一个实施例中，所述复位电路包括第十一晶体管，所述第十一晶体管的控制极连接所述复位信号端，所述第十一晶体管的第一极连接所述第二电压端，所述第十一晶体管的第二极连接所述上拉节点。
在一个实施例中，所述第一下拉电路包括第一晶体管和第二晶体管，所述第二下拉电路包括第三晶体管和第四晶体管，所述第一下拉控制电路包括第五晶体管和第六晶体管，所述第二下拉控制电路包括第七晶体管和第八晶体管，所述输入电路包括第九晶体管，所述输出电路包括第十晶体管和电容器，并且所述复位电路包括第十一晶体管，所述第一晶体管的控制极和所述第二晶体管的控制极连接所述第五晶体管的第二极和所述第六晶体管的第一极，所述第一晶体管的第二极和所述第二晶体管的第二极连接所述第二控制信号端，所述第一晶体管的第一极连接所述上拉节点，并且所述第二晶体管的第一极连接所述输出端，所述第三晶体管的控制极和所述第四晶体管的控制极连接所述第七晶体管的第二极和所述第八晶体管的第一极，所述第三晶体管的第二极和所述第四晶体管的第二极连接所述第一控制信号端，所述第三晶体管的第一极连接所述上拉节点，并且所述第四晶体管的第 一极连接所述输出端，所述第五晶体管的控制极和第一极连接所述第一控制信号端，所述第七晶体管的控制极和第一极连接所述第二控制信号端，并且所述第六晶体管的第二极和所述第八晶体管的第二极连接所述下拉信号端，所述第九晶体管的控制极连接所述输入端，所述第九晶体管的第一极连接所述第一电压端，所述第十一晶体管的控制极连接所述复位信号端，所述第十一晶体管的第一极连接所述第二电压端，并且所述第九晶体管的第二极和所述第十一晶体管的第二极连接所述上拉节点，所述第十晶体管的控制极与所述上拉节点连接，所述第十晶体管的第一极连接所述时钟信号端，所述第十晶体管的第二极连接所述输出端，并且所述电容器的第一端与所述第十晶体管的控制极连接，所述电容的第二端与所述第十晶体管的第二极连接。
根据本公开的另一个方面，提供一种用于驱动上述任一种移位寄存器单元的控制方法，包括：充电阶段，输入端输出输入信号，第一电压端输出第一电压信号，输入电路根据所述输入信号和所述第一电压信号，输出预输出信号到上拉节点；输出阶段，时钟信号端输出时钟信号，输出电路根据所述时钟信号以及所述上拉节点的电位，控制输出端的电位；复位阶段，复位信号端输出复位信号，第二电压端输出第二电压信号，复位电路根据所述复位信号和所述第二电压信号，输出预复位信号到所述上拉节点；降噪阶段，第一控制信号端输出第一控制信号，下拉信号端输出下拉信号，第二控制信号端输出第二控制信号，第一下拉控制电路根据所述第一控制信号和所述下拉信号以及所述上拉节点的电位，输出第三控制信号到第一下拉电路，第二下拉控制电路根据所述第二控制信号和所述下拉信号以及所述上拉节点的电位，输出第四控制信号到第二下拉电路，所述第一下拉电路和所述第二下拉电路，在所述第三控制信号和所述第四控制信号的控制下交替接通，其中，
所述第一下拉电路在所述第三控制信号的控制下接通，并根据所述第二控制信号控制所述上拉节点和所述输出端的电位；或者，所述第二下拉电路在所述第四控制信号的控制下接通，并根据所述第一控制信号控制所述上拉节点和所述输出端的电位。
在一个实施例中，所述第一控制信号具有第一电平，所述第二控制信号具有第二电平，或者所述第一控制信号具有第二电平，所述第 二控制信号具有第一电平，其中所述第一电平和所述第二电平周期***替，以控制所述第三控制信号和所述第四控制信号周期***替。
在一个实施例中，所述第一控制信号和所述第二控制信号的极***替周期为一帧画面的驱动周期的整数倍。
根据本公开的另一个方面，提供一种栅极驱动电路，包括至少3个如上所述的移位寄存器单元，所述移位寄存器单元相互级联；其中，第N级移位寄存器单元的输入端连接第N-1级移位寄存器单元的输出端，第N级移位寄存器单元的复位信号端连接第N+1级移位寄存器单元的输出端；或者，第N级移位寄存器单元的输入端连接第N+1级移位寄存器单元的输出端，第N级移位寄存器单元的复位信号端连接第N-1级移位寄存器单元的输出端。
根据本公开的另一个方面，提供一种显示基板，包括如上所述的栅极驱动电路。
根据本公开的另一个方面，提供一种显示装置，包括如上所述的显示基板。
根据本公开实施例提供的移位寄存器单元及其控制方法、栅极驱动电路、显示基板和显示装置，在移位寄存器单元中设置第一下拉电路和第二下拉电路，通过第一控制信号和第二控制信号的控制，可实现第一下拉电路和第二下拉电路的交替工作，使得第一下拉电路和第二下拉电路中的TFT的阈值电压的漂移问题能够得到补正，从而改善了TFT的漏电特性。
附图说明
图1为本公开提供的移位寄存器单元的一个实施例的结构示意图；
图2为本公开提供的移位寄存器单元的另一个实施例的结构示意图；
图3为本公开提供的移位寄存器单元的又一个实施例的结构示意图；
图4为本公开提供的移位寄存器单元的控制方法的一个实施例的流程示意图；
图5为本公开提供的移位寄存器单元的控制方法的另一个实施例的流程示意图；
图6为本公开提供的移位寄存器单元的一个实施例的控制时序示意图；
图7为本公开提供的栅极驱动电路的一个实施例的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进行详细说明。
需要说明的是，本公开的各个实施例中所使用的“第一”和“第二”均是为了区分两个具有相同名称但非相同的实体或者非相同的参量，因此“第一”和“第二”仅为了表述的方便，不应理解为对本公开实施例的限定。
本公开的发明人发现相关技术至少存在以下问题：在相关技术的GOA中的移位寄存器单元中，下拉TFT(薄膜晶体管)在绝大多数时间均下于接通状态，其栅极与源极的压差VGS＞0V。长时间的正向偏压会导致阈值电压Vth的正向漂移。对于一般的a-Si(非晶硅)TFT，长时间的正向偏压导致的Vth漂移量较小，但对于氧化物TFT(比如a-IGZO TFT)，由于受工艺影响，背沟道容易产生缺陷，在偏压作用下，缺陷捕获电子或是使电荷重新分布，TFT的Vth变化较大，Vth的正向漂移会导致其在接通状态下的开态电流Ion迅速变小，GOA的输出稳定性变差，在长时间运行下极可能产生误输出(Muti-output)及抖动等不良。
为了解决上述问题，根据本公开的一个方面，提出了一种移位寄存器单元。如图1所示，为本公开提供的移位寄存器单元的一个实施例的结构示意图。
如图1所示，所述移位寄存器单元包括输入电路101、输出电路102、复位电路103、第一下拉控制电路104、第二下拉控制电路105、第一下拉电路106和第二下拉电路107。
所述输入电路101连接至输入端G(N-1)、第一电压端VDD和上拉节点PU，用于根据来自所述输入端G(N-1)的输入信号和来自所述第一电压端VDD的第一电压信号，输出预输出信号到所述上拉节点PU，以控制所述上拉节点PU的电位。
所述输出电路102连接至时钟信号端CLK和所述上拉节点PU， 用于根据来自所述时钟信号端CLK的时钟信号以及所述上拉节点PU的电位，控制输出端G(N)的电位。
所述复位电路103连接至复位信号端G(N+1)、第二电压端VSS和所述上拉节点PU，用于根据来自所述复位信号端G(N+1)的复位信号和来自所述第二电压端VSS的第二电压信号，输出预复位信号到所述上拉节点PU，以控制所述上拉节点PU的电位。
所述第一下拉控制电路104连接至第一控制信号端GCL、下拉信号端VGL和所述上拉节点PU，用于根据来自所述第一控制信号端GCL的第一控制信号和来自所述下拉信号端VGL的下拉信号以及所述上拉节点的电位，输出第三控制信号到所述第一下拉电路106，以控制所述第一下拉电路106接通或关断。
所述第二下拉控制电路105连接至第二控制信号端GCH、下拉信号端VGL和所述上拉节点PU，用于根据来自所述第二控制信号端GCH的第二控制信号和来自所述下拉信号端VGL的下拉信号以及所述上拉节点的电位，输出第四控制信号到所述第二下拉电路107，以控制所述第二下拉电路107接通或关断。
所述第一下拉电路106连接至所述第二控制信号端GCH、所述第一下拉控制电路104、所述上拉节点PU和所述输出端G(N)，响应于所述第三控制信号使得所述第一下拉电路106接通，根据所述第二控制信号控制所述上拉节点PU和所述输出端G(N)的电位。
所述第二下拉电路107连接至所述第一控制信号端GCL、所述第二下拉控制电路105、所述上拉节点PU和所述输出端G(N)，响应于所述第四控制信号使得所述第二下拉电路107接通，根据所述第一控制信号控制所述上拉节点PU和所述输出端G(N)的电位。
所述第一下拉电路106和所述第二下拉电路107交替接通。
从上述实施例可以看出，本公开实施例提供的移位寄存器单元，设置第一下拉电路和第二下拉电路，通过第一控制信号和第二控制信号的控制，可实现第一下拉电路和第二下拉电路的交替工作，使得第一下拉电路和第二下拉电路中的TFT的阈值电压的漂移问题能够得到补正，从而改善了TFT漏电特性。
所述第一控制信号端GCL接入的第一控制信号和所述第二控制信号端GCH接入的第二控制信号反相，且所述第一控制信号和所述第二 控制信号的周期相同。在一个实施例中，所述第一控制信号和所述第二控制信号的交替周期为一帧画面的驱动周期的整数倍，例如可以为2s。通过这种周期***替控制信号极性的方式，使得下拉电路中的TFT的阈值电压的漂移问题能够得到较好的补正。
需要说明的是，所述第一控制信号和所述第二控制信号在对应于不同类型的晶体管的情况下，也可以是相同的。
图2为本公开提供的移位寄存器单元的另一个实施例的结构示意图。
如图2所示，所述移位寄存器单元包括输入电路101、输出电路102、复位电路103、第一下拉控制电路104、第二下拉控制电路105、第一下拉电路106和第二下拉电路107。
所述输入电路101连接至输入端G(N-1)、第一电压端VDD和上拉节点PU，用于根据来自所述输入端G(N-1)的输入信号和来自所述第一电压端VDD的第一电压信号，输出预输出信号到所述上拉节点PU，以控制所述上拉节点PU的电位。
所述输出电路102连接至时钟信号端CLK和所述上拉节点PU，用于根据来自所述时钟信号端CLK的时钟信号以及所述上拉节点PU的电位，控制输出端G(N)的电位。
所述复位电路103连接至复位信号端G(N+1)、第二电压端VSS和所述上拉节点PU，用于根据来自所述复位信号端G(N+1)的复位信号和来自所述第二电压端VSS的第二电压信号，输出预复位信号到所述上拉节点PU，以控制所述上拉节点PU的电位。
所述第一下拉控制电路104连接至第一控制信号端GCL、下拉信号端VGL和所述上拉节点PU，用于根据来自所述第一控制信号端GCL的第一控制信号和来自所述下拉信号端VGL的下拉信号以及所述上拉节点PU的电位，输出第三控制信号到所述第一下拉电路106，以控制所述第一下拉电路106接通或关断。
所述第二下拉控制电路105连接至第二控制信号端GCH、下拉信号端VGL和所述上拉节点PU，用于根据来自所述第二控制信号端GCH的第二控制信号和来自所述下拉信号端VGL的下拉信号以及所述上拉节点PU的电位，输出第四控制信号到所述第二下拉电路107，以控制所述第二下拉电路107接通或关断。
所述第一下拉电路106连接至所述第二控制信号端GCH、所述第一下拉控制电路104、所述上拉节点PU和所述输出端G(N)，响应于所述第三控制信号使得所述第一下拉电路106接通，根据所述第二控制信号控制所述上拉节点PU和所述输出端G(N)的电位。
具体地，所述第一下拉电路106还可进一步包括第一晶体管T1和第二晶体管T2。所述第一晶体管T1的控制极连接所述第一下拉控制电路104，所述第一晶体管T1的第一极连接所述上拉节点PU，所述第一晶体管T1的第二极连接所述第二控制信号端GCH。所述第二晶体管T2的控制极连接所述第一下拉控制电路104，所述第二晶体管T2的第一极连接所述输出端G(N)，所述第二晶体管T2的第二极连接所述第二控制信号端GCH。
所述第二下拉电路107连接至所述第一控制信号端GCL、所述第二下拉控制电路105、所述上拉节点PU和所述输出端G(N)，响应于所述第四控制信号使得所述第二下拉电路107接通，根据所述第一控制信号控制所述上拉节点PU和所述输出端G(N)的电位。
具体地，所述第二下拉电路107还可进一步包括第三晶体管T3和第四晶体管T4。所述第三晶体管T3的控制极连接所述第二下拉控制电路105，所述第三晶体管T3的第一极连接所述上拉节点PU，所述第三晶体管T3的第二极连接所述第一控制信号端GCL。所述第四晶体管T4的控制极连接所述第二下拉控制电路105，所述第四晶体管T4的第一极连接所述输出端G(N)，所述第四晶体管T4的第二极连接所述第一控制信号端GCL。
所述第一下拉电路106和所述第二下拉电路107在所述第三控制信号和所述第四控制信号的控制下交替接通。
所述第一控制信号端GCL接入的第一控制信号和所述第二控制信号端GCH接入的第二控制信号反相，且所述第一控制信号和所述第二控制信号周期相同，以控制所述第三控制信号和所述第四控制信号周期***替变化。所述第一控制信号和所述第二控制信号的交替周期为一帧画面的驱动周期的整数倍。这样，通过设计两组下拉TFT(Pull down-TFT)，两组下拉TFT在移位寄存器单元工作时栅极及源极压差VGS的极性相反，配合两组下拉TFT的分时驱动方案(即第一控制信号和第二控制信号周期***替)，可实现对下拉TFT的Vth漂移进行 补正，改善下拉TFT的漏电特性。
需要说明的是，所述第一控制信号和所述第二控制信号在对应于不同类型的晶体管的情况下，也可以是相同的。
图3为本公开提供的移位寄存器单元的又一个实施例的结构示意图。
如图3所示，所述移位寄存器单元，包括输入电路101、输出电路102、复位电路103、第一下拉控制电路104、第二下拉控制电路105、第一下拉电路106和第二下拉电路107。
所述输入电路101连接至输入端G(N-1)、第一电压端VDD和上拉节点PU，用于根据来自所述输入端G(N-1)的输入信号和来自所述第一电压端VDD的第一电压信号，输出预输出信号到所述上拉节点PU，以控制所述上拉节点PU的电位。
具体地，所述输入电路101进一步包括第九晶体管T9。所述第九晶体管T9的控制极连接所述输入端G(N-1)，所述第九晶体管T9的第一极连接所述第一电压端VDD，所述第九晶体管T9的第二极连接所述上拉节点PU。
所述输出电路102连接至时钟信号端CLK和所述上拉节点PU，用于根据来自所述时钟信号端CLK的时钟信号以及所述上拉节点PU的电位，控制输出端G(N)的电位。
具体地，所述输出电路102进一步包括第十晶体管T10和电容C。所述第十晶体管T10的控制极与所述上拉节点PU连接，所述第十晶体管T10的第一极连接所述时钟信号端CLK，所述第十晶体管T10的第二极输出所述输出信号到所述输出端G(N)。所述电容C的第一端与所述第十晶体管T10的控制极连接，所述电容C的第二端与所述第十晶体管T10的第二极连接。
所述复位电路103连接至复位信号端G(N+1)、第二电压端VSS和所述上拉节点PU，用于根据来自所述复位信号端G(N+1)的复位信号和来自所述第二电压端VSS的第二电压信号，输出预复位信号到所述上拉节点PU，以控制所述上拉节点PU的电位。
具体地，所述复位电路103进一步包括第十一晶体管T11。所述第十一晶体管T11的控制极连接所述复位信号端G(N+1)，所述第十一晶体管T11的第一极连接所述第二电压端VSS，所述第十一晶体管T11 的第二极连接所述上拉节点PU。
所述第一下拉控制电路104连接至第一控制信号端GCL、下拉信号端VGL和所述上拉节点PU，用于根据来自所述第一控制信号端GCL的第一控制信号和来自所述下拉信号端VGL的下拉信号以及所述上拉节点PU的电位，输出第三控制信号到所述第一下拉电路106，以控制所述第一下拉电路106接通或关断。
具体地，所述第一下拉控制电路104进一步包括第五晶体管T5和第六晶体管T6。所述第五晶体管T5的控制极和第一极均连接所述第一控制信号端GCL，所述第五晶体管T5的第二极连接所述第一下拉电路106。所述第六晶体管T6的控制极连接所述上拉节点PU，所述第六晶体管T6的第一极连接所述第一下拉电路106，所述第六晶体管T6的第二极连接所述下拉信号端VGL。
所述第二下拉控制电路105连接至第二控制信号端GCH、下拉信号端VGL和所述上拉节点PU，用于根据来自所述第二控制信号端GCH的第二控制信号和来自所述下拉信号端VGL的下拉信号以及所述上拉节点PU的电位，输出第四控制信号到所述第二下拉电路107，以控制所述第二下拉电路107接通或关断。
具体地，所述第二下拉控制电路105进一步包括第七晶体管T7和第八晶体管T8。所述第七晶体管T7的控制极和第一极均连接所述第二控制信号端GCH，所述第七晶体管T7的第二极连接所述第二下拉电路107。所述第八晶体管T8的控制极连接所述上拉节点PU，所述第八晶体管T8的第一极连接所述第二下拉电路107，所述第八晶体管T8的第二极连接所述下拉信号端VGL。
所述第一下拉电路106连接至所述第二控制信号端GCH、所述第一下拉控制电路104、所述上拉节点PU和所述输出端G(N)，响应于所述第三控制信号使得所述第一下拉电路106接通，根据所述第二控制信号控制所述上拉节点PU和所述输出端G(N)的电位。
具体地，所述第一下拉电路106进一步包括第一晶体管T1和第二晶体管T2。所述第一晶体管T1的控制极连接所述第一下拉控制电路104，所述第一晶体管T1的第一极连接所述上拉节点PU，所述第一晶体管T1的第二极连接所述第二控制信号端GCH。所述第二晶体管T2的控制极连接所述第一下拉控制电路104，所述第二晶体管T2的第一 极连接所述输出端G(N)，所述第二晶体管T2的第二极连接所述第二控制信号端GCH。
所述第二下拉电路107连接至所述第一控制信号端GCL、所述第二下拉控制电路105、所述上拉节点PU和所述输出端G(N)，响应于所述第四控制信号使得所述第二下拉电路107接通，根据所述第一控制信号，控制所述上拉节点PU和所述输出端G(N)的电位。
具体地，所述第二下拉电路107进一步包括第三晶体管T3和第四晶体管T4。所述第三晶体管T3的控制极连接所述第二下拉控制电路105，所述第三晶体管T3的第一极连接所述上拉节点PU，所述第三晶体管T3的第二极连接所述第一控制信号端GCL。所述第四晶体管T4的控制极连接所述第二下拉控制电路105，所述第四晶体管T4的第一极连接所述输出端G(N)，所述第四晶体管T4的第二极连接所述第一控制信号端GCL。
所述第一下拉电路106和所述第二下拉电路107在所述第三控制信号和所述第四控制信号的控制下分时交替接通。
这样，所述第一晶体管T1与所述第二晶体管T2组成一组下拉TFT，所述第三晶体管T3与所述第四晶体管T4组成另一组下拉TFT。所述第五晶体管T5与所述第六晶体管T6的接通和关断可调节Q1点的电位，所述第七晶体管T7与所述第八晶体管T8的接通和关断可调节Q2点的电位。Q1点电位控制所述第一晶体管T1与所述第二晶体管T2的接通和关断，Q2点电位控制所述第三晶体管T3与所述第四晶体管T4的接通和关断。
所述输入电路101和所述复位电路103为对称结构，使得在驱动信号调换的情况下二者可以调换使用，即所述输入电路101作为复位电路使用，而所述复位电路103作为输入电路使用，从而满足更多的驱动要求。
根据本公开的另一个方面，提出了一种移位寄存器单元的控制方法。图4为本公开提供的移位寄存器单元的控制方法的一个实施例的流程示意图。
如图4所示，所述移位寄存器单元的控制方法用于驱动如前所述的任一种移位寄存器单元，包括：
步骤201：充电阶段，输入端G(N-1)输出输入信号，第一电压端 VDD输出第一电压信号，输入电路101根据所述输入信号和所述第一电压信号，输出预输出信号到上拉节点PU，以控制所述上拉节点PU的电位；
步骤202：输出阶段，时钟信号端CLK输出时钟信号，输出电路102根据时钟信号以及所述上拉节点PU的电位，控制输出端G(N)的电位；
步骤203：复位阶段，复位信号端G(N+1)输出复位信号，第二电压端VSS输出第二电压信号，复位电路103根据所述复位信号和所述第二电压信号，输出预复位信号到所述上拉节点PU，以控制所述上拉节点PU的电位；
步骤204：降噪阶段，第一控制信号端GCL输出第一控制信号，下拉信号端VGL输出下拉信号，第二控制信号端GCH输出第二控制信号，第一下拉控制电路104根据所述第一控制信号和所述下拉信号以及所述上拉节点PU的电位，输出第三控制信号到第一下拉电路106，第二下拉控制电路105根据所述第二控制信号和所述下拉信号以及所述上拉节点PU的电位，输出第四控制信号到第二下拉电路107，
所述第一下拉电路106和所述第二下拉电路107，在所述第三控制信号和所述第四控制信号的控制下，分时交替接通，其中，
所述第一下拉电路106在所述第三控制信号的控制下接通，并根据所述第二控制信号控制所述上拉节点PU和所述输出端G(N)的电位；
或者，所述第二下拉电路107在所述第四控制信号的控制下接通，并根据所述第一控制信号控制所述上拉节点PU和所述输出端的电位G(N)。
所述第一电压信号和所述第二控制信号为第一电平信号，所述第二电压信号和所述第一控制信号为第二电平信号；或者，所述第一电压信号和所述第一控制信号为第一电平信号，所述第二电压信号和所述第二控制信号为第二电平信号。所述第一电平信号和所述第二电平信号是不同的。需要说明的是，取决于不同晶体管类型，所述第一电平信号和所述第二电平信号也可以是相同的。
从上述实施例可以看出，本公开实施例提供的移位寄存器单元的控制方法，在移位寄存器单元中设置第一下拉电路和第二下拉电路，通过第一控制信号和第二控制信号的控制，可实现第一下拉电路和第 二下拉电路的交替工作，使得第一下拉电路和第二下拉电路中的TFT的阈值电压的漂移问题能够得到补正，从而改善了TFT漏电特性。
所述第一控制信号具有第一电平，所述第二控制信号具有第二电平，或者所述第一控制信号具有第二电平，所述第二控制信号具有第一电平，所述第一电平和所述第二电平周期***替，以控制所述第三控制信号和所述第四控制信号的周期***替。所述第一电平和所述第二电平的交替周期可以为一帧画面的驱动周期的整数倍。
图5为本公开提供的移位寄存器单元的控制方法的另一个实施例的流程示意图。
如图5所示，所述移位寄存器单元的控制方法用于驱动如前所述的任一种移位寄存器单元，包括：参照附图6左半部分的时序图，其中所述第一电压端VDD接入的第一电压信号和第二控制信号端GCH接入的第二控制信号为第一电平信号，所述第二电压端VSS接入的第二电压信号和第一控制信号端GCL接入的第二控制信号为第二电平信号，并且所述第一电平信号和所述第二电平信号不同；
步骤301：在输入阶段，所述输入端G(N-1)接入的输入信号(可为上一级移位寄存器单元的输出信号)为第一电平信号，所述复位信号端G(N+1)接入的复位信号(可为下一级移位寄存器单元的输出信号)为第二电平信号，所述输入电路101在上拉节点PU输出预输出信号，所述输出电路102的输出端G(N)的输出信号为第二电平信号；所述第一下拉控制电路104和所述第二下拉控制电路105均输出第二电平信号，所述第一下拉电路106和所述第二下拉电路107均关断；所述输入信号使得第九晶体管T9接通，输入的第一电平信号给电容C进行充电，使得所述上拉节点PU的电位被拉高，所述上拉节点PU被拉高使得第六晶体管T6和第八晶体管T8接通，Q1点和Q2点处于低电位，第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4均处于关断状态，保证了所述上拉节点PU电位的持续抬升。
步骤302：在输出阶段，所述输入端G(N-1)接入的输入信号和复位信号端G(N+1)接入的复位信号均为第二电平信号，所述时钟信号端CLK接入的时钟信号为第一电平信号，所述上拉节点PU的电位受电容C的自举效应影响进一步抬升，使所述输出电路102输出第一电平信号；所述第一下拉控制电路104和所述第二下拉控制电路105均输 出第二电平信号，所述第一下拉电路106和所述第二下拉电路107均关断；所述输入信号为低电平，第九晶体管T9关断，所述上拉节点PU保持高电位，第十晶体管T10保持接通状态；时钟信号为高电位，所述上拉节点PU受电容C的自举效应(bootstrapping)影响，所述上拉节点PU电压继续抬升，第十晶体管T10进一步接通，使所述输出电路102输出第一电平信号；该阶段Q1点和Q2点继续处于低电位，第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4均处于关断状态，保证了所述上拉节点PU电位及输出信号的稳定。
步骤303：在复位阶段和降噪阶段，所述输入端G(N-1)接入的输入信号为第二电平信号，所述复位信号端G(N+1)接入的复位信号为第一电平信号，所述上拉节点PU被所述第二电压端VSS接入的第二电压信号拉低；所述第一下拉控制电路104输出第二电平信号，所述第二下拉控制电路105输出第一电平信号，所述第一下拉电路106关断，所述第二下拉电路107接通，所述上拉节点PU的电位被持续拉低到所述下拉信号端VGL接入的下拉信号，使所述输出电路102输出第二电平信号；复位信号为第一电平信号，该第一电平信号使得第十一晶体管T11接通，所述上拉节点PU的电位被拉低，第十晶体管T10关断；所述上拉节点PU处于低电位使得第六晶体管T6和第八晶体管T8关断，由于所述第二控制信号(GCH)和所述第一控制信号(GCL)分别处于高电位和低电位，因此Q1点处于低电位，Q2点处于高电位，从而使得第三晶体管T3和第四晶体管T4接通，第一晶体管T1和第二晶体管T2关断；所述上拉节点PU通过第三晶体管T3被所述第一控制信号持续拉低到下拉信号的低电位，所述输出端G(N)的输出信号通过第四晶体管T4被所述第一控制信号持续拉低到下拉信号的低电位。
步骤304：在持续阶段，所述输入端G(N-1)接入的输入信号和复位信号端G(N+1)接入的复位信号均为第二电平信号，所述上拉节点PU的电位保持为所述下拉信号，使所述输出电路102持续输出第二电平信号；所述上拉节点PU、Q1点及Q2点的电位与上一时段相同，所述输出端G(N)的输出信号保持低电平输出直至下一帧该行移位寄存器单元(GOA)重新充放电。
参照附图6右半部分的时序图，其中所述第一电压端VDD接入的第一电压信号和第一控制信号端GCL接入的第一控制信号为第一电平 信号，所述第二电压端VSS接入的第二电压信号和第二控制信号端GCH接入的第二控制信号为第二电平信号时，并且所述第一电平信号和所述第二电平信号不同；
步骤305：在输入阶段，所述输入端G(N-1)接入的输入信号为第一电平信号，所述复位信号端G(N+1)接入的复位信号为第二电平信号，所述输入电路101在所述上拉节点PU输出预输出信号，所述输出电路102输出第二电平信号；所述第一下拉控制电路104和所述第二下拉控制电路105均输出第二电平信号，所述第一下拉电路106和所述第二下拉电路107均关断。
步骤306：在输出阶段，所述输入端G(N-1)接入的输入信号和复位信号端G(N+1)接入的复位信号均为第二电平信号，所述时钟信号端CLK接入的时钟信号为第一电平信号，所述上拉节点PU的电位受电容C的自举效应影响进一步抬升，使所述输出电路102输出第一电平信号；所述第一下拉控制电路104和所述第二下拉控制电路105均输出第二电平信号，所述第一下拉电路106和所述第二下拉电路107均关断。
步骤307：在复位阶段和降噪阶段，所述输入端G(N-1)接入的输入信号为第二电平信号，所述复位信号端G(N+1)接入的复位信号为第一电平信号，所述上拉节点PU被所述第二电压端VSS接入的第二电压信号拉低；所述第二下拉控制电路105输出第二电平信号，所述第一下拉控制电路104输出第一电平信号，所述第二下拉电路107关断，所述第一下拉电路106接通，所述上拉节点PU的电位被持续拉低到所述下拉信号，使所述输出电路102输出第二电平信号；
步骤308：在持续阶段，所述输入端G(N-1)接入的输入信号和复位信号端G(N+1)接入的复位信号均为第二电平信号，所述上拉节点PU的电位保持为所述下拉信号，使所述输出电路102持续输出第二电平信号。
所述第一电平和所述第二电平周期***替，且所述第一电平和所述第二电平的交替周期为一帧画面的驱动周期的整数倍。通过这种周期***替控制信号的方式，使得两组下拉电路中的TFT能够交替工作，从而使其阈值电压的漂移问题能够得到较好的补正。图5中示出所述第一控制信号和所述第二控制信号的变换周期为2s，即驱动120帧后， GCH和GCL的电平互换。可以知道，实际上该周期可随意设定，只要满足一帧时间的整数倍即可。
在前2s，所述第一控制信号端GCL接入的第一控制信号处于低电位，所述第二控制信号端GCH接入的第二控制信号处于高电位，因此Q1点处于低电位，Q2点处于高电位，从而使得第三晶体管T3和第四晶体管T4接通，第一晶体管T1和第二晶体管T2关断。所述上拉节点PU通过第三晶体管T3被所述第一控制信号持续拉低到下拉信号的低电位，所述输出端G(N)的输出信号通过第四晶体管T4被所述第一控制信号持续拉低到下拉信号的低电位。此时第三晶体管T3和第四晶体管T4的VGS处于正向偏压状态，第一晶体管T1和第二晶体管T2的VGS处于反向偏压状态。
在后2s，所述第一控制信号端GCL接入的第一控制信号处于高电位，所述第二控制信号端GCH接入的第二控制信号处于低电位，因此Q1点处于高电位，Q2点处于低电位，从而使得第一晶体管T1和第二晶体管T2接通，第三晶体管T3和第四晶体管T4关断。所述上拉节点PU通过第一晶体管T1被所述第二控制信号持续拉低到下拉信号的低电位，所述输出端G(N)的输出信号通过第二晶体管T2被所述第二控制信号持续拉低到下拉信号的低电位。此时第三晶体管T3和第四晶体管T4的VGS处于反向偏压状态，第一晶体管T1和第二晶体管T2的VGS处于正向偏压状态。
因此，在本公开实施例提出的移位寄存器单元中，通过所述第一控制信号和所述第二控制信号的电平周期***替，可实现第一晶体管T1和第二晶体管T2以及第三晶体管T3和第四晶体管T4这两组下拉TFT的VGS偏压的周期***替，对下拉TFT的Vth漂移进行补正，改善下拉TFT的漏电特性。
从上述实施例可以看出，本公开实施例提供的移位寄存器单元的控制方法，在移位寄存器单元中设置第一下拉电路和第二下拉电路，通过第一控制信号和第二控制信号的控制，可实现第一下拉电路和第二下拉电路的交替工作，使得第一下拉电路和第二下拉电路中的TFT的阈值电压的漂移问题能够得到补正，从而改善了TFT漏电特性。
图7为本公开提供的栅极驱动电路的一个实施例的结构示意图。
如图7所示，所述栅极驱动电路包括至少3个如前所述的任一种 移位寄存器单元，所述移位寄存器单元相互级联。第N级移位寄存器单元的输入端连接第N-1级移位寄存器单元的输出端，第N级移位寄存器单元的复位信号端连接第N+1级移位寄存器单元的输出端。
可替换地，第N级移位寄存器单元的输入端连接第N+1级移位寄存器单元的输出端，第N级移位寄存器单元的复位信号端连接第N-1级移位寄存器单元的输出端。与前述级联方式相比，此时的移位寄存器单元中的输入电路和复位电路的功能进行了调换。
从上述实施例可以看出，本公开实施例提供的栅极驱动电路，在移位寄存器单元中设置第一下拉电路和第二下拉电路，通过第一控制信号和第二控制信号的控制，可实现第一下拉电路和第二下拉电路的交替工作，使得第一下拉电路和第二下拉电路中的TFT的阈值电压的漂移问题能够得到补正，从而改善了TFT的漏电特性。
根据本公开的另一个方面，提出了一种显示基板的一个实施例。
所述显示基板包括如前所述的栅极驱动电路。
从上述实施例可以看出，本公开实施例提供的显示基板，在移位寄存器单元中设置第一下拉电路和第二下拉电路并配合其他电路的工作，通过第一控制信号和第二控制信号的控制，可实现第一下拉电路和第二下拉电路的交替工作，使得第一下拉电路和第二下拉电路中的TFT的阈值电压的漂移问题能够得到补正，从而改善了TFT的漏电特性。
根据本公开的另一个方面，提出了一种显示装置的一个实施例。
所述显示装置包括如前所述的显示基板。
需要说明的是，本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
从上述实施例可以看出，本公开实施例提供的显示装置，在移位寄存器单元中设置第一下拉电路和第二下拉电路并配合其他电路的工作，通过第一控制信号和第二控制信号的控制，可实现第一下拉电路和第二下拉电路的交替工作，使得第一下拉电路和第二下拉电路中的TFT的阈值电压的漂移问题能够得到补正，从而改善了TFT的放电特性。
需要说明的是，上述各实施例中的晶体管独立选自多晶硅薄膜晶体管、非晶硅薄膜晶体管、氧化物薄膜晶体管以及有机薄膜晶体管中的任一种。在各实施例中涉及到的“控制极”具体可以是指晶体管的栅极或基极，“第一极”具体可以是指晶体管的源极或发射极，相应的“第二极”具体可以是指晶体管的漏极或集电极。当然，本领域的技术人员应该知晓的是，该“第一极”与“第二极”可进行互换。
本公开各实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开各实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型晶体管或P型晶体管。在本公开各实施例提供的驱动电路中，所有晶体管均是以N型晶体管为例进行说明的，可以想到的是在采用P型晶体管实现时是本领域技术人员可在没有作出创造性劳动前提下轻易想到的，因此也是在本公开各实施例的保护范围内。
在本公开各实施例中，对于N型晶体管，第一极为源极，第二极为漏极，对于P型晶体管，第一极为漏极，第二极为源极。
所属领域的普通技术人员应当理解：以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (16)

  1. 一种移位寄存器单元，包括：输入电路、复位电路、输出电路、第一下拉控制电路、第二下拉控制电路、第一下拉电路和第二下拉电路；
    所述输入电路连接至输入端、第一电压端和上拉节点，用于根据来自所述输入端的输入信号和来自所述第一电压端的第一电压信号，输出预输出信号到所述上拉节点；
    所述输出电路连接至输出端、时钟信号端和所述上拉节点，用于根据来自所述时钟信号端的时钟信号以及所述上拉节点的电位，控制所述输出端的电位；
    所述复位电路连接至复位信号端、第二电压端和所述上拉节点，用于根据来自所述复位信号端的复位信号和来自所述第二电压端的第二电压信号，输出预复位信号到所述上拉节点；
    所述第一下拉控制电路连接至第一控制信号端、下拉信号端和所述上拉节点，用于根据来自所述第一控制信号端的第一控制信号和来自所述下拉信号端的下拉信号以及所述上拉节点的电位，输出第三控制信号到所述第一下拉电路，以控制所述第一下拉电路接通或关断；
    所述第二下拉控制电路连接至第二控制信号端、下拉信号端和所述上拉节点，用于根据来自所述第二控制信号端的第二控制信号和来自所述下拉信号端的下拉信号以及所述上拉节点的电位，输出第四控制信号到所述第二下拉电路，以控制所述第二下拉电路接通或关断；
    所述第一下拉电路连接至所述第二控制信号端、所述第一下拉控制电路、所述上拉节点和所述输出端，响应于所述第三控制信号使得所述第一下拉电路接通，根据所述第二控制信号控制所述上拉节点和所述输出端的电位；
    所述第二下拉电路连接至所述第一控制信号端、所述第二下拉控制电路、所述上拉节点和所述输出端，响应于所述第四控制信号使得所述第二下拉电路接通，根据所述第一控制信号控制所述上拉节点和所述输出端的电位；
    其中，所述第一下拉电路和所述第二下拉电路交替接通。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述第一控制 信号和所述第二控制信号反相，且所述第一控制信号和所述第二控制信号的周期相同。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述第一下拉电路包括第一晶体管和第二晶体管，
    所述第一晶体管的控制极连接所述第一下拉控制电路，所述第一晶体管的第一极连接所述上拉节点，所述第一晶体管的第二极连接所述第二控制信号端，并且
    所述第二晶体管的控制极连接所述第一下拉控制电路，所述第二晶体管的第一极连接所述输出端，所述第二晶体管的第二极连接所述第二控制信号端。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述第二下拉电路包括第三晶体管和第四晶体管，
    所述第三晶体管的控制极连接所述第二下拉控制电路，所述第三晶体管的第一极连接所述上拉节点，所述第三晶体管的第二极连接所述第一控制信号端，并且
    所述第四晶体管的控制极连接所述第二下拉控制电路，所述第四晶体管的第一极连接所述输出端，所述第四晶体管的第二极连接所述第一控制信号端。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述第一下拉控制电路包括第五晶体管和第六晶体管，
    所述第五晶体管的控制极和第一极连接所述第一控制信号端，所述第五晶体管的第二极连接所述第一下拉电路，并且
    所述第六晶体管的控制极连接所述上拉节点，所述第六晶体管的第一极连接所述第一下拉电路，所述第六晶体管的第二极连接所述下拉信号端。
  6. 根据权利要求1所述的移位寄存器单元，其中，所述第二下拉控制电路包括第七晶体管和第八晶体管，
    所述第七晶体管的控制极和第一极连接所述第二控制信号端，所述第七晶体管的第二极连接所述第二下拉电路，并且
    所述第八晶体管的控制极连接所述上拉节点，所述第八晶体管的第一极连接所述第二下拉电路，所述第八晶体管的第二极连接所述下拉信号端。
  7. 根据权利要求1所述的移位寄存器单元，其中，所述输入电路包括第九晶体管，
    所述第九晶体管的控制极连接所述输入端，所述第九晶体管的第一极连接所述第一电压端，所述第九晶体管的第二极连接所述上拉节点。
  8. 根据权利要求1所述的移位寄存器单元，其中，所述输出电路包括第十晶体管和电容器，
    所述第十晶体管的控制极与所述上拉节点连接，所述第十晶体管的第一极连接所述时钟信号端，所述第十晶体管的第二极连接所述输出端，并且
    所述电容器的第一端与所述第十晶体管的控制极连接，所述电容的第二端与所述第十晶体管的第二极连接。
  9. 根据权利要求1所述的移位寄存器单元，其中，所述复位电路包括第十一晶体管，
    所述第十一晶体管的控制极连接所述复位信号端，所述第十一晶体管的第一极连接所述第二电压端，所述第十一晶体管的第二极连接所述上拉节点。
  10. 根据权利要求1所述的移位寄存器单元，其中，所述第一下拉电路包括第一晶体管和第二晶体管，所述第二下拉电路包括第三晶体管和第四晶体管，所述第一下拉控制电路包括第五晶体管和第六晶体管，所述第二下拉控制电路包括第七晶体管和第八晶体管，所述输入电路包括第九晶体管，所述输出电路包括第十晶体管和电容器，并且所述复位电路包括第十一晶体管，
    所述第一晶体管的控制极和所述第二晶体管的控制极连接所述第五晶体管的第二极和所述第六晶体管的第一极，所述第一晶体管的第二极和所述第二晶体管的第二极连接所述第二控制信号端，所述第一晶体管的第一极连接所述上拉节点，并且所述第二晶体管的第一极连接所述输出端，
    所述第三晶体管的控制极和所述第四晶体管的控制极连接所述第七晶体管的第二极和所述第八晶体管的第一极，所述第三晶体管的第二极和所述第四晶体管的第二极连接所述第一控制信号端，所述第三晶体管的第一极连接所述上拉节点，并且所述第四晶体管的第一极连 接所述输出端，
    所述第五晶体管的控制极和第一极连接所述第一控制信号端，所述第七晶体管的控制极和第一极连接所述第二控制信号端，并且所述第六晶体管的第二极和所述第八晶体管的第二极连接所述下拉信号端，
    所述第九晶体管的控制极连接所述输入端，所述第九晶体管的第一极连接所述第一电压端，所述第十一晶体管的控制极连接所述复位信号端，所述第十一晶体管的第一极连接所述第二电压端，并且所述第九晶体管的第二极和所述第十一晶体管的第二极连接所述上拉节点，
    所述第十晶体管的控制极与所述上拉节点连接，所述第十晶体管的第一极连接所述时钟信号端，所述第十晶体管的第二极连接所述输出端，并且
    所述电容器的第一端与所述第十晶体管的控制极连接，所述电容的第二端与所述第十晶体管的第二极连接。
  11. 一种用于驱动如权利要求1至10中任一项所述的移位寄存器单元的控制方法，包括：
    充电阶段，输入端输出输入信号，第一电压端输出第一电压信号，输入电路根据所述输入信号和所述第一电压信号，输出预输出信号到上拉节点；
    输出阶段，时钟信号端输出时钟信号，输出电路根据所述时钟信号以及所述上拉节点的电位，控制输出端的电位；
    复位阶段，复位信号端输出复位信号，第二电压端输出第二电压信号，复位电路根据所述复位信号和所述第二电压信号，输出预复位信号到所述上拉节点；
    降噪阶段，第一控制信号端输出第一控制信号，下拉信号端输出下拉信号，第二控制信号端输出第二控制信号，第一下拉控制电路根据所述第一控制信号和所述下拉信号以及所述上拉节点的电位，输出第三控制信号到第一下拉电路，第二下拉控制电路根据所述第二控制信号和所述下拉信号以及所述上拉节点的电位，输出第四控制信号到第二下拉电路，
    所述第一下拉电路和所述第二下拉电路，在所述第三控制信号和所述第四控制信号的控制下交替接通，其中，
    所述第一下拉电路在所述第三控制信号的控制下接通，并根据所 述第二控制信号控制所述上拉节点和所述输出端的电位；
    或者，所述第二下拉电路在所述第四控制信号的控制下接通，并根据所述第一控制信号控制所述上拉节点和所述输出端的电位。
  12. 根据权利要求11所述的方法，其中，所述第一控制信号具有第一电平，所述第二控制信号具有第二电平，或者所述第一控制信号具有第二电平，所述第二控制信号具有第一电平，所述第一电平和所述第二电平周期***替，以控制所述第三控制信号和所述第四控制信号周期***替。
  13. 根据权利要求12所述的方法，其中，所述第一电平和所述第二电平的交替周期为一帧画面的驱动周期的整数倍。
  14. 一种栅极驱动电路，包括至少3个如权利要求1-10中任一项所述的移位寄存器单元，所述移位寄存器单元相互级联；
    其中，第N级移位寄存器单元的输入端连接第N-1级移位寄存器单元的输出端，第N级移位寄存器单元的复位信号端连接第N+1级移位寄存器单元的输出端；
    或者，第N级移位寄存器单元的输入端连接第N+1级移位寄存器单元的输出端，第N级移位寄存器单元的复位信号端连接第N-1级移位寄存器单元的输出端。
  15. 一种显示基板，包括如权利要求14所述的栅极驱动电路。
  16. 一种显示装置，包括如权利要求15所述的显示基板。
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