WO2014194669A1 - 半导体器件及其制作方法 - Google Patents
半导体器件及其制作方法 Download PDFInfo
- Publication number
- WO2014194669A1 WO2014194669A1 PCT/CN2014/070150 CN2014070150W WO2014194669A1 WO 2014194669 A1 WO2014194669 A1 WO 2014194669A1 CN 2014070150 W CN2014070150 W CN 2014070150W WO 2014194669 A1 WO2014194669 A1 WO 2014194669A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrode
- semiconductor device
- shape control
- control layer
- layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 146
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 48
- 230000007423 decrease Effects 0.000 claims abstract description 9
- 230000015556 catabolic process Effects 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 26
- 229910002601 GaN Inorganic materials 0.000 claims description 23
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 20
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 238000000206 photolithography Methods 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 10
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- -1 HfA10x Inorganic materials 0.000 claims description 5
- 229910004541 SiN Inorganic materials 0.000 claims description 5
- 229910052681 coesite Inorganic materials 0.000 claims description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
- 229910052905 tridymite Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 42
- 238000009826 distribution Methods 0.000 abstract description 26
- 230000003247 decreasing effect Effects 0.000 description 22
- 239000000463 material Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009828 non-uniform distribution Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42352—Gate electrodes for transistors with charge trapping gate insulator with the gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
Definitions
- the present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method of fabricating the same.
- the distribution of the electric field can be controlled by a number of methods, such as modulation doping of the active region, addition of the field plate to reduce the maximum value of the electric field, and control of the distribution of the electric field by controlling the shape of the electrode.
- Gallium nitride-based high electron mobility transistor which belongs to a planar channel field effect transistor, whose gate shape control is one of the most important device manufacturing processes.
- the planar structure of a high electron mobility transistor causes a non-uniform distribution of the electric field strength, especially in the case where the voltage between the source and the drain is high, an extremely high electric field is generated at the edge of the gate close to the drain. strength.
- Figure 1 shows the electric field intensity distribution between the source and the drain of a gallium nitride-based high electron mobility transistor.
- the electric field strength is 4 ⁇ at the edge of the gate near the drain, once the peak electric field exceeds the nitridation.
- the critical electric field of the gallium material the device will be broken down.
- the withstand voltage of the device is the integral of the electric field between the gate and the drain, the higher the electric field at the gate edge, the lower the voltage the device will withstand than the evenly distributed electric field. This phenomenon can greatly reduce the performance of the device, such as the breakdown voltage of the device and the reliability of the device.
- the distribution of the electric field can be controlled by many methods, such as modulation doping of the active region, using the field plate to reduce the maximum value of the electric field, and also by controlling the shape of the electrode. Constrain the distribution of the electric field.
- the field plate expands the horizontal depletion region of the planar device by vertical depletion of the active region of the planar device, thereby causing a change in the electric field intensity distribution of the planar device.
- the position of the field plate can be at the source, gate or drain, and a single or multiple field plates can be used in the device to vary the distribution of the electric field strength and reduce the maximum electric field strength at the gate edge near the drain.
- the T-gate changes the electric field distribution at the gate by making the shape of the gate into a T-shape, using the shape characteristics of the T-gate itself.
- the dielectric layer is indispensable, and the most common dielectric layer is silicon nitride. Due to the limitations of the manufacturing process, the complex shape of the field plate is difficult to implement in the process, or the manufacturing process is complicated or impossible. Due to the limitations of the manufacturing process, the shape of the gate is also relatively simple, and the gates of various shapes are also difficult to manufacture, or the fabrication process is complicated or impossible. Therefore, there is an urgent need to develop new fabrication processes to implement complex shaped field plates and gates of various shapes.
- the invention discloses an electrode shape control layer, wherein the electrode shape control layer contains aluminum element, and the content of the aluminum element in the layer can be adjusted.
- the electrode shape control layer is etched, the lateral and longitudinal etching speeds are As the content of aluminum changes, the shape of the etched section can be controlled, and the etched sections of different shapes can be designed and fabricated. After the electrodes are deposited, electrodes of corresponding shapes are formed, thereby achieving the purpose of controlling the shape of the electrodes.
- the content of aluminum in the shape control layer of the adjustment electrode is gradually decreased from bottom to top, for example: when the downward trend is linearly decreased, the side of the groove is sloped, and the shape of the etching section is trapezoidal, deposition After the electrode, the electrode section is also trapezoidal, dispersing the distribution of the electric field peak; when the downward trend is decelerating and decreasing, the side of the groove is an arc-shaped slope that is concave toward both sides, and the shape of the etching section is U-shaped, after depositing the electrode
- the electrode cross section is also U-shaped, and the electric field distribution at the edge of the electrode changes correspondingly, smoothing the electric field distribution; when the downward trend is accelerated, the side of the groove is an arc-shaped slope protruding toward the middle, after depositing the electrode
- the electrode section also has the same groove interface, and the electric field distribution at the edge of the electrode changes correspondingly, which smoothes the electric field distribution.
- a semiconductor device comprising:
- Electrode shape control layer on the active region of the semiconductor device, wherein the electrode shape control layer contains an aluminum element, and the content of the aluminum element in all or part of the electrode shape control layer gradually decreases from the bottom to the top of the active region of the semiconductor device Reducing, the electrode shape control layer is provided with an electrode region, and the groove, the side surface of the groove is all or part of a slope, or an arc slope which is trapped to both sides, or an arc-shaped slope which protrudes toward the middle;
- the electrode shape is corresponding to the shape of the groove, and the bottom of the electrode is in contact with the active region of the semiconductor device.
- the electrode shape control layer is a combination of one or both of a semiconductor layer and a first dielectric layer.
- the semiconductor layer in the active region of the semiconductor device and the electrode shape control layer is a combination of one or more of a group III nitride, a silicon, a germanium, a silicon, a mv compound, and an oxide. .
- the first dielectric layer comprises a combination of one or more of SiN, SiAIN, SiAlGaN, SiA10x, AlMgON, HfAlOx.
- the electrode shape control layer is a semiconductor layer and a first dielectric layer
- the first dielectric layer is located above the semiconductor layer, and the content of the aluminum element in any one of the semiconductor layers is higher than the first medium. The content of any aluminum element in the layer.
- the content of the aluminum element in all or part of the electrode shape control layer is linearly decreased from the bottom to the top of the active region of the semiconductor device, or is accelerated down, or decelerated. Drop, or first linearly fall and then remain unchanged, or decelerate and then remain unchanged, or accelerate down and then remain unchanged.
- the groove portion in the electrode shape control layer extends into the active region of the semiconductor device.
- the inner wall of the groove in the electrode shape control layer and the surface of the electrode shape control layer are all or partially deposited with a second dielectric layer, and the electrodes are all or partially located on the second dielectric layer.
- the second dielectric layer comprises a combination of one or more of A1203, A10N, SiN, SiON, SiO2, HfA10x, Hf02.
- the semiconductor device comprises a diode and a triode, the electrode comprising an anode and a cathode of the diode and a source, a drain and a gate of the transistor.
- the active region of the semiconductor device comprises: a high electron mobility transistor formed by an aluminum gallium nitride/gallium nitride heterostructure, a high electron mobility formed by an aluminum gallium indium nitride/gallium nitride heterostructure Rate transistor, high mobility triode with aluminum nitride/gallium nitride heterostructure, gallium nitride MOSFET, device with indium gallium nitride/gallium nitride multiple quantum well structure, light emitting diode composed of p-type nitride, UV- LED, photodetector, hydrogen generator, solar cell, LDMOS, UMOSFET, Schottky diode or avalanche breakdown diode.
- a method for fabricating a semiconductor device comprising:
- an electrode shape control layer on the active region of the semiconductor device, wherein the electrode shape control layer contains aluminum element, and the content of aluminum element in all or part of the electrode shape control layer is from the active region of the semiconductor device
- the electrode shape control layer is provided with an electrode region; the electrode of the pole shape control layer, the side surface of the groove is all or part of a slope, or an arc slope which is trapped to both sides, or protrudes toward the middle. Curved slope
- the steps S3 and S4 are specifically: 531, applying a first mask layer on the electrode shape control layer, performing photolithography to expose the electrode region;
- the electrode shape control layer in the step S2 is a combination of one or two of a semiconductor layer and a first dielectric layer, and the growth mode of the first dielectric layer includes MOCVD, PECVD, LPCVD, MBE, CVD, or GCIB.
- the method further includes:
- Second dielectric layer in whole or in part on the inner wall of the groove and the surface of the electrode shape control layer in the electrode shape control layer, the second dielectric layer comprising one or more of A1203, A10N, SiN, SiON, SiO2, HfA10x, Hf02 Combination of species.
- the beneficial effects of the present invention are as follows:
- the semiconductor device of the present invention and the method of fabricating the same use an electrode shape control layer on the active region of the semiconductor device, and the content of the aluminum element in the electrode shape control layer varies with the thickness.
- Controlling the ratio of the lateral and longitudinal etching speeds during the etching process by controlling the change in the content of the elements in the shape control layer of the electrode, thereby changing the shape of the etching section during the etching process to achieve the electrode during the formation of the control electrode
- the shape from the process to achieve control of a variety of electrode shapes.
- the etching speed is controlled by the material of the material, it is not necessary to change the process parameters in the etching process, so the controllability and repeatability are good, and the cylinder is easy to operate.
- some special shapes can be realized, which is not possible with ordinary etching processes.
- FIG. 1 is a schematic diagram showing the electric field intensity distribution between a source and a drain when a gallium nitride-based high electron mobility transistor operates;
- FIG. 2 is a schematic structural view of a semiconductor device according to Embodiment 1 of the present invention.
- 3A to 3G are schematic flowcharts showing a method of fabricating a semiconductor device according to Embodiment 1 of the present invention.
- FIGS. 4A to 4H are schematic flow charts showing a method of fabricating a semiconductor device according to a second embodiment of the present invention.
- FIG. 5 is a schematic view showing a semiconductor device according to Embodiment 3 of the present invention.
- FIG. 6 is a schematic view showing a semiconductor device in Embodiment 4 of the present invention.
- FIG. 7 is a schematic view showing a semiconductor device in Embodiment 5 of the present invention.
- Embodiment 8 is a schematic view showing a semiconductor device in Embodiment 6 of the present invention.
- Embodiment 7 of the present invention is a schematic view showing a semiconductor device in Embodiment 7 of the present invention.
- FIG. 10 is a schematic view showing a semiconductor device according to Embodiment 8 of the present invention.
- Figure 11 is a schematic view showing a semiconductor device in a ninth embodiment of the present invention.
- Figure 12 is a schematic view showing a semiconductor device in a tenth embodiment of the present invention.
- the embodiment of the invention discloses a semiconductor device, comprising:
- the electrode shape control layer on the active region of the semiconductor device contains aluminum element, and the content of aluminum element in all or part of the electrode shape control layer is from the active region of the semiconductor device From the bottom to the top, the electrode shape control layer is provided with an electrode region, and the electrode region is provided with a groove extending toward the active region of the semiconductor device and extending longitudinally through the electrode shape control layer, and the sides of the groove are all or part of a slope, or both sides a curved slope of a depression, or an arcuate slope that protrudes toward the center;
- the electrode is wholly or partially located in the recess in the electrode region, and the shape of the electrode is corresponding to the shape of the recess, and the bottom of the electrode is in contact with the active region of the semiconductor device.
- the present invention also discloses a method for fabricating a semiconductor device, including:
- an electrode shape control layer on the active region of the semiconductor device, wherein the electrode shape control layer contains aluminum element, and the content of the aluminum element in all or part of the electrode shape control layer is gradually reduced from the bottom to the top of the active region of the semiconductor device, and the electrode shape
- the control layer is provided with an electrode area; the groove of the control layer, the side of the groove is all or part of a slope, or an arc-shaped slope which is trapped to both sides, or an arc-shaped slope which protrudes toward the middle;
- Embodiment 1 is a diagrammatic representation of Embodiment 1:
- the semiconductor device includes: a semiconductor device active region 1;
- the electrode shape control layer 2 on the active region 1 of the semiconductor device contains aluminum element, and the content of the aluminum element gradually decreases from the bottom to the top of the active region of the semiconductor device, and the downward trend is linear decrease, and the electrode shape control layer 2 is defined with an electrode region, the electrode region is provided with a groove extending toward the active region of the semiconductor device and extending longitudinally through the electrode shape control layer, the groove is an inverted trapezoid, and the side surface is a slope;
- the electrode 5 is located in the groove in the electrode region, and the shape of the electrode 5 is corresponding to the shape of the groove.
- the electrode 5 is in contact with the active region 1 of the semiconductor device.
- the electrode 5 is partially in the groove and partially in the groove. Above.
- the method for fabricating the semiconductor device of the present embodiment includes: Providing an active region 1 of the semiconductor device, as shown in FIG. 3A;
- the electrode shape control layer 2 is formed on the active region 1 of the semiconductor device, and the content of the aluminum element in the electrode shape control layer 2 is gradually decreased from bottom to top, and the downward trend is linearly decreased, and the electrode shape is defined on the electrode shape control layer.
- Figure 3B
- the feature of the groove The size can be adjusted by an etching process, and the feature size of the groove can be slightly larger or smaller than the feature size of the photolithography as compared with the feature size of the photolithography, as shown in FIG. 3D1 and FIG. 3D2, respectively;
- the electrode is deposited, the second mask layer 4 is removed, and the electrode 5 is formed, as shown in Fig. 3G.
- the content of the aluminum element in the electrode shape control layer is gradually decreased from bottom to top, and when the downward trend is linearly decreased, the side surface of the groove is a slope, the shape of the etching section is trapezoidal, and after the electrode is deposited, the electrode section is also trapezoidal. This causes the electric field distribution at the edge of the electrode to change linearly, dispersing the distribution of the electric field peaks.
- the electrode shape control layer 2 may be one of a semiconductor layer and a first dielectric layer or a combination of two.
- the semiconductor device semiconductor layer is a combination of one or more of a group III nitride, silicon, germanium, silicon, mv compound, oxide; the first dielectric layer includes one of SiN, SiAlN, SiAlGaN, SiA10x, AlMgON, HfAlOx Combination of species or multiples.
- the first dielectric layer may be grown by MOCVD, PECVD, LPCVD, MBE, CVD, or GCIB.
- the electrode shape control layer 2 is a semiconductor layer and a first dielectric layer
- the first dielectric layer is located above the semiconductor layer, and the content of the aluminum element in any one of the semiconductor layers is higher than the content of any aluminum element in the first dielectric layer.
- the content of the aluminum element in the electrode shape control layer as a whole is gradually decreased linearly from the bottom to the top of the active region of the semiconductor device.
- the active region of the semiconductor device in the embodiment includes: a high electron mobility transistor formed of an aluminum gallium nitride/gallium nitride heterostructure, a high electron mobility transistor formed of an aluminum gallium indium nitride/gallium nitride heterostructure, High mobility transistor made of aluminum nitride/gallium nitride heterostructure, gallium nitride MOSFET, device containing indium gallium nitride/gallium nitride multiple quantum well structure, light emitting diode composed of p-type nitride, UV-LED, photoelectric Detectors, hydrogen generators or solar cells can also be LDMOS, UMOSFET, diodes, Schottky diodes, avalanche breakdown diodes, etc.
- the inner wall of the groove in the electrode shape control layer 2 and the surface of the electrode shape control layer 2 are entirely or partially deposited with a second dielectric layer, and the electrodes are wholly or partially located on the second dielectric layer.
- the second dielectric layer may be a combination of one or more of A1203, A10N, SiN, SiON, SiO2, HfA10x, Hf02, and the deposition method is PECVD, LPCVD, CVD, ALD, MOCVD or PVD.
- Embodiment 2 is a diagrammatic representation of Embodiment 1:
- 4H is a schematic structural view of the semiconductor device described in the second embodiment; the structure is substantially the same as that of the semiconductor device described in the first embodiment, except that the recess portion extends into the active region of the semiconductor device.
- FIG. 4A-4H The manufacturing method corresponding to the embodiment is shown in FIG. 4A-4H, and the specific manufacturing steps are as follows: providing an active region 1 of the semiconductor device, as shown in FIG. 4A;
- the electrode shape control layer 2 is formed on the active region 1 of the semiconductor device, and the content of the aluminum element in the electrode shape control layer 2 is gradually decreased from bottom to top, and the downward trend is linearly decreased, and the electrode shape is defined on the electrode shape control layer.
- Figure 4B
- the shape of the groove varies with the content of the aluminum element in the electrode shape control layer 2, the characteristics of the groove
- the size can be adjusted by an etching process.
- the feature size of the groove can be slightly larger or smaller than the feature size of the photolithography, which is slightly larger than that shown in FIG. 4D;
- Embodiment 3 is a diagrammatic representation of Embodiment 3
- Fig. 5 is a schematic view showing the semiconductor device described in the third embodiment.
- the content of the aluminum element in the electrode shape control layer 2 is gradually decreased from the bottom to the top, and the downward trend is an accelerated decrease.
- the rest is the same as the first embodiment, and details are not described herein again.
- the content of aluminum element in the electrode shape control layer is gradually decreased from bottom to top, and when the downward trend is accelerated, the side surface of the groove is an arc-shaped slope which is convex toward the middle, and after the electrode is deposited, the electrode section also has a groove interface. Similarly, the electric field distribution at the edge of the electrode changes accordingly, smoothing the electric field distribution.
- Embodiment 4 is a diagrammatic representation of Embodiment 4:
- Fig. 6 is a schematic view showing the semiconductor device described in the fourth embodiment.
- the content of the aluminum element in the electrode shape control layer 2 is gradually decreased from the bottom to the top, and the downward trend is the deceleration.
- the rest is the same as the first embodiment, and details are not described herein again.
- the content of the aluminum element in the electrode shape control layer is gradually decreased from bottom to top, and the downward trend is decelerating, and the side surface of the groove is an arc-shaped slope which is recessed toward both sides, and the shape of the etching section is U-shaped, deposition
- the cross section of the electrode is also U-shaped, and the electric field distribution at the edge of the electrode changes correspondingly, which smoothes the electric field distribution.
- Embodiment 5 is a diagrammatic representation of Embodiment 5:
- Fig. 7 is a schematic view showing the semiconductor device described in the fifth embodiment.
- the content of the aluminum element in the electrode shape control layer 2 in this embodiment is linearly decelerated from bottom to top and remains unchanged. The rest is the same as the first embodiment, and details are not described herein again.
- the content of the aluminum element in the electrode shape control layer is linearly decelerated and then remains unchanged.
- the groove is trapezoidal in the linear deceleration portion, and the portion which remains unchanged is a rectangle, and the shape of the etched section is rectangular above and trapezoidal at the bottom.
- the electrode section is the same as the etched section.
- Fig. 8 is a schematic view showing the semiconductor device described in the sixth embodiment.
- the content of the aluminum element in the electrode shape control layer 2 is decelerated from the bottom to the top and then remains unchanged. The rest is the same as the first embodiment, and details are not described herein again.
- the content of the aluminum element in the electrode shape control layer is first decelerated and then remains unchanged, the groove is u-shaped in the deceleration and descending portion, and the portion which remains unchanged is a rectangle, and the shape of the etched section is rectangular above, and the lower part is U-shaped, after the electrode is deposited, the electrode section is the same as the etched section.
- Fig. 9 is a schematic view showing the semiconductor device described in the seventh embodiment.
- the active region of the semiconductor device is a nitride high electron mobility transistor, the nucleation layer 12 grown on any of the substrates 11, the nitride buffer layer 13 grown on the nucleation layer 12, and the nitride buffer A nitride channel layer 14 grown on the layer 13, a nitride barrier layer 15 grown on the nitride channel layer 14, and a nitride layer 16 grown on the nitride barrier layer 15.
- the electrode 51 is a gate electrode, and the electrode 52 and the electrode 53 are respectively a source and a drain of an ohmic contact. Among them, the content of the aluminum element in the electrode shape control layer 2 is gradually decreased from the bottom to the top, and the downward trend is an accelerated decrease. Therefore, the electrode 51 is an arc-shaped structure which is convex toward the center in the electrode shape control layer 2.
- Fig. 10 is a schematic view showing the semiconductor device described in the eighth embodiment.
- the active region of the semiconductor device is an N-channel enhancement type MOSFET, two highly doped N+ regions 12 and 13 on the P-type substrate 11, and the electrode shape control layer 2 is a dielectric layer, wherein the aluminum element The content is gradually decreased from bottom to top, and the downward trend is linearly decreased; the electrode 51 is a gate, the electrode 52 is a source, and the electrode 53 is a drain.
- Figure 11 is a schematic view showing the semiconductor device described in Embodiment 9.
- the active region of the semiconductor device is a Schottky diode fabricated by a common CMOS process, an N-type layer 12 on the P-type substrate 11, an N+ cathode layer 13 in the N-type layer 12, and an electrode shape control layer 2 as a medium.
- the content of the aluminum element is gradually decreased from bottom to top, and the downward trend is linearly decreased; the electrode 51 is an anode, and the electrode 52 is a cathode.
- Fig. 12 is a view showing the semiconductor device of the tenth embodiment.
- the active region of the semiconductor device is a vertical structure PIN diode, the semiconductor N+ layer 12 on the substrate 11, the semiconductor I layer 13 on the semiconductor N+ layer 12, and the semiconductor I layer 13
- the electrode shape control layer 2 is a dielectric layer in which the content of the aluminum element is gradually decreased from bottom to top, and the downward trend is linearly decreased;
- the electrode 51 is an anode, and the electrode 52 is a cathode.
- the semiconductor device of the present invention and the method of fabricating the same use an electrode shape control layer on the active region of the semiconductor device, and the content of the aluminum element in the electrode shape control layer varies with thickness. Varying, by controlling the change in the content of the elements in the shape control layer of the electrode, the ratio of the lateral and longitudinal etching speeds during the etching process is controlled, thereby changing the shape of the etching section during the etching process to achieve the formation of the control electrode.
- the shape of the electrode realizes the control of various electrode shapes from the process.
- the etching speed is controlled by the material of the material, it is not necessary to change the process parameters in the etching process, so the controllability and repeatability are good, and the cylinder is easy to operate.
- some special shapes can be realized, which is not possible with ordinary etching processes.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/896,364 US9640624B2 (en) | 2013-06-06 | 2014-01-06 | Semiconductor device and manufacturing method therefor |
SG11201510008UA SG11201510008UA (en) | 2013-06-06 | 2014-01-06 | Semiconductor device and manufacturing method therefor |
DK14807330.7T DK3010043T3 (da) | 2013-06-06 | 2014-01-06 | Halvlederindretning og fremstillingsfremgangsmåde dertil |
EP14807330.7A EP3010043B1 (en) | 2013-06-06 | 2014-01-06 | Semiconductor device and manufacturing method therefor |
JP2016517130A JP6195979B2 (ja) | 2013-06-06 | 2014-01-06 | 半導体デバイスおよびその製作方法 |
KR1020157037194A KR101780890B1 (ko) | 2013-06-06 | 2014-01-06 | 반도체 소자 및 그 제조 방법 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310223571.7A CN103311284B (zh) | 2013-06-06 | 2013-06-06 | 半导体器件及其制作方法 |
CN201310223571.7 | 2013-06-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014194669A1 true WO2014194669A1 (zh) | 2014-12-11 |
Family
ID=49136305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2014/070150 WO2014194669A1 (zh) | 2013-06-06 | 2014-01-06 | 半导体器件及其制作方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US9640624B2 (zh) |
EP (1) | EP3010043B1 (zh) |
JP (1) | JP6195979B2 (zh) |
KR (1) | KR101780890B1 (zh) |
CN (1) | CN103311284B (zh) |
DK (1) | DK3010043T3 (zh) |
SG (1) | SG11201510008UA (zh) |
WO (1) | WO2014194669A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180151484A1 (en) * | 2014-06-12 | 2018-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad Design for Reliability Enhancement in Packages |
US10833031B2 (en) | 2014-06-12 | 2020-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad design for reliability enhancement in packages |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103311284B (zh) * | 2013-06-06 | 2015-11-25 | 苏州晶湛半导体有限公司 | 半导体器件及其制作方法 |
US9812562B1 (en) | 2016-06-03 | 2017-11-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure, HEMT structure and method of forming the same |
JP2018157141A (ja) * | 2017-03-21 | 2018-10-04 | 株式会社東芝 | 半導体装置及び半導体装置の製造方法 |
CN109935630B (zh) * | 2017-12-15 | 2021-04-23 | 苏州能讯高能半导体有限公司 | 半导体器件及其制造方法 |
CN112349773A (zh) * | 2019-08-07 | 2021-02-09 | 苏州能讯高能半导体有限公司 | 一种半导体器件及其制备方法 |
CN111952360B (zh) * | 2020-08-19 | 2023-02-21 | 深圳方正微电子有限公司 | 场效应管及其制备方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101162695A (zh) * | 2006-10-09 | 2008-04-16 | 西安能讯微电子有限公司 | 氮化镓hemt器件表面钝化及提高器件击穿电压的工艺 |
CN101312207A (zh) * | 2007-05-21 | 2008-11-26 | 张乃千 | 一种增强型氮化镓hemt器件结构 |
CN101320750A (zh) * | 2007-06-06 | 2008-12-10 | 西安能讯微电子有限公司 | Hemt器件及其制造方法 |
CN101604704A (zh) * | 2008-06-13 | 2009-12-16 | 张乃千 | Hemt器件及其制造方法 |
CN102130158A (zh) * | 2011-01-05 | 2011-07-20 | 西安电子科技大学 | 阶梯型凹槽栅高电子迁移率晶体管 |
US20120223320A1 (en) * | 2011-03-04 | 2012-09-06 | Transphorm Inc. | Electrode configurations for semiconductor devices |
CN103311284A (zh) * | 2013-06-06 | 2013-09-18 | 苏州晶湛半导体有限公司 | 半导体器件及其制作方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6235639B1 (en) | 1998-11-25 | 2001-05-22 | Micron Technology, Inc. | Method of making straight wall containers and the resultant containers |
KR100403454B1 (ko) * | 2000-06-20 | 2003-11-01 | 주식회사 하이닉스반도체 | 반도체 소자의 금속 배선 형성 방법 |
KR20020002700A (ko) * | 2000-06-30 | 2002-01-10 | 박종섭 | 금속 배선 형성 방법 |
US7238560B2 (en) * | 2004-07-23 | 2007-07-03 | Cree, Inc. | Methods of fabricating nitride-based transistors with a cap layer and a recessed gate |
US7456443B2 (en) * | 2004-11-23 | 2008-11-25 | Cree, Inc. | Transistors having buried n-type and p-type regions beneath the source region |
US7749911B2 (en) * | 2004-11-30 | 2010-07-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an improved T-shaped gate structure |
US7141486B1 (en) | 2005-06-15 | 2006-11-28 | Agere Systems Inc. | Shallow trench isolation structures comprising a graded doped sacrificial silicon dioxide material and a method for forming shallow trench isolation structures |
JP2007165446A (ja) | 2005-12-12 | 2007-06-28 | Oki Electric Ind Co Ltd | 半導体素子のオーミックコンタクト構造 |
JP2008306083A (ja) * | 2007-06-11 | 2008-12-18 | Nec Corp | Iii−v族窒化物半導体電界効果型トランジスタおよびその製造方法 |
US7859021B2 (en) * | 2007-08-29 | 2010-12-28 | Sanken Electric Co., Ltd. | Field-effect semiconductor device |
JP2010067690A (ja) | 2008-09-09 | 2010-03-25 | Toshiba Corp | 化合物半導体装置およびその製造方法 |
JP5496635B2 (ja) * | 2008-12-19 | 2014-05-21 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
-
2013
- 2013-06-06 CN CN201310223571.7A patent/CN103311284B/zh active Active
-
2014
- 2014-01-06 JP JP2016517130A patent/JP6195979B2/ja active Active
- 2014-01-06 DK DK14807330.7T patent/DK3010043T3/da active
- 2014-01-06 EP EP14807330.7A patent/EP3010043B1/en active Active
- 2014-01-06 KR KR1020157037194A patent/KR101780890B1/ko active IP Right Grant
- 2014-01-06 SG SG11201510008UA patent/SG11201510008UA/en unknown
- 2014-01-06 WO PCT/CN2014/070150 patent/WO2014194669A1/zh active Application Filing
- 2014-01-06 US US14/896,364 patent/US9640624B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101162695A (zh) * | 2006-10-09 | 2008-04-16 | 西安能讯微电子有限公司 | 氮化镓hemt器件表面钝化及提高器件击穿电压的工艺 |
CN101312207A (zh) * | 2007-05-21 | 2008-11-26 | 张乃千 | 一种增强型氮化镓hemt器件结构 |
CN101320750A (zh) * | 2007-06-06 | 2008-12-10 | 西安能讯微电子有限公司 | Hemt器件及其制造方法 |
CN101604704A (zh) * | 2008-06-13 | 2009-12-16 | 张乃千 | Hemt器件及其制造方法 |
CN102130158A (zh) * | 2011-01-05 | 2011-07-20 | 西安电子科技大学 | 阶梯型凹槽栅高电子迁移率晶体管 |
US20120223320A1 (en) * | 2011-03-04 | 2012-09-06 | Transphorm Inc. | Electrode configurations for semiconductor devices |
CN103311284A (zh) * | 2013-06-06 | 2013-09-18 | 苏州晶湛半导体有限公司 | 半导体器件及其制作方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180151484A1 (en) * | 2014-06-12 | 2018-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad Design for Reliability Enhancement in Packages |
US10756007B2 (en) * | 2014-06-12 | 2020-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad design for reliability enhancement in packages |
US10833031B2 (en) | 2014-06-12 | 2020-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad design for reliability enhancement in packages |
US11177200B2 (en) | 2014-06-12 | 2021-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad design for reliability enhancement in packages |
US11600587B2 (en) | 2014-06-12 | 2023-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad design for reliability enhancement in packages |
Also Published As
Publication number | Publication date |
---|---|
EP3010043A1 (en) | 2016-04-20 |
SG11201510008UA (en) | 2016-01-28 |
JP2016524817A (ja) | 2016-08-18 |
US20160126325A1 (en) | 2016-05-05 |
CN103311284A (zh) | 2013-09-18 |
CN103311284B (zh) | 2015-11-25 |
KR101780890B1 (ko) | 2017-09-21 |
DK3010043T3 (da) | 2019-05-06 |
JP6195979B2 (ja) | 2017-09-13 |
US9640624B2 (en) | 2017-05-02 |
EP3010043B1 (en) | 2019-03-06 |
KR20160013218A (ko) | 2016-02-03 |
EP3010043A4 (en) | 2017-03-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2014194669A1 (zh) | 半导体器件及其制作方法 | |
CN109920854B (zh) | Mosfet器件 | |
CN103890923B (zh) | 半导体器件 | |
US9293538B2 (en) | Diode having trenches in a semiconductor region | |
CN108807526B (zh) | 增强型开关器件及其制造方法 | |
US20080017897A1 (en) | Semiconductor device and method of manufacturing same | |
US20170365665A1 (en) | Semiconductor device | |
US9748341B2 (en) | Metal-oxide-semiconductor (MOS) devices with increased channel periphery | |
CN104779290B (zh) | 半导体器件 | |
CN105428412A (zh) | AlGaN/GaN异质结场效应晶体管及其制备方法 | |
CN108807505A (zh) | 一种碳化硅mosfet器件及其制造方法 | |
CN116110796B (zh) | 集成sbd的碳化硅sgt-mosfet及其制备方法 | |
CN117497600B (zh) | 超结碳化硅晶体管的结构、制造方法及电子设备 | |
CN107507858B (zh) | 一种限流二极管 | |
US9613951B2 (en) | Semiconductor device with diode | |
CN111129166B (zh) | 氧化镓基半导体结构及其制备方法 | |
CN218274610U (zh) | 一种混合栅型GaN基的高电子迁移率晶体管 | |
CN114975126B (zh) | 一种降低栅电荷的屏蔽栅沟槽型mosfet制造方法 | |
CN114664934B (zh) | 一种含有场板的dmos晶体管及其制作方法 | |
CN112825330B (zh) | 一种高线性度复合栅结构的GaN晶体管器件及其制备方法 | |
CN111477680A (zh) | 双通道均匀电场调制横向双扩散金属氧化物宽带隙半导体场效应管及制作方法 | |
US7063975B2 (en) | Shallow trench power MOSFET and IGBT | |
CN216288470U (zh) | 一种屏蔽栅mosfet | |
TW201421703A (zh) | 具有終端結構之金氧半二極體元件及其製法 | |
CN117174757B (zh) | 一种超结槽栅碳化硅mosfet及其制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14807330 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2016517130 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14896364 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2014807330 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 20157037194 Country of ref document: KR Kind code of ref document: A |