WO2013086754A1 - 一种通用封装基板、封装结构和封装方法 - Google Patents

一种通用封装基板、封装结构和封装方法 Download PDF

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Publication number
WO2013086754A1
WO2013086754A1 PCT/CN2011/084495 CN2011084495W WO2013086754A1 WO 2013086754 A1 WO2013086754 A1 WO 2013086754A1 CN 2011084495 W CN2011084495 W CN 2011084495W WO 2013086754 A1 WO2013086754 A1 WO 2013086754A1
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Prior art keywords
substrate
chip
wire bonding
silicon
pads
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Application number
PCT/CN2011/084495
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English (en)
French (fr)
Inventor
蔡坚
浦园园
王谦
郭函
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清华大学
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Application filed by 清华大学 filed Critical 清华大学
Priority to US14/365,100 priority Critical patent/US20150115437A1/en
Publication of WO2013086754A1 publication Critical patent/WO2013086754A1/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Definitions

  • the present invention relates to the field of semiconductor packaging, and in particular, to a general package substrate, a package structure, and a packaging method. Background technique
  • Ball Grid Array (BGA) packaging technology is an advanced high-performance surface array packaging technology developed after the 1990s. It has many I/O ports, large pitch, high reliability, and With its short footprint and good coplanarity, it is rapidly growing in applications in light, small, and high-performance devices, and has evolved into a mature high-density packaging technology.
  • Figure 1 shows a schematic diagram of a conventional flip-chip BGA package.
  • the current BGA package is in the phase of chip design and package design, which makes the substrate design different from chip to chip, that is, the independently developed chip needs to be equipped with a separately designed package substrate, so whether it is a sample or a product
  • the cost of pre-package design can be allocated to the cost of the product, but the impact is small, but for small-volume chip packages, because of the small size and high cost, if a new package is needed The design will further increase the cost. Therefore, there is an urgent need for a new package design to meet the requirements of small-volume chip packages. Summary of the invention
  • the invention provides a universal package substrate, a package structure and a packaging method capable of overcoming the above defects, in view of the defects of high packaging cost and long time period in the existing small-scale integrated circuit products and the sample verification thereof.
  • the present invention provides a general-purpose package substrate including a first substrate and a silicon insertion layer, and an upper surface of the first substrate and a lower surface of the silicon insertion layer are formed with the first substrate a plurality of bumps electrically connected to the lower surface of the silicon insertion layer, a plurality of wire bonding pads formed on the upper surface of the silicon insertion layer, and the plurality of wire bonding pads respectively pass through the silicon The through hole is electrically connected to the plurality of bumps.
  • the present invention also provides a package structure comprising the general package substrate as described above and at least one chip, the at least one chip being located on an upper surface of the silicon insertion layer of the universal package substrate, and The pads of the at least one chip are electrically connected to the wire bonding pads formed on the upper surface of the silicon insertion layer, respectively, by wire bonding.
  • the present invention also provides a method of packaging a chip using the above-described universal package substrate, the method comprising:
  • the at least one chip after the wire is molded
  • Ball implantation is performed on the lower surface of the first substrate to effect the extraction of the electrical signals of the at least one chip.
  • the wire bonding pads on the upper surface of the silicon insertion layer are electrically connected to the bumps on the lower surface of the silicon insertion layer through the through silicon vias in the silicon insertion layer.
  • the pad of the chip is electrically connected to the wire pad on the upper surface of the silicon insertion layer by wire bonding, so that different chip designs can be integrated into the flip chip of the same specification through the silicon insertion layer, so that the same type is
  • the universal package substrate of the present invention can be applied to packages of different kinds and sizes of chips, thereby reducing packaging cost and packaging cycle.
  • the general-purpose package substrate and the package structure according to the present invention can also increase the size between the bumps of the substrate and enlarge the bumps, and can also be connected to any pad on the chip by wire bonding, so that the connection method is further improved.
  • FIG. 1 is a cross-sectional view of a prior art BGA package structure
  • FIG. 2 is a cross-sectional view of a general package substrate in accordance with the present invention.
  • Figure 3 is a schematic cross-sectional view of a package structure in accordance with the present invention.
  • Figure 4 is another schematic cross-sectional view of a package structure in accordance with the present invention.
  • Figure 5 is a further schematic cross-sectional view of a package structure in accordance with the present invention.
  • Figure 6 is a further schematic cross-sectional view of a package structure in accordance with the present invention.
  • FIG. 7 is a flow chart of packaging a chip using the universal package substrate of the present invention. Detailed ways
  • the general-purpose package substrate 10 includes a first substrate 102 and a silicon insertion layer 103, and a surface between the upper surface of the first substrate 102 and the lower surface of the silicon insertion layer 103 is formed.
  • a plurality of bumps 106 electrically connected to the upper surface of the first substrate 102 and the lower surface of the silicon insertion layer 103, and a plurality of wire bonding pads are formed on the upper surface of the silicon insertion layer 103, A plurality of wire bonding pads are electrically connected to the plurality of bumps 106 through through silicon vias 105, respectively.
  • the first substrate 102 may be an organic substrate, a silicon substrate or a ceramic substrate, and the design of the structure, the number of layers, the internal interconnect structure and the like of the first substrate 102 may be similar to the design of the BGA package substrate in the prior art. I will not repeat them here.
  • the wire bonding pads formed on the upper surface of the silicon insertion layer 103 may be formed of various materials such as aluminum, copper, gold, etc., and the implementation process thereof is well known to those skilled in the art, and will not be described herein again.
  • the material used for the wire pads can vary depending on the material used for the wire bonding.
  • Figure 3 shows a cross-sectional view of a package structure 1 according to the present invention, wherein the package structure 1 At least one chip 20 and a universal package substrate 10 in accordance with the present invention are included.
  • the general package substrate 10 is used to carry at least one chip 20, and at least one chip 20 is located on the upper surface of the silicon insertion layer 103 of the universal package substrate 10 according to the present invention, and the pads of the at least one chip 20 are respectively punched
  • the wire is electrically connected to the wire pad formed on the upper surface of the silicon insertion layer 103.
  • reference numeral 101 in Figs. 3 to 6 denotes a solder ball for extracting an electrical signal of the packaged chip 20 and achieving electrical connection between the final package and other electronic components.
  • the pads of the chip 20 are connected to the corresponding wires of the universal package substrate 10 according to the present invention by one or more of a gold wire, a copper wire, and an aluminum wire. On the pad.
  • the pads of the chip 20 are connected to the respective wire bonding pads of the universal package substrate according to the present invention by forward wire bonding and/or reverse wire bonding.
  • 3 and 4 show the forward wire bonding mode
  • Fig. 5 shows the reverse wire bonding mode. Since the above-described forward wire bonding and reverse wire bonding processes are well known to those skilled in the art, they will not be described herein.
  • the structure of the general package substrate 10 shown in FIG. 3 is the same as that of the general package substrate 10 shown in FIG. 4, except that the design of the chip 20 in FIG. 3 is different from the design of the chip 20 in FIG. 3 and the chip 20 of different design in FIG. 4 can be connected to the universal package substrate 10 according to the present invention by wire bonding without redesigning the structure of the general package substrate 10 according to the present invention, thereby saving Packaging costs and reduced production time.
  • a multi-chip module (MCM) package can also be realized by using the general-purpose package substrate 10 according to the present invention, as shown in FIG.
  • Figure 7 illustrates a method of packaging using a universal package substrate 10 in accordance with the present invention, the method comprising:
  • the at least one chip 20 may be pasted onto the upper surface of the silicon insertion layer 103 by silver paste or other adhesive.
  • the pads of the at least one chip 20 may be connected to corresponding wire pads of the universal package substrate 10 by one or more of a gold wire, a copper wire, and an aluminum wire.
  • the way of the line can be forward line and/or reverse line.
  • the MCM package can be realized by using the universal package substrate according to the present invention, wherein when the MCM package is implemented, a plurality of chips can be stacked together or both can be attached to the upper surface of the silicon insertion layer (ie, no cascading occurs). ).

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

一种通用封装基板（10），该通用封装基板包括第一基板（102）和硅***层（103），所述第一基板的上表面与所述硅***层的下表面之间形成有将上述表面电连接在一起的多个凸点（106），所述硅***层的上表面上形成有多个打线焊盘，所述多个打线焊盘分别通过硅通孔（105）与所述多个凸点电连接。还公开了一种具有该封装基板的封装结构以及封装方法。该基板适合小批量集成电路产品，且封装成本低、时间周期短。

Description

一种通用封装基板、 封装结构和封装方法
技术领域
本发明涉及半导体封装领域， 尤其涉及一种通用封装基板、 封装结构 和封装方法。 背景技术
焊球阵列 （Ball Grid Array, BGA) 封装技术是 20世纪 90年代以后发 展起来的一种先进的高性能面阵列封装技术， 其因 I/O端口数多、 节距大、 可靠性高、 引脚很短和共面性好等优点而在轻、 小、 高性能器件中应用迅 速增长， 并发展成为一门成熟的高密度封装技术。 其中， 图 1 示出了现有 的倒装 BGA封装示意图。
但是， 目前的 BGA封装处于芯片设计和封装设计相脱离的阶段， 这使 得基板设计会因芯片的不同而不同， 即独立开发的芯片需要配以单独设计 的封装基板， 因此， 无论是样片还是产品都需要前期封装的研发， 这不仅 花费了大量的费用而且还会因基板的设计和制备而延长封装周期。 对于大 批量芯片封装而言， 前期封装设计费用可以分摊到产品成本中， 影响不大， 但对于小批量芯片封装而言， 由于其产品规模不大并且成本较高， 如果还 要进行新的封装设计的话会更进一步增加成本。 因此， 迫切需要一种新的 封装设计来满足小批量芯片封装的要求。 发明内容
本发明针对现有小批量集成电路产品及其样品验证中封装成本高、 时 间周期长的缺陷， 提供一种能够克服上述缺陷的通用封装基板、 封装结构 和封装方法。 本发明提供一种通用封装基板， 该通用封装基板包括第一基板和硅插 入层， 所述第一基板的上表面与所述硅***层的下表面之间形成有将所述 第一基板的上表面与所述硅***层的下表面电连接在一起的多个凸点， 所 述硅***层的上表面上形成有多个打线焊盘， 所述多个打线焊盘分别通过 硅通孔与所述多个凸点电连接。
本发明还提供一种封装结构， 该封装结构包括如上所述的通用封装基 板和至少一个芯片， 所述至少一个芯片位于所述通用封装基板的所述硅插 入层的上表面上， 并且所述至少一个芯片的焊盘分别通过打线的方式电连 接到形成于所述硅***层的上表面上的所述打线焊盘。
本发明还提供一种采用上述的通用封装基板对芯片进行的封装的方 法， 该方法包括：
将至少一个芯片粘贴到所述通用封装基板的所述硅***层的上表面 上；
通过打线的方式将所述至少一个芯片的焊盘电连接到形成于所述硅插 入层的上表面上的所述打线焊盘；
将打线后的所述至少一个芯片进行塑封；
在所述第一基板的下表面上进行植球以实现所述至少一个芯片的电信 号的引出。
由于在根据本发明的通用封装基板和封装结构中， 位于硅***层上表 面上的打线焊盘通过硅***层中的硅通孔与位于硅***层下表面上的凸点 电连接， 而芯片的焊盘则通过打线的方式与硅***层上表面上的打线焊盘 电连接， 这样就能够通过硅***层将不同的芯片设计整合为同规格的倒装 芯片， 使得同一款根据本发明的通用封装基板能够适用于不同种类和尺寸 的芯片的封装， 从而降低了封装成本和封装周期。 另外， 根据本发明的通 用封装基板和封装结构还能够增加基板凸点之间的尺寸， 并放大凸点， 而 且其还能够通过打线的方式连接到芯片上的任意焊盘， 使得连接方式更为 附图说明
图 1是现有技术中的 BGA封装结构的截面图；
图 2是根据本发明的通用封装基板的截面图；
图 3是根据本发明的封装结构的一种截面示意图；
图 4是根据本发明的封装结构的另一截面示意图；
图 5是根据本发明的封装结构的再一截面示意图；
图 6是根据本发明的封装结构的又一截面示意图；
图 7是采用本发明的通用封装基板对芯片进行封装的流程图。 具体实施方式
下面结合附图来详细描述根据本发明的通用封装基板、 封装结构和封 装方法。
如图 2所示， 根据本发明的通用封装基板 10包括第一基板 102和硅插 入层 103，所述第一基板 102的上表面与所述硅***层 103的下表面之间形 成有将所述第一基板 102的上表面与所述硅***层 103的下表面电连接在 一起的多个凸点 106， 所述硅***层 103的上表面上形成有多个打线焊盘， 所述多个打线焊盘分别通过硅通孔 105与所述多个凸点 106电连接。
其中， 第一基板 102可以为有机基板、 硅基板或者陶瓷基板， 并且第 一基板 102 的结构、 层数、 内部互连结构等参数的设计可以类似于现有技 术中 BGA封装基板的设计， 因此此处不再赘述。
另外， 在硅***层 103 的上表面上形成的打线焊盘可以由铝、 铜、 金 等各种材料形成， 其实现工艺为本领域技术人员所熟知， 此处不再赘述， 而且形成打线焊盘所采用的材料可以根据打线所采用材料的不同而不同。
图 3示出了根据本发明的封装结构 1 的截面图， 其中， 该封装结构 1 包括至少一个芯片 20和根据本发明的通用封装基板 10。其中通用封装基板 10用于承载至少一个芯片 20， 并且至少一个芯片 20位于根据本发明的通 用封装基板 10的硅***层 103的上表面上， 并且所述至少一个芯片 20的 焊盘分别通过打线的方式电连接到形成于所述硅***层 103 的上表面上的 所述打线焊盘。
应当说明的是， 图 3至图 6中的标号 101表示焊球， 其用于引出被封 装的芯片 20的电信号并实现最终的封装体与其他电子元器件之间的电气连 接。
在根据本发明的一个优选实施方式中， 芯片 20的焊盘通过打金线、 打 铜线和打铝线中的一种或多种方式连接到根据本发明的通用封装基板 10的 相应打线焊盘上。
在根据本发明的再一优选实施方式中， 所述芯片 20的焊盘通过正向打 线和 /或反向打线的方式连接到根据本发明的通用封装基板的相应打线焊盘 上。 其中图 3和图 4示出的正向打线方式， 图 5示出的是反向打线方式。 由于上述的正向打线、 反向打线工艺是本领域技术人员公知的， 所以此处 不再赘述。
图 3中所示的通用封装基板 10的结构与图 4中所示的通用封装基板 10 的结构相同， 区别在于图 3中的芯片 20的设计与图 2中的芯片 20的设计 不同， 但是图 3和图 4中的设计不同的芯片 20都能够通过打线的方式连接 到根据本发明的通用封装基板 10上， 而不需对根据本发明的通用封装基板 10的结构进行重新设计， 从而节省了封装成本并降低了制作时间。
在根据本发明的又一优选实施方式中， 还可以通过使用根据本发明的 通用封装基板 10来实现多芯片组件 （MCM) 封装， 如图 6所示。
图 7示出了采用根据本发明的通用封装基板 10进行封装的方法， 该方 法包括：
S71、将至少一个芯片 20粘贴到所述通用封装基板 20的所述硅***层 103的上表面上。
其中， 所述至少一个芯片 20可以通过银浆或者其他粘结剂粘贴到硅插 入层 103的上表面上。
572、 通过打线的方式将所述至少一个芯片 20的焊盘电连接到形成于 所述硅***层 103的上表面上的所述打线焊盘。
其中， 所述至少一个芯片 20的焊盘可以通过打金线、 打铜线和打铝线 中的一种或多种方式连接到所述通用封装基板 10的相应打线焊盘上， 并且 打线的方式可以是正向打线和 /或反向打线。
573、 将打线后的所述至少一个芯片 20进行塑封；
574、在所述第一基板 102的下表面上进行植球以实现所述至少一个芯 片 20的电信号的引出。
以上提到采用根据本发明的通用封装基板可以实现 MCM封装， 其中 在实现 MCM封装时， 多个芯片可以层叠在一起， 也可以都粘贴到硅*** 层的上表面上 （即， 没有层叠情况出现）。
以上仅结合本发明的优选实施方式对本发明进行了详细描述， 但是应 当理解， 在不背离本发明精神和范围的情况下， 可以对本发明进行各种变 形和修改。

Claims

权利要求
1、 一种通用封装基板， 该通用封装基板包括第一基板 （102) 和硅插 入层 （103 )， 所述第一基板 （102) 的上表面与所述硅***层 （103 ) 的下 表面之间形成有将所述第一基板 （102) 的上表面与所述硅***层 （103 ) 的下表面电连接在一起的多个凸点 （106)， 所述硅***层 （103 ) 的上表面 上形成有多个打线焊盘， 所述多个打线焊盘分别通过硅通孔 （105 ) 与所述 多个凸点 （106) 电连接。
2、 根据权利要求 1所述的通用封装基板， 其中， 所述第一基板 （102) 为有机基板、 硅基板或者陶瓷基板。
3、 一种封装结构， 该封装结构包括根据权利要求 1至 2中任一项权利 要求所述的通用封装基板和至少一个芯片， 所述至少一个芯片位于所述通 用封装基板的所述硅***层 （103 ) 的上表面上， 并且所述至少一个芯片的 焊盘分别通过打线的方式电连接到形成于所述硅***层 （103 ) 的上表面上 的所述打线焊盘。
4、 根据权利要求 3所述的封装结构， 其中， 所述至少一个芯片的焊盘 通过打金线和 /或打铜线和 /或打铝线的方式连接到相应的打线焊盘上。
5、 根据权利要求 3所述的封装结构， 其中， 所述至少一个芯片的焊盘 通过正向打线和 /或反向打线的方式连接到相应的打线焊盘上。
6、一种采用权利要求 1或 2所述的通用封装基板对芯片进行的封装的 方法， 该方法包括： 将至少一个芯片粘贴到所述通用封装基板的所述硅***层 （103 ) 的上 表面上；
通过打线的方式将所述至少一个芯片的焊盘电连接到形成于所述硅插 入层 （103 ) 的上表面上的所述打线焊盘；
将打线后的所述至少一个芯片进行塑封；
在所述第一基板的下表面上进行植球以实现所述至少一个芯片的电信 号的引出。
7、 根据权利要求 6所述的方法， 其中， 所述至少一个芯片通过银浆粘 贴到所述硅***层 （103 ) 的上表面上。
8、 根据权利要求 6所述的方法， 其中， 所述至少一个芯片的焊盘通过 打金线和 /或打铜线和 /或打铝线的方式连接到所述通用封装基板的相应打 线焊盘上。
9、 根据权利要求 6所述的方法， 其中， 所述至少一个芯片的焊盘通过 正向打线和 /或反向打线的方式连接到所述通用封装基板的相应打线焊盘 上。
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