WO2011103824A2 - 一种同步sram的时序处理方法和电路 - Google Patents

一种同步sram的时序处理方法和电路 Download PDF

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Publication number
WO2011103824A2
WO2011103824A2 PCT/CN2011/072911 CN2011072911W WO2011103824A2 WO 2011103824 A2 WO2011103824 A2 WO 2011103824A2 CN 2011072911 W CN2011072911 W CN 2011072911W WO 2011103824 A2 WO2011103824 A2 WO 2011103824A2
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Prior art keywords
word line
signal
sense amplifier
input
time
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PCT/CN2011/072911
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English (en)
French (fr)
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WO2011103824A3 (zh
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周云明
季秉武
赵坦夫
林崴
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华为技术有限公司
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Priority to CN201180000314.6A priority Critical patent/CN102171761B/zh
Priority to PCT/CN2011/072911 priority patent/WO2011103824A2/zh
Publication of WO2011103824A2 publication Critical patent/WO2011103824A2/zh
Publication of WO2011103824A3 publication Critical patent/WO2011103824A3/zh
Priority to US14/057,863 priority patent/US8988932B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

Definitions

  • Embodiments of the present invention relate to the field of electronic technologies, and in particular, to a timing processing method and circuit for a synchronous SRAM.
  • Static Random Accessible Memory can save its internal data because it does not require a refresh circuit, so it is very helpful to improve system performance.
  • the primary and secondary caches in the central processing unit (CPU) use SRAM.
  • SRAM buffer while the SRAM timing path is one of the key timing paths, limits the increase in CPU operating frequency.
  • SRAM can be divided into two broad categories at a high level: synchronous and asynchronous. Synchronous SRAM uses an input clock to initiate all data processing (eg, read, write, deselect, etc.). Asynchronous SRAM does not have a clock input, and the input must be monitored to obtain commands from the controller. Once a command is identified, the asynchronous SRAM will immediately execute.
  • the address latch 101 latches the input clock signal, when the clock signal and the address signal are used.
  • an internal address signal is output, and the word line decoder 102 logically decodes the internal address signal, and the macro 103 is 103.
  • the bit line and the inverted bit line are connected. When the voltage difference between the bit line and the inverted bit line is expanded to a certain range, the data input by the memory cell array 104 is amplified, and the amplified data is output.
  • the inventors of the present invention have found that at least the following defects exist in the prior art:
  • the address signal is first latched by the address latch, and for the latch, it is necessary to satisfy a certain
  • the setup time and the hold time are followed by the output of the internal address signal, and after the address is latched, it is sent to the address decoder for address decoding. Since the address latch latches the address for a certain amount of time, this increases the timing of the synchronous SRAM's timing path and reduces the operating speed of the synchronous SRAM. Summary of the invention
  • Embodiments of the present invention provide a timing processing method and circuit for a synchronous SRAM, which can improve the working speed of the synchronous SRAM and enable the synchronous SRAM to operate at a higher frequency.
  • the address signal is directly input into the word line decoder for logic decoding
  • the clock input timing generator generates a word line clock signal, and the word line clock signal generates a word line gating signal through the word line controller;
  • the result of the logic decoding of the word line decoder under the control of the word line gating signal that is, the word line decoding signal is input to the word line pulse width generator to generate a word line signal, and the process of turning on the word line is completed;
  • the word line opening will output the data held by the memory cell array to the bit line, and after bit line selection, input to the sense amplifier;
  • the timing generator After the word line signal generates a preset time, the timing generator generates a sense amplifier control signal and inputs it to the sense amplifier to turn on the process of sensitive amplification;
  • the sense amplifier generates a sensitive amplification completion signal and a data output signal, wherein the sensitive amplification completion signal is input to the timing generator to turn off the word line clock signal, thereby controlling the turn-off of the word line gating signal, and finally controlling the word line signal.
  • the data output signal includes data that the sense amplifier performs sensitive amplification on the data selected by the bit line input from the memory cell array.
  • a word line decoder a timing generator, a word line controller, a word line pulse width generator, a memory cell array, and a sense amplifier, wherein
  • a word line decoder for directly performing logic decoding on the input address signal
  • timing generator for generating a word line clock signal and a sense amplifier control signal when the clock is input
  • a word line controller for generating a word line gating signal when a word line clock signal is input
  • a word line pulse width generator for generating a word line signal when inputting a word line gating signal and a result of logic decoding of the word line decoder, that is, a word line decoding signal
  • the storage unit array is configured to output the saved data to the bit line after inputting the word line signal, and select the bit line to input to the sense amplifier;
  • Sensing amplifier for inputting to the memory cell array when inputting a sense amplifier control signal
  • the data is amplified to generate a data output signal, and the sensitive amplification completion signal is fed back to the timing generator, and the sensitive amplification completion signal is input to the timing generator to turn off the word line clock signal, thereby controlling the turn-off of the word line gating signal, and finally
  • the control word line signal is turned off, and the data output signal includes data which is sensed by the sense amplifier to sensitively amplify the data selected by the bit line input from the memory cell array.
  • the embodiments of the present invention have the following advantages:
  • the latch time of the address latch on the timing path is saved, and the timing of each device is set by Each signal is generated, and the data selected by the bit line input input from the memory cell array is sensitively amplified and outputted, that is, the data output signal is generated, and the timing processing process of the entire synchronous SRAM is completed, thereby improving the working speed of the synchronous SRAM and enabling synchronization.
  • SRAM can work at higher frequencies.
  • Figure 1 is a circuit diagram of a conventional synchronous SRAM
  • FIG. 2 is a schematic diagram of timing processing of a synchronous SRAM in an embodiment of the present invention
  • FIG. 3 is a circuit diagram of a synchronous SRAM in an embodiment of the present invention.
  • Fig. 4 is a timing chart showing the waveforms of the synchronous SRAM in the embodiment of the present invention.
  • Embodiments of the present invention provide a timing processing method and circuit for a synchronous SRAM, which can improve the working speed of the synchronous SRAM and enable the synchronous SRAM to operate at a higher frequency.
  • FIG. 2 A schematic diagram of timing processing of a synchronous SRAM according to an embodiment of the present invention is shown in FIG. 2.
  • the address signal is directly input to the word line decoder without being latched by the address latch, so that the latch delay on the timing path can be reduced.
  • the clock input timing generator generates a word line clock signal, and the word line clock signal passes through the word line.
  • the controller generates a word line gating signal;
  • the result of the logic decoding of the word line decoder that is, the word line decoding signal is input to the word line pulse width generator to generate a word line signal, and the process of opening the word line is completed;
  • the word line signal is input to the memory cell array, the word line is turned on, the data stored in the memory cell array is output to the bit line, and the bit line is selected and input to the sense amplifier;
  • the timing generator inputs a sense amplifier control signal to the sense amplifier after the word line signal generates a preset time, and starts the process of sensitive amplification;
  • a sense amplifier control signal is generated for controlling the opening of the sense amplifier, wherein the preset time may also be manually set or automatically according to the timing logic. Generated, not limited here.
  • the sense amplifier generates a sensitive amplification completion signal and a data output signal, wherein the sensitive amplification completion signal is input to the timing generator to turn off the word line clock signal, thereby controlling the turn-off of the word line gating signal, and finally controlling the word line.
  • the signal is turned off, and the data output signal includes data which is sensed by the sense amplifier to sensitively amplify the data selected by the bit line input from the memory cell array.
  • the generation of the word line gating signal and the generation of the word line decoding signal are simultaneous, at this time, the word line gating signal and the word line.
  • the decoded signal After the decoded signal is synchronously generated, it can be input to the word line pulse width generator to generate a word line signal, thereby ensuring that the synchronous SRAM operates at the fastest speed, as described in the following embodiments.
  • the latch time of the address latch on the timing path is saved, and the timing is set by each device.
  • the data selected by the bit line selected by the memory cell array is amplified and outputted, that is, the data output signal is generated, and the timing processing process of the entire synchronous SRAM is completed, thereby improving the working speed of the synchronous SRAM. Synchronous SRAM can operate at higher frequencies.
  • Another embodiment of the present invention provides a synchronous SRAM circuit, as shown in the circuit diagram of FIG.
  • 301 is a wordline decoder
  • 302 is a timing generator
  • 303 is a wordline control
  • 304 is a wordline pulse generator
  • 305 is a storage.
  • the cell array, 306 is a senser amplifer.
  • the generated address signal (address) of the synchronous SRAM directly enters the word line decoder 301.
  • the word line decoder 301 logically decodes the address signal to generate a word line decoding signal, and the clock enters the timing generator 302 to generate a word line clock signal (clock wordline), and the word line clock signal is generated by the word line controller 303.
  • the word line gating signal, the word line gating signal generates a word line signal through the word line pulse width generator 304 to complete the process of turning on the word line, thereby realizing the opening of the control memory cell array 305, after the memory cell array 305 is turned on, the bit line
  • the upper bit voltage open signal accumulates a certain bit line split, and the timing generator 302 generates a sense amplifier control signal and inputs it to the sense amplifier 306 after the word line signal is generated for a preset time, and then the sense amplifier
  • the 306 is controlled by a sense amplifier control signal (clock senser), and after a period of time, the read data is completed, and the senser finished signal is output to the word line clock signal and the data output signal is output.
  • the memory cell array 305 shown in FIG. 3 includes a plurality of cell arrays, but only in a practical application, the number of cell arrays included in the memory cell array is not limited herein.
  • the embodiment of the present invention additionally gives a timing calculation method based on the timing processing of the synchronous SRAM shown in FIG. 2.
  • FIG. 4 For a clear description of the setup time t s of the clock signal and the hold time t h , please refer to FIG. 4 , which is specifically described as follows:
  • Ti is the time from the generation of the address signal to the generation of the decoded signal by the word line decoder.
  • t 2 is the time at which the clock generates a word line clock signal through the timing generator.
  • t 3 is the time at which the word line clock signal generates a word line gating signal through the word line controller.
  • t 4 is the time from the word line gating signal to the word line signal generated by the word line pulse width generator.
  • t 5 is the time from the generation of the word line signal to the timing generator generating the sense amplifier control signal
  • t 6 is the time when the sense amplifier control signal is generated by the sense amplifier to generate the sensitive amplification signal
  • t 7 is the sensitive amplification completion signal fed back to the timing generator
  • t 8 is the time from when the word line clock signal is turned off to when the control word line gating signal is turned off.
  • t 9 is the time taken for the address signal to be logically decoded by the word line decoder.
  • the setup time of the address signal ⁇ satisfies the following relationship:
  • the word line decoding signal and the word line gating signal can be It is synchronous, so it can take the minimum value of 0, so it can be obtained:
  • the retention time t h of the address signal satisfies the following relationship:
  • ⁇ is the time interval between the word line decode signal and the word line gating signal, since the address signal is not latched by the address latch, the word line decode signal and the word line gating signal It can be synchronous, so t w can take the minimum value of 0, so it can be obtained:
  • Th t 2 + t 3 + t 4 + t 5 + t 6 + t 7 + t 8 - t 9 .
  • the address signal does not need to be first latched by the address latch, but directly enters the word line decoder.
  • the logic decoding is performed, the delay of the latch is reduced in the timing path, and the respective signals are generated by setting the timing of each device, thereby realizing the data of the bit line selection input by the memory cell array.
  • the data output signal is generated, and the timing processing of the entire synchronous SRAM is completed, which can improve the working speed of the synchronous SRAM and enable the synchronous SRAM to operate at a higher frequency.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种同步SRAM的时序处理方法和电路，方法包括：直接将地址信号输入到字线译码器进行逻辑译码，并通过对各个器件在时序上的设置以产生各个信号，实现了将存储单元阵列输入的经过位线选择的数据进行灵敏放大后输出，即产生数据输出信号。同步SRAM电路包括：字线译码器，时序产生器，5字线控制器，字线脉宽产生器，存储单元阵列和灵敏放大器。

Description

一种同歩 SRAM的时序处理方法和电路 技术领域
本发明实施例涉及电子技术领域， 尤其涉及一种同步 SRAM的时序处理 方法和电路。
背景技术
静态随机存储器（ SRAM, Static Random Accessible Memory )由于不需要 刷新电路即能保存它内部存储的数据， 因此对提高***性能非常有帮助。 中央 处理器（ CPU, Central Processing Unit )内的一级、二级緩存使用的就是 SRAM, 为了使 CPU的性能得到进一步的提高， 就需要减少 CPU的时序路径， 整合小 容量的外部一级或二级 SRAM緩存， 而 SRAM的时序路径作为关键时序路径 之一， 限制了 CPU的工作频率的提高。 SRAM从高层次上可以划分为两个大 类： 即同步型和异步型。 同步 SRAM釆用一个输入时钟来启动所有数据处理 (例如读、 写、 取消选定等）。 而异步 SRAM则并不具备时钟输入， 且必须监 视输入以获取来自控制器的命令， 一旦识别出某条命令， 异步 SRAM将立即 力口以执行。
目前， 常用的同步 SRAM如图 1所示的电原理图， 下面结合图 1对同步 SRAM的一个时序路径进行描述， 地址锁存器 101 将输入的时钟信号进行锁 存， 当时钟信号和地址信号之间满足一定的建立时间 （setup time )和保持时 间 （ hold time ) 时， 输出内部地址信号 （ internal address ), 字线译码器 102对 内部地址信号进行逻辑译码， 灵^^大器 103和位线、反位线相连， 当位线和 反位线的电压差扩大到一定的范围时对存储单元阵列 104 输入的数据进行放 大， 并将放大后的数据输出。
本发明的发明人在实现本发明的过程中， 发现现有技术至少存在以下缺 陷： 现有的同步 SRAM中首先通过地址锁存器对地址信号进行锁存， 对于锁 存器， 需要满足一定的建立时间和保持时间再输出内部地址信号，地址锁存之 后，再送入地址译码器进行地址译码。 由于地址锁存器进行地址的锁存会消耗 一定的时间， 这就增加了同步 SRAM 的时序路径运行的时间， 降低了同步 SRAM的工作速度。 发明内容
本发明实施例提供了一种同步 SRAM的时序处理方法和电路， 能够提高 同步 SRAM的工作速度， 使同步 SRAM能工作于更高的频率。
本发明实施例提供的同步 SRAM的时序处理方法， 包括：
将地址信号直接输入字线译码器进行逻辑译码；
将时钟输入时序产生器产生字线时钟信号，字线时钟信号经过字线控制器 产生字线门控信号；
在字线门控信号的控制下将字线译码器逻辑译码的结果即字线译码信号 输入字线脉宽产生器以产生字线信号， 完成字线开启的过程；
将字线信号输入到存储单元阵列，字线开启会将存储单元阵列保存的数据 输出到位线上， 经过位线选择， 输入到灵敏放大器；
时序产生器在字线信号产生预置的时间后，将产生灵敏放大器控制信号并 输入到灵敏放大器， 开启灵敏放大的过程；
灵敏放大器产生灵敏放大完成信号和数据输出信号， 其中， 灵敏放大完成 信号用于输入给时序产生器以关断字线时钟信号，从而控制字线门控信号的关 断， 最后控制字线信号的关断，数据输出信号中包含有灵敏放大器将存储单元 阵列输入的经过位线选择的数据进行灵敏放大后输出的数据。
本发明实施例提供的同步 SRAM的电路， 包括：
字线译码器， 时序产生器， 字线控制器， 字线脉宽产生器， 存储单元阵列 和灵敏放大器， 其中，
字线译码器， 用于对输入的地址信号直接进行逻辑译码；
时序产生器， 用于在输入时钟时产生字线时钟信号和灵敏放大器控制信 号；
字线控制器， 用于在输入字线时钟信号时产生字线门控信号；
字线脉宽产生器，用于在输入字线门控信号和字线译码器逻辑译码的结果 即字线译码信号时产生字线信号；
存储单元阵列， 用于在输入字线信号后将保存的数据输出到位线上， 经过 位线选择， 输入到灵敏放大器；
灵敏放大器， 用于在输入灵敏放大器控制信号时，对存储单元阵列输入的 数据进行放大产生数据输出信号， 并向时序产生器反馈灵敏放大完成信号， 灵 敏放大完成信号用于输入给时序产生器以关断字线时钟信号，从而控制字线门 控信号的关断， 最后控制字线信号的关断，数据输出信号中包含有灵敏放大器 将存储单元阵列输入的经过位线选择的数据进行灵敏放大后输出的数据。
从以上技术方案可以看出， 本发明实施例具有以下优点：
在本发明实施例中， 由于直接将地址信号输入到字线译码器进行逻辑译 码， 节省掉了时序路径上地址锁存器的锁存时间， 并通过对各个器件在时序上 的设置以产生各个信号，实现了将存储单元阵列输入的经过位线选择的数据进 行灵敏放大后输出， 即产生数据输出信号， 完成了整个同步 SRAM的时序处 理过程， 能够提高同步 SRAM的工作速度， 使同步 SRAM能工作于更高的频 率。
附图说明
图 1是常用的同步 SRAM的电路图；
图 2是本发明实施例中的同步 SRAM的时序处理示意图；
图 3是本发明实施例中的同步 SRAM的电路图；
图 4是本发明实施例中的同步 SRAM的时序处理波形图。
具体实施方式
本发明实施例提供了一种同步 SRAM的时序处理方法和电路， 够提高同 步 SRAM的工作速度， 使同步 SRAM能工作于更高的频率。
为使得本发明的发明目的、 特征、优点能够更加的明显和易懂， 下面将结 合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、 完整地描 述，显然，下面所描述的实施例仅仅是本发明一部分实施例，而非全部实施例。 基于本发明中的实施例， 本领域的技术人员所获得的所有其他实施例，都属于 本发明保护的范围。
本发明实施例提供的一种同步 SRAM的时序处理示意图， 如图 2所示。
201、 将地址信号直接输入字线译码器进行逻辑译码；
在本发明实施例中， 直接将地址信号输入到字线译码器， 而没有经过地址 锁存器的锁存， 故能够减少时序路径上的锁存延时。
202、 将时钟输入时序产生器产生字线时钟信号， 字线时钟信号经过字线 控制器产生字线门控信号；
203、 在字线门控信号的控制下将字线译码器逻辑译码的结果即字线译码 信号输入字线脉宽产生器以产生字线信号， 完成字线开启的过程；
204、 将字线信号输入到存储单元阵列， 字线开启会将存储单元阵列保存 的数据输出到位线上， 经过位线选择， 输入到灵敏放大器；
205、 时序产生器在字线信号产生预置的时间后， 将产生灵敏放大器控制 信号输入到灵敏放大器， 开启灵敏放大的过程；
在本发明实施例中，当字线信号产生预置的时间后产生灵敏放大器控制信 号， 用于控制灵敏放大器的开启， 其中预置的时间也可以由人工设定也可以根 据该时序逻辑而自动产生， 此处不作限定。
206、 灵敏放大器产生灵敏放大完成信号和数据输出信号， 其中， 灵敏放 大完成信号用于输入给时序产生器以关断字线时钟信号，从而控制字线门控信 号的关断， 最后控制字线信号的关断，数据输出信号中包含有灵敏放大器将存 储单元阵列输入的经过位线选择的数据进行灵敏放大后输出的数据。
需要说明的是， 在本发明实施例中， 另一种优选的方式是， 字线门控信号 的产生和字线译码信号的产生是同时的， 此时， 字线门控信号和字线译码信号 同步产生后就可以输入到字线脉宽产生器产生字线信号，从而保证同步 SRAM 的工作速度是最快的， 可参见如下实施例的描述。
在本发明实施例中，由于直接将地址信号输入到字线译码器进行逻辑译码 的， 节省掉了时序路径上地址锁存器的锁存时间， 并通过对各个器件在时序上 的设置以产生各个信号，实现了将存储单元阵列输入的经过位线选择的数据进 行灵敏放大后输出， 即产生数据输出信号， 完成了整个同步 SRAM的时序处 理过程， 能够提高同步 SRAM的工作速度， 使同步 SRAM能工作于更高的频 率。
本发明实施例另外提供的一种同步 SRAM的电路，如图 3所示的电路图，
301为字线译码器（wordline decoder ), 302为时序产生器（ timing generator ), 303为字线控制器（ wordline control ), 304为字线脉宽产生器（ wordline pulse generator ), 305为存储单元阵列， 306为灵敏放大器（ senser amplifer ), 如图 3所示，产生的同步 SRAM的地址信号（ address )直接进入到字线译码器 301 , 字线译码器 301 对地址信号进行逻辑译码产生字线译码信号， 时钟（clock ) 进入时序产生器 302产生字线时钟信号 （ clock wordline ), 字线时钟信号经过 字线控制器 303 产生字线门控信号， 字线门控信号经过字线脉宽产生器 304 产生字线信号，完成字线开启的过程，从而实现控制存储单元阵列 305的打开， 存储单元阵列 305打开之后，位线上的位电压张开信号会累积一定的位线电压 差（bitline split ), 时序产生器 302在字线信号产生预置的时间后， 产生灵敏放 大器控制信号并输入到灵敏放大器 306, 然后灵敏放大器 306由灵敏放大器控 制信号（clock senser )控制开始工作， 一段时间后读数据釆样完成， 反馈灵敏 放大完成信号 （ senser finished )给字线时钟信号并输出数据输出信号。
需要说明的是， 图 3中给出的存储单元阵列 305包括多个单元阵列，但只 是在实际应用中的一种场景而已，此处不作限定存储单元阵列包括的单元阵列 的个数。
本发明实施例另外给了基于图 2所示的同步 SRAM的时序处理的时序计 算方法，为了清楚的描述时钟信号的建立时间 ts以及保持时间 th,请参阅图 4, 具体说明如下：
ti为从地址信号产生到字线译码器产生译码信号的时间，
t2为时钟经过时序产生器产生字线时钟信号的时间，
t3为字线时钟信号经过字线控制器产生字线门控信号的时间，
t4为从字线门控信号经过字线脉宽产生器产生字线信号的时间，
t5为从字线信号产生到时序产生器产生灵敏放大器控制信号的时间， t6为灵敏放大器控制信号经过灵敏放大器产生灵敏放大完成信号的时间， t7为灵敏放大完成信号反馈到时序产生器并关断字线时钟信号的时间， t8为从关断字线时钟信号到控制字线门控信号关断的时间，
t9为地址信号经过字线译码器逻辑译码所用的时间。
由图 4可知， 地址信号的建立时间 ^满足如下关系：
ts + tl + ts-1=t2 + t3 ,
如图 4所示， 为字线译码信号和字线门控信号之间的时间间隔， 由于地址信号不经过地址锁存器的锁存，故字线译码信号和字线门控信号可以 是同步的， 故 可以取最小值 0, 故可得： 地址信号的保持时间 th满足如下关系：
t2 + 13 + 14 + 15 + 16 + 17 + 18 =th + t9 + th-1,
如图 4所示， ^为字线译码信号和字线门控信号之间的时间间隔， 由于地址信号不经过地址锁存器的锁存，故字线译码信号和字线门控信号可以 是同步的， 故 tw可以取最小值 0, 故可得：
th= t2 + t3 + t4 + t5 + t6 + t7 + t8 - t9。
从以上实施例可以看出， 与现有技术相比， 本发明实施例中没有地址锁存 器，故地址信号不需要首先由地址锁存器进行锁存， 而是直接进入字线译码器 进行逻辑译码， 在时序路径上减少了锁存（latch )的延时， 并通过对各个器件 在时序上的设置以产生各个信号，实现了将存储单元阵列输入的经过位线选择 的数据进行灵敏放大后输出， 即产生数据输出信号， 完成了整个同步 SRAM 的时序处理过程， 能够提高同步 SRAM的工作速度， 使同步 SRAM能工作于 更高的频率。
本发明实施例另外给出了一种计算同步 SRAM的工作频率 fsram的方法， 如下： fsram = l / tcyc tcyc = ts + tac, 其中， tac为从时钟产生到灵敏放大器产生 数据输出信号的时间。， 通过该公式可知访问时间 （ access time ) tac在同等条 件减少了一个锁存的延时时间， 更能够明显的得出提高了工作频率 fsram的结 论。
以上对本发明实施例提供的一种同步 SRAM的时序处理方法和电路进行 以上实施例的说明只是用于帮助理解本发明的方法及其核心思想； 同时，对于 本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均 会有改变之处， 综上所述， 本说明书内容不应理解为对本发明的限制。

Claims

权 利 要 求
1、一种同步静态随机存储器 SRAM的时序处理方法，其特征在于， 包括： 将地址信号直接输入字线译码器进行逻辑译码；
将时钟输入时序产生器产生字线时钟信号，所述字线时钟信号经过字线控 制器产生字线门控信号；
在字线门控信号的控制下将字线译码器逻辑译码的结果即字线译码信号 输入字线脉宽产生器以产生字线信号， 完成字线开启的过程；
将字线信号输入到存储单元阵列，字线开启会将存储单元阵列保存的数据 输出到位线上， 经过位线选择， 输入到灵敏放大器；
时序产生器在字线信号产生预置的时间后，将产生灵敏放大器控制信号并 输入到灵敏放大器， 开启灵敏放大的过程；
灵敏放大器产生灵敏放大完成信号和数据输出信号，所述灵敏放大完成信 号用于输入给时序产生器以关断字线时钟信号， 从而控制字线门控信号的关 断， 最后控制字线信号的关断， 所述数据输出信号中包含有灵敏放大器将存储 单元阵列输入的经过位线选择的数据进行灵敏放大后输出的数据。
2、 根据权利要求 1所述的同步 SRAM的时序处理方法， 其特征在于， 所 述字线门控信号的产生和字线译码信号的产生是同时的。
3、 根据权利要求 1所述的同步 SRAM的时序处理方法， 其特征在于， 从 所述地址信号产生到所述字线译码器输出逻辑译码结果即字线译码信号的时 间为 所述时钟经过时序产生器产生字线时钟信号的时间为 t2, 所述字线时 钟信号经过字线控制器产生字线门控信号的时间为 t3,所述地址信号的建立时 间为 ts, 则 满足如下关系：
ts= t2 + t3 - ti;
从字线门控信号经过字线脉宽产生器产生字线信号的时间为 t4,从所述字 线信号产生到所述时序产生器产生灵敏放大器控制信号的时间为 t5,所述灵敏 放大器控制信号经过灵敏放大器产生灵敏放大完成信号的时间为 t6,所述灵敏 放大完成信号反馈到时序产生器并关断字线时钟信号的时间为 t7,从关断字线 时钟信号到控制字线门控信号关断的时间为 t8,所述地址信号经过所述字线译 码器逻辑译码所用的时间为 t9, 所述地址信号的保持时间为 th, 则 th满足如下 关系：
th= t2 + t3 + t4 + t5 + t6 + t7 + t8 - t9;
所述同步 SRAM的工作频率为 fsram, 则 fsram = l / tcyc, tcyc = ts + tac, 其 中， tac为从所述时钟产生到灵敏放大器产生数据输出信号的时间。
4、 一种同步静态随机存储器 SRAM的电路， 其特征在于， 包括： 字线译码器， 时序产生器， 字线控制器， 字线脉宽产生器， 存储单元阵列 和灵敏放大器， 其中，
字线译码器， 用于对输入的地址信号直接进行逻辑译码；
时序产生器， 用于在输入时钟时产生字线时钟信号和灵敏放大器控制信 号；
字线控制器， 用于在输入字线时钟信号时产生字线门控信号；
字线脉宽产生器，用于在输入字线门控信号和所述字线译码器逻辑译码的 结果即字线译码信号时产生字线信号；
存储单元阵列， 用于在输入字线信号后将保存的数据输出到位线上， 经过 位线选择， 输入到灵敏放大器；
灵敏放大器， 用于在输入灵敏放大器控制信号时，对存储单元阵列输入的 数据进行放大产生数据输出信号， 并向时序产生器反馈灵敏放大完成信号， 所 述灵敏放大完成信号用于输入给时序产生器以关断字线时钟信号，从而控制字 线门控信号的关断， 最后控制字线信号的关断， 所述数据输出信号中包含有灵 敏放大器将存储单元阵列输入的经过位线选择的数据进行灵敏放大后输出的 数据。
5、 根据权利要求 4所述的同步 SRAM的电路， 其特征在于， 所述字线门 控信号的产生和字线译码信号的产生是同时的。
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