WO2010123076A1 - 送信装置、受信装置、送受信システムおよび画像表示システム - Google Patents
送信装置、受信装置、送受信システムおよび画像表示システム Download PDFInfo
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- WO2010123076A1 WO2010123076A1 PCT/JP2010/057168 JP2010057168W WO2010123076A1 WO 2010123076 A1 WO2010123076 A1 WO 2010123076A1 JP 2010057168 W JP2010057168 W JP 2010057168W WO 2010123076 A1 WO2010123076 A1 WO 2010123076A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0091—Transmitter details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/66—Transforming electric information into light information
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
Definitions
- the present invention relates to a transmission device, a reception device, a transmission / reception system, and an image display system.
- An image display system such as a liquid crystal display system includes a transmission device, a reception device, and an image display unit, and transmits image data and a clock from the transmission device to which an image signal is input from the outside to the reception device. , And the image data obtained by the sampling is sent to the signal line, and the image is displayed on the image display unit based on the image data sent to the signal line.
- a transmission device or a device including the transmission device is referred to as a “timing controller”, and the above-described reception device or a device including the device is referred to as a “driver”.
- Patent Document 1 discloses an invention intended to solve the above skew problem.
- the skew information is stored in advance, and when transmitting data and a clock, a predetermined phase difference is given between the two based on the skew information. It is intended to reduce the skew between the data and the clock in the device.
- the present invention has been made to solve the above problems, and an object of the present invention is to provide a transmission device and a reception device that can easily sample data correctly with a clock in the reception device. Another object of the present invention is to provide a transmission / reception system including such a transmission device and a reception device, and an image display system including such a transmission device, a reception device, and an image display unit.
- a transmission device is a transmission device that transmits data and a clock to a reception device, and (1) a data transmission unit that transmits data to the reception device, and (2) a clock transmission that transmits a clock to the reception device. And (3) the phase difference between the data and the clock detected by the receiving device that has received the data transmitted by the data transmission unit and the clock transmitted by the clock transmission unit and the waveform distortion of the data, or A detection signal receiving unit that receives a detection signal representing either one from the receiving device, and (4) a data transmitted by the data transmission unit and a clock transmission unit based on the detection signal received by the detection signal reception unit.
- a control unit that controls either or both of the adjustment of the phase with the clock to be transmitted and the adjustment of the amplitude of the data transmitted by the data transmission unit Characterized in that it comprises a.
- a receiving apparatus is a receiving apparatus that receives data and a clock from a transmitting apparatus, and (1) a data receiving unit that receives data from the transmitting apparatus, and (2) a clock reception that receives a clock from the transmitting apparatus. And (3) a sampler unit that samples the data received by the data receiving unit using the clock received by the clock receiving unit and outputs the data obtained by this sampling, and (4) outputs from the sampler unit.
- a detection unit that performs one of the detections, and (5) a detection signal transmission unit that transmits a detection signal representing a result of detection by the detection unit to the transmission device. And features.
- a transmission / reception system comprises (1) a transmission device according to the present invention and a reception device according to the present invention, and (2) a data reception unit of the reception device is formed by a data transmission unit of the transmission device. Receives data to be transmitted, (3) the clock receiver of the receiver receives the clock transmitted by the clock transmitter of the transmitter, and (4) the detection signal receiver of the transmitter detects the receiver. The detection signal transmitted by the signal transmission unit is received.
- the transmission / reception system including the transmission device and the reception device according to the present invention operates as follows.
- the data transmitted from the data transmission unit of the transmission device is received by the data reception unit of the reception device.
- the clock transmitted from the clock transmission unit of the transmission device is received by the clock reception unit of the reception device.
- the sampler unit of the receiving device the data received by the data receiving unit is sampled by the clock received by the clock receiving unit, and the data obtained by this sampling is output.
- the detection unit of the receiving device receives the phase difference between the data received by the data receiving unit and the clock received by the clock receiving unit, and the data receiving unit. Either or both of the waveform distortions of the detected data are detected.
- a detection signal representing a result of detection by the detection unit is transmitted to the transmission device by the detection signal transmission unit of the reception device.
- the detection signal transmitted from the reception device to the transmission device is received by the detection signal reception unit of the transmission device.
- the control unit adjusts the phase between the data transmitted by the data transmission unit and the clock transmitted by the clock transmission unit based on the detection signal received by the detection signal reception unit, and the data Control of both or either of the adjustment of the amplitude of the data transmitted by the transmission unit is performed. In this way, the phase or amplitude is adjusted by the control unit in the transmission device, so that it is easy to correctly sample the data with the clock in the reception device.
- the control unit causes the data transmission unit to transmit detection signal transmission instruction data for instructing the reception device to transmit a detection signal to the reception device.
- the data receiving unit receives detection signal transmission instruction data instructing to transmit the detection signal from the transmitting device, and (2) the detection signal transmitting unit is detected by the data receiving unit.
- the transmission / reception system includes (1) these transmission devices and reception devices, and (2) data reception unit of the reception device transmits data and detection signal transmitted by the data transmission unit of the transmission device.
- the clock receiving unit of the receiving device receives a clock transmitted by the clock transmitting unit of the transmitting device, and (4) the detection signal receiving unit of the transmitting device transmits the detection signal of the receiving device.
- the detection signal transmitted by the unit is preferably received.
- detection signal transmission instruction data for instructing the reception device to transmit a detection signal is transmitted from the data transmission unit under the control of the control unit.
- the detection signal transmission instruction data is received by the data reception unit, and in response to this, the detection signal transmission unit transmits the detection signal to the transmission device.
- the transmission device includes a plurality of data transmission units, and the plurality of data transmission units and the plurality of reception devices included in the transmission device correspond one-to-one. It is preferable to transmit the detection signal transmission instruction data to each of the plurality of receiving apparatuses at different timings and transmit the detection signal from each of the plurality of receiving apparatuses to the transmitting apparatus at different timings.
- the transmission apparatus it is preferable to include a plurality of sets of data transmission units and clock transmission units.
- the transmission / reception system according to the present invention includes (1) a transmission device and a plurality of reception devices, and (2) a plurality of data transmission units and a plurality of reception devices included in the transmission device have a one-to-one correspondence. (3) The data receiving unit of each of the plurality of receiving devices receives data transmitted by the corresponding data transmitting unit included in the transmitting device, and (4) The clock receiving unit of each of the plurality of receiving devices is Receive the clock transmitted by the corresponding clock transmission unit included in the transmission device, and (5) the detection signal reception unit of the transmission device receives the detection signal transmitted by the detection signal transmission unit of each of the plurality of reception devices. It is preferable to do this.
- the transmission apparatus it is preferable to include a plurality of data transmission units and one clock transmission unit.
- the transmission / reception system according to the present invention includes (1) a transmission device and a plurality of reception devices, and (2) a plurality of data transmission units and a plurality of reception devices included in the transmission device have a one-to-one correspondence.
- the data receiving unit of each of the plurality of receiving devices receives data transmitted by the corresponding data transmitting unit included in the transmitting device, and (4)
- the clock receiving unit of each of the plurality of receiving devices is It is preferable that the clock transmitted by the clock transmission unit of the transmission device is received, and (5) the detection signal reception unit of the transmission device receives the detection signal transmitted by the detection signal transmission unit of each of the plurality of reception devices. It is.
- the control unit when the control unit controls the adjustment of the amplitude of the data transmitted by the data transmission unit, the control unit selectively adjusts the amplitude of the bit data after the level transition of the data. Is preferred.
- the sampler unit samples and outputs the data at the time of bit transition among the data received by the data receiving unit
- the detection unit samples the bits sampled and output by the sampler unit It is preferable to detect the phase difference and / or the waveform distortion based on the data at the time of transition.
- the detection signal reception unit of the transmission device receives the detection signal transmitted by the detection signal transmission unit of each of the plurality of reception devices via a common signal line.
- An image display system includes: the above-described transmission / reception system according to the present invention; and an image display unit that displays an image based on data received by each of a plurality of reception devices included in the transmission / reception system.
- FIG. 1 is a diagram showing a schematic configuration of an image display system 1 according to the present embodiment.
- FIG. 2 is a diagram illustrating a schematic configuration of a transmission / reception system including the transmission device 10 and the N reception devices 20 1 to 20 N according to the present embodiment.
- FIG. 3 is a diagram illustrating configurations of the transmission device 10 and the reception device 20 n according to the present embodiment.
- FIG. 4 is a diagram illustrating a configuration of a first configuration example of the sampler unit 23 of the reception device 20 n according to the present embodiment.
- FIG. 5 is a diagram for explaining the operation of the first configuration example of the sampler unit 23 of the receiving device 20 n according to the present embodiment.
- FIG. 1 is a diagram showing a schematic configuration of an image display system 1 according to the present embodiment.
- FIG. 2 is a diagram illustrating a schematic configuration of a transmission / reception system including the transmission device 10 and the N reception devices 20 1 to 20 N according to the present embodiment.
- FIG. 3 is a diagram
- FIG. 6 is a diagram illustrating a configuration of a second configuration example of the sampler unit 23 of the reception device 20 n according to the present embodiment.
- FIG. 7 is a diagram for explaining the operation of the second configuration example of the sampler unit 23 of the receiving device 20 n according to the present embodiment.
- FIG. 8 is a diagram illustrating a configuration of a first configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 9 is a diagram for explaining the operation of the first configuration example of the detection unit 25 of the receiving device 20 n according to the present embodiment.
- FIG. 10 is a chart for explaining the operation of the first configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 10 is a chart for explaining the operation of the first configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 11 is a flowchart for explaining the operation of the first configuration example of the detection unit 25 of the receiving device 20 n according to the present embodiment.
- FIG. 12 is a diagram illustrating a configuration of a second configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 13 is a diagram illustrating the operation of the second configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 14 is a chart for explaining the operation of the second configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 15 is a flowchart for explaining the operation of the second configuration example of the detection unit 25 of the reception device 20 n according to this embodiment.
- FIG. 12 is a diagram illustrating a configuration of a second configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 13 is a diagram illustrating the operation of the second configuration example of the detection unit 25 of the reception device 20 n according to the
- FIG. 16 is a diagram illustrating detection signal transmission instruction data and detection signal transmission / reception timing between the transmission device 10 and the reception device 20 n according to the present embodiment.
- FIG. 17 is a flowchart illustrating a first adjustment example of the phase and amplitude of data by the control unit 15 in the transmission device 10 according to the present embodiment.
- FIG. 18 is a flowchart illustrating a second adjustment example of the phase and amplitude of data by the control unit 15 in the transmission device 10 according to the present embodiment.
- FIG. 19 is a diagram illustrating a configuration of the phase shift unit 113 of the data transmission unit 11 in the transmission device 10 according to the present embodiment.
- FIG. 20 is a diagram illustrating the operation of the phase shift unit 113 of the data transmission unit 11 in the transmission device 10 according to the present embodiment.
- FIG. 21 is a waveform diagram illustrating amplitude adjustment by the buffer 111 of the data transmission unit 11 in the transmission device 10 according to the present embodiment.
- FIG. 22 is a diagram illustrating a schematic
- FIG. 1 is a diagram showing a schematic configuration of an image display system 1 according to the present embodiment.
- the image display system 1 shown in this figure includes a transmitting device 10, N receiving devices 20 1 to 20 N, and an image display unit 30.
- N is an integer of 2 or more
- n appearing below is an integer of 1 or more and N or less.
- the drive unit and signal lines for vertical scanning of an image in the image display unit 30 are not shown.
- the transmitting device 10 receives an image signal from the outside and transmits image data and a clock to each of the N receiving devices 20 1 to 20 N.
- Each receiving device 20 n receives the image data and clock transmitted from the transmitting device 10, samples the image data by the clock, and uses the image data obtained by this sampling as the signal line 31 of the image display unit 30. and it sends it to the n.
- the image display unit 30 is a liquid crystal panel, for example, and displays an image based on the image data supplied to the signal line 31 n by each receiving device 20 n .
- the signal line 31n may be one or more.
- FIG. 2 is a diagram illustrating a schematic configuration of a transmission / reception system including the transmission device 10 and the N reception devices 20 1 to 20 N according to the present embodiment.
- the transmission apparatus 10 includes a detection signal reception unit 14, a control unit 15, a clock generation unit 16, and N transmission units 19 1 to 19 N.
- Each transmission unit 19 n includes a set of data transmission unit and clock transmission unit.
- the N transmission units 19 1 to 19 N have a common configuration.
- the N receiving apparatuses 20 1 to 20 N have a common configuration.
- the transmission unit 19 n and the reception device 20 n have a one-to-one correspondence.
- the transmission unit 19 n of the transmission device 10 transmits data and a clock to the reception device 20 n .
- the receiving device 20 n receives the data and clock transmitted from the transmitting unit 19 n , samples the data using this clock, and outputs the data obtained by this sampling.
- the receiving device 20 n detects the phase difference between the received data and the clock and / or the waveform distortion of the data, and sends a detection signal indicating the detection result to the transmitting device 10. .
- the detection signal receiver 14 of the transmission device 10 receives the detection signal transmitted from each reception device 20 n .
- Control unit 15 based on the received detection signal by the detection signal receiving unit 14, both or either of adjustment and the adjustment of the amplitude of the data of the phase between the data and the clock transmitted by the transmission section 19 n One control is performed.
- the clock generation unit 16 generates a reference clock for instructing a reference timing when each transmission unit 19 n of the transmission device 10 transmits data and a clock, and gives this clock to each transmission unit 19 n .
- the signal line may be physically a single line, or may be a pair of lines that transmit differential data, such as low-voltage differential signaling (LVDS). Good.
- LVDS low-voltage differential signaling
- FIG. 3 is a diagram illustrating configurations of the transmission device 10 and the reception device 20 n according to the present embodiment. This figure shows the configuration of the n-th transmission unit 19 n among the N transmission units 19 1 to 19 N included in the transmission device 10 and the configuration of the reception device 20 n corresponding to the transmission unit 19 n. It is shown in detail.
- the transmission unit 19 n includes a data transmission unit 11, a clock transmission unit 12, and an encoder unit 13.
- the data transmission unit 11 transmits data to the reception device 20 n and includes a buffer 111, a flip-flop 112, and a phase shift unit 113.
- the phase shift unit 113 receives the reference clock output from the clock generation unit 16, changes the phase of the reference clock by the phase shift amount instructed by the control unit 15, and outputs it to the flip-flop 112.
- the flip-flop 112 latches the data output from the encoder unit 13 at a timing indicated by the clock output from the phase shift unit 113, and outputs the latched data to the buffer 111.
- the buffer 111 transmits the data output from the flip-flop 112 to the receiving device 20 n with the amplitude instructed by the control unit 15.
- the clock transmission unit 12 transmits a clock to the reception device 20 n and includes a buffer 121 and a flip-flop 122.
- the flip-flop 122 latches the clock output from the encoder unit 13 at a timing indicated by the reference clock output from the clock generation unit 16, and outputs the latched data to the buffer 121.
- the buffer 121 transmits the data output from the flip-flop 112 to the receiving device 20 n .
- the detection signal receiving unit 14 receives the detection signal sent from the receiving device 20n .
- the detection signal received by the detection signal receiving unit 14 is between the data and the clock detected by the receiving device 20 n that has received the data transmitted by the data transmitting unit 11 and the clock transmitted by the clock transmitting unit 12.
- the phase difference and / or waveform distortion of data are represented.
- the control unit 15 is transmitted by the data transmission unit 11 by controlling the phase shift amount of the reference clock in the phase shift unit 113 of the data transmission unit 11 based on the detection signal received by the detection signal reception unit 14. The phase between the data and the clock transmitted by the clock transmission unit 12 is adjusted. In addition, the control unit 15 adjusts the amplitude of data transmitted by the data transmission unit 11 by controlling the output amplitude in the buffer 111 of the data transmission unit 11. Further, the control unit 15, a detection signal transmission instruction data instructing to transmit a detection signal to the receiving device 20 n, and to output from the encoder unit 13, is transmitted by the data transmitter 11 to the receiver 20 n Is preferred.
- the receiving device 20 n includes a data receiving unit 21, a clock receiving unit 22, a sampler unit 23, a decoder unit 24, a detecting unit 25, and a detection signal transmitting unit 26.
- the data reception unit 21 receives data transmitted from the data transmission unit 11 of the transmission device 10.
- the clock reception unit 22 receives the clock transmitted from the clock transmission unit 12 of the transmission device 10.
- the sampler unit 23 samples the data received by the data receiving unit 21 based on the clock received by the clock receiving unit 22, and outputs the data obtained by this sampling to the decoder unit 24 and the detecting unit 25.
- the decoder unit 24 sends the data output from the sampler unit 23 to the signal line 31 n .
- the detection unit 25 Based on the data output from the sampler unit 23, the detection unit 25 detects the phase difference between the data received by the data reception unit 21 and the clock received by the clock reception unit 22, and the data reception unit 21. Either or both of the waveform distortions of the received data are detected.
- the detection signal transmission unit 26 transmits a detection signal representing the detection result by the detection unit 25 to the detection signal reception unit 14 of the transmission device 10.
- the decoder unit 24 receives the data reception unit 22 and performs sampling by the sampler unit 23.
- the detected signal is determined to be detection signal transmission instruction data, and the detection signal transmission unit 26 transmits the detection signal in response to the determination in the decoder unit 24.
- the detection signal may be based on a detection result started after determining the detection signal transmission instruction data, or may be based on a result detected in advance.
- the transmission / reception system configured as described above operates as follows. Data transmitted from the data transmitting unit 11 of the transmitter 10 is received by the data receiving unit 21 of the reception apparatus 20 n. Clock transmitted from the clock transmission section 12 of the transmitter 10 is received by the clock receiver 22 of the reception apparatus 20 n. In the sampler unit 23 of the receiving device 20 n , the data received by the data receiving unit 21 is sampled by the clock received by the clock receiving unit 22, and the data obtained by this sampling is output. This data is sent to the signal line 31 n through the decoder unit 24 and used for image display in the image display unit 30.
- the detection unit 25 of the reception device 20 n based on the data output from the sampler unit 23, the phase difference between the data received by the data reception unit 21 and the clock received by the clock reception unit 22, and Either or both of the waveform distortions of the data received by the data receiving unit 21 are detected.
- the detection signal transmitting unit 26 of the receiving device 20 n transmits a detection signal representing the detection result by the detecting unit 25 to the transmitting device 10.
- the detection signal transmitted from the receiving device 20 n to the transmitting device 10 is received by the detection signal receiving unit 14 of the transmitting device 10.
- the phase between the data transmitted by the data transmission unit 11 and the clock transmitted by the clock transmission unit 12 is controlled by the control unit 15 based on the detection signal received by the detection signal reception unit 14.
- the adjustment and / or the adjustment of the amplitude of the data transmitted by the data transmission unit 11 are controlled.
- the control unit 15 in the transmitter 10 By the phase or amplitude is adjusted by the control unit 15 in the transmitter 10 this way, it becomes easy to sample the data correctly by 20 n Oite clocks to the receiver.
- the reception device 20 n receives the detection signal transmission instruction data by the data reception unit 21.
- the detection signal transmission unit 25 transmits a detection signal to the transmission device 10.
- the phase-shifted clock is input to the data transmission unit clock.
- the data transmission unit 11 is input with the phase-shifted clock.
- a clock shifted in phase may be input to the clock transmission unit 12.
- the clock generator 16 Since the purpose is to change the phase of the data and the clock, the clock generator 16 generates a clock of a plurality of phases, and an appropriate clock is generated from the clock of the plurality of phases in a portion corresponding to the phase shift circuit. It is also possible to select.
- FIG. 4 is a diagram illustrating a configuration of a first configuration example of the sampler unit 23 of the reception device 20 n according to the present embodiment.
- FIG. 5 is a diagram for explaining the operation of the first configuration example of the sampler unit 23 of the receiving device 20 n according to the present embodiment.
- the sampler unit 23 of the first configuration example includes a flip-flop 231 and a flip-flop 232.
- the frequency of the clock transmitted from the clock transmission unit 12 of the transmission device 10 and received by the clock reception unit 22 of the reception device 20 n is transmitted from the data transmission unit 11 of the transmission device 10.
- the bit rate of the data received by the data receiving unit 21 of the receiving device 20n becomes the same. That is, for example, if the bit rate is 10 Gbps, the clock frequency is 10 GHz.
- the flip-flop 231 latches the data output from the data receiving unit 21 at the timing indicated by the rising edge of the clock output from the clock receiving unit 22 and latches the data.
- Data D is output to the decoder unit 24 and the detection unit 25.
- the data D represents the value of each bit of data received by the data transmitting unit 11 receiving apparatus is transmitted from the 20 n of the data receiving unit 21 of the transmitting apparatus 10.
- the flip-flop 232 latches the data output from the data receiving unit 21 at a timing indicated by the falling edge of the clock output from the clock receiving unit 22, and outputs the latched data XD to the detecting unit 25.
- the data XD represents the value at the time of bit transitions of the data received by the receiving device 20 n of the data receiving unit 21 from the data transmission unit 11 is transmitted in the transmitting apparatus 10.
- FIG. 6 is a diagram illustrating a configuration of a second configuration example of the sampler unit 23 of the reception device 20 n according to the present embodiment.
- FIG. 7 is a diagram for explaining the operation of the second configuration example of the sampler unit 23 of the receiving device 20 n according to the present embodiment.
- the sampler unit 23 of the second configuration example includes flip-flops 231 to 234 and a two-phase clock generation unit 235.
- the frequency of the clock transmitted from the clock transmission unit 12 of the transmission device 10 and received by the clock reception unit 22 of the reception device 20 n is transmitted from the data transmission unit 11 of the transmission device 10. is the same as the bit rate of data received by the data receiving unit 21 of the reception apparatus 20 n is.
- the two-phase clock generation unit 235 receives the clock output from the clock reception unit 22 and generates the two-phase clocks CLK1 and CLK2 based on this clock.
- the flip-flop 231 latches the data output from the data receiving unit 21 at the timing indicated by the rising edge of the first clock CLK1 output from the two-phase clock generation unit 235, and the latched data D is the decoder unit. 24 and the detection unit 25.
- the flip-flop 232 latches the data output from the data reception unit 21 at a timing indicated by the falling edge of the first clock CLK1 output from the two-phase clock generation unit 235, and the latched data D is decoded. Output to the unit 24 and the detection unit 25.
- These data D represents the value of each bit of data received by the data transmitting unit 11 receiving apparatus is transmitted from the 20 n of the data receiving unit 21 of the transmitting apparatus 10.
- the flip-flop 233 latches the data output from the data reception unit 21 at a timing indicated by the rising edge of the second clock CLK2 output from the two-phase clock generation unit 235, and the latched data D is detected by the detection unit.
- the flip-flop 234 latches the data output from the data receiver 21 at the timing indicated by the falling edge of the second clock CLK2 output from the two-phase clock generator 235, and detects the latched data D To the unit 25.
- These data XD represents the value at the time of bit transitions of the data received by the receiving device 20 n of the data receiving unit 21 from the data transmission unit 11 is transmitted in the transmitting apparatus 10.
- the sampler section 23, the data received by the data transmission unit 11 reception unit 20 n of the data receiving section 21 is transmitted from the transmitting apparatus 10
- Data D of each bit and data XD at the time of bit transition of the data are output.
- the decoder unit 24 receives the data D output from the sampler unit 23.
- the detection unit 25 receives the data D and the data XD output from the sampler unit 23, and based on these data, the data received by the data reception unit 21 and the clock received by the clock reception unit 22 And / or the waveform distortion of the data received by the data receiving unit 21 is detected.
- FIG. 8 is a diagram illustrating a configuration of a first configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 9 is a diagram for explaining the operation of the first configuration example of the detection unit 25 of the receiving device 20 n according to the present embodiment.
- FIG. 10 is a chart for explaining the operation of the first configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 11 is a flowchart for explaining the operation of the first configuration example of the detection unit 25 of the reception device 20 n according to this embodiment.
- the detection unit 25 of the first configuration example includes a phase difference between the data received by the data reception unit 21 and the clock received by the clock reception unit 22 based on the data D and XD output from the sampler unit 23. Detection is performed.
- the detection unit 25 includes flip-flops 251, 252, 254, 255, a phase detection unit 256, and a phase determination unit 257.
- the flip-flops 251 and 252 are cascaded to form a shift register.
- the first stage flip-flop 251 receives data D output from the sampler unit 23.
- the flip-flops 254 and 255 are cascaded to constitute a shift register.
- the first flip-flop 254 receives the data XD output from the sampler unit 23.
- the phase detector 256 inputs the data latched by the flip-flops 251, 252, and 255, respectively. That is, as shown in FIG. 9, the phase detection unit 256 inputs a value D1 of a certain bit, a value D2 of the next bit, and a value XD at the time of transition of these two bits D1 and D2. . Further, the phase detection unit 256 inputs the data D1, XD, D2 at every clock cycle.
- the phase detection unit 256 receives, based on the input data D1, XD, D2, whether or not there is a data transition between these two bits for each clock cycle (Edge). Whether the phase of the received clock is early (Early), whether the phase of the received clock is late (Late), and whether the frequency of the received clock and the bit rate of the data are unlocked (Unlock) is detected.
- the phase detection unit 256 sets the variable Edge to the value 1 when there is a data transition between the two bits, and sets the variable Edge to the value 0 otherwise.
- the variable Early is set to the value 1 when the clock phase is fast, and the variable Early is set to the value 0 otherwise.
- the variable Late is set to the value 1 when the clock phase is late, and the variable Late is set to the value 0 otherwise.
- the variable Unlock is set to the value 1 when the state is unlocked, and the variable Unlock is set to the value 0 otherwise.
- the phase detection unit 256 gives each value of these variables Edge, Early, Late, and Unlock to the phase determination unit 257.
- the phase determination unit 257 determines whether the data received by the data reception unit 21 and the clock received by the clock reception unit 22 are based on the values of the variables Edge, Early, Late, and Unlock received from the phase detection unit 256. The phase difference is detected. Specifically, as shown in FIG. 11, the phase determination unit 257 performs the following processing using variables EdgeCnt, EarlyCnt, LateCnt, and UnlockCnt, and constants EdgeCntThreshold, EarlyCntThreshold, LateCntThreshold, and UnlockCntThreshold.
- step S11 the values of the variables EdgeCnt, EarlyCnt, LateCnt, and UnlockCnt are initialized in the phase determination unit 257, and then, in step S12, the value of the variable Edge is cumulatively added to the variable EdgeCnt for each clock cycle.
- the value of the variable Early is cumulatively added to the variable EarlyCnt
- the value of the variable Late is cumulatively added to the variable LateCnt
- the value of the variable Unlock is cumulatively added to the variable UnlockCnt.
- step S13 it is determined whether or not the value of the variable UnlockCnt is equal to or greater than the constant UnlockCntThreshold. If so, it is determined that the clock frequency and the data bit rate are in an unlocked state (Unlock). .
- step S14 If it is determined in step S13 that the value of the variable UnlockCnt is less than the constant UnlockCntThreshold, it is determined in step S14 whether the value of the variable EdgeCnt is greater than or equal to the constant EdgeCntThreshold. If it is determined in step S14 that the value of the variable EdgeCnt is less than the constant EdgeCntThreshold, the process returns to step S12.
- step S14 If it is determined in step S14 that the value of the variable EdgeCnt is greater than or equal to the constant EdgeCntThreshold, it is determined in step S15 whether or not the value of the variable LateCnt is greater than or equal to the constant LateCntThreshold. Is determined to be late (Late). In step S16, it is determined whether or not the value of the variable EarlyCnt is equal to or greater than the constant EarlyCntThreshold. If so, it is determined that the clock phase is fast (Early). Otherwise, it is determined that the phase difference is within the allowable range (Lock).
- the phase determination unit 257 repeats such determination and gives a detection signal indicating the determination result (Late, Early, Lock, Unlock) to the detection signal transmission unit 26.
- the detection signal transmission unit 26 transmits this detection signal to the detection signal reception unit 14 of the transmission device 10.
- FIG. 12 is a diagram illustrating a configuration of a second configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 13 is a diagram illustrating the operation of the second configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 14 is a chart for explaining the operation of the second configuration example of the detection unit 25 of the reception device 20 n according to the present embodiment.
- FIG. 15 is a flowchart for explaining the operation of the second configuration example of the detection unit 25 of the reception device 20 n according to this embodiment.
- the detection unit 25 of the second configuration example detects the waveform distortion of the data received by the data reception unit 21 based on the data D and XD output from the sampler unit 23.
- the detection unit 25 includes flip-flops 251 to 255, a waveform distortion detection unit 258 and a waveform distortion determination unit 259.
- the flip-flops 251 to 253 are cascaded to form a shift register.
- the first stage flip-flop 251 receives data D output from the sampler unit 23.
- the flip-flops 254 and 255 are cascaded to constitute a shift register.
- the first flip-flop 254 receives the data XD output from the sampler unit 23.
- the waveform distortion detection unit 258 inputs data latched by the flip-flops 251, 252, 253, and 255, respectively. That is, as shown in FIG. 13, the waveform distortion detection unit 258 includes a value D0 of a certain bit, a value D1 of the next bit, a value D2 of the next bit, and the two bits D1 and D2. The value XD at the time of transition is input. In addition, the waveform distortion detection unit 258 inputs the data D0, D1, XD, D2 for each clock cycle.
- the waveform distortion detector 258 determines whether or not there is a data transition between the two bits D1 and D2 for each clock cycle based on the input data D0, D1, XD, and D2. (Edge) Whether the waveform distortion of the data is large because the amplitude of the high frequency component of the received data is small (Underequalize), or whether the waveform distortion of the data is large because the amplitude of the high frequency component of the received data is large (Overequalize) and whether the received clock frequency and data bit rate are in an unlocked state (Unlock) are detected.
- the waveform distortion detection unit 258 sets the variable Edge to the value 1 when there is a data transition between the two bits D1 and D2, and sets the variable Edge to the value 0 otherwise.
- the variable Underequalize is set to the value 1 when the waveform distortion of the data is large because the amplitude of the high frequency component of the received data is small, and the variable Underequalize is set to the value 0 otherwise.
- the variable Overequalize is set to the value 1 when the waveform distortion of the data is large because the amplitude of the high frequency component of the received data is large, and the variable Overequalize is set to the value 0 otherwise.
- the variable Unlock is set to the value 1 when the state is unlocked, and the variable Unlock is set to the value 0 otherwise.
- the waveform distortion detection unit 258 gives the values of these variables Edge, Underequalize, Overequalize, and Unlock to the waveform distortion determination unit 259.
- the waveform distortion determination unit 259 detects the waveform distortion of the data received by the data reception unit 21 based on the values of the variables Edge, Underequalize, Overequalize, and Unlock received from the waveform distortion detection unit 258. Specifically, as shown in FIG. 15, the waveform distortion determination unit 259 performs the following processing using variables EdgeCnt, OverequalizeCnt and UnderequalizeCnt, and constants EdgeCntThreshold, OverequalizeCntThreshold, and UnderCntThreshold.
- step S21 the waveform distortion determination unit 259 first initializes the values of the variables EdgeCnt, OverequalizeCnt, and UnderequalizeCnt, and then, in step S22, the value of the variable Edge is cumulatively added to the variable EdgeCnt for each clock cycle.
- the value of variable Overequalize is cumulatively added to variable OverequalizeCnt
- the value of variable Underequalize is cumulatively added to variable UnderequalizeCnt.
- step S23 it is determined whether or not the value of the variable EdgeCnt is greater than or equal to the constant EdgeCntThreshold. If it is determined in step S23 that the value of the variable EdgeCnt is less than the constant EdgeCntThreshold, the process returns to step S22.
- step S24 it is determined in step S24 whether or not the value of the variable OverequalizeCnt is greater than or equal to the constant OverequalizeCntThreshold. It is determined that the waveform distortion of the data is large because the amplitude of the high-frequency component of the data is large (Overequalize).
- step S25 it is determined whether or not the value of the variable UnderequalizeCnt is equal to or greater than the constant UnderequalizeCntThreshold. If so, it is determined that the waveform distortion of the data is large because the amplitude of the high frequency component of the received data is small. (Underequalize) Otherwise, it is determined that the amplitude of the high frequency component of the received data is within the allowable range (Justequalize).
- the waveform distortion determination unit 259 repeats such determination, and provides the detection signal transmission unit 26 with a detection signal indicating the determination result (Overequalize, Underequalize, Justequalize).
- the detection signal transmission unit 26 transmits this detection signal to the detection signal reception unit 14 of the transmission device 10.
- the detection unit 25 includes flip-flops 251 to 255, a phase detection unit 256, a phase determination unit 257, a waveform distortion detection unit 258, and a waveform distortion determination unit 259, and receives data and clock received by the data reception unit 21. Both the detection of the phase difference from the clock received by the unit 22 and the detection of the waveform distortion of the data received by the data receiving unit 21 may be performed.
- FIG. 16 is a diagram illustrating detection signal transmission instruction data and detection signal transmission / reception timing between the transmission device 10 and the reception device 20 n according to the present embodiment.
- the data transmission unit 11 included in the transmission unit 19 n of the transmission device 10 receives normal data (indicated as “normal” in the drawing) used for image display in the image display unit 30 under the control of the control unit 15, and receives calibration data to be used for the detection of the phase difference or the waveform distortion in the device 20 n (denoted in the figure as "calibration"), and the transmission of the detection and the detection signal of the phase difference or waveform distortion to the receiving device 20 n Each data of the detection signal transmission instruction data to instruct is transmitted to the receiving device 20 n at a predetermined timing.
- the transmission device 10 transmits detection signal transmission instruction data to the reception device 20 n in a period (for example, a blanking period) different from the period in which normal data is transmitted, and then transmits calibration data.
- the receiving device 20 n that has received the detection signal transmission instruction data subsequently detects a phase difference or waveform distortion by using the received calibration data, and detects a detection signal representing the detection result to the transmitting device 10. Send.
- Such transmission / reception is sequentially performed for the N receiving apparatuses 20 1 to 20 N.
- the data used when detecting the phase difference or waveform distortion in the detection unit 25 of the reception device 20 n may be normal data used for image display in the image display unit 30.
- the reception device 20 n when the reception device 20 n receives the detection signal transmission instruction data, the reception device 20 n can transmit a detection signal representing the phase difference or waveform distortion result detected by the detection unit 25 until then to the transmission device 10.
- the control unit 15 of the transmission device 10 uses the value of the detection signal transmitted from the detection signal transmission unit 26 of the reception device 20 n and received by the detection signal reception unit 14 to use the data transmission unit included in the transmission unit 19 n. 11 buffers 111 and the phase shift unit 113 are controlled.
- the detection signal is representative of a variable Late obtained by the detection of the phase difference and the waveform distortion detection unit 25 of the reception apparatus 20 n, Early, Lock, Unlock , Overequalize, Underequalize, the values of Justequalize.
- FIG. 17 is a flowchart illustrating a first adjustment example of the phase and amplitude of data by the control unit 15 in the transmission device 10 according to the present embodiment.
- the control unit 15 determines that when both the variable Lock and the variable Justequalize are significant values, that is, the phase difference between the data received by the receiving device 20 n and the clock is within an allowable range. If the amplitude of the high frequency component of the data is within the allowable range, no adjustment is made to the buffer 111 and the phase shift unit 113 of the data transmission unit 11 included in the transmission unit 19 n corresponding to the reception device 20 n. Without performing the process for the next receiving device 20 n + 1 .
- the control unit 15 performs the following control when any of the variable Lock and the variable Justequalize is not a significant value.
- the control unit 15, the time variable Late is a significant value (when the clock phase is late with respect to the data received by the receiving device 20 n), the phase shift of the data transmission unit 11 included in the transmission section 19 n
- the clock phase is advanced by a predetermined amount with respect to the data.
- the control unit 15, the time variable Early is a significant value (when the clock phase is early relative received by the receiving device 20 n data), the phase shift of the data transmission unit 11 included in the transmission section 19 n
- the clock phase is delayed by a predetermined amount with respect to the data.
- the control unit 15 includes the data transmission unit included in the transmission unit 19 n. No adjustment is performed on the eleven phase shift units 113.
- the control unit 15 is included in the transmission unit 19 n when the variable Unlock is a significant value (when the clock frequency received by the reception device 20 n and the data bit rate are in the unlocked state). By adjusting the phase shift unit 113 of the data transmission unit 11, the phase of the clock is largely changed.
- control unit 15 When the variable Unlock is not a significant value, the control unit 15 further performs the following control according to each value of the variables Overequalize, Underequalize, and Justequalize.
- the control unit 15 is included in the transmission unit 19 n .
- the buffer 111 of the data transmission unit 11 By adjusting the buffer 111 of the data transmission unit 11 to be generated, the amplitude of the bit data after the data level transition is increased by a predetermined amount.
- the control unit 15 is included in the transmission unit 19 n .
- the amplitude of the bit data after the data level transition is reduced by a predetermined amount.
- the control unit 15 includes the data transmission unit 11 included in the transmission unit 19 n. No adjustment is made to the buffer 111.
- Control unit 15 the above adjustment process is completed, transmits a detection signal transmission instruction data to the reception apparatus 20 n, receives a detection signal from the reception apparatus 20 n, again performing the above-described adjustment process. Then, the control unit 15, when both the variable Lock and variable Justequalize is a significant value, and ends the processing for the receiving device 20 n, performs processing for the next reception apparatus 20 n + 1.
- FIG. 18 is a flowchart illustrating a second adjustment example of the phase and amplitude of data by the control unit 15 in the transmission device 10 according to the present embodiment.
- the control unit 15 causes the receiving device to wait until the variable Lock becomes a significant value (the phase difference between the data received by the receiving device 20 n and the clock is within an allowable range).
- the control unit 15 causes the receiving device to wait until the variable Lock becomes a significant value (the phase difference between the data received by the receiving device 20 n and the clock is within an allowable range).
- the control unit 15 receives the reception device 20 until the variable Justequalize becomes a significant value (the amplitude of the high-frequency component of the data received by the reception device 20 n falls within the allowable range).
- the transmission of the detection signal transmission instruction data to n , the reception of the detection signal from the receiving device 20 n , and the adjustment to the buffer 111 that are performed depending on which of the variables Overequalize and Underequalize are significant values are repeated.
- Adjustment to the phase shift unit 113 or the buffer 111 in the second adjustment example is the same as in the first adjustment example. Then, the control unit 15, when both the variable Lock and variable Justequalize is a significant value, and ends the processing for the receiving device 20 n, performs processing for the next reception apparatus 20 n + 1.
- FIG. 19 is a diagram illustrating a configuration of the phase shift unit 113 of the data transmission unit 11 in the transmission device 10 according to the present embodiment.
- FIG. 20 is a diagram illustrating the operation of the phase shift unit 113 of the data transmission unit 11 in the transmission device 10 according to the present embodiment.
- the clock generation unit 16 is a PLL frequency synthesizer, for example, and outputs M-phase clocks Clock_1 to Clock_M whose phases are different by a predetermined amount.
- the phase shift unit 113 receives the M-phase clocks Clock_1 to Clock_M output from the clock generation unit 16 and also receives the selection instruction signal Select output from the control unit 15 to input the M-phase clock Clock_1.
- the clock Clock indicated by the selection instruction signal Select among the Clock_M is selectively output to the flip-flop 112. As a result, the phase difference between the data transmitted from the transmitting device 10 and the clock is adjusted, and the phase difference between the data received by the receiving device 20 n and the clock is within the allowable range.
- FIG. 21 is a waveform diagram illustrating amplitude adjustment by the buffer 111 of the data transmission unit 11 in the transmission device 10 according to the present embodiment.
- the buffer 111 sets the amplitude (PreEmphasisLevel) of the bit data after the level transition of the data to be transmitted to the amplitude of the bit data at the same level as the previous bit according to an instruction from the control unit 15. Increase to (Normal Level). Further, the buffer 111 adjusts the amplitude (PreEmphasisLevel) of the bit data after the level transition of the data to be transmitted according to the instruction from the control unit 15.
- the amplitude of the high frequency component of the data received by the receiving device 20 n is within the allowable range, the distortion of the data inhibit Is done.
- FIG. 22 is a diagram illustrating a schematic configuration of a transmission apparatus 10A according to a modification.
- the transmission apparatus 10 according to the embodiment described above includes N sets (N is an integer of 2 or more) of data transmission units 11 and a clock transmission unit 12, and the phase of data with respect to the clock is set in each set. It was something to be adjusted. Therefore, these clock transmission units can be made common. Therefore, the transmission apparatus 10A according to the modification shown in FIG. 22 includes N data transmission units 11 1 to 11 N and one clock transmission unit 12. In this figure, the encoder unit is not shown.
- Each of the N data transmission units 11 1 to 11 N has the same configuration as that of the data transmission unit 11 in the embodiment described above.
- the data transmission unit 11 n and the reception device 20 n have a one-to-one correspondence.
- the clock transmission unit 12 has the same configuration as the clock transmission unit 12 in the embodiment described above.
- the control unit 15 controls the phase shift amount of the reference clock in the phase shift unit 113 of the data transmission unit 11 n based on the detection signal transmitted from the reception device 20 n and received by the detection signal reception unit 14. The phase between the data transmitted by the data transmitter 11 n and the clock transmitted by the clock transmitter 12 is adjusted.
- the control unit 15, by controlling the output amplitude of the data transmission unit 11 n of the buffer 111, to adjust the amplitude of the data transmitted by the data transmission unit 11 n.
- SYMBOLS 1 ... Image display system 10, 10A ... Transmission apparatus, 11 ... Data transmission part, 12 ... Clock transmission part, 13 ... Encoder part, 14 ... Detection signal reception part, 15 ... Control part, 16 ... Clock generation part, 19 ... Transmission unit, 20 ... receiving device, 21 ... data receiving unit, 22 ... clock receiving unit, 23 ... sampler unit, 24 ... decoder unit, 25 ... detection unit, 26 ... detection signal transmission unit, 30 ... image display unit, 31 ... Signal line.
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Abstract
Description
Claims (19)
- データおよびクロックを受信装置へ送信する送信装置であって、
データを前記受信装置へ送信するデータ送信部と、
クロックを前記受信装置へ送信するクロック送信部と、
前記データ送信部により送信されたデータと前記クロック送信部により送信されたクロックとを受信した前記受信装置において検出された前記データと前記クロックとの間の位相差および前記データの波形歪の双方または何れか一方を表す検出信号を前記受信装置から受信する検出信号受信部と、
前記検出信号受信部により受信された検出信号に基づいて、前記データ送信部により送信されるデータと前記クロック送信部により送信されるクロックとの間の位相の調整、および、前記データ送信部により送信されるデータの振幅の調整、の双方または何れか一方の制御を行う制御部と、
を備えることを特徴とする送信装置。 - 前記制御部が、前記受信装置に対して前記検出信号を送信するよう指示する検出信号送信指示データを、前記データ送信部により前記受信装置へ送信させる、ことを特徴とする請求項1に記載の送信装置。
- 複数組の前記データ送信部および前記クロック送信部を備えることを特徴とする請求項1に記載の送信装置。
- 複数の前記データ送信部と1つの前記クロック送信部とを備えることを特徴とする請求項1に記載の送信装置。
- 前記制御部が、前記データ送信部により送信されるデータの振幅の調整の制御を行う際に、該データのレベル遷移後のビットのデータの振幅を選択的に調整する、ことを特徴とする請求項1に記載の送信装置。
- データおよびクロックを送信装置から受信する受信装置であって、
データを前記送信装置から受信するデータ受信部と、
クロックを前記送信装置から受信するクロック受信部と、
前記クロック受信部により受信されたクロックにより、前記データ受信部により受信されたデータをサンプリングして、このサンプリングにより得られたデータを出力するサンプラ部と、
前記サンプラ部から出力されるデータに基づいて、前記データ受信部により受信されたデータと前記クロック受信部により受信されたクロックとの間の位相差、および、前記データ受信部により受信されたデータの波形歪、の双方または何れか一方の検出を行う検出部と、
前記検出部による検出の結果を表す検出信号を前記送信装置へ送信する検出信号送信部と、
を備えることを特徴とする受信装置。 - 前記データ受信部が、前記検出信号を送信するよう指示する検出信号送信指示データを前記送信装置から受信し、
前記検出信号送信部が、前記データ受信部が前記検出信号送信指示データを受信したことを受けて、前記検出信号を前記送信装置へ送信する、
ことを特徴とする請求項6に記載の受信装置。 - 前記サンプラ部が、前記データ受信部により受信されたデータのうちビット遷移の際のデータをもサンプリングして出力し、
前記検出部が、前記サンプラ部によりサンプリングされて出力されたビット遷移の際のデータに基づいて、前記位相差および前記波形歪の双方または何れか一方の検出を行う、
ことを特徴とする請求項6に記載の受信装置。 - 送信装置と、受信装置とを備え、
前記送信装置は、
データおよびクロックを受信装置へ送信する送信装置であって、
データを前記受信装置へ送信するデータ送信部と、
クロックを前記受信装置へ送信するクロック送信部と、
前記データ送信部により送信されたデータと前記クロック送信部により送信されたクロックとを受信した前記受信装置において検出された前記データと前記クロックとの間の位相差および前記データの波形歪の双方または何れか一方を表す検出信号を前記受信装置から受信する検出信号受信部と、
前記検出信号受信部により受信された検出信号に基づいて、前記データ送信部により送信されるデータと前記クロック送信部により送信されるクロックとの間の位相の調整、および、前記データ送信部により送信されるデータの振幅の調整、の双方または何れか一方の制御を行う制御部と、
を備え、
前記受信装置は、
データおよびクロックを送信装置から受信する受信装置であって、
データを前記送信装置から受信するデータ受信部と、
クロックを前記送信装置から受信するクロック受信部と、
前記クロック受信部により受信されたクロックにより、前記データ受信部により受信されたデータをサンプリングして、このサンプリングにより得られたデータを出力するサンプラ部と、
前記サンプラ部から出力されるデータに基づいて、前記データ受信部により受信されたデータと前記クロック受信部により受信されたクロックとの間の位相差、および、前記データ受信部により受信されたデータの波形歪、の双方または何れか一方の検出を行う検出部と、
前記検出部による検出の結果を表す検出信号を前記送信装置へ送信する検出信号送信部と、
を備え、
前記受信装置のデータ受信部が、前記送信装置のデータ送信部により送信されるデータを受信し、
前記受信装置のクロック受信部が、前記送信装置のクロック送信部により送信されるクロックを受信し、
前記送信装置の検出信号受信部が、前記受信装置の検出信号送信部により送信される検出信号を受信する、
ことを特徴とする送受信システム。 - 前記送信装置において、前記制御部が、前記受信装置に対して前記検出信号を送信するよう指示する検出信号送信指示データを、前記データ送信部により前記受信装置へ送信させ、
前記受信装置において、前記データ受信部が、前記検出信号を送信するよう指示する検出信号送信指示データを前記送信装置から受信し、
前記検出信号送信部が、前記データ受信部が前記検出信号送信指示データを受信したことを受けて、前記検出信号を前記送信装置へ送信する、
送受信システムであって、
前記受信装置のデータ受信部が、前記送信装置のデータ送信部により送信されるデータおよび検出信号送信指示データを受信し、
前記受信装置のクロック受信部が、前記送信装置のクロック送信部により送信されるクロックを受信し、
前記送信装置の検出信号受信部が、前記受信装置の検出信号送信部により送信される検出信号を受信する、
ことを特徴とする請求項9に記載の送受信システム。 - 前記送信装置が複数のデータ送信部を含み、
前記送信装置に含まれる複数のデータ送信部と複数の受信装置とが1対1に対応していて、
前記送信装置から前記複数の受信装置それぞれへの検出信号送信指示データの送信を互いに異なるタイミングで行い、
前記複数の受信装置それぞれから前記送信装置への検出信号の送信を互いに異なるタイミングで行う、
ことを特徴とする請求項10記載の送受信システム。 - 前記送信装置の検出信号受信部が、前記複数の受信装置それぞれの検出信号送信部により送信される検出信号を、共通の信号線を介して受信する、ことを特徴とする請求項11に記載の送受信システム。
- 請求項11に記載の送受信システムと、
前記送受信システムに含まれる複数の受信装置それぞれにより受信されたデータに基づいて画像を表示する画像表示部と、
を備えることを特徴とする画像表示システム。 - 前記送信装置において、複数組の前記データ送信部および前記クロック送信部を備え、
前記受信装置は複数であり、
前記送信装置に含まれる複数のデータ送信部と前記複数の受信装置とが1対1に対応していて、
前記複数の受信装置それぞれのデータ受信部が、前記送信装置に含まれる対応するデータ送信部により送信されるデータを受信し、
前記複数の受信装置それぞれのクロック受信部が、前記送信装置に含まれる対応するクロック送信部により送信されるクロックを受信し、
前記送信装置の検出信号受信部が、前記複数の受信装置それぞれの検出信号送信部により送信される検出信号を受信する、
ことを特徴とする請求項9に記載の送受信システム。 - 前記送信装置の検出信号受信部が、前記複数の受信装置それぞれの検出信号送信部により送信される検出信号を、共通の信号線を介して受信する、ことを特徴とする請求項14に記載の送受信システム。
- 請求項14に記載の送受信システムと、
前記送受信システムに含まれる複数の受信装置それぞれにより受信されたデータに基づいて画像を表示する画像表示部と、
を備えることを特徴とする画像表示システム。 - 前記送信装置において、複数の前記データ送信部と1つの前記クロック送信部とを備え、
前記受信装置は、複数であり、
前記送信装置に含まれる複数のデータ送信部と前記複数の受信装置とが1対1に対応していて、
前記複数の受信装置それぞれのデータ受信部が、前記送信装置に含まれる対応するデータ送信部により送信されるデータを受信し、
前記複数の受信装置それぞれのクロック受信部が、前記送信装置のクロック送信部により送信されるクロックを受信し、
前記送信装置の検出信号受信部が、前記複数の受信装置それぞれの検出信号送信部により送信される検出信号を受信する、
ことを特徴とする請求項9に記載の送受信システム。 - 前記送信装置の検出信号受信部が、前記複数の受信装置それぞれの検出信号送信部により送信される検出信号を、共通の信号線を介して受信する、ことを特徴とする請求項17に記載の送受信システム。
- 請求項17に記載の送受信システムと、
前記送受信システムに含まれる複数の受信装置それぞれにより受信されたデータに基づいて画像を表示する画像表示部と、
を備えることを特徴とする画像表示システム。
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EP10767133.1A EP2424153B1 (en) | 2009-04-23 | 2010-04-22 | Transmission apparatus, reception apparatus, transmission-reception system, and image display system |
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JP5789148B2 (ja) * | 2011-07-21 | 2015-10-07 | シャープ株式会社 | 映像表示装置の駆動に用いられる半導体装置及び表示装置 |
KR20140007698A (ko) * | 2012-07-10 | 2014-01-20 | 삼성전자주식회사 | Hdmi 신호 보정 방법, hdmi 신호 수신장치, hdmi 신호 전송장치 및 hdmi 신호 처리 시스템 |
JP5776657B2 (ja) * | 2012-09-18 | 2015-09-09 | 株式会社デンソー | 受信回路 |
JP5807048B2 (ja) * | 2013-08-26 | 2015-11-10 | 株式会社セレブレクス | キャリブレーション装置,キャリブレーション機能付き画像表示装置 |
JP6034273B2 (ja) * | 2013-10-04 | 2016-11-30 | ザインエレクトロニクス株式会社 | 送信装置、受信装置、送受信システムおよび画像表示システム |
KR102329928B1 (ko) * | 2014-12-30 | 2021-11-23 | 엘지디스플레이 주식회사 | 저전압 차등 시그널 시스템 |
KR102265723B1 (ko) * | 2014-12-30 | 2021-06-16 | 엘지디스플레이 주식회사 | 저전압 차등 시그널 시스템 및 이를 채용한 표시장치 |
KR102223496B1 (ko) * | 2014-12-31 | 2021-03-08 | 엘지디스플레이 주식회사 | 표시장치 |
JP6480226B2 (ja) * | 2015-03-25 | 2019-03-06 | ラピスセミコンダクタ株式会社 | スキュー調整装置 |
JP6606405B2 (ja) * | 2015-11-05 | 2019-11-13 | シチズン時計株式会社 | 表示装置 |
JP6875823B2 (ja) * | 2016-10-21 | 2021-05-26 | シャープ株式会社 | データ送受信装置 |
JP6416956B2 (ja) * | 2017-03-01 | 2018-10-31 | ファナック株式会社 | シリアル通信ユニットおよびシリアル通信ユニットの通信方法 |
JP2018167466A (ja) * | 2017-03-29 | 2018-11-01 | ブラザー工業株式会社 | 通信装置、及びこれを備えた記録装置 |
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US9019259B2 (en) | 2015-04-28 |
KR101367518B1 (ko) | 2014-02-27 |
EP2424153A4 (en) | 2017-12-20 |
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KR20110135961A (ko) | 2011-12-20 |
JP2010258671A (ja) | 2010-11-11 |
EP2424153B1 (en) | 2019-01-02 |
JP5670622B2 (ja) | 2015-02-18 |
CN102428674B (zh) | 2016-06-01 |
US20120068995A1 (en) | 2012-03-22 |
CN102428674A (zh) | 2012-04-25 |
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