WO2009075288A1 - シリコン基板とその製造方法 - Google Patents

シリコン基板とその製造方法 Download PDF

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Publication number
WO2009075288A1
WO2009075288A1 PCT/JP2008/072400 JP2008072400W WO2009075288A1 WO 2009075288 A1 WO2009075288 A1 WO 2009075288A1 JP 2008072400 W JP2008072400 W JP 2008072400W WO 2009075288 A1 WO2009075288 A1 WO 2009075288A1
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WIPO (PCT)
Prior art keywords
silicon substrate
manufacturing
same
concentration
omega
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PCT/JP2008/072400
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English (en)
French (fr)
Inventor
Kazunari Kurita
Shuichi Omote
Original Assignee
Sumco Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corporation filed Critical Sumco Corporation
Priority to JP2009545430A priority Critical patent/JPWO2009075288A1/ja
Publication of WO2009075288A1 publication Critical patent/WO2009075288A1/ja

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14698—Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Thermal Sciences (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

　ゲッタリング能力の確実性とその向上を図るために、ＣＺ法によりＢ濃度が抵抗率８ｍΩｃｍ～１０ｍΩｃｍに相当する濃度、Ｃ濃度が０．５×１０１６～１０×１０１６ａｔｏｍｓ／ｃｍ３、酸素濃度が１×１０１８～１０×１０１８ａｔｏｍｓ／ｃｍ３を有するシリコン単結晶を引き上げる工程と、 　引き上げたシリコン単結晶からスライスしたシリコン基板に６００～８００°Cで０．２５～３時間の熱処理をおこなう析出を促進する熱処理工程とを有する。
PCT/JP2008/072400 2007-12-11 2008-12-10 シリコン基板とその製造方法 WO2009075288A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009545430A JPWO2009075288A1 (ja) 2007-12-11 2008-12-10 シリコン基板とその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007320129 2007-12-11
JP2007-320129 2007-12-11

Publications (1)

Publication Number Publication Date
WO2009075288A1 true WO2009075288A1 (ja) 2009-06-18

Family

ID=40755530

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/072400 WO2009075288A1 (ja) 2007-12-11 2008-12-10 シリコン基板とその製造方法

Country Status (3)

Country Link
JP (1) JPWO2009075288A1 (ja)
TW (1) TW200937530A (ja)
WO (1) WO2009075288A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110052923A1 (en) * 2009-09-03 2011-03-03 Sumco Corporation Method of producing epitaxial wafer as well as epitaxial wafer
JP2011096979A (ja) * 2009-11-02 2011-05-12 Sumco Corp シリコンウェーハ及びその製造方法
JP2012059849A (ja) * 2010-09-08 2012-03-22 Shin Etsu Handotai Co Ltd シリコンエピタキシャルウェーハおよびシリコンエピタキシャルウェーハの製造方法
WO2014200686A1 (en) * 2013-06-11 2014-12-18 Sunedison Semiconductor Limited Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the czochralski method
JP2019149471A (ja) * 2018-02-27 2019-09-05 株式会社Sumco 半導体ウェーハのゲッタリング能力の評価方法および該評価方法を用いた半導体ウェーハの製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1050715A (ja) * 1996-07-29 1998-02-20 Sumitomo Sitix Corp シリコンウェーハとその製造方法
JP2000272995A (ja) * 1999-03-26 2000-10-03 Sumitomo Metal Ind Ltd シリコン単結晶、シリコンウェーハ及びエピタキシャルウェーハ
JP2005170778A (ja) * 2003-11-21 2005-06-30 Shin Etsu Handotai Co Ltd シリコン単結晶の製造方法
JP2007008795A (ja) * 2004-08-25 2007-01-18 Sumco Corp シリコンウェーハ及びその製造方法、並びにシリコン単結晶育成方法
JP2007145692A (ja) * 2005-10-24 2007-06-14 Sumco Corp シリコン半導体基板およびその製造方法
JP2007273959A (ja) * 2006-03-06 2007-10-18 Matsushita Electric Ind Co Ltd 光検出素子及びその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11204534A (ja) * 1998-01-14 1999-07-30 Sumitomo Metal Ind Ltd シリコンエピタキシャルウェーハの製造方法
KR100745309B1 (ko) * 2002-04-10 2007-08-01 엠이엠씨 일렉트로닉 머티리얼즈 인코포레이티드 이상적인 산소 침전 실리콘 웨이퍼에서 디누드 구역깊이를 조절하기 위한 방법
JP4604889B2 (ja) * 2005-05-25 2011-01-05 株式会社Ｓｕｍｃｏ シリコンウェーハの製造方法、並びにシリコン単結晶育成方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1050715A (ja) * 1996-07-29 1998-02-20 Sumitomo Sitix Corp シリコンウェーハとその製造方法
JP2000272995A (ja) * 1999-03-26 2000-10-03 Sumitomo Metal Ind Ltd シリコン単結晶、シリコンウェーハ及びエピタキシャルウェーハ
JP2005170778A (ja) * 2003-11-21 2005-06-30 Shin Etsu Handotai Co Ltd シリコン単結晶の製造方法
JP2007008795A (ja) * 2004-08-25 2007-01-18 Sumco Corp シリコンウェーハ及びその製造方法、並びにシリコン単結晶育成方法
JP2007145692A (ja) * 2005-10-24 2007-06-14 Sumco Corp シリコン半導体基板およびその製造方法
JP2007273959A (ja) * 2006-03-06 2007-10-18 Matsushita Electric Ind Co Ltd 光検出素子及びその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110052923A1 (en) * 2009-09-03 2011-03-03 Sumco Corporation Method of producing epitaxial wafer as well as epitaxial wafer
JP2011096979A (ja) * 2009-11-02 2011-05-12 Sumco Corp シリコンウェーハ及びその製造方法
JP2012059849A (ja) * 2010-09-08 2012-03-22 Shin Etsu Handotai Co Ltd シリコンエピタキシャルウェーハおよびシリコンエピタキシャルウェーハの製造方法
WO2014200686A1 (en) * 2013-06-11 2014-12-18 Sunedison Semiconductor Limited Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the czochralski method
US9634098B2 (en) 2013-06-11 2017-04-25 SunEdison Semiconductor Ltd. (UEN201334164H) Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method
JP2019149471A (ja) * 2018-02-27 2019-09-05 株式会社Sumco 半導体ウェーハのゲッタリング能力の評価方法および該評価方法を用いた半導体ウェーハの製造方法

Also Published As

Publication number Publication date
JPWO2009075288A1 (ja) 2011-04-28
TW200937530A (en) 2009-09-01

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