WO2005083452A1 - アレイ基板の検査方法およびアレイ基板の製造方法 - Google Patents
アレイ基板の検査方法およびアレイ基板の製造方法 Download PDFInfo
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- WO2005083452A1 WO2005083452A1 PCT/JP2005/002814 JP2005002814W WO2005083452A1 WO 2005083452 A1 WO2005083452 A1 WO 2005083452A1 JP 2005002814 W JP2005002814 W JP 2005002814W WO 2005083452 A1 WO2005083452 A1 WO 2005083452A1
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- array substrate
- substrate
- signal
- pixel
- pixel electrode
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
Definitions
- the present invention relates to an array substrate inspection method for inspecting an array substrate, which is a component of a liquid crystal display panel, for example, and a method for manufacturing an array substrate.
- Liquid crystal display panels are used in various places such as a display section of a notebook personal computer (notebook PC), a display section of a mobile phone, and a display section of a television receiver.
- the liquid crystal display panel includes an array substrate on which a plurality of pixel electrodes are arranged in a matrix, an opposing substrate having an opposing electrode facing the plurality of pixel electrodes, and a liquid crystal held between the array substrate and the opposing substrate. And a layer.
- the array substrate includes a plurality of pixel electrodes arranged in a matrix, a plurality of scanning lines arranged along rows of the plurality of pixel electrodes, and a plurality of signals arranged along columns of the plurality of pixel electrodes. Lines, and a plurality of switching elements arranged near intersections of these scanning lines and signal lines.
- array substrates There are two types of array substrates. That is, there are an array substrate in which the switching element is a thin film transistor using a semiconductor thin film of amorphous silicon, and an array substrate in which the switching element is a thin film transistor using a semiconductor thin film of polysilicon.
- Polysilicon has a higher carrier mobility than amorphous silicon.
- a drive circuit for scanning lines and signal lines which can be formed only by switching elements for pixel electrodes, can be incorporated in the array substrate.
- the above array substrate undergoes a detection process in order to detect a defective product in the manufacturing process.
- a detection process there are techniques disclosed in JP-A-11-271177, JP-A-2000-3142, and U.S.P. 5, 268, 638.
- Japanese Patent Application Laid-Open No. 11-271177 discloses a technique in which a point defect inspection process is characterized in an inspection of an amorphous type LCD substrate.
- direct light of a DC component is applied to the entire surface of the LCD substrate, and the amorphous silicon film becomes light-sensitive and becomes conductive. Take advantage of that.
- the state of the defect can be determined by detecting the amount of charge leakage stored in the auxiliary capacitance.
- the technique disclosed in Japanese Patent Application Laid-Open No. 2000-3142 utilizes the fact that secondary electrons emitted when an electron beam is irradiated on a pixel electrode are proportional to the voltage applied to the thin film transistor.
- USP 5,268,638 also uses secondary electrons emitted when an electron beam is irradiated on a pixel electrode.
- the product price of a liquid crystal display panel is greatly affected by the yield rate of the product. Yield rates are also affected by whether product defects are found during the manufacturing process and the repair rate is high.
- the present invention improves the yield rate of the product by increasing the detection rate and therefore the repair rate when there is a defect in the manufacturing process of the liquid crystal display panel, thereby improving the product price. It is an object of the present invention to provide an array substrate inspection method and a method of manufacturing an array substrate, which can reduce the number of pixels.
- An inspection method of an array substrate according to an aspect of the present invention comprises:
- a substrate a plurality of scanning lines formed on the substrate and extending in a row direction; a plurality of signal lines extending in a column direction so as to intersect with the scanning lines;
- a method for detecting an array substrate comprising: a plurality of pixel portions each including a switching element and an auxiliary capacitor formed by a thin film transistor and a pixel electrode, each of which is formed in the vicinity of an intersection between a vertical line and a signal line;
- the array substrate is inspected for defects. After the pixel portion is provided with the pixel electrode, the array substrate is inspected for defects.
- a method for manufacturing an array substrate according to another aspect of the present invention includes:
- a pixel electrode is formed so as to be connected to the switching element, and the pixel electrode is connected to the pixel electrode via the first pad and the wiring while the second pad is electrically connected to the first pad.
- An electric signal is supplied to the pixel electrode, an electron beam is irradiated on the pixel electrode, and the presence or absence of a defect in the pixel electrode is detected based on information on secondary electrons emitted from the pixel electrode.
- a substrate a plurality of scanning lines formed on the substrate and extending in a row direction; a plurality of signal lines extending in a column direction so as to intersect with the scanning lines;
- a plurality of pixel sections each including a switching element and an auxiliary capacitor formed by a thin film transistor using polysilicon and a pixel electrode, which are formed in the vicinity of the intersection of the ⁇ line and the signal line.
- a scanning line driving circuit provided on the substrate and connected to the plurality of scanning lines to supply a scanning line driving signal to the plurality of pixel portions in the row direction; and a scanning line driving circuit provided on the substrate.
- a signal line drive circuit connected to the plurality of signal lines and providing a signal line drive signal in the column direction to the plurality of pixel portions, and comprising an array substrate main region and an array substrate sub-region.
- a plurality of regular pads connected to the scanning line driving circuit and the signal line driving circuit are formed in the array substrate main area;
- a plurality of common pads are formed in the array substrate sub-region, and a plurality of logic terminals, a plurality of power supply terminals, and a plurality of signal input terminals of the plurality of terminals of the scanning line drive circuit and the signal line drive circuit are provided for each type.
- the plurality of terminals are grouped into a plurality of terminal groups, and the plurality of terminals of the terminal group are connected to any of the plurality of common pads formed on the substrate. Disconnect the pad and
- FIG. 1 is a view for explaining a technology underlying the present invention, and is an explanatory view showing a basic configuration of an amorphous silicon type array substrate.
- FIG. 2 is a view for explaining a technology underlying the present invention, and is an explanatory view showing a basic configuration of a polysilicon type array substrate.
- FIG. 3 is a schematic sectional view of a liquid crystal display panel according to an embodiment of the present invention.
- FIG. 4 is a perspective view showing a part of the liquid crystal display panel.
- FIG. 5 is an explanatory diagram showing an example of the arrangement of an array substrate on a mother substrate.
- FIG. 6 is a view schematically showing an array substrate taken out according to an embodiment of the present invention.
- FIG. 7 is a schematic plan view showing a part of a pixel region of the array substrate shown in FIG. 6 in an enlarged manner.
- FIG. 8 is a schematic sectional view of a liquid crystal display panel provided with the array substrate shown in FIG. 7.
- FIG. 9 is a flowchart shown to explain an inspection method according to the embodiment of the present invention.
- FIG. 10 is an explanatory diagram showing a main part of an array substrate before forming a color filter and a pixel electrode according to an embodiment of the present invention.
- FIG. 11 is an explanatory view showing a main part of the array substrate after forming the color filter and the pixel electrode according to the embodiment of the present invention.
- FIG. 12 is a diagram shown to explain a basic configuration and operation of the electron beam tester according to the embodiment of the present invention.
- an amorphous silicon type array substrate has a pixel area 30 and a pad group PDa consisting of about 3000 terminals for connecting external circuits.
- a polysilicon type array substrate In addition to the area 30, a scanning line driving circuit 40 and a signal line driving circuit 50 for driving all the pixels of the X and Y coordinates are formed, and these circuits are constituted by thin film transistors (hereinafter, referred to as TFTs). . Therefore, the number of terminals of the pad group PDp is equal to the number of inputs of the scanning line driving circuit 40 and the signal line driving circuit 50, so that the total number is about 300.
- the above-mentioned array substrate requires a product inspection during the manufacturing process.
- a tester for detecting the state of the pixel region 30 there are an electric tester and an electron beam tester (hereinafter, referred to as an EB tester).
- the detection using an electric tester is performed by accumulating electric charges in an auxiliary capacitance of a pixel portion and then reading out the accumulated electric charges by a probe.
- the detection using the EB test is performed by accumulating electric charges in a storage capacitor of a pixel portion, irradiating the pixel portion with an electron beam, and detecting the emitted secondary electrons.
- the liquid crystal display panel includes an array substrate 101, an opposing substrate 102 arranged opposite to the array substrate while maintaining a predetermined gap, and a liquid crystal layer sandwiched between these two substrates. 103.
- the array substrate 101 and the opposing substrate 102 maintain a predetermined gap by a columnar spacer 127 as a spacer.
- the peripheral edges of the array substrate 101 and the opposing substrate 102 are joined by a sealing material 160, and a liquid crystal injection port 161 formed in a part of the sealing material is sealed by a sealing material 162.
- FIG. 5 shows a substrate (hereinafter, referred to as a mother substrate) 100 having a size larger than the array substrate, and shows an example in which four array substrates 101 are configured using the mother substrate.
- a mother substrate a substrate having a size larger than the array substrate
- four array substrates 101 are configured using the mother substrate.
- the configuration of one array substrate 101 will be described as a representative.
- the array substrate 101 has a main region and a sub-region which are unique points of the present invention, which will be described later in detail.
- the array substrate 101 includes, in addition to the pixel electrodes P, a plurality of scanning lines Y arranged along the rows of the pixel electrodes P, and a plurality of signal lines X arranged along the columns of the pixel electrodes P. Further, the array substrate 101 includes a TFTSW as a switching element disposed near an intersection of the scanning line ⁇ and the signal line X, a scanning line driving circuit 40 for driving a plurality of scanning lines, and a plurality of signal lines. A signal line driving circuit 50 is provided.
- Each TFTSW applies the signal voltage of the corresponding signal line X to the corresponding pixel electrode P when driven via the corresponding scanning line Y.
- the scanning line driving circuit 40 and the signal line driving circuit 50 are arranged adjacent to the edge of the array substrate 101 and outside the pixel region 30. Further, the scanning line driving circuit 40 and the signal line driving circuit 50 are configured using a TFT using a polysilicon semiconductor film similar to the TFTSW.
- the array substrate 101 is arranged along one side of the cut line of the array substrate, and includes a plurality of terminals connected to the scanning line driving circuit 40 and the signal line driving circuit 50. It has PD group PDp.
- the node group PDp is used not only for inputting different signals but also for inputting and outputting signals for inspection.
- the array substrate 101 is separated and cut out by cutting the mother substrate 100, for example, along the edge e of the array substrate (FIG. 5).
- FIG. 7 is a diagram showing a plan view
- FIG. 8 is a diagram showing a cross section.
- the array substrate 101 has a substrate 111 as a transparent insulating substrate (glass) (FIG. 8).
- a plurality of signal lines X and a plurality of scanning lines Y are arranged in a matrix on a substrate 111, and a TFTSW (surrounded by a circle 171 in FIG. 7) is provided at each intersection of the signal lines and the scanning lines. Section).
- the TFTSW has a semiconductor film 112 made of polysilicon and having source Z drain regions 112a and 112b, and a gate electrode 115b extending a part of the scanning line Y.
- auxiliary capacitance lines 116 forming the auxiliary capacitance elements 131 are formed, and extend in parallel with the scanning lines Y.
- the corresponding pixel electrode P is formed in this portion (see a portion surrounded by a circle 172 in FIG. 7 and FIG. 8).
- a semiconductor film 112 and a storage capacitor lower electrode 113 are formed on a substrate 111, and a gate insulating film 114 is formed on the substrate including the semiconductor film and the storage capacitor lower electrode 113. Is filmed.
- the auxiliary capacitance lower electrode 113 is formed of polysilicon similarly to the semiconductor film 112.
- the scanning line Y, the gate electrode 115b, and the storage capacitance line 116 are provided on the gate insulating film 114.
- the storage capacitance line 116 and the storage capacitance lower electrode 113 are opposed to each other with the gate insulating film 114 interposed therebetween.
- An interlayer insulating film 117 is formed on the gate insulating film 114 including the scanning line Y, the gate electrode 115b, and the auxiliary capacitance line 116.
- a contact electrode 121 and a signal line X are formed on the interlayer insulating film 117.
- the contact electrodes 121 are respectively connected to the source / drain regions 112a of the semiconductor film 112 and the pixel electrodes P via contact holes.
- the signal line X is connected to the source Z drain region 112b of the semiconductor film via a contact hole.
- a protective insulating film 122 is formed on the contact electrode 121, the signal line X, and the interlayer insulating film 117. Further, on the protective insulating film 122, a striped green colored layer 12 is formed. 4G, a red coloring layer 124R, and a blue coloring layer 124B are arranged adjacently and alternately to form a color filter.
- the pixel electrodes P are respectively formed on the coloring layers 124G, 124R, and 124B by a transparent conductive film such as ITO (indium tin oxide). Each pixel electrode P is connected to a contact electrode 121 via a contact hole 125 formed in the coloring layer and the protective insulating film 122. The periphery of the pixel electrode P is located so as to overlap the auxiliary capacitance line 116 and the signal line X.
- the auxiliary capacitance element 131 connected to the pixel electrode P functions as an auxiliary capacitance that accumulates electric charges.
- a columnar spacer 127 (see FIG. 7) is formed on the coloring layers 124R and 124G. Although not shown, a plurality of columnar spacers 127 are formed on each colored layer at a desired density.
- An alignment film 128 is formed on the coloring layers 124G, 124R, 124B and the pixel electrodes P.
- the counter substrate 102 has a substrate 151 as a transparent insulating substrate. On this substrate 151, a counter electrode 152 formed of a transparent material such as ITO and an alignment film 153 are sequentially formed.
- FIG. 9 schematically shows a process of inspecting the array substrate 101 in two stages.
- step S1 when the inspection of the array substrate is started, in the array process of step S2, an array substrate before the color filter is formed is manufactured.
- step S3 the array substrate is inspected by an electric tester as an array intermediate inspection in step S3. If a defect is detected in the array substrate in step S4, the array substrate is sent to a repair process (step S5) for repairing and repairing the array substrate or to a discard process.
- step S6 the process proceeds to the next COA (color filter on array) process (step S6).
- a color filter and a pixel electrode are formed on the array substrate.
- step S7 the array substrate on which the pixel electrodes are formed is detected by an electron beam as a final array detection. More specifically, by irradiating the charged pixel electrode P with an electron beam and detecting and analyzing the secondary electrons emitted from the pixel electrode, whether the pixel electrode P normally holds the charge is determined. Is checked.
- the detection is not only the defect of the pixel electrode P itself, but also the defect of the TFTSW connected to the pixel electrode and the auxiliary capacitance including the pixel electrode. Inspection of the pixel electrode, such as a defect of the element 131, means the inspection.
- step S8 when a defect is detected in the array substrate, it is sent to a repair process (step S9) for repairing and repairing the array substrate or a discard process.
- the array intermediate detection is a first step
- the final array detection is a second step. If the array substrate is good in step S8 or if the repair is performed in step S9, the inspection of the array substrate ends (step S10).
- the advantage of providing the first step before the second step in the above-described detection process will be described.
- the second step is performed after the formation of the color filter and the pixel electrode, so that the lower layer array wiring cannot be repaired and repaired.
- the first step even if the array wiring is broken, it can be repaired and repaired. Thereby, the array substrate sent in the discarding step in the second step can be suppressed.
- the product yield rate can be improved, and as a result, manufacturing costs can be reduced.
- FIG. 10 shows an example of a pad group PDp provided on a part of the array substrate to be inspected in the first step described above, which is partially enlarged.
- the array substrate 101 has an array substrate main region 101a and an array substrate sub-region 101b outside the array substrate main region 101a. It should be noted that the array substrate sub-region 101b is cut out by, for example, drawing a scribe line along the cut-out line e2 after the completion of the second step.
- connection pad group CPDp is provided at the edge of the array substrate sub-region 101b.
- the connection pad group CPDp is connected by a force S formed to connect to the pad group PDp on the array substrate main area 10 la side via wiring, at the non-connection portion 600 of the array substrate before the color filter is formed.
- the pad group CPDp and the pad group PDp are formed in a disconnected state. This point, that is, the connection relationship between the connection pad group CPDp and the pad group PDp is an important point of the present invention.
- This pad group PDp in the array substrate main area 101a will be described.
- This pad group PDp includes a plurality of regular terminals.
- the plurality of regular terminals are connected to the scan line shown in FIG. They are connected to a line drive circuit 40 and a signal line drive circuit 50, respectively.
- the types of terminals constituting the pad group PDp arranged in this area are classified, they are classified into logic terminals, power supply terminals, inspection terminals, and signal input terminals.
- the logic terminal has a terminal CLK and a terminal ST.
- the signals input to these terminals CLK and ST are a clock signal and a start pulse signal.
- the clock signal and the start pulse signal are signals input to the scanning line driving circuit 40 and the signal line driving circuit 50, respectively. Therefore, the pad group PDp includes, for example, two terminals ST. Also, when inputting a clock signal, for example, input from two places, there are two terminals CLK.
- the detection terminal is a serial out terminal s / o.
- the signal output from the terminal s / o is a serial output output from the shift register (s / r) of the scanning line driving circuit 40 and the signal line driving circuit 50 in response to the start pulse.
- the power supply terminal there are a plurality of types of terminals such as a terminal VDD and a terminal VSS.
- the power supply terminals are classified into two, terminal VDD and terminal VSS.
- the signals input to the terminal VDD and the terminal VSS are a high-level power supply and a low-level power supply.
- Terminal VIDEO is used as the signal input terminal.
- the signal input to the terminal VIDEO is, for example, a video signal.
- the terminal VIDEO is a few hundred terminals, and occupies a large proportion of the node group PDp.
- connection pad group CPDp on the side of the array substrate sub-region 101b will be described below.
- the pad group PDp is classified for each terminal to which the same signal is input, and is divided into a plurality of terminal groups.
- a common connection pad group CPDp is prepared for each of the classified terminal gnorapes.
- the common terminals are a common terminal for clock cCLK, a common terminal for high level cVDD, a common terminal for low level cVSS, and a common terminal for signal cVI DE ⁇ , which are arranged on the edge e of the 10 lb array substrate sub area. ing.
- Each of these common terminals is arranged in a non-connected state with the corresponding pad group PDp of the array substrate main area 10 la.
- a probe is connected to each of the pads PDp of the array substrate 101, and the scanning line driving circuit 40 and the signal A scan line drive signal and a signal line drive signal are supplied to the pixel portion via the line drive circuit 50, and charges are stored in an auxiliary capacitor of the pixel portion. After that, by reading out the accumulated charges through the probe, the presence or absence of a defect in each pixel portion is detected.
- wirings 401 and 402 connected to the scan line drive circuit 40 are connected to the terminal ST and the terminal sZo, respectively.
- wirings 501 and 502 connected to the signal line driving circuit 50 are connected to another terminal ST and another terminal sZo, respectively.
- the scanning line driving circuit 40 and the signal line driving circuit 50 have a shift register (s / r). Therefore, when a start pulse is input to the scanning line driving circuit 40 and the signal line driving circuit 50 from the terminal ST, a serial output is output via the shift register. As described above, the terminal ST and the terminal s / o are connected to the common terminal dST and the common terminal ds / o, respectively.
- connection pad group CPDp and the pad group PDp in the non-connection state can be processed.
- FIG. 11 shows an example of a pad group PDp provided on a part of the array substrate after the color filters and the pixel electrodes are formed on the substrate and the array substrate is partially enlarged. Further, the pad group PDp and the connection pad group CPDp of the array substrate 101 after the formation of the pixel electrode are processed to be connected via the connection part 700.
- the connection portion 700 is formed as described above, for example, it is formed using ITO as the same material as the pixel electrode. Having this processing step is also a characteristic of the present invention.
- connection pad group CPDp The connection relationship between the above-described connection pad group CPDp and the node group PDp will be described.
- Array base The terminal ST and the terminal s / o on the board main area 101a are connected to the slave terminal dST and the slave terminal ds / o on the array board sub area 101b via wiring. This is because terminal ST and terminal s / o do not belong to the same classification.
- the plurality of terminals CLK on the array substrate main area 101a side belong to the same classification, they are commonly connected to the terminal cCLK.
- the plurality of terminals VDD on the side of the array substrate main area 101a belong to the same classification, and are connected to the common terminal cVDD.
- the plurality of terminals VSS on the side of the array substrate main area 101a belong to the same classification, and are connected to the common terminal cVSS. Since the plurality of terminals VIDEO on the array substrate main area 101a belong to the same classification, they are connected to the common terminal cVIDEO on the array substrate sub-area 10lb side.
- the configuration is such that the plurality of terminals VIDEO are connected to the common terminal cVIDEO as one common pad, but any configuration that is connected to a small number of common pads is acceptable.
- the number of pads of the connection pad group CPDp provided in the array substrate sub-region 101b is significantly reduced as compared with the number of pads of the pad group PDp provided in the array substrate main region 101a.
- the arrangement of the terminals constituting the connection pad group CPDp can be designed according to the arrangement of the probes.
- FIG. 12 shows a method for inspecting the array substrate 101 using the EB tester. This inspection is performed after the pixel electrodes P are formed on the substrate and before the array substrate 101 is cut from the mother substrate 100 along the edge e.
- a plurality of probes connected to the signal generator and the signal analyzer 902 correspond to a plurality of corresponding nodes 801 and 802 (nodes 801 and 802, respectively, the connection node CPDp shown in FIG. 11). Connected to).
- the drive signal output from the signal generator and the signal analyzer 902 is supplied to the pixel unit 803 via the probe and the pads 801 and 802. After the drive signal is supplied to the pixel portion 803, the pixel portion is irradiated with an electron beam EB emitted from the electron beam source 901.
- the irradiation emits secondary electrons SE representing the voltage of the pixel portion 803, and the secondary electrons SE are detected by the electron detector DE. Secondary electrons SE are proportional to the voltage at the point where they are emitted.
- the pixel portion 803 of the array substrate 101 is electrically scanned by a driving signal from a signal generator and a signal analyzer 902. This run is an electron beam
- the EB is performed in synchronization with the scanning on the surface of the array substrate 101 indicated by the arrow a.
- the information on the secondary electrons detected by the electron detector DE is sent to a signal generator and a signal analyzer 902 for analysis of the pixel unit 803.
- the voltage change corresponding to the secondary electrons indicates the state of the pixel portion 803.
- the information of the secondary electrons sent to the signal generator and the signal analyzer 902 reflects the response performance of each pixel unit to a drive signal supplied to the TFT terminal of each pixel unit 803. This makes it possible to detect the state of the voltage of the pixel electrode P of each pixel portion 803. That is, when there is a defect in the pixel portion 803, the defect can be detected by the EB tester.
- the array substrate before forming the color filter is formed by an electric tester. After inspection, the array substrate after pixel electrode formation is inspected by an EB tester. In the manufacturing process, product defects can be more effectively found, and a liquid crystal display panel with a high product yield can be obtained. Also, since the number of pads of the connection pad group CPDp in the second step is small, the number of probes of the inspection device is also small. Therefore, a high production yield can be realized by reducing the production cost and the cost of the inspection device, and good inspection can be performed. When the pixel electrode P is formed, the pad PDp and the connection pad CPDp are connected by the connection unit 700. Thus, connection processing can be performed without increasing the number of manufacturing steps.
- the overall time required for the inspection can be reduced. That is, it is not necessary to inspect the scanning line driving circuit 40 and the signal line driving circuit 50 in a separately provided process.
- connection pad group CPDp By arranging the arrangement of the terminals constituting the connection pad group CPDp in accordance with the arrangement of the probes, even if the arrangement of the pad group PDp in the array substrate main area 101a and the arrangement of the pads are changed, the connection pads are not changed.
- the sequence of the group CPDp can be forcibly formed to be the sequence of the probe of the detection device.
- the flexibility of the inspection apparatus can be expanded by devising a mutual combination form of the inspection apparatus and the array substrate. In addition, it reduces opportunities for design changes and corrections of inspection equipment, and consequently suppresses increases in panel product prices. Can be obtained.
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2006519361A JP4921969B2 (ja) | 2004-02-27 | 2005-02-22 | アレイ基板の製造方法 |
US11/508,858 US20060284642A1 (en) | 2004-02-27 | 2006-08-24 | Method of inspecting array substrate and method of manufacturing array substrate |
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JP2004054894 | 2004-02-27 | ||
JP2004-054894 | 2004-02-27 |
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US11/508,858 Continuation US20060284642A1 (en) | 2004-02-27 | 2006-08-24 | Method of inspecting array substrate and method of manufacturing array substrate |
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US (1) | US20060284642A1 (ja) |
JP (1) | JP4921969B2 (ja) |
KR (1) | KR20060118595A (ja) |
CN (1) | CN1922500A (ja) |
TW (1) | TW200602712A (ja) |
WO (1) | WO2005083452A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JPWO2004109377A1 (ja) * | 2003-06-06 | 2006-07-20 | 東芝松下ディスプレイテクノロジー株式会社 | アレイ基板およびアレイ基板の検査方法 |
CN102385190B (zh) * | 2011-11-14 | 2014-04-09 | 深圳市华星光电技术有限公司 | 液晶显示模组及其制造方法 |
US9251750B2 (en) | 2011-11-14 | 2016-02-02 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | LCD module and manufacturing method thereof |
KR101991099B1 (ko) * | 2012-03-29 | 2019-06-20 | 삼성디스플레이 주식회사 | 화소 및 그 화소 어레이의 시험 방법 |
CN108364597B (zh) * | 2018-02-23 | 2021-03-09 | 京东方科技集团股份有限公司 | 阵列基板及其显示异常的确定方法、显示面板和显示装置 |
US11037980B2 (en) * | 2018-08-10 | 2021-06-15 | Sharp Kabushiki Kaisha | Image display device |
JP2022019449A (ja) * | 2020-07-17 | 2022-01-27 | 株式会社ジャパンディスプレイ | アレイ基板の検査方法、表示装置及び検査治具 |
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JPH01292736A (ja) * | 1988-05-18 | 1989-11-27 | Matsushita Electric Ind Co Ltd | スイッチング素子を有したアクティブ基板の欠陥検査装置および欠陥検査方法 |
JPH02251931A (ja) * | 1989-03-27 | 1990-10-09 | Matsushita Electric Ind Co Ltd | アクティブマトリックスアレイ |
JPH1184420A (ja) * | 1997-09-09 | 1999-03-26 | Toshiba Corp | 液晶表示装置、アレイ基板の検査方法およびアレイ基板用テスタ |
JP2001004968A (ja) * | 1999-06-18 | 2001-01-12 | Sharp Corp | 液晶表示装置及びその検査装置 |
JP2003029296A (ja) * | 2001-07-13 | 2003-01-29 | Toshiba Corp | アレイ基板及びその検査方法並びに液晶表示装置 |
JP2003337546A (ja) * | 2002-05-21 | 2003-11-28 | Wintest Corp | アクティブマトリクス基板の検査方法及び検査装置並びにそれに用いる検査用プログラム及び情報記録媒体 |
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US5694053A (en) * | 1995-06-07 | 1997-12-02 | Xerox Corporation | Display matrix tester |
TW588423B (en) * | 1998-08-21 | 2004-05-21 | Samsung Electronics Co Ltd | Integrated semiconductor error detection and repair system and its controlling method |
US6762735B2 (en) * | 2000-05-12 | 2004-07-13 | Semiconductor Energy Laboratory Co., Ltd. | Electro luminescence display device and method of testing the same |
CN101044537A (zh) * | 2003-06-04 | 2007-09-26 | 东芝松下显示技术有限公司 | 阵列基板检查方法 |
CN1802593A (zh) * | 2003-06-04 | 2006-07-12 | 东芝松下显示技术有限公司 | 阵列基板检查方法及阵列基板检查设备 |
WO2004109376A1 (ja) * | 2003-06-04 | 2004-12-16 | Toshiba Matsushita Display Technology Co., Ltd. | アレイ基板の検査方法 |
-
2005
- 2005-02-22 JP JP2006519361A patent/JP4921969B2/ja active Active
- 2005-02-22 CN CNA2005800059818A patent/CN1922500A/zh active Pending
- 2005-02-22 KR KR1020067017004A patent/KR20060118595A/ko not_active Application Discontinuation
- 2005-02-22 WO PCT/JP2005/002814 patent/WO2005083452A1/ja active Application Filing
- 2005-02-24 TW TW094105647A patent/TW200602712A/zh unknown
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2006
- 2006-08-24 US US11/508,858 patent/US20060284642A1/en not_active Abandoned
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JPH01292736A (ja) * | 1988-05-18 | 1989-11-27 | Matsushita Electric Ind Co Ltd | スイッチング素子を有したアクティブ基板の欠陥検査装置および欠陥検査方法 |
JPH02251931A (ja) * | 1989-03-27 | 1990-10-09 | Matsushita Electric Ind Co Ltd | アクティブマトリックスアレイ |
JPH1184420A (ja) * | 1997-09-09 | 1999-03-26 | Toshiba Corp | 液晶表示装置、アレイ基板の検査方法およびアレイ基板用テスタ |
JP2001004968A (ja) * | 1999-06-18 | 2001-01-12 | Sharp Corp | 液晶表示装置及びその検査装置 |
JP2003029296A (ja) * | 2001-07-13 | 2003-01-29 | Toshiba Corp | アレイ基板及びその検査方法並びに液晶表示装置 |
JP2003337546A (ja) * | 2002-05-21 | 2003-11-28 | Wintest Corp | アクティブマトリクス基板の検査方法及び検査装置並びにそれに用いる検査用プログラム及び情報記録媒体 |
Also Published As
Publication number | Publication date |
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TW200602712A (en) | 2006-01-16 |
KR20060118595A (ko) | 2006-11-23 |
JPWO2005083452A1 (ja) | 2007-11-22 |
CN1922500A (zh) | 2007-02-28 |
US20060284642A1 (en) | 2006-12-21 |
JP4921969B2 (ja) | 2012-04-25 |
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