WO2003071604A1 - Procede de liaison de semi-conducteurs et semi-conducteur multicouches ainsi fabrique - Google Patents

Procede de liaison de semi-conducteurs et semi-conducteur multicouches ainsi fabrique Download PDF

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Publication number
WO2003071604A1
WO2003071604A1 PCT/JP2003/001848 JP0301848W WO03071604A1 WO 2003071604 A1 WO2003071604 A1 WO 2003071604A1 JP 0301848 W JP0301848 W JP 0301848W WO 03071604 A1 WO03071604 A1 WO 03071604A1
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Prior art keywords
bonding
semiconductors
semiconductor
electrode
resin layer
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PCT/JP2003/001848
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English (en)
Japanese (ja)
Inventor
Tadatomo Suga
Akira Yamauchi
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Toray Engineering Co., Ltd.
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Publication of WO2003071604A1 publication Critical patent/WO2003071604A1/fr

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7501—Means for cleaning, e.g. brushes, for hydro blasting, for ultrasonic cleaning, for dry ice blasting, using gas-flow, by etching, by applying flux or plasma
    • H—ELECTRICITY
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
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    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to a method for bonding semiconductors and a laminated semiconductor prepared by the method, and particularly to a method for bonding wafers and a semiconductor suitable for sequentially stacking and bonding three or more wafers.
  • the present invention relates to a method and a laminated semiconductor produced by the method.
  • FIG. 13 As a method for bonding semiconductors, for example, for bonding wafers, a method as shown in FIG. 13 is known.
  • an electrode 102 is formed on the surface of a silicon substrate 101, a circuit 103 is formed between the electrodes, and a portion between the electrodes 102 on the substrate surface and a peripheral portion thereof.
  • a resin layer 104 made of polyimide or the like is provided, and the wafers 105 are joined with the corresponding electrodes 102 exposed on the surface and the resin layers 104 facing each other.
  • the exposed electrode portions and the resin layer 104 filling the gap between them are also called a rewiring layer.
  • the front end surfaces of the exposed electrode portions and the surface of the resin layer 104 filling the gap between them were formed substantially flush.
  • the corresponding electrodes 1 0 2 s to metal bonding, c but is desirable to seal the gap between the two wafers 1 0 5 over the entire surface, and the electrodes are If the resin layers contact each other at the same time, or if the resin layers contact each other before the electrodes, the resin may wrap around the tip surface of the electrode. If the resin goes around, there is a possibility that the desired electrodes cannot be joined to each other or a connection failure may occur. In particular, such a problem is likely to occur when the pitch between adjacent electrodes is reduced to about several tens of meters / m and the electrode area is small.
  • Japanese Patent No. 27191429 discloses metal bonding by irradiating an energy wave or an energy particle, particularly an inert gas ion beam or an inert gas fast atom beam in a vacuum at room temperature. A method is disclosed in which the surface of a part is cleaned and activated, and the surface activation enables bonding at a low temperature.
  • an object of the present invention is to focus on the problems in the conventional technology as described above, and to prevent the occurrence of undesired behavior of the surface coating resin when bonding semiconductors, especially wafers, to each other.
  • a laminated semiconductor produced by the method in which bonding can be reliably performed over the entire predetermined bonding surface, preferably without causing voids at low temperatures. Is to provide.
  • Another object of the present invention is to provide a laminated semiconductor having a three-dimensional circuit configuration in which three or more semiconductors are laminated and bonded, and in particular, a laminated wafer, for which great demand is expected in the future. It can be created easily and efficiently without causing, in order to achieve the c the purpose is to provide a stacked semiconductor created by bonding method and a method of semiconductors, semiconductor bonding method according to the present invention
  • a resin layer is formed by filling a resin around the electrodes, at least one of the semiconductor electrodes is projected from the surface of the resin layer, the electrodes of the two semiconductors are brought into contact with each other, and the electrodes are pressed at the contact portions.
  • the method is characterized in that the surface of the resin layer is brought into contact with the surface of the other semiconductor. That is, this is a bonding method in which the corresponding electrodes are brought into contact with each other before the surface of the resin layer, and the electrodes are sufficiently bonded at the contact portions between the electrodes until the electrodes are spread.
  • the method of projecting the electrode is not particularly limited. For example, a method of separately forming a projecting portion by using a method, or a method of projecting naturally after filling with a resin by using the property of expansion and contraction and expansion of the resin is used. A method in which the resin at the periphery of the electrode is wiped off by the pressure of a squeegee by screen-printing the resin, a method in which the resin is dry or X-etched, and the like can be applied.
  • the semiconductors in a vacuum.
  • the degree of vacuum is preferably not more than 1 3 0 X 1 0- 3 P a.
  • At least one electrode of the semiconductor may be protruded from the surface thereof, but it is preferable that the electrode on the semiconductor side forming the resin layer is protruded from the surface of the resin layer.
  • electrodes may be projected from their surfaces.
  • the electrode of the semiconductor forming the resin layer protrudes from the surface of the resin layer, a void portion recessed from the surface of the resin layer is formed around the electrode protruding from the surface of the resin layer. It is preferable that the volume of the electrode portion protruding from the surface of the layer and the volume of the gap be substantially the same.
  • the term “substantially the same size” means within about ⁇ 5%, and it is preferable that the volume on the electrode side is large.
  • the resin layer is formed so that the outer peripheral portion of the semiconductor is high, and when joining the semiconductors, After temporarily bonding the inside surrounded by the outer peripheral portion in a state of being sealed in a vacuum state, it is also possible to perform the main bonding with a high pressure.
  • the actual bonding at this high pressure can be performed by another pressurizing device.
  • the filling of the resin can be performed by printing, for example, by screen printing.
  • printing is performed in a vacuum, it is possible to easily prevent entrapment of a void in the vacuum.
  • the bonding surfaces of the two semiconductors are irradiated with energy waves or energy particles to clean the surfaces, and the cleaned bonding surfaces are bonded together. You can also. In this case, the semiconductors whose bonding surfaces have been cleaned can be aligned and then connected.
  • the bonding surface at the time of bonding is, for example, 180 ° C or less. (Lower than the temperature in the conventional hang bonding) may be performed.
  • any of plasma including atmospheric pressure plasma
  • ion beam ion beam
  • atomic beam atomic beam
  • radical beam and laser
  • plasma including atmospheric pressure plasma
  • ion beam atomic beam
  • radical beam and laser
  • the bonding method according to the present invention is suitable for sequentially stacking three or more semiconductors, and for producing a semiconductor integrated circuit having a three-dimensional circuit configuration. For example, it is possible to provide a through electrode in at least one of the semiconductors and join the semiconductors sequentially in three or more layers.
  • an electrode exposed surface of the second semiconductor on which the resin layer is formed and a through-electrode is provided is joined to an electrode exposed surface of the first semiconductor to laminate both semiconductors. Polishing the anti-joining surface of the second semiconductor to expose the through electrode; The resin layer is formed on the through-electrode exposed surface of the second semiconductor, and the electrode-exposed surface of the third semiconductor on which the through-electrode is provided is joined to form a third semiconductor, and the second semiconductor is laminated.
  • the “anti-joining surface” is the surface on the opposite side of the joint.
  • the semiconductor can be treated as a semiconductor capable of bonding with wires, and furthermore, bumps can be formed thereon.
  • it can be treated as a semiconductor for flip chips.
  • the joint surface of the two semiconductors is irradiated with the same energy wave or energy particles as described above. Then, the surfaces can be cleaned, and the cleaned bonding surfaces can be bonded together. For example, after aligning semiconductors whose joint surfaces have been cleaned, they can be joined. Also, when producing a laminated semiconductor, similarly to the above, heating at 180 ° C. or less can be performed at the time of joining, and a pressing force can be applied between the joining surfaces of both semiconductors to be joined.
  • the joining surface of both semiconductors is irradiated with energy waves or energy particles to activate the surface, and the electrodes are joined by surface activation.
  • the resin can be cured by heating.
  • the electrodes can be joined at room temperature to 100 ° C, especially at room temperature o
  • the semiconductor with the exposed electrodes and the redistribution layer of the semiconductor are bonded together at room temperature after cleaning with energy waves or energy particles in a vacuum.
  • the electrodes are bonded with high accuracy without being affected by thermal expansion.
  • the resin of the rewiring layer uses a resin that temporarily lowers its viscosity by heating and then hardens. By bonding and then applying heat and pressure, the electrodes are crushed and the viscosity of the resin decreases at the same time. It can be pushed and expanded, creating a void The resin layer can be brought into close contact with the semiconductor without causing this.
  • the resin may be cured by heating at, for example, about 220 ° C, and both high-precision joining between the electrodes and complete sealing with the resin layer can be achieved. .
  • a resin having a low viscosity in a semi-cured state is used for the resin layer from the beginning, it may be merely cured by heating.
  • the electrodes can be reliably brought into contact with each other first at the time of joining, and reliable joining between the electrodes can be achieved.
  • the resin can be reliably filled without generating a void between the electrodes.
  • a desired bonding state between the wafers can be reliably obtained.
  • the method for bonding semiconductors according to the present invention as described above is particularly suitable when the semiconductor is a wafer.
  • the present invention is not limited to wafers, but includes, for example, IC chips, semiconductor chips, optical elements, various semiconductor mounted components, resin substrates, glass substrates, film substrates, and the like, regardless of the type or size, and is included in the category called semiconductor. Applicable to everything.
  • the laminated semiconductor according to the present invention is formed by the above-described method of bonding semiconductors.
  • the semiconductor is a laminated semiconductor, which is a wafer.
  • it is suitable for manufacturing a laminated semiconductor having a three-dimensional circuit configuration in which three or more semiconductors are laminated.
  • FIG. 1 is a schematic flow chart of a wafer laminating step including a semiconductor bonding method according to one embodiment of the present invention.
  • FIG. 2 is a partial cross-sectional view of an opposing wafer showing an example of an electrode protruding state in the step of FIG.
  • FIG. 3 is a cross-sectional view around the electrodes in a state where the wafers of FIG. 2 are joined together.
  • c Figure 5 is a cross-sectional view around the electrodes of the wafer showing another example of an electrode protruded state formation, and cross-sectional view of yet around the wafer one electrode showing another example of an electrode protruded state form 5 because You.
  • FIG. 6 is a schematic configuration diagram showing an example of a state in which wafers whose bonding surfaces are not smooth are bonded to each other.
  • FIG. 7 is a schematic configuration diagram showing an example of temporary joining when the outer peripheral portion of the resin layer is formed high.
  • C is a schematic configuration diagram showing an example of full joining after temporary joining.
  • FIG. 9 is an enlarged schematic sectional view showing a state of lamination of wafers.
  • FIG. 10 is a schematic configuration diagram showing an example of cleaning the bonding surface of one wafer in one chamber.
  • FIG. 11 is a schematic configuration diagram showing an example in which wafers are subsequently aligned in the chamber of FIG.
  • FIG. 12 is a schematic configuration diagram showing an example in which wafers are subsequently joined in the chamber of FIG.
  • FIG. 13 is a schematic configuration diagram showing a conventional example of bonding wafers.
  • FIG. 1 shows a method for bonding semiconductors according to an embodiment of the present invention, particularly, a bonding method for bonding wafers to each other and finally forming a laminated wafer in which three or more wafers are laminated.
  • a metal electrode 2 to be in a through state in a later step is provided on a wafer substrate 1 made of silicon as a base material.
  • the entire surface of the wafer is collectively exposed by a mask aligner or the like on the silicon substrate 1
  • a resist 3 is formed, a portion other than the electrode forming portion is masked, and a non-masking portion 4 is etched.
  • the etching portion 5 is filled with a tribute electrode 6 and the resist 3 is removed to form the electrode 2.
  • a printing method in a vacuum that can be filled with a void dress can be used.
  • a predetermined circuit 7 is provided between the electrodes 2.
  • a conventionally known method can be used.
  • each electrode 2 is further extended upward on the silicon substrate 1 on which the predetermined circuit 7 is provided by the copper wiring or the like.
  • a resin such as polyimide is filled between the electrodes 2 and around the electrodes 2 on the silicon substrate 1 to form a resin layer 8.
  • the resin layer 8 is provided, for example, by screen printing, and is preferably printed in a vacuum so as not to generate voids or the like.
  • the resin layer 8 is formed, as shown in FIG. 2, at least one of the wafers to be joined together is formed so that the surface of each electrode 2 projects from the surface of the resin layer 8 (in the example of FIG. 2, Protruding on both wafers), the rewiring layer 9 of the present invention is formed.
  • the rewiring layer forming step (3) two wafers 10a and 10b to be bonded to each other are created when the wafers are bonded to each other.
  • the wafers 10a and 10b are subjected to a wafer-stacking step 1 by bonding.
  • a method of removing the resin around the electrode 2 by the pressure of a squeegee in screen printing of the resin layer 8, or filling the resin using the properties of the resin itself Thereafter, a method in which the resin is shrunk to relatively protrude the electrode 2 can be adopted.
  • a method in which the electrode 2 is protruded by a separate method is also applicable.
  • the resin layer can be dented by dry or wet etching.
  • the bonding surfaces of the wafers 10a and 10b are opposed to each other.
  • both bonding surfaces are irradiated with energy waves or energy particles to clean the surfaces, and both wafers 10a and 10b are positioned at predetermined positions. After the alignment, the bonding surfaces of the cleaned wafers 10a and 10b are bonded together.
  • the cleaning is performed by irradiating the ion beam 12 from the irradiation unit 11. I have.
  • both bonding surfaces can be cleaned substantially simultaneously. After the bonded surfaces are aligned with the cleaned wafers 10a and 10b close to a predetermined distance, the wafers 10a and 10b are pressure-welded.
  • voids 13 and 14 recessed from the surface of the resin layer 8 are formed around the electrode 2 protruding from the surface of the resin layer 8. If the volume of the electrode portion 2 a protruding from the surface of the resin layer 8 and the volume of the voids 13 and 14 are formed to be approximately the same size, the electrodes 2 that have been crushed by pressure to increase the volume The joining portion fills the gap 13, and the state in which excess resin is pushed out can be avoided. In addition, the joint between the electrodes 2 can be easily pushed out, so that a desired favorable joint state can be obtained more reliably. Note that the voids 14 in FIG. 5 are formed by etching on the resin layer side.
  • the bonding surface 15 is wavy or a minute gap is easily formed, but in such a case, the bonding is performed with the pressurizing operation, so that the two wafers 10 a and 1 The bonding surface of 0b is securely adhered and bonded.
  • the wafers 10a and 10b whose surfaces have been cleaned by irradiation with energy waves or energy particles are surface-activated, so that they can be bonded well even at a low temperature. If more reliable bonding is desired, heating may be used in combination. However, high-temperature heating as in the case of the conventional hang junction is unnecessary, and low-temperature heating of 180 or less is required. Is enough. Also, the pressure applied between the joining surfaces is sufficient if a force capable of pushing and expanding the above-mentioned electrode contact portion is sufficient.
  • the electrodes can be joined by this surface activation, and the resin can be cured by heating. .
  • the resin can be pressed once while the viscosity is reduced by heating, and then expanded by pressing, followed by heating to cure the resin. it can.
  • the electrodes can be joined at a temperature in the range of room temperature to 100 ° C (normal temperature).
  • the outer periphery 18 of the resin layers 17a and 17b a, 18b are formed high, and the wafers 16a, 16b are surrounded by the outer peripheral portions 18a, 18b when the electrodes 19a, 19b are brought into contact with each other and joined.
  • the pre-joined portion is kept in a vacuum state and is temporarily joined, the actual joining can be performed at a high pressure in the final joining process as a subsequent process.
  • the main joining with a high pressure may be carried out successively with the same rice paddle, or may be carried out by a separate device. For example, as shown in Fig.
  • a method of performing the main joining with a high pressurizing force is a method using a high pressure chamber 20a (Fig. 8 (A)), a method using a breathing means 20b such as a hydraulic press (Fig. 8). 8 (B)), two laminated wafers 10a, 1a joined in the c- wafer laminating step 4 to which a method of applying pressure using a pair of pressure rolls 20c (FIG. 8 (C)) can be applied.
  • the surface on the side opposite to the bonding surface (the surface on the side of the silicon substrate 1) of the first wafer 1Ob is polished in the polishing step (1), and the through electrode 2 is exposed.
  • the surface on the rewiring layer side of the next wafer can be joined to the exposed surface of the electrode to laminate the next wafer.
  • the wafer Returning to the laminating step (1), the same laminating and joining operations as described above may be repeated for the required number of times (for the required number of sheets).
  • the semiconductor circuit surface is covered with resin, there is no charge-up due to cleaning ions in bonding, no reattachment of impurities due to etching, etc., and there is no effect on the circuit surface. For this reason, bonding can be performed even in semiconductors that require delicate handling without being able to perform surface activated bonding. What The number of layers is not limited to three or more, but may be two.
  • bumps 40 are provided on the exposed electrodes on the polished surface of the lowermost wafer to take out connection terminals or joint terminals with other components.
  • a laminated wafer is formed in which a first wafer 10a, a second wafer 10b, a third wafer 10c, and a fourth wafer 10d are sequentially bonded.
  • both the penetrating electrode 2b and the non-penetrating electrode 2c are often provided.
  • the first layer wafer 10a may not have a through electrode as shown in the figure.
  • a penetrating electrode 2b is provided together with an electrode 2c that does not penetrate, and the penetrating electrode 2 may be provided so that it can be electrically connected to an electrode of a lower wafer.
  • only the through electrodes are provided in the third and subsequent layers.
  • the common electrode or heat dissipation post is directly bonded to the wafer.
  • MCM multi-chip module
  • An example of an application is a semiconductor packaged as a system LSI by stacking four memory chips and mounting an RF chip, an arithmetic processing chip, a high-frequency chip, a communication chip, and an optical element. If a bump is formed at the bottom, it becomes a SIP (system-in-package) chip for a bare chip.
  • the cleaning, alignment, and pressure bonding in the wafer laminating step (1) can be performed in one chamber, for example, a vacuum chamber, as shown in FIGS. 10 to 12, for example.
  • FIG. 10 shows a cleaning step.
  • the upper wafer 10 a is held by the holding means 21, and the lower wafer 10 b is held by the holding means 22.
  • the bonding surfaces of the two wafers 10a and 10b are arranged and held in the chamber 23 so as to face each other as described above.
  • the chamber 23 is a true chamber capable of reducing the degree of vacuum in the chamber 23 to 13 0 X 10 _ 3 Pa or less, for example. Members.
  • This chamber 23 is irradiated with an energy wave or energy particle from the side into a gap 14 formed between the opposed wafers 10a and 1Ob.
  • One irradiation means 25 for substantially simultaneously cleaning the bonding surface of 10b is provided, and in the present embodiment, the irradiation means 25 comprises means for irradiating the ion beam 26. .
  • Ion beam 2 6, as described above, is irradiated in a state where the degree of vacuum in the chamber 2 3 below 1 3 0 X 1 0- 3 P a.
  • irradiation is further performed in an inert gas atmosphere such as an argon gas atmosphere.
  • the holding means 22 for the lower wafer 1 Ob is formed in a disk shape, and is preferably moved up and down in the plane direction and the rotation direction by the position adjusting means 27 arranged around the periphery. As for the direction, the position can be adjusted.
  • the holding means 22 can be moved up and down by the elevating means 28.
  • the facing surface 29 of the irradiation port 15a of the irradiation means 25 is inclined in a direction to prevent the reflection of the ion beam 26 as an irradiation energy wave or energy particle in the direction of the gap 24. Have been.
  • a suction means 30 composed of a vacuum pump or the like is further connected to the inclined opposing surface 29 to remove impurities generated from the wall surface by the reflection or etching by irradiation of the ion beam 26.
  • the reflection and flight in the gap 24 direction can be more reliably prevented, and the adhesion of these impurities to the bonding surface can be prevented.
  • the suction means 3 0, the degree of vacuum in the chamber 2 3 1 3 0 X 1 0- 3 P wafer 1 which is also capable der cleaning also serve as a vacuum suction means for a below 0 a, 1 0 b is For example, as shown in FIG. 11, the alignment process is performed to adjust the relative positions of the two within a predetermined positional accuracy.
  • the lower wafer 10b is raised together with the holding means 22 by the elevating means 28, and is brought close to the upper wafer 10a with a small gap.
  • the relative positions of both wafers 10a and 10b are adjusted within a predetermined accuracy range.
  • the recognition marks for alignment provided on both wafers 10a and 10b or the holding means 21 and 22 thereof are read, and the relative positional relationship between the two at that time is read. Is detected.
  • an infrared light source 32 is placed above, as shown by the two-dot chain line in Fig. 11, and the infrared rays emitted from above are held by the holding means 21, 22, and both wafers 10.
  • a, 10b may be transmitted, and each recognition mark may be detected by the infrared camera 33 via the transmitted infrared rays.c
  • the alignment can be performed without passing through the laminated wafer, which is preferable.
  • Reading of the alignment recognition mark is not limited to infrared rays, and may be performed by other means. For example, use of X-rays or visible light is also possible.
  • Reference numeral 34 in FIG. 11 denotes an annular or cylindrical bellows, which is provided on the upper holding means 21 side in the present embodiment for the next pressure joining step.
  • the gap between the lower end of the bellows 34 and the lower holding means 22 is opened with a gap.
  • a bonding step by pressure is started, for example, as shown in FIG.
  • the lower wafer 10b is raised together with the holding means 22 by the elevating means 28, and the bonding surfaces of the upper wafer 10a and the lower wafer 10b are brought into contact with each other.
  • the bellows 34 is also lowered, and the lower end of the bellows 34 or a crimping member provided thereon is pressed against the upper surface of the holding means 22 to form a space 35 between the upper and lower holding means 21, 22. Is closed in a sealed state.
  • the space 35 between the holding means 2 1, 2 2, the chamber 2 3 space 3 6 otherwise, both predetermined vacuum state (e.g., vacuum 1 above 3 0 X 1 0- 3 State below Pa).
  • both bonding surfaces are kept clean by washing, and the inclination of the facing surface 29 of the irradiation port 25a of the chamber 23 prevents reflection of impurities generated by etching to the bonding portion due to the inclination. As a result, impurities are prevented from being mixed into the junction, and an excellent junction state without impurities can be obtained.
  • the joining is performed in a vacuum state in the space 35, the possibility that voids or the like are generated or remain in the joining portion is substantially eliminated.
  • a pressing operation is applied during bonding, and the position adjusting means 27 with the holding means 22 can be separated, and pressure is applied following the wafer bonding surface, so that there is a non-smooth portion on the bonding surface. Even if an appropriate pressure is applied, the joining surfaces are surely brought into close contact with each other over a predetermined area, and a desired good joining state can be obtained. In the case of thin-film wafers in particular, laminating thin films or performing high-temperature heat treatment may cause the surface of the wafer to become non-smooth.
  • the desired good bonding state can be obtained by pressing. When heating is performed, the heater can be used together by embedding a heater in the wafer holding means.
  • the internal pressure in the spaces 35 and 36 in the chamber 23 may be returned to the atmospheric pressure, and the joined object may be taken out from the chamber 23.
  • the next wafer may be sequentially stacked and bonded to the stacked body of the previously bonded wafers.
  • the method for bonding semiconductors according to the present invention can be applied to all methods for bonding semiconductors having a resin layer formed on at least one semiconductor surface, and is particularly suitable for a method for layering and bonding wafers.
  • a laminated semiconductor bonded by this method particularly a laminated wafer in which three or more wafers are laminated, it is possible to obtain a laminated semiconductor having a three-dimensional circuit configuration.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé de liaison de semi-conducteurs, selon lequel des électrodes sont exposées sur les surfaces par disposition d'une résine autour d'une électrode sur la surface d'au moins un semi-conducteur, de manière à former une couche de résine, à former en saillie l'électrode sur le semi-conducteur à partir de la surface de la couche de résine, à amener les électrodes sur les semi-conducteurs en contact entre elles, à les comprimer entre elles pour provoquer la dilatation des parties de contact, et à amener la surfaces de la couche de résine en contact avec la surface de l'autre semi-conducteur. Cette invention a également trait à un semi-conducteur multicouches élaboré au moyen de ce procédé. Ledit procédé permet aussi la liaison de semi-conducteurs, notamment de plaquettes, la prévention de comportements non souhaités de la résine de revêtement de surface. Les électrodes métalliques sont liées de manière fiable. En outre, il est possible de lier fiablement des surfaces de liaison prédéterminées à des températures basses sans formation de vide.
PCT/JP2003/001848 2002-02-22 2003-02-20 Procede de liaison de semi-conducteurs et semi-conducteur multicouches ainsi fabrique WO2003071604A1 (fr)

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JP2002046087A JP2003249620A (ja) 2002-02-22 2002-02-22 半導体の接合方法およびその方法により作成された積層半導体

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CN100355034C (zh) * 2004-11-08 2007-12-12 北京邮电大学 晶片键合表面处理剂及晶片键合方法
CN102376664A (zh) * 2010-08-09 2012-03-14 三菱电机株式会社 半导体装置、半导体电路基板以及半导体电路基板的制造方法
TWI764681B (zh) * 2021-02-26 2022-05-11 台灣積體電路製造股份有限公司 半導體封裝及封裝組件及製造方法

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DE102004034421A1 (de) * 2004-07-15 2006-02-09 Pac Tech - Packaging Technologies Gmbh Verfahren und Vorrichtung zur wechselseitigen Kontaktierung von zwei Wafern
JP4826408B2 (ja) * 2006-09-21 2011-11-30 富士通株式会社 接合用基板と半導体装置
KR100945504B1 (ko) * 2007-06-26 2010-03-09 주식회사 하이닉스반도체 스택 패키지 및 그의 제조 방법
JP2009049051A (ja) * 2007-08-14 2009-03-05 Elpida Memory Inc 半導体基板の接合方法及びそれにより製造された積層体
JP5159273B2 (ja) * 2007-11-28 2013-03-06 ルネサスエレクトロニクス株式会社 電子装置の製造方法
KR100986175B1 (ko) * 2008-05-29 2010-10-07 앰코 테크놀로지 코리아 주식회사 반도체 장치 제조 방법
JP5508111B2 (ja) 2010-04-20 2014-05-28 株式会社ディスコ 半導体装置の製造方法
JP5570298B2 (ja) * 2010-05-21 2014-08-13 株式会社ディスコ ウエーハの加工方法
JP2011243906A (ja) 2010-05-21 2011-12-01 Disco Abrasive Syst Ltd ウエーハの加工方法
JP5544228B2 (ja) 2010-07-14 2014-07-09 株式会社ディスコ ウェーハの加工方法
JP5917850B2 (ja) * 2011-08-01 2016-05-18 株式会社ディスコ ウエーハの加工方法
JP5955635B2 (ja) 2012-05-11 2016-07-20 株式会社ディスコ 洗浄装置
JP2021044347A (ja) 2019-09-10 2021-03-18 キオクシア株式会社 半導体装置
JP2023049827A (ja) 2021-09-29 2023-04-10 株式会社ディスコ 積層デバイスチップの製造方法
JP2023109616A (ja) 2022-01-27 2023-08-08 株式会社ディスコ ウエーハの製造方法

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CN102376664A (zh) * 2010-08-09 2012-03-14 三菱电机株式会社 半导体装置、半导体电路基板以及半导体电路基板的制造方法
TWI764681B (zh) * 2021-02-26 2022-05-11 台灣積體電路製造股份有限公司 半導體封裝及封裝組件及製造方法
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