TWI600095B - 用於具有晶粒對晶粒第一接合的半導體裝置封裝的方法和系統 - Google Patents

用於具有晶粒對晶粒第一接合的半導體裝置封裝的方法和系統 Download PDF

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TWI600095B
TWI600095B TW102141433A TW102141433A TWI600095B TW I600095 B TWI600095 B TW I600095B TW 102141433 A TW102141433 A TW 102141433A TW 102141433 A TW102141433 A TW 102141433A TW I600095 B TWI600095 B TW I600095B
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die
interposer
semiconductor dies
semiconductor
dies
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TW102141433A
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TW201430972A (zh
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麥可Ｇ 凱利
羅納 派翠克 休莫勒
杜旺朱
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艾馬克科技公司
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    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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Description

用於具有晶粒對晶粒第一接合的半導體裝置封裝的方法和系統 【相關申請案之交互參照/納入參考】
此申請案係參考到2012年11月15日申請的美國申請案序號13/678,012(代理人文件編號25963US01)、2012年11月15日申請的美國申請案序號13/678,058(代理人文件編號25031US01)、以及2012年11月15日申請的美國申請案序號13/678,046(代理人文件編號25032US01)。
以上所引用的申請案的每一個茲在此以其整體納入作為參考。
本發明的某些實施例係有關於半導體晶片封裝。更明確地說，本發明的某些實施例係有關於一種用於具有晶粒對晶粒第一接合的半導體裝置封裝的方法和系統。
半導體封裝係保護積體電路或晶片免於物理性損壞以及外部的應力。此外，其可以提供一導熱路徑以有效率地移除在一晶片中所產生的熱，並且例如亦提供電連接至其它例如是印刷電路板的構件。用於半導體封裝的材料通常包括陶瓷或塑膠，並且外觀形狀尺寸已經從陶瓷扁平封裝及雙排型封裝進步到尤其是針柵陣列及無引線的晶片載體封裝。
透過此種系統與如同在本申請案的其餘部分中參考圖式所闡述的本發明比較，習知及傳統的方法的進一步限制及缺點對於具有此項技術的技能者而言將會變成是明顯的。
本發明的一態樣為一種用於半導體封裝之方法，該方法係包括：接合包括電子裝置的一或多個半導體晶粒至一中介層晶粒；在該一或多個半導體晶粒以及該中介層晶粒之間施加一底膠填充材料；施加一模製材料以囊封接合的該一或多個半導體晶粒；薄化該中介層晶粒以露出直通矽晶穿孔(TSV)；施加金屬接點至露出的該TSV；以及將具有接合的該一或多個半導體晶粒的該中介層晶粒接合至一封裝基板。
本發明的另一態樣為一種用於半導體封裝之方法，該方法係包括：在一晶粒對晶粒的第一接合製程中產生一半導體封裝，該製程包括：接合包括電子裝置的一或多個半導體晶粒至一中介層晶粒；在該一或多個半導體晶粒以及該中介層晶粒之間施加一底膠填充材料；施加一模製材料以囊封接合的該一或多個半導體晶粒；薄化該中介層晶粒以露出直通矽晶穿孔(TSV)；施加金屬接點至露出的該TSV；以及將具有接合的該一或多個半導體晶粒的該中介層晶粒接合至一封裝基板。
本發明的另一態樣為一種用於半導體封裝之方法，該方法係包括：在一晶粒對晶粒的第一接合製程中產生一半導體封裝，該製程包括：將包括電子裝置的一或多個半導體晶粒的一第一表面設置在一黏著層上；將該一或多個半導體晶粒的一相反的表面接合至一中介層晶粒；從該一或多個半導體晶粒的該第一表面移除該黏著層；在該一或多個半導體晶粒以 及該中介層晶粒之間施加一底膠填充材料；施加一模製材料以囊封接合的該一或多個半導體晶粒；以及將具有接合的該一或多個半導體晶粒的該中介層晶粒接合至一封裝基板。
100‧‧‧封裝
101‧‧‧積體電路晶粒
103‧‧‧封裝基板
105‧‧‧被動元件
107‧‧‧中介層晶粒
109‧‧‧微凸塊
111‧‧‧焊料球
113‧‧‧蓋子
115‧‧‧直通矽晶穿孔(TSV)
117‧‧‧背面凸塊
118‧‧‧熱介面材料
119‧‧‧墊
121‧‧‧動態隨機存取記憶體(DRAM)(晶粒)
123‧‧‧金屬互連
125‧‧‧底膠填充材料
127‧‧‧中介層
129‧‧‧黏著層
131‧‧‧金屬墊
150‧‧‧封裝
201‧‧‧中介層晶粒
203A、203B‧‧‧半導體晶粒
205‧‧‧微凸塊
207‧‧‧直通矽晶穿孔(TSV)
209‧‧‧前側墊
210‧‧‧底膠填充材料
211‧‧‧模製材料
213‧‧‧背面凸塊
215‧‧‧封裝基板
219‧‧‧接觸墊
221‧‧‧蓋子
225‧‧‧黏著劑
227‧‧‧焊料球
301、303A、303B、305A、305B、307、309、311、313‧‧‧步驟
401‧‧‧晶舟
403‧‧‧夾子
405‧‧‧半導體晶粒
407‧‧‧中介層
501‧‧‧晶舟
505‧‧‧半導體晶粒
507‧‧‧中介層
509‧‧‧真空密封環
511‧‧‧真空通道
513‧‧‧閥
515‧‧‧真空源
601‧‧‧載體晶圓
603‧‧‧晶圓
605‧‧‧背面凸塊
607‧‧‧聚合物層
609A‧‧‧頂端夾頭
609B‧‧‧底部夾頭
611‧‧‧膜框架
701‧‧‧頂端半導體晶粒
703‧‧‧微凸塊
705‧‧‧底部半導體晶粒
707‧‧‧接觸墊
709‧‧‧底膠填充層
711‧‧‧井
圖1A是描繪根據本發明的一範例實施例的一種被配置有一晶粒到晶圓的第一接合之積體電路封裝之概要圖。
圖1B是描繪根據本發明的一範例實施例的一種被配置有一中介層到晶圓的第一接合以及堆疊的晶粒之積體電路封裝之概要圖。
圖1C-1E係描繪根據本發明的一範例實施例的用於利用一黏著膜來接合多個晶粒的步驟。
圖2A-2F係描繪在根據本發明的一範例實施例的一晶粒對晶粒的第一接合結構中的步驟。
圖3是描繪在根據本發明的一範例實施例的一晶粒對晶粒的第一接合製程中的步驟之概要圖。
圖4是描繪根據本發明的一範例實施例的一機械式平坦化裝置之圖。
圖5是描繪根據本發明的一範例實施例的一真空平坦化裝置之圖。
圖6A-6E係描繪根據本發明的一範例實施例的用於脫黏具有大的背面凸塊的晶圓之步驟。
圖7是描繪根據本發明的一範例實施例的利用一圖案化的底膠填充層的晶粒接合之圖。
本發明的某些特點可見於一種用於一具有一晶粒對晶粒的第一接合的半導體裝置封裝之方法及系統。本發明的範例特點可包括接合一或多個包括電子裝置的半導體晶粒至一中介層(interposer)晶粒。一種底膠填充(underfill)材料可被施加在該一或多個半導體晶粒以及該中介層晶粒之間，並且一種模製材料可被施加以囊封該一或多個接合的半導體晶粒。該中介層晶粒可被薄化以露出直通矽晶穿孔(TSV)。金屬接點可被施加至該露出的TSV，並且具有該接合的一或多個半導體晶粒的中介層晶粒可被接合到一封裝基板。該一或多個半導體晶粒的接合可包括：將該一或多個半導體晶粒附著到一黏著層；以及將該黏著的一或多個半導體晶粒接合至該中介層晶粒。該一或多個半導體晶粒可包括用於耦接至該中介層晶粒的微凸塊，其中該接合係包括定位該微凸塊在一設置在該中介層晶粒上的層中之個別的井中，以及接合該微凸塊至該中介層晶粒。該底膠填充材料可利用一毛細管底膠填充製程來加以施加。該一或多個半導體晶粒可以利用一質量回焊製程或是一熱壓縮製程而被接合至該中介層晶粒。該一或多個額外的半導體晶粒可以利用一質量回焊製程而被接合至該一或多個半導體晶粒。一或多個額外的半導體晶粒可利用一熱壓縮製程而被接合至該一或多個半導體晶粒。該模製材料可包括一種聚合物。該一或多個半導體晶粒的接合可包括設置該一或多個半導體晶粒以及該中介層晶粒在一固定裝置中，該固定裝置係容許該一或多個半導體晶粒以及該中介層晶粒在一方向上彎曲，而不是在一相反的方向上彎曲，以及透過一回焊製程來處理該一或多個半導體晶粒以及該中介層晶粒。
圖1A是描繪根據本發明的一範例實施例的一種被配置有一 晶粒到晶圓的第一接合之積體電路封裝之概要圖。參照圖1A，其係展示有一種封裝100，其係包括積體電路晶粒101、一封裝基板103、被動元件105、一中介層晶粒107、焊料球111、一蓋子113以及熱介面材料118。
該晶粒101可包括已經從一或多個半導體晶圓分開的積體電路晶粒。例如，該晶粒101可包括像是數位信號處理器(DSP)、網路處理器、電源管理單元、音訊處理器、RF電路，無線基頻系統單晶片(SoC)處理器、感測器以及特殊應用積體電路之電路。此外，該複數個晶粒101可包括微凸塊109，以用於在該複數個晶粒101中的電路以及在該中介層晶粒107的表面上的接觸墊之間提供電性接觸。
該中介層晶粒107可包括一例如是矽晶粒的半導體晶粒，其具有提供從該中介層晶粒107的一表面至相對的表面之導電的路徑之直通矽晶穿孔(TSV)115。該中介層晶粒107亦可包括用於達成電性及機械的接觸至該封裝基板103之背面凸塊117。在另一範例情節中，該中介層晶粒107可包括玻璃或是一種有機積層材料，任一種材料都能夠具有例如是500x500mm的數量級的大面板格式。
該封裝基板103可包括一用於該中介層晶粒107、晶粒101、被動元件105、以及蓋子113的機械式支承結構。例如，該封裝基板103可包括在底表面上的焊料球111，以用於提供電性接觸至外部的裝置及電路。該封裝基板103亦可包括在一種非導電材料中之導電的線路以用於經由墊來提供從該焊料球至該晶粒101的導電的路徑，該墊被配置以接收該中介層107上的背面凸塊117。此外，該封裝基板103可包括用於接收該焊料球111的墊119。例如，該墊119可包括一或多種凸塊下的金屬，以用於在該 封裝基板103以及該焊料球111之間提供一適當的電性及機械的接觸。
例如，該被動元件105可包括例如是電阻器、電容器及電感器的電性元件，其可以提供功能給在該晶粒101中的元件及電路。該被動元件105可包括可能是難以整合在該晶粒101中的積體電路內之元件，例如高值的電容器或電感器。在另一範例情節中，該被動元件105可包括一或多個晶體振盪器，以用於提供一或多個時脈信號至該晶粒101。
該蓋子113可提供氣密密封給在藉由該蓋子113以及封裝基板103所界定的凹處內之元件。一熱介面可被產生以用於從該晶粒101經由該熱介面材料118來將熱傳出至該蓋子113，該熱介面材料118亦可作用為一黏著劑。
在一範例情節中，當該中介層晶粒107包括一個別的晶粒時，該封裝100可藉由第一接合該晶粒101至該中介層晶粒107來加以製造，並且可利用一質量回焊或是熱壓縮製程來加以接合。在其中該晶粒101是利用一質量回焊製程來接合的實例中，在該中介層晶粒107上的背面凸塊若存在的話，其亦可被回焊。於是，該晶粒101可在該背面凸塊117被設置之前先被接合至該中介層晶粒107。該具有附接的晶粒101之中介層晶粒107可加以處理，以供進一步組裝。例如，該中介層晶粒107可被薄化(例如，在上述的晶粒接合之前或之後)以露出該直通矽晶穿孔(TSV)115，並且該背面凸塊117可加以沉積。再者，在一模製製程被利用以囊封該複數個晶粒101之前，一種毛細管底膠填充材料可被置放在該晶粒101以及該中介層晶粒107之間(例如，在一其中利用一種非導電膏及/或帶的底膠填充並未在該接合製程期間被執行的範例情節中)。
包括該晶粒101以及該中介層晶粒107的組件可以如上所述地加以處理，並且該組件接著例如可利用一質量回焊或是熱壓縮製程的任一種而被接合至該封裝基板103。該蓋子113可被置放在該接合的組件上以提供氣密密封，保護該電路不受外部環境的影響，且/或作為一散熱器。最後，電性測試可在該接合製程之後來加以執行，以驗證是否達成適當的電連接並且沒有短路或開路存在。
圖1B是描繪根據本發明的一範例實施例的一種被配置有一晶粒對晶粒的第一接合以及堆疊的晶粒之積體電路封裝之概要圖。參照圖1B，其係展示有一種封裝150，其包括該晶粒101、封裝基板103、被動元件105、中介層晶粒107以及動態隨機存取記憶體(DRAM)121的一堆疊。例如，該晶粒101、封裝基板103、被動元件105以及中介層晶粒107可以是實質如同相關圖1A所述者，但是對於該不同的晶粒101以及DRAM 121的堆疊係具有不同的電連接。
該DRAM 121可包括晶粒的一堆疊，以用於提供高密度的記憶體給在該晶粒101中的電路、或是在該封裝150外部的電路。該DRAM 121可以前後地加以堆疊，並且因此包括用於在該個別的晶粒之間提供電連接的TSV。
在一範例情節中，當該中介層晶粒107處於晶粒形式時，該封裝150可藉由第一接合該晶粒101以及該DRAM 121至該中介層晶粒107來加以製造。該晶粒101以及該DRAM 121可利用一質量回焊或是熱壓縮製程來加以接合。
在其中該晶粒101以及DRAM 121的堆疊是利用一質量回焊 製程加以接合的實例中，在該中介層晶粒107上的背面凸塊若存在的話，其亦可在該回焊製程時被回焊。於是，該晶粒101以及DRAM 121的堆疊可以在該背面凸塊117被設置之前先被接合至該中介層晶粒107。該具有附接的晶粒101之中介層晶粒107以及DRAM 121的堆疊可加以處理，以供進一步的組裝。例如，該中介層晶粒107可被薄化以露出該直通矽晶穿孔(TSV)115，並且該背面凸塊117可加以沉積。再者，在一模製製程被利用以囊封該晶粒101以及DRAM 121的堆疊之前，一種毛細管底膠填充材料可被置放在該晶粒101、DRAM 121的堆疊以及該中介層晶粒107之間(例如，在一其中利用一種非導電膏及/或帶的底膠填充並未在該接合製程期間被執行的範例情節中)。
電性測試可在該接合製程之後來加以執行，以驗證是否達成適當的電連接並且沒有短路或開路存在。再者，如同先前關於圖1A所敘述的，該組件可被接合至該封裝基板103並且接著加以包覆成型及/或裝蓋。
圖1C-1E係描繪根據本發明的一範例實施例的用於利用一黏著膜來接合多個晶粒的步驟。參照圖1C，其係展示有複數個晶粒121以及一黏著層129。該晶粒121可包括金屬互連123，以用於後續的接合至其它晶粒。在另一範例情節中，該金屬互連123例如可包括微凸塊或是銅柱。
例如，該黏著膜129可包括該晶粒121可被接合至其的一黏著帶或是柔性層，即例如在圖1C中所繪者。例如，該黏著膜129可以是一暫時性黏著劑，以用於將多個晶粒附接至一或多個其它晶粒。例如，該中介層127可包括一個別的中介層晶粒。在一範例情節中，該晶粒121可以暫時被置放在該黏著膜129上。
在利用該黏著膜129來將該晶粒121接合至該中介層127之前，一種選配的底膠填充材料125亦可被置放在該中介層127上，例如由圖1D中的底膠填充材料125所描繪者。該底膠填充材料125例如可被使用於後續的熱壓縮接合製程，並且可容許有在一後續的熱壓縮接合製程期間透過一快速固化之瞬間的底膠填充。此可以改善接合良率，因為相較於在一習知的製程中用在該晶粒121的每一個之一個別的置放及底膠填充製程，單一底膠填充製程可以被利用於該複數個晶粒121。該晶粒121可以面朝上地被置放，因而在該金屬互連123可耦接至一接收的晶粒。
例如在圖1D及1E中所示，在該黏著膜129上的晶粒121接著可被置放在該中介層127上，其中在該黏著膜129上的晶粒121之最初的設置可以致能細微的控制該晶粒121和該中介層127的間隔與對齊。在一範例情節中，該中介層127可被多端子接合(gang bond)至該個別的晶粒121。該中介層127可包括用於接收該金屬互連123的金屬墊131。一旦該晶粒121被設置在該中介層127上，一熱壓縮接合製程可以為了在該金屬互連123以及金屬墊131之間的適當電性及機械的接合來加以執行。一旦接合後，該黏著膜129可被移除，此係產生在圖1E中所示的結構。
圖2A-2F係描繪在根據本發明的一範例實施例的一晶粒對晶粒的第一接合結構中的步驟。參照圖2A，其係展示有一中介層晶粒201以及複數個半導體晶粒203A及203B。該半導體晶粒203A及203B可包括已經從一或多個半導體晶圓分開的積體電路晶粒。例如，該半導體晶粒203A及203B可包括像是數位信號處理器(DSP)、網路處理器、電源管理單元、音訊處理器、RF電路、無線基頻系統單晶片(SoC)處理器、感測器、以及特殊 應用積體電路之電路。
此外，該半導體晶粒203A及203B可包括微凸塊205，以用於在該半導體晶粒203A及203B中的電路以及在該中介層晶粒201的表面上的前側墊209之間提供電性接觸。儘管兩個晶粒被展示在圖2A-2F中，但本發明並非如此受限的，因為根據晶片面積而定之任意數目的晶粒都可被接合至該中介層晶粒201。
該中介層晶粒201可包括前側墊209，以用於提供電性接觸至該半導體晶粒203A及203B。再者，該中介層晶粒201例如可包括直通矽晶穿孔(TSV)207，以用於在該中介層晶粒201已經被薄化後，提供從該中介層的一表面至另一表面之導電的路徑。
該半導體晶粒203A及203B可被置放在該中介層晶粒201上，並且例如是利用一熱壓縮接合技術來加以接合。在另一範例情節中，一質量回焊製程可被利用來接合該半導體晶粒203A及203B。一種非導電膏(NCP)亦可被利用以協助形成該接合。此外，一毛細管底膠填充接著可被施加，並且可填入在該半導體晶粒203A及203B以及該中介層晶粒201之間的容積內。圖2B係描繪利用底膠填充材料210而被接合至該中介層晶粒201的半導體晶粒203A及203B。當沉積或置放該底膠填充材料210時，其例如可包括一膜、膏、b階段的膜、或是一液體。
例如在圖2C中所繪的，在該半導體晶粒203A及203B的個別周長之間及/或附近的空間可被填入以一種模製材料211。該模製材料211例如可包括一種聚合物材料，其可提供一非導電的結構支撐給被接合至該中介層晶粒201的晶粒，此係在後續的處理步驟中保護該晶粒。注意的是， 該模製材料211在各種的範例情節中都可覆蓋該半導體晶粒203A及203B中的一或多個的頂端。在一範例情節中，該中介層晶粒201例如可利用一背面拋光或研磨而被薄化，以露出該TSV 207。
儘管該底膠填充材料210被展示在圖2B-2F中，該模製材料本身亦可被利用作為用於例如是在該晶粒203A及203B以及該中介層晶粒201之間的每個耦接的介面之底膠填充材料。在另一範例實施例中，底膠填充材料可以用一種液體或膏而被***、用一膜或是一b階段的膜來加以置放，並且可以隨著每個晶粒至基板或是晶粒至晶粒的接合完成時依序地被置放、或是可以在所有的電性接合完成之後全部一次來加以完成。
在另一範例情節中，該中介層晶粒201可被薄化至一其中該TSV仍然稍微被覆蓋的厚度，其接著可選擇性地在覆蓋該TSV的區域中被蝕刻。一保護層接著可沉積在其餘的矽之上，並且該露出的金屬的一拋光可加以執行，以用於改善至該TSV 207的接觸。此外，為了與該背面凸塊213更佳的接觸，金屬墊可沉積在該拋光後的TSV的表面上。
在另一範例情節中，在接收該半導體晶粒203A及203B之前，該中介層晶粒201可以是已經被薄化並且包括該背面凸塊213。在此例中，像是被描繪在圖6A-6E中的結構支承件、黏著膜及膜框架例如可被利用以處理該中介層晶粒201。
如同在圖2D中所示，在該中介層晶粒201已經被薄化之後，該背面凸塊213可加以沉積，以用於在該TSV 207以及接著接合的基板(例如，封裝基板)之間達成接觸。
如同在圖2E中所繪，包括該半導體晶粒203A及203B以及 該中介層晶粒201的組件接著可經由該背面凸塊213而被接合至該封裝基板215。例如，該封裝基板215可包括一用於晶粒組件之機械式的支承結構，並且亦可支承被動元件以及一蓋子。該封裝基板215可包括接觸墊219，以用於和在該中介層晶粒201上的背面凸塊213達成接觸並且亦用於焊料球227(或是替代的結構)之後續的設置，即如同在圖2F中所示者。
此外，該蓋子221可被置放在該封裝組件上，其中係和一在該封裝基板215的表面之黏著劑225做成一氣密密封，該蓋子221亦可包括一種熱介面材料。於是，為了散熱之目的，該蓋子221可以接觸到該半導體晶粒203A及203B的頂表面(例如，直接或是透過一種熱介面材料)。該焊料球227例如可包括用於和一印刷電路板達成電性及機械的接觸之金屬球體。
圖3是描繪在根據本發明的一範例實施例的一種晶粒對晶粒的第一接合製程中的步驟之概要圖。參照圖3，其係展示有一種晶粒對晶粒製程，其係開始以一晶粒至中介層晶粒的附接步驟301。例如，該一或多個晶粒可利用一熱壓縮接合技術或是一質量回焊製程來加以接合。在圖3所示的例子中，一質量回焊製程被利用。額外的晶粒亦可被接合至該第一接合的晶粒，例如由圖1B中所示的DRAM 121的堆疊所描繪者、或是如同在圖1A中所示的中介層晶圓。
在該晶粒被設置在該中介層晶粒上之後，該組件接著可受到一回焊製程303A，其中該組件可被加熱以在金屬互連之間提供一適當的電性及機械的連接。一底膠填充製程305A可在該接合製程之後被利用(例如，在一其中底膠填充並未在該接合製程期間發生的範例情節中)，其可提供在 接點之間的一絕緣的阻障，並且可以填入在該晶粒以及該中介層晶圓之間的容積內。
例如，在該背面加工步驟309中的薄化該中介層晶粒以露出該TSV之前，一模製步驟307接著可被利用以封裝該晶粒/中介層組件。此外，背面接點可被施加至在該中介層晶圓中之露出的TSV(例如，在一其中此種接點先前尚未被形成的範例情節中)。
一旦該背面接點被設置後，該組件可以在該附接晶粒堆疊至基板的步驟311中被附接至一封裝基板。此接著可以是一用於產生適當的電性及機械的接合至該封裝基板的第二回焊步驟303B、以及一用於填充在該晶粒及中介層組件以及該封裝基板之間的容積內的底膠填充步驟305B。最後，該接合的封裝可受到一最終的測試步驟313以用於評估在該接合的晶粒中的電子電路的效能並且測試在該接合製程中所完成的電性接點。
圖4是描繪根據本發明的一範例實施例的一種機械式平坦化裝置之圖。參照圖4，其係展示有一晶舟401、夾子403、複數個半導體晶粒405、以及一中介層407，其中該中介層407可以是處於晶粒形式。該晶舟401可包括一剛性支承結構或是固定裝置，其中一晶粒/中介層組件可藉由該夾子403而被置放且保持在適當的地方。該晶舟401可以是能夠承受用於處理該晶粒/中介層組件的高溫，例如是超過200℃。
當該中介層407處於晶粒形式時，該複數個半導體晶粒405在被置放在該晶舟401中之前，例如可經由一熱壓縮接合技術而被接合至該中介層407。隨著該晶舟401、複數個半導體晶粒405、以及中介層407的溫度增高，在該夾子403在該組件的外部邊緣提供一向下的力之下，包 括該複數個半導體晶粒405以及中介層407的一組件之曲率可能會變平。隨著該曲率接近零，在橫向的方向上增大的長度可藉由該組件在該夾子403之下的滑動而被容納。此外，該晶舟401係結合該夾子403之向下的力來提供機械式的支撐，藉此平坦化該組件。
該晶舟401以及夾子403可以允許該部分組裝的封裝以正常的方式加熱，但是當該晶粒/中介層組件已經在增高的溫度下變成平坦時，該晶舟401以及夾子403係抵抗翹曲的正常發展，此係保持該部分組裝的封裝，在加熱期間使其變平並且接著隨著溫度上升而維持該矽中介層的該平坦度。
圖5是描繪根據本發明的一範例實施例的一種真空平坦化裝置之圖。參照圖5，其係展示有一晶舟501、複數個半導體晶粒505、一中介層507、真空密封環509、真空通道511、一閥513、以及一真空源515。
在一範例情節中，該晶舟501可包括一真空系統或是固定裝置，以在該中介層507處於晶粒形式時，將包括該複數個半導體晶粒505以及中介層507之部分組裝的封裝變平。該真空機械式的系統係允許該部分組裝的封裝以正常的方式加熱，但是當該部分組裝的封裝已經變成平坦時，該真空機械式的系統係抵抗翹曲的正常發展，此係在加熱期間保持該部分組裝的封裝處於一變平的形態並且接著隨著溫度增高而維持該矽中介層晶粒507的該平坦度。
該真空可以在室溫或是稍微升高的溫度下，利用該真空源515經由該閥513以及真空通道511而被施加，並且可利用該高溫的密封環509來加以保持，因而該真空機械式的晶舟501可行進通過一標準的回焊爐 並且仍然維持充分的真空，以維持中介層矽的頂表面之平面性。
圖6A-6E係描繪根據本發明的一範例實施例的用於脫黏具有大的背面凸塊的晶圓之範例步驟。參照圖6A，其係展示有一載體晶圓601、一具有背面凸塊605的晶圓603、以及一聚合物層607。
例如，該晶圓603可包括一電子元件晶圓或是一中介層晶圓，其可包括在脫黏製程中可能容易受損的大的背面凸塊605。於是，該聚合物層607可被施加以在脫黏製程期間保護該背面凸塊605。例如，該聚合物層607可包括一種抗蝕材料或是一黏著膜或帶，其可被施加在該元件晶圓603的背面凸塊605之上。儘管晶圓被展示在圖6A中，該技術亦可被利用在晶粒上。
例如利用一真空技術之後續的夾頭附著至該載體晶圓601以及該聚合物層607的頂表面被展示在圖6B中。該頂端夾頭609A可被移動在一橫向的方向上，同時該底部夾頭609B可被移動在相反的方向上，以分開該載體晶圓601與該晶圓603。該聚合物層607可以致能一適當的真空密封至該表面，其中當真空直接施加至該背面凸塊605時，其可能是一劣質的密封。
圖6C係展示在從該載體晶圓601脫黏後之一產生的結構。當該載體晶圓601仍然附接至該頂端夾頭609A時，從該載體晶圓601剩下的任何黏著劑殘留物都可在一清洗製程中加以移除。
如同在圖6D中所示，在該背面凸塊605面朝上並且從該頂端夾頭609A分離下，該被清洗後的結構接著可被黏貼至一膜框架611。該聚合物層607接著可以用化學或是熱的方式來加以移除，並且之後可進行 一表面清洗，此係產生例如在圖6E中所示之接合的晶圓603。該膜框架611可以致能進一步處理以及便於該接合的晶圓603的傳輸。
圖7是描繪根據本發明的一範例實施例的利用一圖案化的底膠填充層的晶粒接合之圖。參照圖7，其係展示有一具有微凸塊703的頂端半導體晶粒701以及一包括接觸墊707以及一底膠填充層709的底部半導體晶粒705。
在一範例情節中，該微凸塊703例如可包括銅柱，並且可對應於在該底部半導體晶粒705中的接觸墊707。儘管該底部半導體晶粒705被展示為單一晶粒，但是在另一範例情節中，其可包括一整個晶圓的晶粒(例如，一中介層晶圓)，其中相對於單一晶粒，複數個頂端半導體晶粒701被接合至該晶圓。在一範例情節中，該底部半導體晶粒705係包括單一中介層晶粒。該底膠填充層709可包括一種施加至該底部半導體晶粒705的頂表面之聚合物，例如是頂端半導體晶粒701之下一層級的晶粒將會被接合至該頂表面。該聚合物可包括一再保護或是預先施加的底膠填充，其將會流動且接合至兩個晶粒表面，此係除去對於後續的底膠填充製程之需求。
再者，該底膠填充層709可利用微影技術或是雷射剝蝕而被圖案化以產生該井711，藉此在該底部半導體晶粒705中露出適當的接觸墊707，例如是藉由在該底膠填充層709中形成井。該底膠填充層709可包括一膜，其中該開口例如可包括利用雷射剝蝕或是微影技術所產生的完全深度的凹穴或是部分深度的凹穴。例如，在該部分深度的凹穴中剩餘的材料可有助於該頂端晶粒701至該底部晶粒705的接合製程。
該露出的墊可被利用以將該頂端半導體晶粒701對準到該 底部半導體晶粒705。該晶粒例如可利用一熱壓縮或是質量回焊技術而被接合。一助焊劑浸漬(flux dip)可被利用以助於焊料從一表面至另一表面的潤濕，並且該底膠填充可以“快速固化”並且密封至該頂端及底部晶粒表面兩者。再者，該底膠填充可以在該接合製程期間，在該微凸塊703以及接觸墊707之下到處流動。
在本發明的一範例實施例中，方法被揭示以用於一具有一晶粒對晶粒的第一接合的半導體裝置封裝。就此點而言，本發明的特點可包括接合一或多個包括電子裝置的半導體晶粒101、121、203A、203B、405、505、701至一中介層晶粒107、201。一種底膠填充材料210可被施加在該一或多個半導體晶粒101、121、203A、203B、405、505、701以及該中介層晶粒107、201之間，並且一種模製材料211可被施加以囊封該一或多個接合的半導體晶粒101、121、203A、203B、405、505、701。在其中該底部半導體晶粒705包括一中介層晶粒的實例中，該中介層晶粒107、201及705可被薄化以露出直通矽晶穿孔(TSV)115、207。在其中該底部半導體晶粒705包括一中介層晶粒的實例中，金屬接點213可被施加至該露出的TSV 115、207以及該中介層晶粒107、201及705，其中該接合的一或多個半導體晶粒101、121、203A、203B、405、505、701可被接合至一封裝基板103、215。
該一或多個半導體晶粒101、121、203A、203B、405、505、701的接合可包括：將該一或多個半導體晶粒101、121、203A、203B、405、505、701附著至一黏著層611；以及在其中該底部半導體晶粒705包括一中介層晶粒的實例中，接合該黏著的一或多個半導體晶粒101、121、203A、203B、405、505、701至該中介層晶粒107、201及705。該一或多個半導體 晶粒101、121、203A、203B、405、505、701可包括微凸塊109、205、703，以用於在其中該底部半導體晶粒705包括一中介層晶粒的實例中耦接至該中介層晶粒107、201及705，其中該接合係包括：在其中該底部半導體晶粒705包括一中介層晶粒的實例中，定位該微凸塊109、205、703在一設置在該中介層晶粒107、201及705上的層709中之個別的井711內、以及在其中該底部半導體晶粒705包括一中介層晶粒的實例中，接合該微凸塊109、205、703至該中介層晶粒107、201及705。該底膠填充材料210可以利用一毛細管底膠填充製程來加以施加。在其中該底部半導體晶粒705包括一中介層晶粒的實例中，該一或多個半導體晶粒101、121、203A、203B、405、505、701可利用一質量回焊製程或是一熱壓縮製程而被接合至該中介層晶粒107、201及705。
一或多個額外的半導體晶粒121、701可利用一質量回焊製程而被接合至該一或多個半導體晶粒101、121、203A、203B、405、505、701。該一或多個額外的半導體晶粒121、701可利用一熱壓縮製程而被接合至該一或多個半導體晶粒101、121、203A、203B、405、505、701。該模製材料211可包括一種聚合物。該一或多個半導體晶粒101、121、203A、203B、405、505、701的接合可包括：在其中該底部半導體晶粒705包括一中介層晶粒的實例中設置該一或多個半導體晶粒101、121、203A、203B、405、505、701以及該中介層晶粒107、201及705在一固定裝置401、501中，其係容許在其中該底部半導體晶粒705包括一中介層晶粒的實例中，該一或多個半導體晶粒以及該中介層晶粒107、201及705能夠彎曲在一方向上，而不是在一相反的方向上彎曲；以及在其中該底部半導體晶粒705包括一中介 層晶粒的實例中，透過一回焊製程來處理該一或多個半導體晶粒101、121、203A、203B、405、505、701以及該中介層晶粒107、201及705。
儘管本發明已經參考某些實施例來加以敘述，但是將會被熟習此項技術者所理解的是可以完成各種的改變並且可以用等同物來加以取代，而不脫離本發明的範疇。此外，可以對於本發明的教示完成許多修改以適配一特定的情況或材料，而不脫離其範疇。因此，所欲的是本發明並不受限於該揭露的特定實施例，而是本發明將會包含所有落在所附的申請專利範圍的範疇內之實施例。
201‧‧‧中介層晶粒
203A、203B‧‧‧半導體晶粒
205‧‧‧微凸塊
207‧‧‧直通矽晶穿孔(TSV)
209‧‧‧前側墊

Claims (18)

  1. 一種用於半導體封裝之方法，該方法係包括：接合包括電子裝置的一或多個半導體晶粒至一中介層晶粒；在該一或多個半導體晶粒以及該中介層晶粒之間施加一底膠填充材料；施加一模製材料以囊封接合的該一或多個半導體晶粒；薄化該中介層晶粒以露出直通矽晶穿孔(TSV)；施加金屬接點至露出的該TSV；以及將具有接合的該一或多個半導體晶粒的該中介層晶粒接合至一封裝基板，其中該一或多個半導體晶粒的接合包括：將該一或多個半導體晶粒附著到一黏著層；以及將黏著的該一或多個半導體晶粒接合至該中介層晶粒。
  2. 根據申請專利範圍第1項之方法，其中該底膠填充材料利用一毛細管底膠填充製程而被施加。
  3. 根據申請專利範圍第1項之方法，其係包括利用一質量回焊製程來接合該一或多個半導體晶粒至該中介層晶粒。
  4. 根據申請專利範圍第1項之方法，其係包括利用一熱壓縮製程來接合該一或多個半導體晶粒至該中介層晶粒。
  5. 根據申請專利範圍第1項之方法，其係包括利用一質量回焊製程來接合一或多個額外的半導體晶粒至該一或多個半導體晶粒。
  6. 根據申請專利範圍第1項之方法，其係包括利用一熱壓縮製程來接合 一或多個額外的半導體晶粒至該一或多個半導體晶粒。
  7. 根據申請專利範圍第1項之方法，其中該模製材料包括一聚合物。
  8. 根據申請專利範圍第1項之方法，其中該一或多個半導體晶粒的接合包括：設置該一或多個半導體晶粒以及該中介層晶粒在一固定裝置中，該固定裝置容許該一或多個半導體晶粒以及該中介層晶粒在一方向上彎曲，而不是在一相反的方向上彎曲；以及透過一回焊製程來處理該一或多個半導體晶粒以及該中介層晶粒。
  9. 一種用於半導體封裝之方法，該方法係包括：接合包括電子裝置的一或多個半導體晶粒至一中介層晶粒；在該一或多個半導體晶粒以及該中介層晶粒之間施加一底膠填充材料；施加一模製材料以囊封接合的該一或多個半導體晶粒；薄化該中介層晶粒以露出直通矽晶穿孔(TSV)；施加金屬接點至露出的該TSV；以及將具有接合的該一或多個半導體晶粒的該中介層晶粒接合至一封裝基板，其中該一或多個半導體晶粒包括用於耦接至該中介層晶粒的微凸塊，其中該接合包括：定位該微凸塊在設置在該中介層晶粒上的一層中之個別的井中；以及接合該微凸塊至該中介層晶粒。
  10. 一種用於半導體封裝之方法，該方法係包括：在一晶粒對晶粒的第一接合製程中產生一半導體封裝，該製程包括： 接合包括電子裝置的一或多個半導體晶粒至一中介層晶粒；在該一或多個半導體晶粒以及該中介層晶粒之間施加一底膠填充材料；施加一模製材料以囊封接合的該一或多個半導體晶粒；薄化該中介層晶粒以露出直通矽晶穿孔(TSV)；施加金屬接點至露出的該TSV；以及將具有接合的該一或多個半導體晶粒的該中介層晶粒接合至一封裝基板，其中該一或多個半導體晶粒的接合包括：將該一或多個半導體晶粒附著到一黏著層；以及將黏著的該一或多個半導體晶粒接合至該中介層晶粒。
  11. 根據申請專利範圍第10項之方法，其中該一或多個半導體晶粒包括用於耦接至該中介層晶粒的微凸塊，其中該接合包括：定位該微凸塊在設置在該中介層晶粒上的一層中之個別的井中；以及接合該微凸塊至該中介層晶粒。
  12. 根據申請專利範圍第10項之方法，其中該底膠填充材料利用一毛細管底膠填充製程而被施加。
  13. 根據申請專利範圍第10項之方法，其係包括利用一質量回焊製程來接合該一或多個半導體晶粒至該中介層晶粒。
  14. 根據申請專利範圍第10項之方法，其係包括利用一熱壓縮製程來接合該一或多個半導體晶粒至該中介層晶粒。
  15. 根據申請專利範圍第10項之方法，其係包括利用一質量回焊製程來 接合一或多個額外的半導體晶粒至該一或多個半導體晶粒。
  16. 根據申請專利範圍第10項之方法，其係包括利用一熱壓縮製程來接合一或多個額外的半導體晶粒至該一或多個半導體晶粒。
  17. 根據申請專利範圍第10項之方法，其中該一或多個半導體晶粒的接合包括：設置該一或多個半導體晶粒以及該中介層晶粒在一固定裝置中，該固定裝置容許該一或多個半導體晶粒以及該中介層晶粒在一方向上彎曲，而不是在一相反的方向上彎曲；以及透過一回焊製程來處理該一或多個半導體晶粒以及該中介層晶粒。
  18. 一種用於半導體封裝之方法，該方法係包括：在一晶粒對晶粒的第一接合製程中產生一半導體封裝，該製程包括：將包括電子裝置的一或多個半導體晶粒的一第一表面設置在一黏著層上；將該一或多個半導體晶粒的一相反的表面接合至一中介層晶粒；從該一或多個半導體晶粒的該第一表面移除該黏著層；在該一或多個半導體晶粒以及該中介層晶粒之間施加一底膠填充材料；施加一模製材料以囊封接合的該一或多個半導體晶粒；以及將具有接合的該一或多個半導體晶粒的該中介層晶粒接合至一封裝基板。
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