WO2000057481A3 - Mos-transistorstruktur mit einer trench-gate-elektrode und einem verringerten spezifischen einschaltwiderstand und verfahren zur herstellung einer mos-transistorstruktur - Google Patents
Mos-transistorstruktur mit einer trench-gate-elektrode und einem verringerten spezifischen einschaltwiderstand und verfahren zur herstellung einer mos-transistorstruktur Download PDFInfo
- Publication number
- WO2000057481A3 WO2000057481A3 PCT/DE2000/000621 DE0000621W WO0057481A3 WO 2000057481 A3 WO2000057481 A3 WO 2000057481A3 DE 0000621 W DE0000621 W DE 0000621W WO 0057481 A3 WO0057481 A3 WO 0057481A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- transistor structure
- mos
- producing
- gate electrode
- methods
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 2
- 210000000746 body region Anatomy 0.000 abstract 2
- 238000002513 implantation Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/701,291 US6465843B1 (en) | 1999-03-24 | 2000-03-01 | MOS-transistor structure with a trench-gate-electrode and a limited specific turn-on resistance and method for producing an MOS-transistor structure |
JP2000607274A JP2002540603A (ja) | 1999-03-24 | 2000-03-01 | トレンチゲート電極を備えスイッチング比抵抗の低減されたmosトランジスタ構造体およびmosトランジスタ構造体の製造方法 |
EP00920348A EP1145324A3 (de) | 1999-03-24 | 2000-03-01 | Mos-transistorstruktur mit einer trench-gate-elektrode und einem verringerten spezifischen einschaltwiderstand und verfahren zur herstellung einer mos-transistorstruktur |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19913375.1 | 1999-03-24 | ||
DE19913375A DE19913375B4 (de) | 1999-03-24 | 1999-03-24 | Verfahren zur Herstellung einer MOS-Transistorstruktur |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2000057481A2 WO2000057481A2 (de) | 2000-09-28 |
WO2000057481A3 true WO2000057481A3 (de) | 2001-07-26 |
Family
ID=7902261
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2000/000621 WO2000057481A2 (de) | 1999-03-24 | 2000-03-01 | Mos-transistorstruktur mit einer trench-gate-elektrode und einem verringerten spezifischen einschaltwiderstand und verfahren zur herstellung einer mos-transistorstruktur |
Country Status (5)
Country | Link |
---|---|
US (1) | US6465843B1 (de) |
EP (1) | EP1145324A3 (de) |
JP (1) | JP2002540603A (de) |
DE (1) | DE19913375B4 (de) |
WO (1) | WO2000057481A2 (de) |
Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001210823A (ja) * | 2000-01-21 | 2001-08-03 | Denso Corp | 半導体装置 |
US7745289B2 (en) | 2000-08-16 | 2010-06-29 | Fairchild Semiconductor Corporation | Method of forming a FET having ultra-low on-resistance and low gate charge |
US6916745B2 (en) | 2003-05-20 | 2005-07-12 | Fairchild Semiconductor Corporation | Structure and method for forming a trench MOSFET having self-aligned features |
US6710403B2 (en) | 2002-07-30 | 2004-03-23 | Fairchild Semiconductor Corporation | Dual trench power MOSFET |
US6818513B2 (en) | 2001-01-30 | 2004-11-16 | Fairchild Semiconductor Corporation | Method of forming a field effect transistor having a lateral depletion structure |
US6803626B2 (en) | 2002-07-18 | 2004-10-12 | Fairchild Semiconductor Corporation | Vertical charge control semiconductor device |
JP4932088B2 (ja) * | 2001-02-19 | 2012-05-16 | ルネサスエレクトロニクス株式会社 | 絶縁ゲート型半導体装置の製造方法 |
US7291884B2 (en) * | 2001-07-03 | 2007-11-06 | Siliconix Incorporated | Trench MIS device having implanted drain-drift region and thick bottom oxide |
US7009247B2 (en) * | 2001-07-03 | 2006-03-07 | Siliconix Incorporated | Trench MIS device with thick oxide layer in bottom of gate contact trench |
US6569738B2 (en) * | 2001-07-03 | 2003-05-27 | Siliconix, Inc. | Process for manufacturing trench gated MOSFET having drain/drift region |
US7033876B2 (en) | 2001-07-03 | 2006-04-25 | Siliconix Incorporated | Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same |
US20060038223A1 (en) * | 2001-07-03 | 2006-02-23 | Siliconix Incorporated | Trench MOSFET having drain-drift region comprising stack of implanted regions |
US6849898B2 (en) | 2001-08-10 | 2005-02-01 | Siliconix Incorporated | Trench MIS device with active trench corners and thick bottom oxide |
US6764906B2 (en) * | 2001-07-03 | 2004-07-20 | Siliconix Incorporated | Method for making trench mosfet having implanted drain-drift region |
DE10239862B4 (de) * | 2002-08-29 | 2007-03-15 | Infineon Technologies Ag | Trench-Transistorzelle, Transistoranordnung und Verfahren zur Herstellung einer Transistoranordnung |
US7576388B1 (en) | 2002-10-03 | 2009-08-18 | Fairchild Semiconductor Corporation | Trench-gate LDMOS structures |
US6710418B1 (en) | 2002-10-11 | 2004-03-23 | Fairchild Semiconductor Corporation | Schottky rectifier with insulation-filled trenches and method of forming the same |
JP5299373B2 (ja) * | 2003-01-16 | 2013-09-25 | 富士電機株式会社 | 半導体素子 |
US7652326B2 (en) | 2003-05-20 | 2010-01-26 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
US7166890B2 (en) | 2003-10-21 | 2007-01-23 | Srikant Sridevan | Superjunction device with improved ruggedness |
KR100994719B1 (ko) | 2003-11-28 | 2010-11-16 | 페어차일드코리아반도체 주식회사 | 슈퍼정션 반도체장치 |
US7368777B2 (en) | 2003-12-30 | 2008-05-06 | Fairchild Semiconductor Corporation | Accumulation device with charge balance structure and method of forming the same |
DE102004009323B4 (de) * | 2004-02-26 | 2017-02-16 | Infineon Technologies Ag | Vertikaler DMOS-Transistor mit Grabenstruktur und Verfahren zu seiner Herstellung |
WO2005084221A2 (en) * | 2004-03-01 | 2005-09-15 | International Rectifier Corporation | Self aligned contact structure for trench device |
TWI256676B (en) * | 2004-03-26 | 2006-06-11 | Siliconix Inc | Termination for trench MIS device having implanted drain-drift region |
US7045857B2 (en) * | 2004-03-26 | 2006-05-16 | Siliconix Incorporated | Termination for trench MIS device having implanted drain-drift region |
US7352036B2 (en) | 2004-08-03 | 2008-04-01 | Fairchild Semiconductor Corporation | Semiconductor power device having a top-side drain using a sinker trench |
DE102005012117B4 (de) * | 2005-03-16 | 2008-10-16 | Infineon Technologies Austria Ag | Transistorbauelement |
JP2006269720A (ja) * | 2005-03-24 | 2006-10-05 | Toshiba Corp | 半導体素子及びその製造方法 |
CN102867825B (zh) | 2005-04-06 | 2016-04-06 | 飞兆半导体公司 | 沟栅场效应晶体管结构及其形成方法 |
WO2006135746A2 (en) | 2005-06-10 | 2006-12-21 | Fairchild Semiconductor Corporation | Charge balance field effect transistor |
US7492003B2 (en) * | 2006-01-24 | 2009-02-17 | Siliconix Technology C. V. | Superjunction power semiconductor device |
US7446374B2 (en) | 2006-03-24 | 2008-11-04 | Fairchild Semiconductor Corporation | High density trench FET with integrated Schottky diode and method of manufacture |
US7319256B1 (en) | 2006-06-19 | 2008-01-15 | Fairchild Semiconductor Corporation | Shielded gate trench FET with the shield and gate electrodes being connected together |
US20090053869A1 (en) * | 2007-08-22 | 2009-02-26 | Infineon Technologies Austria Ag | Method for producing an integrated circuit including a trench transistor and integrated circuit |
JP2010541212A (ja) | 2007-09-21 | 2010-12-24 | フェアチャイルド・セミコンダクター・コーポレーション | 電力デバイスのための超接合構造及び製造方法 |
US9484451B2 (en) | 2007-10-05 | 2016-11-01 | Vishay-Siliconix | MOSFET active area and edge termination area charge balance |
US7772668B2 (en) | 2007-12-26 | 2010-08-10 | Fairchild Semiconductor Corporation | Shielded gate trench FET with multiple channels |
JP5298565B2 (ja) * | 2008-02-22 | 2013-09-25 | 富士電機株式会社 | 半導体装置およびその製造方法 |
US20120273916A1 (en) | 2011-04-27 | 2012-11-01 | Yedinak Joseph A | Superjunction Structures for Power Devices and Methods of Manufacture |
JP5216801B2 (ja) | 2010-03-24 | 2013-06-19 | 株式会社東芝 | 半導体装置 |
US8432000B2 (en) | 2010-06-18 | 2013-04-30 | Fairchild Semiconductor Corporation | Trench MOS barrier schottky rectifier with a planar surface using CMP techniques |
CN102468169A (zh) * | 2010-11-01 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Umos晶体管及其形成方法 |
US8786010B2 (en) | 2011-04-27 | 2014-07-22 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
US8772868B2 (en) | 2011-04-27 | 2014-07-08 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
US8836028B2 (en) | 2011-04-27 | 2014-09-16 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
US8673700B2 (en) | 2011-04-27 | 2014-03-18 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
JP2014518017A (ja) | 2011-05-18 | 2014-07-24 | ビシャイ‐シリコニックス | 半導体デバイス |
CN102412266B (zh) * | 2011-10-13 | 2014-12-10 | 上海华虹宏力半导体制造有限公司 | 提高soa能力的功率器件结构及其制造方法 |
US9431249B2 (en) | 2011-12-01 | 2016-08-30 | Vishay-Siliconix | Edge termination for super junction MOSFET devices |
US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
US9508596B2 (en) | 2014-06-20 | 2016-11-29 | Vishay-Siliconix | Processes used in fabricating a metal-insulator-semiconductor field effect transistor |
US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
CN105632931B (zh) | 2014-11-04 | 2020-04-28 | 台湾积体电路制造股份有限公司 | 半导体器件的制造方法及半导体器件 |
JP6032337B1 (ja) | 2015-09-28 | 2016-11-24 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN116666222A (zh) * | 2023-07-28 | 2023-08-29 | 江西萨瑞半导体技术有限公司 | 一种Trench MOS器件及其制备方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5122474A (en) * | 1988-06-23 | 1992-06-16 | Dallas Semiconductor Corporation | Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough |
US5216275A (en) * | 1991-03-19 | 1993-06-01 | University Of Electronic Science And Technology Of China | Semiconductor power devices with alternating conductivity type high-voltage breakdown regions |
US5637898A (en) * | 1995-12-22 | 1997-06-10 | North Carolina State University | Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance |
JPH1126758A (ja) * | 1997-07-03 | 1999-01-29 | Fuji Electric Co Ltd | トレンチ型mos半導体装置およびその製造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4906588A (en) * | 1988-06-23 | 1990-03-06 | Dallas Semiconductor Corporation | Enclosed buried channel transistor |
US4943537A (en) * | 1988-06-23 | 1990-07-24 | Dallas Semiconductor Corporation | CMOS integrated circuit with reduced susceptibility to PMOS punchthrough |
JPH0621468A (ja) * | 1992-06-29 | 1994-01-28 | Toshiba Corp | 絶縁ゲート型半導体装置 |
JP2837033B2 (ja) * | 1992-07-21 | 1998-12-14 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US5410170A (en) * | 1993-04-14 | 1995-04-25 | Siliconix Incorporated | DMOS power transistors with reduced number of contacts using integrated body-source connections |
US6001678A (en) * | 1995-03-14 | 1999-12-14 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device |
KR100199997B1 (ko) * | 1995-09-06 | 1999-07-01 | 오카메 히로무 | 탄화규소 반도체장치 |
WO1997029518A1 (de) * | 1996-02-05 | 1997-08-14 | Siemens Aktiengesellschaft | Durch feldeffekt steuerbares halbleiterbauelement |
DE69739206D1 (de) * | 1996-07-19 | 2009-02-26 | Siliconix Inc | Hochdichte-graben-dmos-transistor mit grabenbodemimplantierung |
JP3938964B2 (ja) * | 1997-02-10 | 2007-06-27 | 三菱電機株式会社 | 高耐圧半導体装置およびその製造方法 |
DE19808182C1 (de) * | 1998-02-26 | 1999-08-12 | Siemens Ag | Elektrisch programmierbare Speicherzellenanordnung und ein Verfahren zu deren Herstellung |
KR100275756B1 (ko) * | 1998-08-27 | 2000-12-15 | 김덕중 | 트렌치 절연 게이트 바이폴라 트랜지스터 |
DE19908809B4 (de) * | 1999-03-01 | 2007-02-01 | Infineon Technologies Ag | Verfahren zur Herstellung einer MOS-Transistorstruktur mit einstellbarer Schwellspannung |
-
1999
- 1999-03-24 DE DE19913375A patent/DE19913375B4/de not_active Expired - Fee Related
-
2000
- 2000-03-01 JP JP2000607274A patent/JP2002540603A/ja not_active Abandoned
- 2000-03-01 US US09/701,291 patent/US6465843B1/en not_active Expired - Lifetime
- 2000-03-01 WO PCT/DE2000/000621 patent/WO2000057481A2/de not_active Application Discontinuation
- 2000-03-01 EP EP00920348A patent/EP1145324A3/de not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5122474A (en) * | 1988-06-23 | 1992-06-16 | Dallas Semiconductor Corporation | Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough |
US5216275A (en) * | 1991-03-19 | 1993-06-01 | University Of Electronic Science And Technology Of China | Semiconductor power devices with alternating conductivity type high-voltage breakdown regions |
US5637898A (en) * | 1995-12-22 | 1997-06-10 | North Carolina State University | Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance |
JPH1126758A (ja) * | 1997-07-03 | 1999-01-29 | Fuji Electric Co Ltd | トレンチ型mos半導体装置およびその製造方法 |
Non-Patent Citations (2)
Title |
---|
DEBOY G ET AL: "NEW GENERATION OF HIGH VOLTAGE MOSFETS BREAKS THE LIMIT LINE OF SILICON", INTERNATIONAL ELECTRON DEVICES MEETING,US,NEW YORK, NY: IEEE, 6 December 1998 (1998-12-06), pages 683 - 685, XP000859463, ISBN: 0-7803-4775-7 * |
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 04 30 April 1999 (1999-04-30) * |
Also Published As
Publication number | Publication date |
---|---|
DE19913375A1 (de) | 2000-10-05 |
US6465843B1 (en) | 2002-10-15 |
WO2000057481A2 (de) | 2000-09-28 |
EP1145324A3 (de) | 2001-10-24 |
DE19913375B4 (de) | 2009-03-26 |
JP2002540603A (ja) | 2002-11-26 |
EP1145324A2 (de) | 2001-10-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2000057481A3 (de) | Mos-transistorstruktur mit einer trench-gate-elektrode und einem verringerten spezifischen einschaltwiderstand und verfahren zur herstellung einer mos-transistorstruktur | |
US5558313A (en) | Trench field effect transistor with reduced punch-through susceptibility and low RDSon | |
US8354711B2 (en) | Power MOSFET and its edge termination | |
US5674766A (en) | Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer | |
US7625793B2 (en) | Power MOS device with improved gate charge performance | |
WO2003017349A3 (de) | Dmos-transistor | |
WO2005036650A3 (en) | Insulated gate type semiconductor device and manufacturing method thereof | |
AU2002310514A1 (en) | Power mosfet having a trench gate electrode and method of making the same | |
WO2001082380A3 (en) | Power semiconductor device having a trench gate electrode and method of making the same | |
TWI256089B (en) | Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same | |
WO2004100223A3 (en) | Semiconductor fabrication process with asymmetrical conductive spacers | |
WO2005053032A3 (en) | Trench insulated gate field effect transistor | |
WO2005057615A3 (en) | Closed cell trench metal-oxide-semiconductor field effect transistor | |
EP1542270A4 (de) | Vertikal-sperrschichtfeldeffekttransistor und verfahren zu seiner herstellung | |
EP2043158A3 (de) | Graben-DMOS-Transformator | |
WO2006033923A3 (en) | Enhanced resurf hvpmos device with stacked hetero-doping rim and gradual drift region | |
TW200711123A (en) | Deep trench isolation structures and methods of formation thereof | |
EP1113501A3 (de) | Leistungs-MOSFET mit einer Graben-Gateelektrode | |
WO1996024953B1 (en) | TRENCH FIELD EFFECT TRANSISTOR WITH REDUCED PUNCH-THROUGH SUSCEPTIBILITY AND LOW R¿DSon? | |
US6960499B2 (en) | Dual-counterdoped channel field effect transistor and method | |
WO2005053031A3 (en) | Trench insulated gate field effect transistor | |
TW200611409A (en) | Lateral semiconductor device using trench structure and method of manufacturing the same | |
EP2108194A1 (de) | Superjunction-leistungshalbleiterbauelement | |
WO2003071585A3 (en) | High voltage power mosfet having low on-resistance | |
WO2005053033A3 (en) | Trench insulated gate field-effect transistor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2000920348 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 09701291 Country of ref document: US |
|
AK | Designated states |
Kind code of ref document: A3 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
WWP | Wipo information: published in national office |
Ref document number: 2000920348 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 2000920348 Country of ref document: EP |