WO1998035293A1 - Systeme de memoire - Google Patents

Systeme de memoire Download PDF

Info

Publication number
WO1998035293A1
WO1998035293A1 PCT/JP1998/000492 JP9800492W WO9835293A1 WO 1998035293 A1 WO1998035293 A1 WO 1998035293A1 JP 9800492 W JP9800492 W JP 9800492W WO 9835293 A1 WO9835293 A1 WO 9835293A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
module
signal selection
selection circuit
board
Prior art date
Application number
PCT/JP1998/000492
Other languages
English (en)
Japanese (ja)
Inventor
Kouichi Ikeda
Takeshi Ikeda
Original Assignee
T.I.F. Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by T.I.F. Co., Ltd. filed Critical T.I.F. Co., Ltd.
Publication of WO1998035293A1 publication Critical patent/WO1998035293A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width

Definitions

  • the present invention relates to a memory system in which a plurality of memory chips are mounted.
  • Computer devices such as personal computers and workstations are built around a central processing unit (hereinafter referred to as CPU), which is connected to memories and various controllers.
  • the CPU has a plurality of data input / output terminals for transmitting and receiving data to / from a memory or the like, and the number of data input / output terminals is often a multiple of 8 such as eight or sixteen.
  • the number of data input / output terminals of the CPU is not constant, and the number of variations tends to increase in the future.
  • the present invention has been made in view of the above points, and a purpose thereof is to provide a memory system capable of easily switching a bus width.
  • a signal selection circuit for switching the number of data input / output signals transmitted and received between the module substrate and another substrate is provided on the module substrate.
  • the memory system of the present invention sends all the data input / output signals of each memory chip to the main board without performing the work of adjusting the data bus width in the module board.
  • the main board some of the data input / output signals from the module board are combined by a signal selection circuit to reduce the data bus width.
  • the memory system of the present invention can be used to select data input / output in consideration of the fact that the data bus width of ordinary computer equipment is often 4 bits, 8 bits, or 16 bits. Set the number of signals to at least 4, 8, or 16 signals.
  • the memory system of the present invention switches the signal input to the control terminal of the memory chip according to the desired data bus width.
  • the upper bits of the address signal are input to the chip select terminal and the CAS terminal of the memory chip, and the data bus width is switched by the logic of the upper bits.
  • FIG. 1 is a plan view schematically showing a memory module constituting a part of a memory system
  • FIG. 2 is a sectional view taken along the line A—A ′ in FIG. 1
  • FIG. 3 is a perspective view showing a part of the memory module shown in FIG. 1
  • FIG. 4 is a circuit diagram of the memory module shown in FIG. 1
  • FIG. 5 is a diagram showing a configuration of the signal selection circuit shown in FIG. 4,
  • FIG. 6 is a diagram showing the configuration of the signal selection circuit shown in FIG. 4,
  • FIG. 7 is a circuit diagram of a memory module when a data bus width of 16 bits is selected
  • FIG. 8 is a circuit diagram of a memory module when an 8-bit data bus width is selected
  • FIG. 9 is a circuit diagram of a memory module when a 4-bit data bus width is selected.
  • FIG. 10 is a memory configuration diagram.
  • FIG. 10A shows a configuration when a 16-bit data bus width is selected
  • FIG. 10B shows an 8-bit data bus.
  • FIG. 3C is a diagram showing a configuration when an evening bus width is selected.
  • FIG. 4C is a diagram showing a configuration when a 4-bit data bus width is selected.
  • Fig. 11 is a diagram showing an example of a memory system in which a plurality of memory modules are mounted on an SO-DIMM board.
  • Fig. 11 (a) is a diagram showing one surface
  • Fig. 11 (b) is a diagram showing the other. Diagram showing a plane
  • FIG. 12 is a diagram showing a configuration of a memory module not including a signal selection circuit.
  • FIG. 13 is a diagram showing a modification of the memory module.
  • FIG. 14 is a diagram showing another modification of the memory module
  • FIG. 15 is a diagram showing another modification of the memory module
  • FIG. 16 is a diagram showing another modification of the memory module
  • FIG. 17 is a diagram showing another modified example of the memory module
  • FIG. 18 is a diagram showing another modification of the memory module
  • FIG. 19 is a diagram showing another modification of the memory module
  • FIG. 20 is a diagram showing another modification of the memory module
  • FIG. 21 is a diagram showing another modification of the memory module
  • FIG. 22 is a diagram showing another modification of the memory module
  • FIG. 23 is a diagram showing another modified example of the memory module
  • FIG. 24 is a view showing a modified example of the bare chip for memory.
  • FIG. 24A shows a bare chip for memory in which a pad is arranged at the center of the short side
  • FIG. 25 is a diagram showing another modified example of the memory bare chip. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a plan view schematically showing a memory module constituting a part of the memory system
  • FIG. 2 is a cross-sectional view taken along line AA ′ of FIG.
  • the memory module 10 shown in FIG. 1 includes four memory bare chips 1A, 1B, 1C, and 1D cut out from a semiconductor wafer and a signal selection circuit 21 for switching the data bus width. And a module substrate 2 on which is mounted.
  • Each of the memory bear chips 1A to 1D is a DRAM having a memory capacity of, for example, 4M ⁇ 4 bits.Each of the memory bear chips 1A has a rectangular shape, and is arranged in a line along a long side thereof. A plurality of pads 3 are formed.
  • the signal selection circuit 21 on the module board 2 switches the signal input to each control terminal of each memory chip 1A to 1D, and the signal selection circuit 22 inputs data of each memory bare chip 1A etc. Switches the output signal.
  • the detailed configuration of the signal selection circuits 21 and 22 will be described later.
  • the module board 2 has an external dimension that can be mounted on an S-type DIMM (Small Out Dualine Inline Memory Module) board, which will be described later.
  • Pad 4 is formed at the bottom. Two bare chips 1A to 1D for memory are mounted on both sides with the pad 4 interposed therebetween, and the direction in which the pads 4 on the module board 2 are lined up and the bare chips 1A to 1D for each memory are mounted. The directions in which the pads 3 are arranged are almost parallel.
  • the pad 4 on the module substrate 2 and the pad 3 on the memory bare chips 1A to 1D are connected by bonding wires 5-, respectively.
  • the pad 4 includes one in which two bonding wires 5 are connected and one in which one bonding wire 5 is connected.
  • Memory pan For terminals that are commonly connected to a plurality of memory bare chips 1A, such as address terminals for chip 1A, etc. padding is achieved by connecting a plurality of bonding wires 5 to pads 4 on the module board 2. 4 is being shared. As a result, the number of pads 4 can be reduced as compared with the total number of pads 3 on memory bare chips 1A to 1D, and the amount of wiring in module substrate 2 can be reduced. Further, by arranging the memory bare chips 1A to 1D to face each other at substantially the same distance from the pad 4 on the module substrate 2, the lengths of the bonding wires 5 can be made substantially equal.
  • a plurality of external connection terminals 8 formed in a concave shape are provided on the side surface of the module substrate 2, and these external connection terminals 8 are electrically connected to the pads 4 on the module substrate 2 via a wiring pattern. are doing.
  • the memory module 10 of the present embodiment covers the upper surface of the wire bonded memory chip 1A or the like with a resin 6 to prevent disconnection or the like.
  • a sealing frame 7 is attached near the outer periphery of the module substrate 2, and the resin 6 is poured into the sealing frame 7.
  • the resin layer may be formed by, for example, a transfer molding method, or the resin layer may be formed without using any mold or the like.
  • FIG. 3 is a perspective view showing a part of the memory module 10 shown in FIG. 1.
  • the memory module 10 of the present embodiment uses a so-called LCC (Leadless Chip Carrier) method such as an SO-DIMM substrate. It is mounted on the main board, and specifically, is fixed on the main board by pouring solder into a concave portion of the external connection terminal 8.
  • LCC Leadless Chip Carrier
  • connection to the main board is performed by normal soldering, repair (replacement) when the memory module 10 becomes defective can be performed relatively easily.
  • the yield of the main board on which is mounted can be improved.
  • FIG. 4 is a circuit diagram of the memory module 10 shown in FIG. In this figure, some terminals such as a power terminal and a ground terminal are omitted for simplification. Bare chip for each memory 1 A to 1 D Address terminals A 0 to 10 are connected to external connection terminals AO to 10, control terminal RAS is connected to external connection terminal RAS, control terminal WE is connected to external connection terminal WE. The control terminal ⁇ E is connected to the external connection terminal OE. Further, each CAS terminal of each of the memory base chips 1A to 1D is connected to the signal selection circuit 21, and data input / output terminals I / O 0 to 3 are connected to the signal selection circuit 22.
  • the signal selection circuit 21 outputs the control signals CS0 to CS3 in accordance with the logic between the upper bits A12 and All of the address signal and the external connection terminal CS.
  • the signal selection circuit 22 switches the number of input / output data lines by cutting a predetermined portion of the wiring pattern.
  • FIG. 5 is a diagram showing a detailed configuration of the signal selection circuit 21.
  • the signal selection circuit 21 has four AND gates 30, 32, 34, and 36 whose output terminals are connected to the CAS terminals of the memory bare chips 1 A to 1 D.
  • the input terminals are connected to the external connection terminals All and A12 respectively, and are connected to the respective output terminals of the two inverters 38, 40 and 38, 40, respectively.
  • the pull-up resistor 42 and the inverter 38 point a in FIG. 5
  • the pull-up resistor 44 and the inverter Each wiring pattern between 40 and 40 (point b in Fig. 5) is cut by laser light irradiation or the like. Therefore, the four memory bare chips 1A to 1D are simultaneously selected according to the logic of the chip select signal input to the external connection terminal CS.
  • the memory module 10 When the memory module 10 is used with an 8-bit width, only the wiring pattern between the pull-up resistor 44 and the inverter 40 is cut by laser light irradiation or the like. Therefore, one of two of memory bare chips 1A and IB or two of memory bare chips 1C and 1D is selected by a combination of upper bit All of the address signal and chip select signal CS.
  • the signal selection circuit 21 shown in FIG. 5 is operated in the same configuration. Therefore, one of the four memory bare chips 1A to 1D is selected according to the combination of the address signals A11 and A12.
  • FIG. 6 is a diagram showing a detailed configuration of the signal selection circuit 22.
  • the signal selection circuit 22 has input / output terminals for each of the memory bare chips 1A to 1D.
  • the wiring patterns between I / O 0-3 and the external connection terminals D0-3, D4-7, D8-ll, D12-15 are partially connected.
  • the memory bear chips 1A and 1C the memory bear chips 1A and 1B, and the memory bear chips 1B and 1D, wire the corresponding input / output terminals I / O 0-3. They are connected by a patron.
  • the memory module 10 when the memory module 10 is used with a 16-bit width, it is necessary to separately draw out the input / output terminals I / O 0 to 3 of the four memory bare chips 1 A to 1 D. Then, all the wiring patterns at points c, d and e shown in FIG. 6 are cut. When the memory module 10 is used with an 8-bit width, only the wiring pattern at the point c is cut off. When the memory module 10 is used with a 4-bit width, any wiring pattern is used. Do not disconnect.
  • the data width of the memory module 10 can be changed to any one of 16 bits, 8 bits, and 4 bits.
  • the circuit diagram of FIG. 4 is equivalent to that of FIG. 7, and similarly, when 8 bits and 4 bits are selected, FIG.
  • the equivalent circuit diagrams are as shown in Figs. 8 and 9 respectively.
  • FIG. 10 is a diagram showing a memory space of the memory module 10.
  • 16 bits are selected as the data width, as shown in FIG. 10 (a)
  • four A bare memory chips 1A to 1 16-bit data input / output in parallel with D is specified.
  • 8 bits are selected as the data width, as shown in FIG. 10 (b)
  • the two bare chips 1A, IB or 1C, 8-bit data to be input / output in parallel to any of D is specified.
  • 4 bits are selected as the data width, as shown in FIG. 10 (c)
  • the data is input to or output from one of the memory patches 1A to 1D by the addresses A0 to A10. 4-bit data is specified.
  • the signal selection circuit 21 for switching the signal input to the CAS terminal of each memory chip 1 A and the data of each memory bare chip 1 A etc.
  • FIG. 11 is a diagram showing an example of a memory system in which a plurality of memory modules 10 shown in FIGS. 1 to 4 are mounted on an SO-DIMM board 11.
  • FIG. 11 Is a plan view on the front side of the SO-DIMM substrate 11, and
  • FIG. 11 (b) is a plan view on the back side.
  • two memory modules 10 are mounted on both the front and back sides.
  • Two noise-prevention capacitors hereafter referred to as two
  • a controller 13 for checking the memory bare chip 1A and the like is mounted.
  • Each memory module 10 is implemented by the above-described LCC scheme, and the bypass capacitor 12 and the controller 13 are implemented by an SMT (Surface Mount Technology) scheme.
  • SMT Surface Mount Technology
  • the S ⁇ —DIMM board in Fig. 11 has the same result as mounting a total of 16 memory ICs with 8 on each side.
  • the bare chip for memory that constitutes each memory module 10 In the case of 4 MX 4 bits, the memory capacity of each memory module 10 is 8 Mbytes, and the memory capacity of the entire SO-DIMM board is 32 Mbytes.
  • the data bus width of the SO-DIMM board is set to 64 bits by the standard, the data bus width of each memory module is set to 16 bits by the setting of the signal selection circuit described above. You.
  • the signal selection circuit 21 shown in FIG. 4 switches the upper bits of the address terminal according to the data bus width
  • the lower bits of the address terminal may be switched.
  • the unit of switching the data bus width is not limited to 4 bits, 8 bits, and 16 bits, and may be, for example, 1 bit / 2 bits.
  • FIG. 1 shows an example in which the signal selection circuits 21 and 22 for switching the data bus width are provided on the module substrate 2, but may be provided on the main substrate of the memory system. That is, signals may always be transmitted and received between the memory module 10 and the main board with a 16-bit data bus width, and the data bus width may be switched on the main board.
  • the structure of the module substrate can be simplified, the memory module 10 can be reduced in size, and the cost can be reduced.
  • COB Chip On Glass
  • COF Chip On Film
  • the memory bare chip 1A etc. are flip-chip mounted on the module substrate 2 using bumps such as solder balls or gold balls. You may.
  • a main substrate such as an S0_DIMM by the LCC method
  • a BGA All Grid Array
  • the number of memory chips 1A and the like mounted on the module substrate 2 is not limited to four, and is not particularly limited as long as it is two or more. However, since the memory capacity of ordinary computer equipment is often set to a multiple of 4, an even number of memory chip 1A and the like mounted on the module board is desirable.
  • FIGS. 13 to 22 show modified examples of the memory module.
  • attention is paid to the arrangement state of the memory bare chip and the wiring state by the bonding wire 5, and the signal selection circuits 21 and 22 are omitted.
  • the bonding wires 5 may be alternately drawn out from the memory bare chips arranged on both sides to the pads 4 formed in a line in the center of the module substrate 2.
  • the bonding wires 5 are alternately drawn in units of a plurality of wires, or as shown in FIG. 15, two or more rows formed on the module substrate 2 (two rows in the same figure).
  • the bonding wire 5 may be connected to the pad 4.
  • pads 3 are formed in two rows along the long side of the memory bear chip, and bonding wires 5 are formed on both sides of each memory bear chip. Or, as shown in Fig. 18 to Fig. 21, form pads 3 in two rows along the short side of the bare memory chip and pull out the bonding wires 5 on both sides of each bare memory chip. You may do so. Further, as shown in FIG. 22, a memory module may be constituted by using two memory chips.
  • pads 4 ′ are formed on the module substrate 2 at the same intervals as the pads on the memory bare chip, and these pads 4 ′ and the pads on the memory bare chip are formed.
  • the flip chip mounting may be performed by arranging them so as to face each other.
  • the mounting state may be unstable.
  • the pads 3 When the pads 3 are formed in a row on the memory bare chip, the pads 3 may be formed in a stepwise manner as shown in FIG. .
  • a signal selection circuit for switching the number of data input / output signals transmitted / received between a module substrate and another substrate is provided on the module substrate.
  • the module board can be mounted on the same board, the versatility of the module board is improved, and costs can be reduced by mass production effects.
  • a signal selection circuit for integrating data input / output signals transmitted / received to / from the module board is provided on the main board, so that it is not necessary to adjust the data bus width in the module board.
  • the module board can be mounted on a plurality of types of main boards having different data bus widths. Therefore, the configuration of the module substrate can be simplified, and the cost of the module substrate can be reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

L'invention concerne un système de mémoire dans lequel la largeur de bus de données peut être facilement modifiée. Le système de mémoire est obtenu par montage, sur une plaquette principale, d'une plaquette module (2) pourvue de quatre puces nues pour mémoire (1A-1D). La plaquette module (2) est pourvue d'un circuit de sélection de signal (21) servant à commuter des signaux à appliquer aux bornes CAS des puces nues pour mémoire (1A-1D) montées sur la plaquette module (2), et d'un circuit de sélection de signal (22) servant à la commutation de bornes d'entrée/de sortie de données des puces nues pour mémoire (1A-1D). La largeur de bus de données de la plaquette module (2) peut être modifiée par modification des réglages des circuits de sélection de signal (21, 22). Ainsi, un module de mémoire équipé de composants de cette façon peut être monté sur divers types de plaquettes mères ou sur des plaquettes de mémoire de différentes largeurs de bus de données. Grâce à ce procédé de montage, le champ d'utilisation d'un module de mémoire est beaucoup plus grand.
PCT/JP1998/000492 1997-02-07 1998-02-06 Systeme de memoire WO1998035293A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP9/39844 1997-02-07
JP3984497 1997-02-07
JP23540597 1997-08-15
JP9/235405 1997-08-15

Publications (1)

Publication Number Publication Date
WO1998035293A1 true WO1998035293A1 (fr) 1998-08-13

Family

ID=26379255

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1998/000492 WO1998035293A1 (fr) 1997-02-07 1998-02-06 Systeme de memoire

Country Status (1)

Country Link
WO (1) WO1998035293A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10125911A1 (de) * 2001-05-28 2002-12-12 Infineon Technologies Ag Vorrichtung zum Bilden einer Schnittstelle
JP2009200101A (ja) * 2008-02-19 2009-09-03 Liquid Design Systems:Kk 半導体チップ及び半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01277946A (ja) * 1988-04-30 1989-11-08 Oki Electric Ind Co Ltd ワード長可変記憶装置
JPH02310644A (ja) * 1989-05-25 1990-12-26 Fanuc Ltd メモリモジュール
JPH0465738A (ja) * 1990-07-05 1992-03-02 Koufu Nippon Denki Kk メモリ装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01277946A (ja) * 1988-04-30 1989-11-08 Oki Electric Ind Co Ltd ワード長可変記憶装置
JPH02310644A (ja) * 1989-05-25 1990-12-26 Fanuc Ltd メモリモジュール
JPH0465738A (ja) * 1990-07-05 1992-03-02 Koufu Nippon Denki Kk メモリ装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10125911A1 (de) * 2001-05-28 2002-12-12 Infineon Technologies Ag Vorrichtung zum Bilden einer Schnittstelle
JP2009200101A (ja) * 2008-02-19 2009-09-03 Liquid Design Systems:Kk 半導体チップ及び半導体装置

Similar Documents

Publication Publication Date Title
WO1998021752A1 (fr) Module de memoire
US5790384A (en) Bare die multiple dies for direct attach
JP3718008B2 (ja) メモリモジュールおよびその製造方法
US5444296A (en) Ball grid array packages for high speed applications
US7061785B2 (en) Stacked large-scale integrated circuit (LSI) semiconductor device with miniaturization and thinning of package
JP2000340737A (ja) 半導体パッケージとその実装体
US11594522B2 (en) Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
KR20180067695A (ko) 제어된 임피던스 부하를 갖는 고대역폭 메모리 응용
TW201517243A (zh) 相互支援之ｘｆｄ封裝
US10679956B2 (en) Semiconductor memory chip, semiconductor memory package, and electronic system using the same
JP3123338B2 (ja) 集積回路装置
WO1998035293A1 (fr) Systeme de memoire
JPH01144664A (ja) 半導体メモリ用集積回路装置
CN113987991A (zh) 信号传输装置及电子设备
JP3904296B2 (ja) メモリシステム
JPH0714002B2 (ja) チップへの信号供給方法
JP3846777B2 (ja) ボールグリッドアレイパッケージ
JPH10116958A (ja) メモリシステム
JPH10242190A (ja) メモリモジュール
JPH10284681A (ja) メモリモジュール
JPH10284682A (ja) メモリモジュール
JPS58184735A (ja) 集積回路チツプ
WO1998038680A1 (fr) Module memoire
JPH10322078A (ja) メモリモジュール
JPH10303362A (ja) メモリシステム

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase