US8259502B2 - NAND flash memory - Google Patents

NAND flash memory Download PDF

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US8259502B2
US8259502B2 US12/886,275 US88627510A US8259502B2 US 8259502 B2 US8259502 B2 US 8259502B2 US 88627510 A US88627510 A US 88627510A US 8259502 B2 US8259502 B2 US 8259502B2
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side selection
line
drain side
mos transistor
control
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US20110128788A1 (en
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Yasuhiko Honda
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Kioxia Corp
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Toshiba Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Definitions

  • the present invention relates to a NAND flash memory.
  • a NAND flash memory of the ABL (All Bit Line) sense scheme in which sense amplifiers are provided for all bit lines BL and all bit lines BL are sensed at the same time is known (see, for example, JP-A-2009-158048 (KOKAI)).
  • a NAND flash memory a plurality of memory cells connected to one word line (i.e., one page address) in one block in one memory cell array formed in one well are subject to reading and writing at the same time according to the conventional art.
  • the number of memory cells which can be sensed at the same time i.e., the storage capacity in one page (page length) is increased by using the ABL scheme as compared with a scheme in which sense amplifiers are provided for alternate bit lines BL and even-numbered bit lines BLe and odd-numbered bit lines BLo are sensed alternately. As a result, it becomes possible to improve the readout speed per unit.
  • one row decoder simultaneously selects word lines of the same address for two memory cell arrays and conducts writing into the two memory cell arrays (see, for example, JP-A-11-224492 (KOKAI)).
  • a data latch circuit is provided for each of the two memory cell arrays. In other words, bit lines are not connected in common in these memory cell arrays. Furthermore, in the conventional NAND flash memory, operation for a random page address in one memory cell array is not prescribed.
  • FIG. 1 is a block diagram showing an example of a configuration of a NAND flash memory 100 according to a first embodiment of the present invention
  • FIG. 2 is a circuit diagram showing an example of a configuration according to the first embodiment including a memory cell array 1 , a bit line control circuit 2 and a row decoder 6 ;
  • FIG. 3 is a sectional view showing a section of one memory cell transistor M in the memory cell array 1 shown in FIG. 2 ;
  • FIG. 4 is a sectional view showing a section of the drain side selection MOS transistors SGDETr and SGDOTr and the source side selection MOS transistor SGSTr in the memory cell array 1 shown in FIG. 2 ;
  • FIG. 5 is a sectional view of a vicinity of a NAND cell unit 1 a E connected to a bit line BLEn of the block BLKOn shown in FIG. 2 obtained when seen along the bit line BLEn;
  • FIG. 6 is a sectional view of a vicinity of a NAND cell unit 1 a O connected to a bit line BLOn of the block BLKOn shown in FIG. 2 obtained when seen along the bit line BLOn;
  • FIG. 7 is a sectional view of a vicinity of a NAND cell unit 1 a E connected to a bit line BLEn+1 of the block BLKOn shown in FIG. 2 obtained when seen along the bit line BLEn+1;
  • FIG. 8 is a plan view of the block BLKOn in the vicinity of the drain side selection MOS transistors SGDETr and SGDOTr;
  • FIG. 9 is a diagram showing an example of a model of the on/off state of the drain side selection MOS transistors at the time of a write operation or a read operation of the NAND flash memory 100 shown in FIG. 2 ;
  • FIG. 10 is a diagram showing another example of a model of the on/off state of the drain side selection MOS transistors at the time of a write operation or a read operation of the NAND flash memory 100 shown in FIG. 2 ;
  • FIG. 11 is a flow diagram showing an example of relations between command inputs and operations of the NAND flash memory 100 ;
  • FIG. 12 is a circuit diagram showing an example of a configuration according to the second embodiment which includes the memory cell array 1 , the bit line control circuit 2 and the row decoder 6 shown in FIG. 1 ;
  • FIG. 13 is a diagram showing an example of a configuration of a logic circuit 600 which generates selection signals SEL 0 , SEL 1 and SEL 2 in the driver circuit shown in FIG. 12 ;
  • FIG. 14 is a diagram showing an example of a model of the on/off state of the drain side selection MOS transistors at the time of a write operation or a read operation of the NAND flash memory 100 shown in FIG. 12 ;
  • FIG. 15 is a diagram showing another example of a model of the on/off state of the drain side selection MOS transistors at the time of a write operation or a read operation of the NAND flash memory 100 shown in FIG. 12 ;
  • FIG. 16 is a circuit diagram showing an example of a configuration according to the third embodiment which includes the memory cell array 1 , the bit line control circuit 2 and the row decoder 6 shown in FIG. 1 .
  • a NAND flash memory has a memory cell array formed of a plurality of blocks including memory cell transistors arranged in a matrix form.
  • the NAND flash memory has a first bit line; a first sense amplifier connected to the first bit line, the first sense amplifier sensing or controlling a potential on the first bit line; a second bit line; and a second sense amplifier connected to the second bit line to sense or control a potential on the second bit line.
  • the NAND flash memory has a first drain side selection gate line; a second drain side selection gate line; a third drain side selection gate line; a fourth drain side selection gate line; a first source side selection gate line; and a second source side selection gate line.
  • the NAND flash memory has a first block; and a second block.
  • the first block has a first drain side selection MOS transistor connected at a gate thereof to the first drain side selection gate line and connected at a drain diffusion layer thereof to the first bit line, a first source side selection MOS transistor connected at a gate thereof to the first source side selection gate line, a plurality of first memory cell transistors connected in series between the source diffusion layer of the first drain side selection MOS transistor and the drain diffusion layer of the first source side selection MOS transistor, a second drain side selection MOS transistor connected at a gate thereof to the second drain side selection gate line and connected at a drain diffusion layer thereof to the second bit line, a second source side selection MOS transistor connected at a gate thereof to the first source side selection gate line, and a plurality of second memory cell transistors connected in series between the source diffusion layer of the second drain side selection MOS transistor and the drain diffusion layer of the second source side selection MOS transistor.
  • the second block has the third drain side selection MOS transistor connected at a gate thereof to the third drain side selection gate line and connected at a drain diffusion layer thereof to the first bit line, a third source side selection MOS transistor connected at a gate thereof to the second source side selection gate line, a plurality of third memory cell transistors connected in series between the source diffusion layer of the third drain side selection MOS transistor and the drain diffusion layer of the third source side selection MOS transistor, a fourth drain side selection MOS transistor connected at a gate thereof to the fourth drain side selection gate line and connected at a drain diffusion layer thereof to the second bit line, a fourth source side selection MOS transistor connected at a gate thereof to the second source side selection gate line, and a plurality of fourth memory cell transistors connected in series between the source diffusion layer of the fourth drain side selection MOS transistor and the drain diffusion layer of the fourth source side selection MOS transistor.
  • the NAND flash memory has a decoder which turns on one of the first and third drain side selection MOS transistors and turns off the other, and which turns on one of the
  • FIG. 1 is a block diagram showing an example of a configuration of a NAND flash memory 100 according to a first embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing an example of a configuration according to the first embodiment including a memory cell array 1 , a bit line control circuit 2 and a row decoder 6 .
  • the NAND flash memory 100 includes a memory cell array 1 , a bit line control circuit 2 , a column decoder 3 , a data input/output buffer 4 , a data input/output terminal 5 , a row decoder 6 , a control circuit 7 , a control signal input terminal 8 , a source line control circuit 9 , and a well control circuit 10 .
  • the memory cell array 1 includes a plurality of bit lines, a plurality of word lines, and source lines.
  • the memory cell array 1 includes a plurality of blocks ( FIG. 2 ) each including EEPROM cells and electrically data rewritable memory cell transistors arranged in a matrix form.
  • the bit line control circuit 2 for controlling a voltage on a bit line and the row decoder 6 for controlling a voltage on a word line are connected to the memory cell array 1 . At the time of data erasing operation, some block is selected by the row decoder 6 and remaining blocks are made unselected.
  • the bit line control circuit 2 includes a sense amplifier SA ( FIG. 2 ) for sensing and amplifying a voltage on a bit line in the memory cell array 1 and a data storage circuit (not illustrated) which has roles of a circuit for conducting writing and a data latch circuit for latching the circuit for conducting writing.
  • SA sense amplifier
  • the bit line control circuit 2 reads out data in a memory cell transistor in the memory cell array 1 via a bit line, detects a state in the memory cell transistor via a bit line, and applies a write control voltage to the memory cell transistor via a bit line to write data into the memory cell transistor.
  • the column decoder 3 and the data input/output buffer 4 are connected to the bit line control circuit 2 .
  • the data storage circuit in the bit line control circuit 2 is selected by the column decoder 3 , and data in the memory cell transistor read out in the data storage circuit is output from the data input/output terminal 5 to the outside via the data input/output buffer 4 .
  • write data which is input from the outside to the data input/output terminal 5 is stored in the data storage circuit selected by the column decoder 3 . From the data input/output terminal 5 , various commands such as writing, reading, erasing and status reading and an address are also input besides write data.
  • the row decoder 6 is connected to the memory cell array 1 .
  • the row decoder 6 applies a voltage required for reading, writing or erasing to a word line of the memory cell array 1 .
  • the source line control circuit 9 is connected to the memory cell array 1 .
  • the source line control circuit 9 is adapted to control a voltage on a source line.
  • the well control circuit 10 is connected to the memory cell array 1 .
  • the well control circuit 10 is adapted to control a voltage on a semiconductor substrate (well) on which memory cell transistors are formed.
  • the control circuit 7 is adapted to control the memory cell array 1 , the bit line control circuit 2 , the column decoder 3 , the data input/output buffer 4 , the row decoder 6 , the source line control circuit 9 and the well control circuit 10 .
  • a boosting circuit (not illustrated) which boosts the power supply voltage is included in the control circuit 7 .
  • the control circuit 7 boosts the power supply voltage by using the boosting circuit as occasion demands, and supplies the boosted voltage to the bit line control circuit 2 , the column decoder 3 , the data input/output buffer 4 , the row decoder 6 , the source line control circuit 9 and the well control circuit 10 .
  • the control circuit 7 conducts control operation on the basis of a control signal (such as a command latch enable signal CLE, an address latch enable signal ALE, or a ready/busy signal RY/BY) which is input from the outside via the control signal input terminal 8 and a command which is given from the data input/output terminal 5 via the data input/output buffer 4 .
  • a control signal such as a command latch enable signal CLE, an address latch enable signal ALE, or a ready/busy signal RY/BY
  • the control circuit 7 generates desired voltages at the time of data programming, verifying, reading and erasing according to the control signal and the command, and supplies the voltages to respective units in the memory cell array 1 .
  • the memory cell array 1 includes blocks BLKOn, BLKIn, BLKOn ⁇ 1, BLKIn ⁇ 1, BLKOn ⁇ 2 and BLKIn ⁇ 2 each configured by connecting a plurality of NAND cell units 1 a E in even-numbered columns and a plurality of NAND cell units 1 a O in odd-numbered columns.
  • Each of the NAND cell units 1 a E in even-numbered columns includes x (for example, 64) memory cell transistors M connected in series, a drain side selection MOS transistor SGDETr, and a source side selection MOS transistor SGSTr.
  • the drain side selection MOS transistors SGDETr in even-numbered columns are connected to bit lines BLEn and BLEn+1 in even-numbered columns, respectively.
  • source side selection MOS transistors SGSTr are connected to a source line SRC.
  • each of the NAND cell units 1 a E in odd-numbered columns includes x memory cell transistors M connected in series, a drain side selection MOS transistor SGDOTr, and a source side selection MOS transistor SGSTr.
  • the drain side selection MOS transistors SGDOTr in odd-numbered columns are connected to bit lines BLOn and BLOn+1 in odd-numbered columns, respectively.
  • source side selection MOS transistors SGSTr are connected to a source line SRC.
  • Control gates of the memory cell transistors M arranged in rows are connected to word lines WL 0 to WLx, respectively.
  • bit lines BLEn, BLEn+1, BLOn and BLOn+1 are arranged perpendicularly to the word lines WL 0 to WLx and the common source lines SRC.
  • Gates of the drain side selection MOS transistors SGDETr are connected to a drain side selection gate line SGDE.
  • Gates of the drain side selection MOS transistors SGDOTr are connected to a drain side selection gate line SGDO.
  • Gates of the source side selection MOS transistors SGSTr are connected to a source side selection gate line SGS.
  • Sense amplifiers SAEn, SAOn, SAEn+1 and SAOn+1 in the bit line control circuit 2 are connected to bit lines BLEn, BLOn, BLEn+1 and BLOn+1, respectively.
  • the sense amplifiers SAEn, SAOn, SAEn+1 and SAOn+1 are adapted to sense or control potentials on the connected bit lines BLEn, BLOn, BLEn+1 and BLOn+1, respectively.
  • the row decoder 6 includes driver circuits 6 a O and 6 a I, a plurality of (block) decoders 6 b On, 6 b On ⁇ 1, 6 b On ⁇ 2, 6 b In, 6 b In ⁇ 1 and 6 b In ⁇ 2, and control lines CGSGS, CGSGDE, CGSGDO and CGWL.
  • the decoders 6 b On, 6 b On ⁇ 1, 6 b On ⁇ 2, 6 b In, 6 b In ⁇ 1 and 6 b In ⁇ 2 are arranged, for example, on the left and right of the memory cell array 1 (outer side and inner side) at a 2-block pitch to be opposed to each other with the memory cell array 1 between in the word line WL direction.
  • a decoder 6 b On for selecting an even-numbered block BLKOn is disposed in a space located on the left side of the even-numbered block BLKOn and an odd-numbered block BLKIn.
  • a decoder 6 b In for selecting an odd-numbered block BLKIn is disposed in a space located on the right side of the even-numbered block BLKOn and the odd-numbered block BLKIn.
  • a decoder 6 b On ⁇ 1 for selecting an even-numbered block BLKOn ⁇ 1 is disposed in a space located on the left side of the even-numbered block BLKOn ⁇ 1 and an odd-numbered block BLKIn ⁇ 1.
  • a decoder 6 b In ⁇ 1 for selecting an odd-numbered block BLKIn ⁇ 1 is disposed in a space located on the right side of the even-numbered block BLKOn ⁇ 1 and the odd-numbered block BLKIn ⁇ 1.
  • a decoder 6 b On ⁇ 2 for selecting an even-numbered block BLKOn ⁇ 2 is disposed in a space located on the left side of the even-numbered block BLKOn ⁇ 2 and an odd-numbered block BLKIn ⁇ 2.
  • a decoder 6 b In ⁇ 2 for selecting an odd-numbered block BLKIn ⁇ 2 is disposed in a space located on the right side of the even-numbered block BLKOn ⁇ 2 and the odd-numbered block BLKIn ⁇ 2.
  • the decoders 6 b On to 6 b On ⁇ 2 and 6 b In to 6 b In ⁇ 2 correspond to the blocks BLKOn, BLKIn, BLKOn ⁇ 1, BLKIn ⁇ 1, BLKOn ⁇ 2 and BLKIn ⁇ 2, respectively.
  • each of the decoders 6 b On to 6 b On ⁇ 2 and 6 b In to 6 b In ⁇ 2 includes a plurality of transfer MOS transistors TSGS, TSGDE, TSGDO and TWL 0 to TWLx, which are nMOS transistors.
  • Drains of the transfer MOS transistors TSGS, TSGDE and TSGDO are connected to the source side selection gate line SGS, and the drain side selection gate lines SGDE and SGDO, respectively. Drains of the transfer MOS transistors TWL 0 to TWLx are connected respectively to the word lines WL 0 to WLx, which are connected to control gates of the memory cell transistors M.
  • Sources of the transfer MOS transistors TSGS, TSGDE, TSGDO, and TWL 0 to TWLx are connected respectively to the control lines CGSGS, CGSGDE, CGSGDO and CGWL, which are connected to the driver circuits 6 a O and 6 a I.
  • control lines CGSGS, CGSGDE, CGSGDO and CGWL are arranged to be common to the decoders 6 b On, 6 b On ⁇ 1 and 6 b On ⁇ 2.
  • control lines CGSGS, CGSGDE, CGSGDO and CGWL are arranged to be common to the decoders 6 b In, 6 b In ⁇ 1 and 6 b In ⁇ 2.
  • the driver circuits 6 a O and 6 a I are adapted to control gate voltage and source voltages of the transfer MOS transistors TSGS, TSGDE, TSGDO, and TWL 0 to TWLX according to the output of the control circuit 7 .
  • a block selection signal is input to the gates of the transfer MOS transistors TSGS, TSGDE, TSGDO, and TWL 0 to TWLx in accordance with an address which is input to the driver circuits 6 a O and 6 a I from an internal address line which is not illustrated.
  • the row decoder 6 controls the transfer MOS transistors TSGS, TSGDE, TSGDO, and TWL 0 to TWLx in the decoders 6 b On to 6 b On ⁇ 2 by controlling the gate voltage and the source voltages in the driver circuit 6 a O. As a result, the row decoder 6 selects one of the blocks BLKOn, BLKOn ⁇ 1 and BLKOn ⁇ 2 in the memory cell array 1 , and controls write operation and read operation of the selected block.
  • the row decoder 6 controls the transfer MOS transistors TSGS, TSGDE, TSGDO, and TWL 0 to TWLX in the decoders 6 b In to 6 b In ⁇ 2 by controlling the gate voltage and the source voltages in the driver circuit 6 a I. As a result, the row decoder 6 selects one of the blocks BLKIn, BLKIn ⁇ 1 and BLKIn ⁇ 2 in the memory cell array 1 , and controls write operation and read operation of the selected block.
  • (block) decoders 6 b On to 6 b On ⁇ 2 arranged at a 2-block pitch on the left side (outer side) of the memory cell array 1 control the operation of the blocks BLKOn, BLKOn ⁇ 1 and BLKOn ⁇ 2 on the basis of the control signals of a first system which are output from the driver circuit 6 a O.
  • a first internal address line which is not illustrated, is connected to the driver circuit 6 a O to select one of the blocks BLKOn, BLKOn ⁇ 1 and BLKOn ⁇ 2.
  • the driver circuit 6 a O selects one of the blocks BLKOn, BLKOn ⁇ 1 and BLKOn ⁇ 2 in accordance with an address which is input from the first internal address line.
  • (block) decoders 6 b In to 6 b In ⁇ 2 arranged at a 2-block pitch on the right side (inner side) of the memory cell array 1 control the operation of the blocks BLKIn, BLKIn ⁇ 1 and BLKIn ⁇ 2 on the basis of the control signals of a second system which are different from the control signals of the first system.
  • a second internal address line which is different from the first internal address line and which is not illustrated, is connected to the driver circuit 6 a I to select one of the blocks BLKIn, BLKIn ⁇ 1 and BLKIn ⁇ 2.
  • the driver circuit 6 a I selects one of the blocks BLKIn, BLKIn ⁇ 1 and BLKIn ⁇ 2 in accordance with an address which is input from the second internal address line.
  • FIG. 3 is a sectional view showing a section of one memory cell transistor M in the memory cell array 1 shown in FIG. 2 .
  • the memory cell transistor M includes a floating gate FG, a control gate CG (WL), and a diffusion layer 42 .
  • the control gate CG is electrically connected to a word line WL, and the control gate CG is common among a plurality of memory cell transistors M.
  • a floating gate FG is formed over the well 41 via a gate insulation film (tunnel insulation film) 43 .
  • a control gate CG is formed over the floating gate FG via a gate insulation film 45 .
  • the memory cell transistor M stores data according to a threshold voltage. And data stored in the memory cell transistor M can be rewritten by controlling the threshold voltage.
  • the threshold voltage depends upon a charge quantity stored in the floating gate FG.
  • the charge quantity in the floating gate FG can be changed by a tunnel current which passes through the gate insulation film 43 .
  • control gate is provided with a voltage which is sufficiently high as compared with the well 41 and the diffusion layer (source diffusion layer/drain diffusion layer) 42 , then electrons are injected into the floating gate FG through the gate insulation film 43 .
  • the threshold voltage of the memory cell transistor M becomes high (for example, which corresponds to a write state in the case where stored data is bi-valued).
  • the well 41 and the diffusion layer (source diffusion layer/drain diffusion layer) 42 is provided with a voltage which is sufficiently high as compared with the control gate CG, then electrons are emitted from the floating gate FG through the gate insulation film 43 . As a result, the threshold voltage of the memory cell transistor M becomes low (for example, which corresponds to an erased state in the case where stored data is bi-valued).
  • FIG. 4 is a sectional view showing a section of the drain side selection MOS transistors SGDETr and SGDOTr and the source side selection MOS transistor SGSTr in the memory cell array 1 shown in FIG. 2 .
  • a diffusion layer 47 which becomes a source diffusion layer/drain diffusion layer of the drain side selection MOS transistors SGDETr and SGDOTr and the source side selection MOS transistor SGSTr is formed in the well 41 .
  • a control gate 49 (the transfer MOS transistors SGS, SGDE and SGDO) is formed over the well 41 via a gate insulation film 48 .
  • a well (substrate) in which the drain side selection MOS transistors SGDETr and SGDOTr, the source side selection MOS transistor SGSTr, and the aforementioned memory cell transistors M are formed and a well (substrate) in which the transfer MOS transistors TSG 1 , TSG 2 and TWL 0 to TWL 63 ( FIG. 2 ) are formed are subject to element isolation by using the STI (Shallow Trench Isolation) or the like.
  • the substrate (well) voltage of the drain side selection MOS transistors SGDETr and SGDOTr, the source side selection MOS transistor SGSTr, and the memory cell transistors M and the substrate (well) voltage of the transfer MOS transistors TSGS, TSGDE, TSGDO, and TWL 0 to TWLx can be controlled separately.
  • FIG. 5 is a sectional view of a vicinity of a NAND cell unit 1 a E connected to a bit line BLEn of the block BLKOn shown in FIG. 2 obtained when seen along the bit line BLEn.
  • FIG. 6 is a sectional view of a vicinity of a NAND cell unit 1 a O connected to a bit line BLOn of the block BLKOn shown in FIG. 2 obtained when seen along the bit line BLOn.
  • FIG. 7 is a sectional view of a vicinity of a NAND cell unit 1 a E connected to a bit line BLEn+1 of the block BLKOn shown in FIG. 2 obtained when seen along the bit line BLEn+1.
  • the plurality of memory cell transistors M are connected in series between the source diffusion layer 47 of the drain side selection MOS transistor SGDETr and the drain diffusion layer 47 of the source side selection MOS transistor SGSTr.
  • the drain side selection MOS transistor SGDETr is connected at its gate to the drain side selection gate line SGDE (i.e., the drain side selection MOS transistor SGDETr is common at its gate to the drain side selection gate line SGDE) and connected at its drain diffusion layers 47 and 50 to the bit line BLEn.
  • a part of the drain side selection gate line SGDO is located over the expanded drain diffusion layer 50 of the drain side selection MOS transistor SGDETr via the insulation film 48 .
  • the drain side selection gate line SGDO does not form a MOS transistor.
  • a plurality of memory cell transistors M are connected in series between the source diffusion layers 47 and 51 of the drain side selection MOS transistor SGDOTr and the drain diffusion layer 47 of the source side selection MOS transistor SGSTr.
  • the drain side selection MOS transistor SGDOTr is connected at its gate to the drain side selection gate line SGDO (i.e., the drain side selection MOS transistor SGDOTr is common at its gate to the drain side selection gate line SGDO) and connected at its drain diffusion layer 47 to the bit line BLOn.
  • a part of the drain side selection gate line SGDE is located over the expanded drain diffusion layer 51 of the drain side selection MOS transistor SGDOTr via the insulation film 48 .
  • the drain side selection gate line SGDE does not form a MOS transistor.
  • a plurality of memory cell transistors M are connected in series between the source diffusion layers 47 of the drain side selection MOS transistor SGDETr and the drain diffusion layer 47 of the source side selection MOS transistor SGSTr.
  • the drain side selection MOS transistor SGDETr is connected at its gate to the drain side selection gate line SGDE (i.e., the drain side selection MOS transistor SGDETr is common at its gate to the drain side selection gate line SGDE) and connected at its drain diffusion layers 47 and 50 to the bit line BLEn+1.
  • a part of the drain side selection gate line SGDE is located over the expanded drain diffusion layer 50 of the drain side selection MOS transistor SGDETr via the insulation film 48 .
  • the drain side selection gate line SGDO does not form a MOS transistor.
  • FIG. 8 is a plan view of the block BLKOn in the vicinity of the drain side selection MOS transistors SGDETr and SGDOTr.
  • bit lines BLEn, BLOn, BLEn+1 and BLOn+1 As regards the bit lines BLEn, BLOn, BLEn+1 and BLOn+1, only contact parts are shown in FIG. 8 for brevity.
  • element regions AAEn, AAEn+1, AAOn and AAOn+1 in the wells 41 are formed to extend in the bit line direction. These element regions AAEn, AAEn+1, AAOn and AAOn+1 are subject to element isolation from each other by using the STI or the like.
  • a diffusion layer 50 is formed in regions which intersect the drain side selection gate line SGDO extending in the word line direction perpendicular to the bit line direction.
  • a diffusion layer 51 is formed in regions which intersect the drain side selection gate line SGDE extending in the word line direction perpendicular to the bit line direction.
  • the diffusion layers 50 and 51 are formed in the wells 41 in a zigzag form.
  • the blocks BLKOn and BLKIn are formed on the same well 41 .
  • FIG. 9 is a diagram showing an example of a model of the on/off state of the drain side selection MOS transistors at the time of a write operation or a read operation of the NAND flash memory 100 shown in FIG. 2 .
  • FIG. 10 is a diagram showing another example of a model of the on/off state of the drain side selection MOS transistors at the time of a write operation or a read operation of the NAND flash memory 100 shown in FIG. 2 .
  • FIGS. 9 and 10 a configuration relating to the blocks BLKOn, BLKIn, BLKOn ⁇ 1 and BLKIn ⁇ 1 included in the configuration shown in FIG. 2 is shown for brevity.
  • a black circle indicates that the drain side selection MOS transistor is in the on-state, whereas a white circle indicates that the drain side selection MOS transistor is in the off-state.
  • the decoder 6 b On controls potentials on the drain side selection gate lines SGDO and SGDE in the block BLKOn
  • the decoder 6 b In controls potentials on the drain side selection gate lines SGDO and SGDE in the block BLKIn.
  • the drain side selection MOS transistor SGDETr turns on and the drain side selection MOS transistor SGDOTr turns off.
  • the drain side selection MOS transistor SGDETr turns off and the drain side selection MOS transistor SGDOTr turns on.
  • the sense amplifiers SAEn and SAEn+1 in even-numbered columns are brought into the selected state.
  • the sense amplifiers SAOn and SAOn+1 in odd-numbered columns are brought into the selected state.
  • the decoders 6 b On and 6 b In control potentials on the source side selection gate line SGS, the drain side selection gate lines SGDE and SGDO, and the word lines WL 0 to WLx in accordance with the control signals of the first and second systems.
  • the write operations or read operations can be controlled on two different blocks BLKOn and BLKIn in parallel.
  • the two decoders 6 b On and 6 b In control potentials on the source side selection gate line SGS, the drain side selection gate lines SGDE and SGDO, and the word lines WL 0 to WLx in accordance with the control signals of the first and second systems.
  • the erase operations can be controlled on all memory cell transistors in the two selected different blocks BLKOn and BLKIn in parallel.
  • the decoder 6 b On controls potentials on the drain side selection gate lines SGDO and SGDE in the block BLKOn
  • the decoder 6 b In ⁇ 1 controls potentials on the drain side selection gate lines SGDO and SGDE in the block BLKIn ⁇ 1.
  • the drain side selection MOS transistor SGDETr turns on and the drain side selection MOS transistor SGDOTr turns off.
  • the drain side selection MOS transistor SGDETr turns off and the drain side selection MOS transistor SGDOTr turns on.
  • the sense amplifiers SAEn and SAEn+1 in even-numbered columns are brought into the selected state.
  • the sense amplifiers SAOn and SAOn+1 in odd-numbered columns are brought into the selected state.
  • the decoders 6 b On and 6 b In ⁇ 1 control potentials on the source side selection gate line SGS, the drain side selection gate lines SGDE and SGDO, and the word lines WL 0 to WLx in accordance with the control signals of the first and second systems.
  • the write operations or read operations can be controlled on two different blocks BLKOn and BLKIn ⁇ 1 in parallel.
  • the two decoders 6 b On and 6 b In ⁇ 1 control potentials on the source side selection gate line SGS, the drain side selection gate lines SGDE and SGDO, and the word lines WL 0 to WLx in accordance with the control signals of the first and second systems.
  • the erase operations can be controlled on all memory cell transistors in the two selected different blocks BLKOn and BLKIn ⁇ 1 in parallel.
  • FIG. 11 is a flow diagram showing an example of relations between command inputs and operations of the NAND flash memory 100 .
  • a command 60 h is first input to the control circuit 7 via the data input/output terminal 5 and the data input/output buffer 4 .
  • a page address “a” which specifies a first block and word line to be selected (row address) is input.
  • the page address “a” specifies a sense amplifier in an even-numbered column as an address.
  • the row decoder 6 selects a block, a word line, and a sense amplifier in accordance with a control signal which is output from the control circuit 7 .
  • the command 60 h is input to the control circuit 7 again via the data input/output terminal 5 and the data input/output buffer 4 .
  • a page address “b” which specifies a second block and word line (row address) to be selected is input.
  • the page address “b” specifies a sense amplifier in an odd-numbered column as an address.
  • the row decoder 6 selects a block, a word line, and a sense amplifier in accordance with a control signal which is output from the control circuit 7 .
  • a command 30 h is input to the control circuit 7 via the data input/output terminal 5 and the data input/output buffer 4 .
  • a ready/busy signal RY/BY changes from its “high” level to its “low” level.
  • the control circuit 7 controls the internal read operation.
  • the ready/busy signal RY/BY changes from the “low” level to the “high” level.
  • a command 00 h is input to the control circuit 7 via the data input/output terminal 5 and the data input/output buffer 4 .
  • a page address “a” specifying a first block which outputs data and a word line, and a column address specifying a sense amplifier in an even-numbered column which starts serial data output are input.
  • the command 00 h is input to the control circuit 7 again via the data input/output terminal 5 and the data input/output buffer 4 .
  • a page address “b” specifying a second block which outputs data and a word line, and a column address specifying a sense amplifier in an odd-numbered column which starts serial data output are input.
  • control operations such as reading or writings can be conducted on two different blocks in one memory cell array as described heretofore. Therefore, it is possible to provide a NAND flash memory which is also highly convenient for users who attach great importance to the access performance for the random page address besides a greater capacity.
  • an example of a configuration of a NAND flash memory which conducts control operations on an odd-numbered block and an even-numbered block in parallel has been described.
  • one block is selected from among even-numbered blocks BLKOn, BLKOn ⁇ 1 and BLKOn ⁇ 2 by the driver circuit 6 a O disposed on the left side (outer side) of the memory cell array 1 and one block is selected from among odd-numbered blocks BLKIn, BLKIn ⁇ 1 and BLKIn ⁇ 2 by the driver circuit 6 a I disposed on the right side (inner side) of the memory cell array 1
  • the driver circuit 6 a O the case where one block is selected from among even-numbered blocks BLKOn, BLKOn ⁇ 1 and BLKOn ⁇ 2 by the driver circuit 6 a O disposed on the left side (outer side) of the memory cell array 1 and one block is selected from among odd-numbered blocks BLKIn, BLKIn ⁇ 1 and BLKIn ⁇ 2 by the driver circuit 6 a I disposed on the right side (inner side) of the
  • a general configuration of the NAND flash memory according to the second embodiment is the same as the configuration in the first embodiment shown in FIG. 1 .
  • FIG. 12 is a circuit diagram showing an example of a configuration according to the second embodiment which includes the memory cell array 1 , the bit line control circuit 2 and the row decoder 6 shown in FIG. 1 .
  • the same characters as those in the first embodiment shown in FIG. 2 denote like components in the first embodiment.
  • interconnections connected to the driver circuit 6 a I in the right side row decoder 6 and circuit configurations of the decoders 6 b In, 6 b In ⁇ 1 and 6 b In ⁇ 2 are omitted in FIG. 12 for brevity, they are similar to the interconnections connected to the driver circuit 6 a O in the left side row decoder 6 and the circuit configurations of the decoders 6 b On, 6 b On ⁇ 1 and 6 b On ⁇ 2.
  • the configuration of the row decoder 6 is different from the configuration in the first embodiment shown in FIG. 2 , and configurations of the memory cell array 1 , the sense amplifiers SAEn, SAEn+1, SAOn and SAOn+1 are the same as those in the first embodiment shown in FIG. 2 .
  • the row decoder 6 includes driver circuits 6 a O and 6 a I, a plurality of (block) decoders 6 b On, 6 b On ⁇ 1, 6 b On ⁇ 2, 6 b In, 6 b In ⁇ 1 and 6 b In ⁇ 2, and control lines CGSGS, CGSGDE, CGSGDO and CGWL. Furthermore, select lines SEL 0 , SEL 1 and SEL 2 are disposed in each of decoders 6 b On, 6 b On ⁇ 1, 6 b On ⁇ 2, 6 b In, 6 b In ⁇ 1 and 6 b In ⁇ 2.
  • the decoder 6 b On corresponds to the block BLKOn, and includes a plurality of transfer MOS transistors TSGS, TSGDE 1 , TSGDE 2 , TSGDO 1 , TSGDO 2 , and TWL 0 to TWLx, which are nMOS transistors.
  • the decoders 6 b On+1 to 6 b On ⁇ 2 and 6 b In to 6 b In ⁇ 2 respectively correspond to the blocks BLKOn, BLKIn, BLKOn ⁇ 1, BLKIn ⁇ 1, BLKOn ⁇ 2 and BLKIn ⁇ 2, and include a plurality of transfer MOS transistors, which are nMOS transistors.
  • Drains of the transfer MOS transistors TSGS, TSGDE 1 , TSGDE 2 , TSGDO 1 and TSGDO 2 are connected to the source side selection gate line SGS, and the drain side selection gate lines SGDE and SGDO, respectively. Drains of the transfer MOS transistors TWL 0 to TWLx are connected respectively to the word lines WL 0 to WLx, which are connected to control gates of the memory cell transistors M.
  • Sources of the transfer MOS transistors TSGS, TSGDE 1 , TSGDE 2 , TSGDO 1 , TSGDO 2 and TWL 0 to TWLx are connected respectively to the control lines CGSGS, CGSGDE 1 , CGSGDE 2 , CGSGDO 1 , CGSGDO 2 and CGWL, which are connected to the driver circuit 6 a O.
  • control lines CGSGS, CGSGDE 1 , CGSGDE 2 , CGSGDO 1 , CGSGDO 2 and CGWL are arranged to be common to the decoders 6 b On, 6 b On ⁇ 1 and 6 b On ⁇ 2.
  • control lines are arranged to be common to the decoders 6 b In, 6 b In ⁇ 1 and 6 b In ⁇ 2.
  • the driver circuit 6 a O is adapted to control gate voltage and source voltages of the transfer MOS transistors TSGS, TSGDE 1 , TSGDE 2 , TSGDO 1 , TSGDO 2 and TWL 0 to TWLx according to the output of the control circuit 7 .
  • the row decoder 6 controls the transfer MOS transistors TSGS, TSGDE 1 , TSGDE 2 , TSGDO 1 , TSGDO 2 and TWL 0 to TWLx in the decoders 6 b On to 6 b On ⁇ 2 by controlling the gate voltage and the source voltages in the driver circuit 6 a O.
  • the driver circuit 6 a O brings potentials on the select lines SEL 0 and SEL 1 in the decoder 6 b On to the “high” level and brings the potential on the select line SEL 2 in the decoder 6 b On to the “low” level.
  • the control line CGSGDE 1 is electrically connected to the gate of the drain side selection MOS transistor SGDETr in the block BLKOn, and the control line CGSGDO 1 is electrically connected to the gate of the drain side selection MOS transistor SGDOTr.
  • the drain side selection MOS transistors SGDOTr and SGDETr can be controlled to turn on or off by controlling potentials on the control lines CGSGDE 1 and CGSGDO 1 .
  • an even-numbered block BLKOn is selected, and it becomes possible to conduct reading and writing by using the sense amplifiers SAEn and SAEn+1 in an even-numbered column.
  • the driver circuit 6 a O brings the potential on the select lines SEL 0 and SEL 2 in the decoder 6 b On ⁇ 1 to the “high” level and the potential on the select line SEL 1 in the decoder 6 b On to the “low” level in parallel.
  • the transfer MOS transistors TSGS, TSGDE 2 , TSGDO 2 and TWL 0 to TWLx in the decoder 6 b On ⁇ 1 turn on, and the transfer MOS transistors TSGDE 1 and TSGDO 1 in the decoder 6 b On ⁇ 1 turn off.
  • the control line CGSGDE 2 is electrically connected to the gate of the drain side selection MOS transistor SGDETr in the block BLKOn ⁇ 1, and the control line CGSGDO 2 is electrically connected to the gate of the drain side selection MOS transistor SGDOTr.
  • the drain side selection MOS transistors SGDOTr and SGDETr can be controlled to turn on or off by controlling potentials on the control lines CGSGDE 2 and CGSGDO 2 .
  • an even-numbered block BLKOn ⁇ 1 is selected in parallel to the even-numbered block BLKOn, and it becomes possible to conduct reading and writing by using the sense amplifiers SAOn and SAOn+1 in an odd-numbered column.
  • the driver circuit 6 a O can select two blocks from among even-numbered blocks BLKOn, BLKOn ⁇ 1 and BLKOn ⁇ 2 in the memory cell array 1 and control write operations and read operations on the selected blocks.
  • the control lines CGSGDE and CGSGDO included in the control signals of the first system which are output from the driver circuit 6 a O are further divided into two systems: the control lines CGSGDE 1 and CGSGDE 2 ; and the control lines CGSGDO 1 and CGSGDO 2 .
  • double switches (the transfer MOS transistors TSGDE 1 , TSGDE 2 , TSGDO 1 and TSGDO 2 ) are provided in each of the decoders 6 b On, 6 b On ⁇ 1 and 6 b On ⁇ 2, and exclusive control is exercised. As a result, multiple selection by the driver circuits on the same side is implemented.
  • one block is selected from among even-numbered blocks BLKOn, BLKOn ⁇ 1 and BLKOn ⁇ 2 by the driver circuit 6 a O disposed on the left side (outer side) of the memory cell array 1
  • one block is selected from among odd-numbered blocks BLKIn, BLKIn ⁇ 1 and BLKIn ⁇ 2 by the driver circuit 6 a I disposed on the right side (inner side) of the memory cell array 1 .
  • erase operations can be conducted on two blocks selected from among the blocks BLKOn, BLKOn ⁇ 1 and BLKOn ⁇ 2 in parallel by, for example, driving two decoders selected from among the decoders 6 b On to 6 b On ⁇ 2 in parallel.
  • Control operation on the decoders 6 b In to 6 b In ⁇ 2 is the same as that on the decoders 6 b On to 6 b On ⁇ 2.
  • one block is selected from among even-numbered blocks BLKOn, BLKOn ⁇ 1 and BLKOn ⁇ 2 by the driver circuit 6 a O disposed on the left side (outer side) of the memory cell array 1
  • one block is selected from among odd-numbered blocks BLKIn, BLKIn ⁇ 1 and BLKIn ⁇ 2 by the driver circuit 6 a I disposed on the right side (inner side) of the memory cell array 1 .
  • FIG. 13 is a diagram showing an example of a configuration of a logic circuit 600 which generates selection signals SEL 0 , SEL 1 and SEL 2 in the driver circuit shown in FIG. 12 .
  • a logic circuit 600 which generates selection signals SEL 0 , SEL 1 and SEL 2 in the driver circuit shown in FIG. 12 .
  • the first internal address line which is described in the first embodiment and which is not illustrated is divided into two systems: address lines ad 1 and ad 2
  • the second internal address line is also divided into two systems: ad 1 and ad 2 , in the same way.
  • the address line ad 1 is activated in accordance with the page address “a” for specifying the first block and a word line to be selected which is described with reference to FIG. 11
  • the address line ad 2 is activated in accordance with the page address “b” for specifying the second block and a word line to be selected which is described with reference to FIG. 11
  • the logic circuit 600 includes an AND circuit 6 a 1 connected at its inputs to an address line ad 1 and connected at its output to a select line SEL 1 , an AND circuit 6 a 2 connected at its inputs to an address line ad 2 and connected at its output to a select line SEL 2 , and an OR circuit 6 a 3 connected at its inputs to the select lines SEL 1 and SEL 2 and connected at its output to a select line SEL 0 .
  • the logic circuit 600 is provided in the driver circuits 6 a O and 6 a I in association with the decoders 6 b On to 6 b On ⁇ 2 and 6 b In to 6 b In ⁇ 2.
  • the logic circuit 600 corresponding to the decoder 6 b On will now be described. If the page address “a” which is input from the outside specifies the block BLKOn, then the address line ad 1 is activated and the potential on the select line SEL 1 becomes the “high” level whereas the address line ad 2 is not activated and the potential on the select line SEL 2 becomes the “low” level. Therefore, the potential on the select line SEL 0 becomes the “high” level. As a result, the block BLKOn is selected.
  • control line CGSGDE 1 is provided with a potential of the “high” level and the control line CGSGDO 1 is provided with a potential of the “low” level by the driver circuit 6 a O.
  • the transfer MOS transistors TSGS, TSGDE 1 , TSGDO 1 , and TWL 0 to TWLX in the decoder 6 b On are in the on-state, and the transfer MOS transistors TSGDE 2 and TSGDO 2 in the decoder 6 b On are in the off-state. Therefore, potentials on the control lines CGSGS, CGWL, CGSGDE 1 and CGSGDO 1 are transferred, and read operation and write operation can be implemented by the sense amplifiers SAEn and SAEn+1 in the even-numbered column.
  • the logic circuit 600 corresponding to the decoder 6 b On ⁇ 1 will now be described. If the page address “b” which is input from the outside specifies the block BLKOn, then the address line ad 2 is activated and the potential on the select line SEL 2 becomes the “high” level whereas the address line ad 1 is not activated and the potential on the select line SEL 1 becomes the “low” level. Therefore, the potential on the select line SEL 0 becomes the “high” level. As a result, the block BLKOn ⁇ 1 is selected.
  • control line CGSGDE 2 is provided with a potential of the “high” level and the control line CGSGDO 2 is provided with a potential of the “low” level by the driver circuit 6 a O.
  • the transfer MOS transistors TSGS, TSGDE 2 , TSGDO 2 , and TWL 0 to TWLx in the decoder 6 b On are in the on-state, and the transfer MOS transistors TSGDE 1 and TSGDO 1 in the decoder 6 b On are in the off-state. Therefore, potentials on the control lines CGSGS, CGWL, CGSGDE 2 and CGSGDO 2 are transferred, and read operation and write operation can be implemented by the sense amplifiers SAOn and SAOn+1 in the odd-numbered column.
  • FIG. 14 is a diagram showing an example of a model of the on/off state of the drain side selection MOS transistors at the time of a write operation or a read operation of the NAND flash memory 100 shown in FIG. 12 .
  • FIG. 15 is a diagram showing another example of a model of the on/off state of the drain side selection MOS transistors at the time of a write operation or a read operation of the NAND flash memory 100 shown in FIG. 12 .
  • FIGS. 14 and 15 a configuration relating to the blocks BLKOn, BLKIn, BLKOn+1 and BLKIn+1 included in the configuration shown in FIG. 12 is shown for brevity.
  • a black circle indicates that the drain side selection MOS transistor is in the on-state, whereas a white circle indicates that the drain side selection MOS transistor is in the off-state.
  • the decoder 6 b On controls potentials on the drain side selection gate lines SGDO and SGDE in the block BLKOn
  • the decoder 6 b On ⁇ 1 controls potentials on the drain side selection gate lines SGDO and SGDE in the block BLKOn ⁇ 1.
  • the drain side selection MOS transistor SGDETr turns on and the drain side selection MOS transistor SGDOTr turns off.
  • the drain side selection MOS transistor SGDETr turns off and the drain side selection MOS transistor SGDOTr turns on.
  • the sense amplifiers SAEn and SAEn+1 in even-numbered columns are brought into the selected state.
  • the sense amplifiers SAOn and SAOn+1 in odd-numbered columns are brought into the selected state.
  • each of at least the control lines CGSGDE and CGSGDO is further divided into two different systems.
  • the first internal address line is also divided into two systems: the address lines ad 1 and ad 2 .
  • the decoders 6 b On and 6 b On ⁇ 1 control potentials on the source side selection gate line SGS, the drain side selection gate lines SGDE and SGDO, and the word lines WL 0 to WLx.
  • the write operations or read operations can be controlled on two different blocks BLKOn and BLKOn ⁇ 1 in parallel.
  • each of at least the control lines CGSGDE and CGSGDO is further divided into two different systems.
  • the first internal address line is also divided into two systems: the address lines ad 1 and ad 2 .
  • the decoders 6 b On and 6 b On ⁇ 1 control potentials on the source side selection gate line SGS, the drain side selection gate lines SGDE and SGDO, and the word lines WL 0 to WLx.
  • the erase operations can be controlled on all memory cell transistors in two selected different blocks BLKOn and BLKOn ⁇ 1 in parallel.
  • the decoder 6 b In controls potentials on the drain side selection gate lines SGDO and SGDE in the block BLKIn
  • the decoder 6 b In ⁇ 1 controls potentials on the drain side selection gate lines SGDO and SGDE in the block BLKIn ⁇ 1.
  • the drain side selection MOS transistor SGDETr turns on and the drain side selection MOS transistor SGDOTr turns off.
  • the drain side selection MOS transistor SGDETr turns off and the drain side selection MOS transistor SGDOTr turns on.
  • the sense amplifiers SAEn and SAEn+1 in even-numbered columns are brought into the selected state.
  • the sense amplifiers SAOn and SAOn+1 in odd-numbered columns are brought into the selected state.
  • each of at least the control lines CGSGDE and CGSGDO is further divided into two different systems.
  • the second internal address line is also divided into two systems: the address lines ad 1 and ad 2 .
  • the decoders 6 b In and 6 b In ⁇ 1 control potentials on the source side selection gate line SGS, the drain side selection gate lines SGDE and SGDO, and the word lines WL 0 to WLx.
  • the write operations or read operations can be controlled on two different blocks BLKIn and BLKIn ⁇ 1 in parallel.
  • each of at least the control lines CGSGDE and CGSGDO is further divided into two different systems.
  • the second internal address line is also divided into two systems: the address lines ad 1 and ad 2 .
  • the two decoders 6 b In and 6 b In ⁇ 1 control potentials on the source side selection gate line SGS, the drain side selection gate lines SGDE and SGDO, and the word lines WL 0 to WLx.
  • the erase operations can be controlled on all memory cell transistors in two selected different blocks BLKIn and BLKIn ⁇ 1 in parallel.
  • control operations such as reading or writings can be conducted in parallel on two different blocks in one memory cell array as described heretofore.
  • driver circuits are disposed on both sides of the memory cell array to cause a driver circuit on the first side and a driver circuit on the second side to conduct block selection alternately and control operations can be conducted in parallel not only in the case where a driver circuit on the first side and a driver circuit on the second side conduct multiple selection of blocks but also in the case where driver circuits on the first side conduct multiple selection of blocks or driver circuits on the second side conduct multiple selection of blocks.
  • a general configuration of the NAND flash memory according to the present third embodiment is similar to that in the first embodiment shown in FIG. 1 .
  • FIG. 16 is a circuit diagram showing an example of a configuration according to the third embodiment which includes the memory cell array 1 , the bit line control circuit 2 and the row decoder 6 shown in FIG. 1 .
  • the same characters as those in the second embodiment shown in FIG. 12 denote like components in the second embodiment.
  • interconnections connected to the driver circuit 6 a I in the right side row decoder 6 and circuit configurations of the decoders 6 b In, 6 b In ⁇ 1 and 6 b In ⁇ 2 are omitted in FIG. 16 for brevity, they are similar to the interconnections connected to the driver circuit 6 a O in the left side row decoder 6 and the circuit configurations of the decoders 6 b On, 6 b On ⁇ 1 and 6 b On ⁇ 2.
  • the configuration of the row decoder 6 is different from the configuration in the second embodiment shown in FIG. 12 , and configurations of the memory cell array 1 , the sense amplifiers SAEn, SAEn+1, SAOn and SAOn+1 are the same as those in the first embodiment shown in FIG. 2 .
  • the row decoder 6 includes driver circuits 6 a O and 6 a I, a plurality of (block) decoders 6 b On, 6 b On ⁇ 1, 6 b On ⁇ 2, 6 b In, 6 b In ⁇ 1 and 6 b In ⁇ 2, and control lines CGSGS, CGSGDE, CGSGDO and CGWL.
  • the control line CGWL includes control lines CGWL 0 a , CGWL 0 b , CGWLxa and CGWLxb.
  • select lines SEL 0 , SEL 1 and SEL 2 are disposed in each of decoders 6 b On, 6 b On ⁇ 1, 6 b On ⁇ 2, 6 b In, 6 b In ⁇ 1 and 6 b In ⁇ 2.
  • the decoder 6 b On corresponds to the block BLKOn, and includes a plurality of transfer MOS transistors TSGS, TSGDE 1 , TSGDE 2 , TSGDO 1 , TSGDO 2 , TWL 0 a , TWL 0 b to TWLxa and TWL 0 b , which are nMOS transistors.
  • the decoders 6 b On+1 to 6 b On ⁇ 2 and 6 b In to 6 b In ⁇ 2 respectively correspond to the blocks BLKOn, BLKIn, BLKOn ⁇ 1, BLKIn ⁇ 1, BLKOn ⁇ 2 and BLKIn ⁇ 2, and include a plurality of transfer MOS transistors, which are nMOS transistors.
  • the 6 b On to 6 b On ⁇ 2 and 6 b In to 6 b In ⁇ 2 in the third embodiment differs from the second embodiment in that the number of transfer MOS transistors connected to one word line is two.
  • Drains of the transfer MOS transistors TWL 0 a and TWL 0 b are connected to the word line WL 0 , which is connected to control gates of the memory cell transistors M. Drains of the transfer MOS transistors TWLxa and TWLxb are connected to the word line WLx, which is connected to control gates of the memory cell transistors M.
  • Sources of the transfer MOS transistors TWL 0 a , TWL 0 b , TWLxa and TWLxb are connected respectively to the control lines CGWL 0 a , CGWL 0 b , CGWLxa and CGWLxb, which are connected to the driver circuit 6 a O.
  • the remaining configuration of the row decoder 6 in the third embodiment is the same as that of the row decoder 6 in the second embodiment.
  • the driver circuit 6 a O is adapted to control gate voltage and source voltages of the transfer MOS transistors TSGS, TSGDE 1 , TSGDE 2 , TSGDO 1 , TSGDO 2 and TWL 0 a to TWLxb according to the output of the control circuit 7 .
  • the row decoder 6 controls the transfer MOS transistors TSGS, TSGDE 1 , TSGDE 2 , TSGDO 1 , TSGDO 2 and TWL 0 a to TWLxb in the decoders 6 b On to 6 b On ⁇ 2 by controlling the gate voltage and the source voltages in the driver circuit 6 a O.
  • the driver circuit 6 a O brings potentials on the select lines SEL 0 and SEL 1 in the decoder 6 b On to the “high” level and brings the potential on the select line SEL 2 in the decoder 6 b On to the “low” level.
  • the word line WL 0 in the block BLKOn is electrically connected to the control line CGWL 0 a and the word line WLx is electrically connected to the control line CGWLxa.
  • potentials on the word lines WL 0 and WLx in the block BLKOn can be controlled by controlling potentials on the control lines CGWL 0 a and CGWLxa.
  • the driver circuit 6 a O brings the potential on the select lines SEL 0 and SEL 2 in the decoder 6 b On ⁇ 1 to the “high” level and the potential on the select line SEL 1 in the decoder 6 b On ⁇ 1 to the “low” level.
  • the transfer MOS transistors TWL 0 b and TWLxb in the decoder 6 b On ⁇ 1 turn on, and the transfer MOS transistors TWL 0 a and TWLxa in the decoder 6 b On turn off.
  • the word line WL 0 in the block BLKOn ⁇ 1 is electrically connected to the control line CGWL 0 b and the word line WLx is electrically connected to the control line CGWLxb.
  • potentials on the word lines WL 0 and WLx in the block BLKOn ⁇ 1 can be controlled by controlling potentials on the control lines CGWL 0 b and CGWLxb.
  • Remaining operation of the row decoder 6 in the third embodiment is the same as that of the row decoder 6 in the second embodiment.
  • control operations such as reading or writings can be conducted in parallel on two different blocks in one memory cell array in the same way as the second embodiment as described heretofore.
  • two different blocks in one memory cell array can be controlled to have different potentials on word lines.

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JP2009158048A (ja) 2007-12-27 2009-07-16 Toshiba Corp 半導体記憶装置

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