US7461114B2 - Fourier transform apparatus - Google Patents

Fourier transform apparatus Download PDF

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US7461114B2
US7461114B2 US10/645,498 US64549803A US7461114B2 US 7461114 B2 US7461114 B2 US 7461114B2 US 64549803 A US64549803 A US 64549803A US 7461114 B2 US7461114 B2 US 7461114B2
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data
permutating
fourier transform
parallel
transform
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US20040039765A1 (en
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Toshiro Nakazuru
Shigeaki Okutani
Noboru Morita
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Fujitsu Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm

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  • the present invention relates to a Fourier transform apparatus capable of performing discrete Fourier transform at a high speed. More particularly, the present invention is concerned with a Fourier transform apparatus which is divided into two stages, i.e., a preceding stage and a succeeding stage, wherein a same number of radix 2 Fourier transform pipelines (radix 2 pipeline FFTs) are disposed.
  • radix 2 pipeline FFTs radix 2 pipeline FFTs
  • the M(2 m : hereinafter written as 2**m)-point radix 2 pipeline FFT is known as an arithmetic pipeline implemented in m stages each including data permutation and arithmetic operation modules.
  • arithmetic pipeline implemented in m stages each including data permutation and arithmetic operation modules.
  • L-point parallel type Fourier transform circuit (whose inputs/outputs are equal to the transform point number L) is disposed in each of the preceding stage and the succeeding stage, wherein a data permutating circuit termed the corner turner is disposed in precedence to each of the L-point parallel type Fourier transform circuits for data supply thereto.
  • the corner turner is a circuit designed to output two-dimensional data after effecting the transposition thereof by regarding the two-dimensional data as a matrix (refer to Japanese Patent Application Laid-Open No. 59-087575).
  • the input parallel point number or the pipeline width assumes a value greater than or equal to the square root of the Fourier transform point number, which means that the pipeline width smaller than the square root of the transform point number N can not be obtained, to a disadvantage (refer to Patent Publication No. 63-36553).
  • the input parallel point number or the pipeline width can be determined with less dependency on the Fourier transform point number.
  • the input parallelism or the transform point number of the parallel type Fourier transform circuits in the succeeding stage is equal to the number A of the radix 2 pipeline FFTs each of two parallel input/outputs disposed in the preceding stage (i.e., a half of the pipeline width of the apparatus), implementation of the apparatus will encounter difficulty due to the spatial parallelity of the parallel type Fourier transform circuits in the succeeding stage, giving rise to a problem (refer to Japanese Patent Application Laid-Open No. 4-245562).
  • the Fourier transform apparatus features that the first data supply means includes a first memory circuit implemented in a two-bank structure, a writing means for writing alternately and sequentially the input data on an M-by-M basis while changing over banks of the first memory circuit, and a reading means for reading out simultaneously the data from corresponding positions of the two banks of the first memory circuit for supplying the data to the transform means of the preceding stage.
  • An exemplary embodiment of the apparatus described above is shown in FIG. 2 .
  • the Fourier transform apparatus features that the first data supply means is comprised of first and second data permutating modules in two stages for permutating the data in a predetermined order, said first and second data permutating modules being composed of second and third memory circuits for storing data, a read or write address generating circuit conforming to predetermined logics of the second and third memory circuits, respectively, and corner turners for permutating data read out from the second and third memory circuits, respectively, and that the second data supply means is comprised of a third data permutating module, said third data permutating module being composed of a fourth memory circuit for storing data, a read or write address generating circuit conforming to a predetermined logic of the fourth memory circuit and corner turners for permutating data read out from the fourth memory circuit.
  • An exemplary embodiment of the apparatus described above is shown in FIGS. 4 and 5 .
  • the Fourier transform apparatus features that in the case where the number a of the pipeline FFT circuits incorporated in the transform means of the preceding stage and the succeeding stage is two, the first data supply means is comprised of fourth and fifth data permutating modules in two stages, said fourth and fifth data permutating modules being composed of fifth and sixth memory circuits for storing data, respectively, read or write address generating circuits conforming to predetermined logics of the fifth and sixth memory circuits, respectively, and corner turners for permutating data read out from the fifth memory circuit, and that the second data supply means is comprised of a sixth data permutating module, said sixth data permutating module being composed of a seventh memory circuit for storing data, a read or write address generating circuit conforming to a predetermined logic of the seventh memory circuit.
  • the apparatus described above corresponds, for example, to those shown in FIGS. 4 and 5 from which the corner turner 324 is omitted.
  • the Fourier transform apparatus features that in the case where the number a of the pipeline FFT circuits incorporated in the transform means of the preceding stage and the succeeding stage is one, the first data supply means is comprised of seventh and eighth data permutating modules, wherein the seventh data permutating module is composed of an eighth memory circuit for storing data, a read or write address generating circuit which conforms to a predetermined logic of the eighth memory circuit and a parallel-in serial-out circuit for permutating the data read out from the eighth memory circuit, while the eighth data permutating module includes a ninth memory circuit constituted by two banks so that upon data storing, data are written in the two banks alternately M by M data whereas upon data reading, corresponding data of corresponding data sets each of M point data are simultaneously read out from the two banks, respectively, to constitute two parallel imputs of said pipeline FFT circuits and a read or write address generating circuit which operates in conformance to a predetermined logic of the ninth memory circuit, and that the second data supply means is comprised of
  • This apparatus is described in the section (parallel disposition) in the description of the preferred mode for carrying out the invention.
  • the Fourier transform apparatus features that the data distributing/permutating means mentioned above is composed of an eleventh memory circuit for storing data corresponding to the number of Fourier transform apparatuses disposed in parallel, a read or write address generating circuit which conforms to a predetermined logic of the eleventh memory circuit and corner turners for permutating data read out from the eleventh memory circuit to output the data in parallel to the Fourier transform apparatuses, respectively, which are disposed in parallel.
  • An exemplary embodiment of the apparatus described above is shown in FIG. 12 .
  • the Fourier transform apparatus features that the Fourier transform apparatus includes a bypass means for bypassing arithmetic operation performed by the transform means of the preceding stage and the succeeding stage. This apparatus is described in conjunction with the bypass processing in the description of the preferred mode for carrying out the invention.
  • the Fourier transform for M ⁇ M points is performed by dividing the apparatus into two stages, i.e., preceding stage and succeeding stage and disposing a same number of M-point radix 2 pipeline FFT circuits each having two parallel inputs/outputs (with pipeline width of “2”) in each stage.
  • the overall pipeline width is adjusted by the number a of the pipeline FFT circuits disposed in parallel.
  • the M-point Fourier transform are shared by the individual pipeline FFT circuits on a (M/a)-sets basis, respectively, whereby the control such as data distribution, etc. can be facilitated.
  • each radix 2 pipeline FFT circuit having two parallel inputs/outputs is “2” at the most.
  • the intricacy of the signals in the radix 2 pipeline FFT circuit is mitigated, presenting substantially no problem in the implementation.
  • it is required to provide the data permutating means in each stage as the data supplying means.
  • the pipeline stages of the M-point radix 2 pipeline FFT circuits each having two parallel inputs/outputs can be so arranged as to bypass only the arithmetic operation sequentially from the leading stage, whereby the Fourier transform point number can be reduced half by half.
  • transform of M ⁇ M, (M/2) ⁇ M, . . . , 2 ⁇ M points can be realized by changing the mode setting or the like.
  • FIG. 1 is a block diagram showing a Fourier transform apparatus according to the present invention.
  • FIG. 2 is a block diagram showing a first exemplary embodiment of a data permutating module in a preceding stage.
  • FIG. 3 is a block diagram showing an exemplary embodiment of a first read address generating circuit.
  • FIG. 4 is a block diagram showing a data permutating module in the preceding stage in the case where a is not smaller than “2”.
  • FIG. 5 is a block diagram showing a data permutating module in the succeeding stage in the case where a is not smaller than “2”.
  • FIG. 6 is a block diagram showing a second read address generating circuit.
  • FIG. 7 is a block diagram showing a third read address generating circuit.
  • FIG. 8 is a block diagram showing a data permutating module in the preceding stage in the case where a is “1”.
  • FIG. 9 is a block diagram showing a data permutating module in the succeeding stage in the case where a is “1”.
  • FIG. 10 is a block diagram showing a fourth read address generating circuit in the case where a is “1”.
  • FIG. 11 is a block diagram showing a fifth read address generating circuit in the case where a is “1”.
  • FIG. 12 is a block diagram showing a structure of a data distributing/permutating unit.
  • FIG. 13 is a block diagram showing a sixth read address generating circuit in the case where a is not smaller than “2”.
  • FIG. 14 is a block diagram showing the sixth read address generating circuit in the case where a is “1”.
  • FIG. 15 is a block diagram showing 64-point FFT.
  • FIG. 16 is a block diagram showing a data permutating module in the preceding stage of the 64-point FFT.
  • FIG. 17 is a block diagram showing a data permutating module in the succeeding stage of the 64-point FFT.
  • FIG. 1 is a block diagram showing a basic structure of the Fourier transform apparatus according to an embodiment of the present invention (i.e., a mode for carrying out the invention).
  • An FFT 100 shown in FIG. 1 is implemented in two stages, i.e., a preceding stage A and a succeeding stage B, wherein as the transform circuits of the preceding stage, there are provided a number a of M-point radix 2 pipeline FFT circuits 1 each having two parallel inputs/outputs together with a data permutating module 3 which is designed to serve as a first data supply means for supplying data to the pipeline FFT circuits 1 .
  • the transform circuits of the succeeding stage there are provided a number a of M-point radix 2 pipeline FFT circuits 2 each having two parallel inputs/outputs, a data permutating module 4 serving as a second data supply means for supplying data to the pipeline FFT circuits 2 , a twiddle factor multiplication module 7 which is disposed immediately following the data permutating module 4 and which includes 2a complex multiplication circuits 5 for multiplication of twiddle factors and a coefficient memory 6 for storing the twiddle factors.
  • the twiddle factor multiplication module 7 may be provided immediately before the data permutating module 4 of the succeeding stage by altering or modifying appropriately the sequence or order in which the twiddle factors are supplied.
  • FIG. 2 is a block diagram illustrating a first exemplary embodiment (method 1) of the data permutating module of the preceding stage which serves as the data supply means in the preceding stage.
  • a buffer memory 301 is implemented in a double buffering structure for enabling simultaneous write and read accesses and realized in a two-bank structure including banks 301 A and 301 B so that data groups belonging to two different sets can be simultaneously read out in the read-out operation.
  • buffer memory or simply “memory” means the double buffer memory.
  • the input data are sequentially written in the banks by changing over the banks on an M-by-M data basis by means of a write address generating circuit 302 .
  • data are simultaneously read out from corresponding locations of the two banks by means of a first read address generating circuit 303 , whereby every M-th data can be obtained pairwise or on a two-by-two basis, i.e., two data can be obtained in parallel with M data apart.
  • FIGS. 4 and 8 are block diagrams showing a second exemplary embodiment (method 2) of the data permutating module serving as the data supply means in the preceding stage, wherein FIG. 4 shows a preferred exemplary embodiment in the case where a is not smaller than “2” while FIG. 8 shows a preferred exemplary embodiment in the case where a is equal to “1”.
  • Each of the data permutating module 3 B; 3 C of the preceding stage shown in FIGS. 4 and 8 is implemented in a two-stage structure including a first half part and a second half part.
  • data trains are first generated each on an M-by-M data basis from the time-serial parallel data by a first data permutating circuit 310 ; 330 in correspondence to M-point radix 2 pipeline FFT circuits each having two parallel inputs/outputs, respectively, i.e., in a column of a (i.e., two columns in each set of M data), whereon data permutation is so performed by means of the second data permutating circuit 320 ; 340 of the second half part that data is fetched one by one from blocks aligned in a column of a on an M-by-M data basis as generated in the first half part, whereby M data sets are obtained for every M-th data in terms of time-serial data.
  • the first data permutating circuit 310 constituting the first half part of the data permutating module 3 B of the preceding stage is composed of a memory and corner turners, as shown in FIG. 4 , wherein the memory includes a buffer memory 311 serving as a storage means having an input/output width of the data number which corresponds to the input data width, a write address generating circuit 312 and a second read address generating circuit 313 .
  • the corner turners 314 are constituted by a pair of corner turners 314 a and 314 b in correspondence to the odd-numbered input data and the even-numbered input data, respectively.
  • the second data permutating circuit 320 constituting the second half part of the data permutating module 3 B of the preceding stage is comprised of a memory and corner turners similarly to the first data permutating circuit 310 of the first half part, wherein the memory includes a buffer memory 321 serving as the storage means having the input/output width of the data number corresponding to the pipeline width of the transform module, a write address generating circuit 322 and a third read address generating circuit 323 , while the corner turners 324 include four sets of corner turners 324 a , 324 b , 324 c and 324 d into which data group outputted every third line counted from the leading one in the output line array of the memory, data group outputted every third line counted from the third line, data group outputted every third line counted from the second line and data group outputted every third line counted from the fourth line are inputted, respectively, for the data permutation.
  • the memory includes a buffer memory 321 serving as the storage means having the input/
  • the first data permutating circuit 330 of the first half part in the data permutating module 3 C is composed of a memory and corner turners, as shown in FIG. 8 , wherein the memory includes a buffer memory 331 serving as a storage means having an input/output width of the data number which corresponds to the input data width, a write address generating circuit 332 and a fourth read address generating circuit 333 .
  • the corner turners are comprised of a pair of parallel-in/seerial-out circuits 334 a and 334 b in correspondence to the odd-numbered input data and the even-numbered input data, respectively.
  • the second data permutating circuit 340 of the second half part is composed of a buffer memory of a two-bank configuration including memory banks 341 A and 341 B so that two different data groups can simultaneously be read out in the read operation and provided with a write address generating circuit 342 and a fifth read address generating circuit 343 , respectively.
  • the equation (2) can be realized by multiplying the individual outputs resulting from the processing in accordance with the equation (1) by twiddle factor, respectively.
  • This multiplication processing can be carried out by a group of the twiddle factor multiplication circuits disposed in parallel in a number 2a without interruption.
  • the equation (3) for which n 0 is fixed represents M-point DFT equation, which means that the processing can be executed by the M-point radix 2 pipeline FFT circuits.
  • the equation (1) indicates that it is necessary to fetch every M-th data from those inputted serially and supply them to the pipelines on the conditions that k 0 is fixed to a given value and that the value of k 1 varies in a range of “0” to “M ⁇ 1”. This operation is performed by the data permutating circuit of the preceding stage.
  • the index of X 2 is given by M ⁇ n 0 +k 0 . Accordingly, the indexes must assume contiguous values on the presumption that n 0 is fixed to a given value while the value of k 0 varies in a range of “0” to “M ⁇ 1”. Furthermore, the indexes make appearance upon every M-th data in the output of the preceding stage. Thus, it is required to rearrange or permutate the outputs as acquired such that the output data are made contiguous for the indexes before being supplied to the pipelines. In other words, it is necessary to fetch every M-th data from the data array outputted from the preceding stage and supply them to the pipelines. This operation is carried out by the data permutating module of the succeeding stage.
  • the first input data line, . . . , the 2b-th input data line are shown orderly from the top.
  • 2b represents the parallelism of the inputs
  • b represents a power of “2” because M must be aliquot
  • a represents the numbers of the individual pipeline FFT circuits in the preceding and succeeding stages, respectively, and thus a is a divisor of M, also a power of “2”.
  • each group mentioned above is a data set including M point data contiguous time-serially
  • the permutating method in the preceding stage resides in collecting the data at the corresponding locations in M groups one by one to acquire a data set including M data apart by M points time-serially.
  • each pipeline FFT has two parallel inputs, it is to read the data simultaneously from two data groups.
  • the memory is divided into banks so that odd-numbered data group and even-numbered data group can be stored in the different bank memories, respectively.
  • the data permutating module 3 A of the preceding stage shown in FIG. 2 in conjunction with the method 1 is so arranged that the data inputted in parallel on a 2b-by-2b data basis are stored 2b by 2b in one of the banks 301 A and 301 B of the double buffer memory by changing over alternately the banks every time the number of data attains M while 2b data are read out simultaneously from two banks of the other memory with a data required from the 2b data being sent out.
  • FIG. 3 is a block diagram showing an exemplary structure of the first read address generating circuit 303 .
  • the first read address generating circuit may be so implemented as to avoid useless read operation although it depends on the memory device configuration.
  • a group number counter 3031 M/2-counter
  • a column number counter 3032 B-counter
  • a row group number counter 3033 C-counter
  • the column data read address is constituted simply by concatenating the bits of the group number counter 3031 and the column number counter 3032 in this order.
  • the value of the row group number counter 3033 is employed as a select signal for selecting a concerned data from the column.
  • the group number counter 3031 , the column number counter 3032 and the row group number counter 3033 are so interconnected that with the carry in the group number counter 3031 , the row group number counter 3033 is updated while with the carry in the row group number counter 3033 , the column number counter 3032 is updated, as a result of which a data held at corresponding locations in the individual groups (i.e., data for which the positions of the relevant columns are same in the individual groups and whose positions in the columns are same) are contiguously read out on a time-serial basis.
  • the permutation is performed in a single step, while in the case of the method 2 illustrated in FIGS. 4 and 8 , the permutation is carried out in two steps.
  • the first data permutating circuit 310 is so designed as to rearrange or permutate M data sets each consisting of M point data which are time-serially continuous into a a columns. More specifically, permutation is so performed that in each of the data sets, data are arrayed in two columns. Processing procedure to this end will be described below.
  • M groups are classified into A clusters each having a groups to be processed in the manner as follows.
  • A is equal to “M/a” and represents the number of M point data sets to be processed by one FFT circuit.
  • a column consisting of b data of even-valued indexes (every odd-numbered data) of the first column in each of the groups belonging to the first cluster as well as a column consisting of a data of odd-valued indexes (every even-numbered data) of the first column mentioned above are generated, whereon transposition is performed on the odd-numbered data and the even-numbered data by regarding them as being arrayed in a (b ⁇ a) matrix.
  • a column consisting of b odd-numbered data and a column consisting of b even-numbered data are generated from the second columns of every groups of the first cluster, whereon the odd-numbered data and the even-numbered data are transposed, being regarded as the (b ⁇ a) matrix, to be disposed laterally next to the transposed data of the first column.
  • columns each consisting of b odd-numbered data and b even-numbered data are generated from the B-th columns of every group belonging to the first cluster, whereon the odd-numbered data and the even-numbered data are transposed on the presumption that these data are arrayed in the (b ⁇ a) matrix to be disposed laterally next to the transposed data of the (B ⁇ 1)-th column.
  • the second group mentioned below is derived from individual groups of the second cluster, and finally the A-th group is derived from the A-th cluster, as shown in the following table 2.
  • the first data permutating circuit 310 shown in FIG. 4 is so arranged that the data inputted in parallel on a 2b-by-2b basis are stored orderly 2b by 2b in one of the buffers of the double buffer memory 311 while the data are read out 2b by 2b in parallel from the other buffer of the memory 311 in the read-out order mentioned above with the data being sent out a by a from each of the pair of corner turners (i.e., 2a data in total are sent out from the two corner turners).
  • FIG. 6 shows a typical arrangement of the second read address generating circuit 313 .
  • a group cluster number counter 3131 A-counter
  • a group number counter 3132 a-counter
  • a column number counter 3133 B-counter
  • the address 3134 is constituted simply by concatenating the bits of these counters in this order.
  • the group number counter 3132 and the column number counter 3133 are carry-connected such that the column number counter 3133 is updated by the carry of the group number counter 3132 by interchanging the connecting destinations of the carries of the group number counter 3132 and the column number counter 3133 .
  • the columns located at corresponding positions in every group belonging to the cluster are read out contiguously on the time serial basis.
  • the time-serially contiguous M-point data sets (each set consisting of two columns) are organized into a columns. Accordingly, by collecting subsequently the data at corresponding positions in the individual sets one-by-one, there can be acquired the data set consisting of M data mutually separated time-serially by M points on a time-serial basis. Since data in each data set are arrayed two columns, each of the columns in the group includes two data points which belong to the same set of the contiguous M-point data. Thus, when reading is performed on a column-by-column basis, there can be obtained the data for two pipeline FFTs. In general, for the a pipeline FFT circuits, read-out processing may be performed on an a/2-by-a/2 column basis.
  • the individual groups are processed on a cluster-by-cluster basis in the manner described below.
  • every third data is fetched, starting from the leading one, to form a/2 columns each of a/2 data, every third data is fetched, starting from the third one, to form a/2 columns each of a/2 data, every third data is fetched, starting from the second one, to form a/2 columns each of a/2 data, and every third data is fetched, starting from the fourth one, to form a/2 columns each of a/2 data, whereon transposition is performed by regarding that they are each in the form of a (a/2) ⁇ (a/2) matrix.
  • every third data is fetched, starting from the leading one, to form a/2 columns each of a/2 data
  • every third data is fetched, starting from the third one, to form a/2 columns each of a/2
  • every third data is fetched, starting from the second one, to form a/2 columns each of a/2 data
  • every third data is fetched, starting from the fourth one, to form a/2 columns each of a/2 data, whereon the transposition is performed by regarding that they are each in the form of a (a/2) ⁇ (a/2) matrix, to be disposed laterally next to the transposed data fetched from the first group.
  • a/2 columns each of a/2 data fetched third by third, staring from the leading data, in each column of the first cluster belonging to the A-th group, a/2 columns each of a/2 data fetched third by third, starting from the third data, a/2 columns each of a/2 data fetched third by third, starting from the second data, and a/2 columns each of a/2 data fetched third by third, starting from the fourth data, are transposed by regarding that they are in the form of a (a/2) ⁇ (a/2) matrix to be disposed laterally next to the data fetched from the (A ⁇ 1)-th group and transposed.
  • data are fetched in the form of a (a/2) ⁇ (a/2) matrix to be transposed and then disposed laterally next to the transposed data of the (A ⁇ 1)-th group.
  • a third group can be obtained.
  • the data inputted in parallel on a 2a-by-2a data basis are stored sequentially in one of the double buffer memories on a 2a-by-2a basis while the data are read out in parallel from the other memory on a 2a-by-2a basis in the read-out sequence mentioned above with the data being sent out a/2 by a/2 from each of the four corner turners (i.e., 2a data from the four corner turners in total).
  • FIG. 7 shows a typical arrangement of the third read address generating circuit 323 .
  • a group number counter 3231 A-counter
  • a column cluster number counter 3232 A-counter
  • a column number counter 3233 a/2-counter
  • the address is constituted simply by concatenating bits of these counter in this order.
  • the group number counter 3231 and the column cluster number counter 3232 are carry-connected such that the column cluster number counter 3232 is updated by the carry of the group number counter 3231 .
  • reading of the column clusters located at corresponding positions in the individual groups is performed consecutively on a time-serial basis.
  • Operation of the data permutating module of the succeeding stage is utterly same as that of the second half part of the permutating method 2 in the preceding stage.
  • the outputs of pipeline FFTs in the preceding stage are arrayed, as shown in the undermentioned table 4. Individual lines conform to the data output sequence from the output lines of the preceding stage (i.e., two lines correspond to one pipeline output).
  • data sets each of M data separated by M points are formed from the FFT output array of the preceding stage to be permutated in a columns.
  • data in each data set are arrayed in two columns. Since in the output of the preceding stage, M-point data sets (each set is in a column of two) are arrayed in a columns, there can be obtained the data set constituted by M data separated by M points can be obtained by collecting one-by-one the data of the corresponding positions in the individual sets.
  • each of the columns in the group contains two data which belong to the same M-point data set.
  • data may be read out and permutated on an a/2-by-a/2 column basis.
  • Each group can be divided into A clusters each constituted by a/2 columns on the presumption that every cluster consists of a/2 columns.
  • the individual groups are processed on a cluster-by-cluster basis in a manner described below.
  • every third data is fetched, starting from the leading one, to form a/2 columns each of a/2 data
  • every third data is fetched, starting from the third one, to form a/2 columns each of a/2 data
  • every third data is fetched, starting from the second one, to form a/2 columns each of a/2 data
  • every third data is fetched, starting from the fourth one, to form a/2 columns each of a/2 data, whereon the data are transposed by regarding that they are each in the form of (a/2) ⁇ (a/2) matrix.
  • every third data is fetched, starting from the leading one, to form a/2 columns each of a/2 data
  • every third data is fetched, starting from the third one, to form a/2 columns each of a/2
  • every third data is fetched, starting from the second one, to form a/2 columns each of a/2 data
  • every third data is fetched, starting from the fourth one, to form a/2 columns each of a/2 data, whereon the transposition is performed by regarding that they are each in the form of (a/2) ⁇ (a/2) matrix, to be disposed laterally next to the transposed data fetched from the first group.
  • every third data is fetched, starting from the leading one, to form a/2 columns each of a/2 data
  • every third data is fetched, starting from the third one, to form a/2 columns each of a/2 data
  • every third data is fetched, starting from the second one, to form a/2 columns each of a/2 data
  • every third data is fetched, starting from the fourth one, to form a/2 columns each of a/2 data, whereon the transposition is performed by regarding that they are each in the form of (a/2) ⁇ (a/2) matrix and then disposed laterally next to the transposed data matrix of the (A ⁇ 1)-th group.
  • data are fetched in the form of a (a/2) ⁇ (a/2) matrix to be transposed and then disposed laterally next to the transposed data derived from the (A ⁇ 1)-th group.
  • the output processing can be started by transposing them in the form of the (a/2)/ ⁇ (a/2) matrixes, respectively.
  • the data inputted in parallel on a 2a-by-2a basis are stored sequentially in one of the double buffer memories while the data are read out in parallel from the other memory on a 2a-by-2a basis in the read-out sequence mentioned above with the data being sent out a/2 by a/2 from each of the four corner turners, i.e., 2a data in total from the four corner turners, similarly to the case of the second data permutating circuit 320 constituting the second half part of the data permutating method 2 in the preceding stage.
  • the third read address generating circuit 323 is same as the second data permutating circuit.
  • twiddle factor multiplication module In succession to the data permutation in the succeeding stage, multiplication of twiddle factors is performed by the twiddle factor multiplication module.
  • the twiddle factors are such as enumerated in the table 6.
  • the output index order resulting from the processing of the equation (1) with the radix 2 pipeline FFTs bears bit-reverse relation to the index order derived from the DFT equation.
  • data array is given by the one-dimensional expression.
  • the values multiplied by M represent the row indexes with the remainder representing the column indexes.
  • the exponent of the twiddle factor it is necessary to use the bit reverse value of the row index. Since the number of the pipeline FFT circuits is a, the rows of the data array are divided into a sets each of two rows, and each set is subdivided into A subsets each consisting of M point data. From the viewpoint of the column, the whole can be regarded as being divided into A groups.
  • the array of the twiddle factors corresponding to that of the input data are such as mentioned below, where BR[ ] represents the bit reverse operation on the presumption that the numerical value parenthesized by [ ] is m bits binary data.
  • the first data permutating circuit 330 shown in this figure is so arranged as to permutate M data sets each of M point data contiguous time-serially to one column.
  • the data are so permutated to be two columns. Procedure to this end will so described below.
  • M groups are processed as follows.
  • a column consisting of b odd-numbered data and a column consisting of b even-numbered data are formed, whereon the odd-numbered data and the even-numbered data are transposed by regarding that they are in the form of (b ⁇ 1) matrix.
  • a column consisting of b odd-numbered data and a column consisting of b even-numbered data are generated from the second column of first group, whereon the odd-numbered data and the even-numbered data are transposed, being regarded as the (b ⁇ 1) matrix, to be disposed laterally next to the transposed data of the first column.
  • a column consisting of b odd-numbered data and a column consisting of b even-numbered data are generated from the B-th column of first group, whereon the odd-numbered data and the even-numbered data are transposed on the presumption that these data are arrayed in the (b ⁇ 1) matrix to be disposed laterally next to the data transposed from the (B ⁇ 1)-th column.
  • the second group shown in the table 8 mentioned below is derived from the second group.
  • the M-th group shown in the table 8 is obtained from the M-th group.
  • output processing can be started immediately after reading out from the memory the column consisting of b odd-numbered data and the column of the b even-numbered data by executing the transposition processing on these data regarded as being arrayed in the (b ⁇ 1)-matrix.
  • the first data permutating circuit 330 shown in FIG. 8 is so arranged that the data inputted in parallel on a 2b-by-2b basis are stored sequentially on a 2b-by-2b basis in one of the double buffer memories while the data are read out in parallel from the other memory on a 2b-by-2b basis in the read-out order mentioned previously with the data being sent out one by one from each of the two sets of corner turners (parallel-in, serial-out circuit in this case), i.e., 2 data in total are sent out from the two corner turners.
  • FIG. 10 shows an exemplary arrangement of the fourth read address generating circuit 333 .
  • a group number counter (M-counter) 3331 and a column number counter (B-counter) 3332 serve as the means for specifying the groups and the columns in the groups, respectively, as described hereinbefore in conjunction with the permutation.
  • the address is constituted simply by concatenating the bits of these counters in this order.
  • data sets each consisting of M data separated time-serially by M points are formed on the basis of the results of the first half part so that they can be inputted to one pipeline FFT circuit. In other words, it is necessary to permutate or rearrange them in a column of one.
  • the time-serially contiguous M point data sets (each set consisting of two columns) are organized into one column. Accordingly, by collecting subsequently the data at the corresponding positions in the individual sets one-by-one, there can be obtained the data set constituted by M data mutually separated by M points time-serially. Since the data in each set are arrayed in two columns, two data of each column in the group belong to other set also consisting of M data separated by M points. Assuming that the whole column is to be read out on a column-by-column basis, the other column is not immediately required but repeated read operation is required since only one set of pipeline FFT circuit is provided. However, because the pipeline FFT circuit is so implemented as to have two-parallel inputs/outputs, other one data of the same set of M data separated by M points is required. In other words, data read operation has to be performed simultaneously from the two groups.
  • the data groups obtained from the first data permutating circuit 330 are stored in the buffer memory which is divided into two banks, i.e., the odd-numbered groups are stored in one bank with the even-numbered groups being stored in the other bank. From each of the groups stored in the banks, respectively, data is read out one by one, starting from the leading data, and hence two data in total are inputted to the pipeline FFT circuit as two parallel input data. More specifically, from the individual groups stored in the banks, data located at corresponding positions in the individual groups are read out one by one, e.g.
  • the second data permutating circuit 340 shown in FIG. 8 is implemented such that the data inputted thereto in parallel two by two are stored in one of the double buffer memories on a two-by-two basis which alternately changing over the double buffer memories every time M data have been stored in one of the double buffer memories, while two data are simultaneously read out from two banks, respectively, of the other memory, whereon the one necessary data of the two read out from the two banks, respectively, and hence two data in total are sent out.
  • FIG. 11 shows an exemplary arrangement or configuration of the fifth read address generating circuit 343 .
  • a group number counter 3431 M/2-counter
  • a column number counter 3432 M/2-counter
  • a row number counter 3433 (2-counter) serves as select means for selecting one data from the column data (including two data).
  • the column data read address is constituted simply by concatenating the bits of the group number counter 3431 and the column number counter 3432 .
  • the value of the row number counter 3433 is employed as a select signal for selecting one concerned data from the column.
  • the group number counter 3431 , the column number counter and the row number counter 3433 are so interconnected that with the carry in the group number counter 3431 , the row number counter is updated while with the carry in the row number counter 3433 , the column number counter is updated, as a result of which one data held at corresponding locations in the individual groups (i.e., data for which the positions of the relevant columns are same in the individual groups and whose positions in the columns are same) is successively read out on a time-serial basis.
  • Operation of the data permutating module 4 B of the succeeding stage shown in FIG. 9 is utterly same as that of the second data permutating circuit 340 of the data permutating module of the preceding stage (second half part of the method 2).
  • the outputs of the pipeline FFTs in the preceding stage are in the array such as shown in the undermentioned table 10. Individual lines correspond to the data output sequences from the FFT output lines of the preceding stage.
  • data sets each of M data separated by M points from the FFT output array of the preceding stage are formed and permutated so as to be in one column. More specifically, data in each data set are arrayed in two columns. Since in the FFT output of the preceding stage, M-point data sets (each set constituted by two columns) are arrayed in one column, there can be obtained the data set constituted by M data spaced or separated by M points by collecting the data at corresponding positions in the individual sets on a one-by-one basis.
  • the data groups obtained from the pipeline FFT circuit of the preceding stage are stored in the buffer memory which is divided into two banks (bank A, bank B), i.e., the odd-numbered groups are stored in one bank with the even-numbered groups being stored in the other bank, respectively.
  • Data is read out one by one, starting from the leading data of the corresponding group in the bank, and hence two data in total are inputted to the pipeline FFT circuit as two parallel input data.
  • the lines constitute two parallel inputs to the pipeline FFT circuit. In practical application, however, it is not required to wait for completion of the permutation described above until all the groups up to the M-th group have been obtained.
  • the data can be read out from the two banks to be immediately outputted to the pipeline FFT circuit.
  • the data permutating module 4 B of the succeeding stage shown in FIG. 9 is implemented such that the data inputted thereto in parallel on a two-by-two basis are stored two by two in one of the double buffer memories by alternately changing over the banks 341 A′ and 341 B′ every time M data have been stored, while two data are simultaneously read out from the two banks, respectively, of the other memory, whereon one necessary data of the two read out from each of the two banks are sent out.
  • the fifth read address generating circuit 343 ′ is implemented in the same configuration as the fifth read address generating circuit 343 of the second data permutating circuit 340 of the first data permutating circuit 330 in the preceding stage.
  • twiddle factor multiplication module In succession to the data permutation in the succeeding stage, multiplication of twiddle factors is performed by the twiddle factor multiplication module.
  • BR[ ] represents the bit reverse operation with the numerical value parenthesized by [ ] being m bits binary data.
  • the input rate of data can not be coped with due to restrictions imposed from the viewpoint of the package and others.
  • the input rate of data is equal to operation rate of the apparatus and the data input parallelism 2b is greater than the total pipeline width 2a of the pipeline FFTs and others.
  • the measures for tackling the problem there is known a method according to which the apparatuses are disposed in parallel.
  • the data input lines may be coupled to the individual apparatuses through the medium of multiplexer.
  • FIG. 12 shows an arrangement of a data distributing/permutating module 8 suited for the scheme mentioned just above.
  • the size (number of words) of the integrated buffer memory is so selected as to be equal to the product of the number of data to undergo Fourier transform (also referred to as the Fourier transform point number) and the number of the apparatuses disposed in parallel with the memory size corresponding to the Fourier transform point number being allocated to keep data for apparatuses each (the memory size is doubled when the buffering part is included). Further, the size of the corner turners for the data permutation is selected to correspond to the multiple of the number of the apparatuses disposed in parallel. Writing to the integrated buffer is performed orderly on a Fourier transform point number basis for each apparatus.
  • reading from each apparatuses-allocated area is effected sequentially a times, i.e., for a columns, on a 2b-by-2b basis in parallel, to be outputted to the corner turners, as described hereinbefore in conjunction with the data permutation (method 2) in the preceding stage.
  • a sixth read address generating circuit 82 corresponding to the demultiplexer control for the data read operation is implemented in such configuration as shown in FIG. 13 .
  • an apparatus counter 824 is additionally provided for the purpose of controlling selection of individual apparatuses-allocated areas of the buffer memory.
  • a group cluster number counter 821 (A-counter), a group number counter 822 (a-counter) and a column number counter 823 (B-counter) serve as the means for specifying the cluster, the groups in the cluster and the columns in the groups, respectively, similarly to the first permutating circuit (first half part) designed for carrying out the permutating method 2 as described hereinbefore.
  • the apparatus counter serves as the means for specifying the object data (clusters) of the individual apparatuses.
  • the address is constituted simply by concatenating the bits of the apparatus counter 824 , the group cluster number counter 821 , the group number counter 822 and the column number counter 823 in this order.
  • the apparatus counter 824 is updated by the carry of the group number counter 822
  • the column number counter 823 is updated by the carry of the apparatus counter 824
  • the group cluster number counter 821 is updated by the carry of the column number counter 823 .
  • the sixth read address generating circuit shown in FIG. 13 is modified to the structure shown in FIG. 14 in which the a counter shown in FIG. 13 is spared.
  • FFT fast Fourier transform
  • the data permutating circuit module is so arranged as to permutate M input data such that paired data composed of those data which are mutually separated by M/(2**1) at the first stage, paired data composed of those data which are mutually separated by M/(2*2) at the second stage, paired data composed of those data which are mutually separated by M/(2**3) at the third stage, and hence paired data composed of those data which are mutually separated by one at the final stage constitute the two parallel inputs for the arithmetic modules, respectively.
  • one of the two parallel inputs is multiplied by a twiddle factor, whereon the product resulting from the multiplication and the other input undergo the butterfly operation (for determining a sum and a difference of the two inputs).
  • data permutation is effected such that when one string of M point time-serial data is supplied to two input ports via a demultiplexer or alternatively when M point time-serial data is divided just at a midpoint, whereon temporally earlier half of M/(2**1) time-serially contiguous data is supplied to the port x with the later half of M/(2**1) time-serially contiguous data being supplied to the port y , then the temporally earlier half of M/(2**1) contiguous data are outputted from the port a while the temporally later half of M/(2**1) contiguous data are outputted from the port b .
  • data permutation is performed such that M/(2**1) data inputted through the input port x is divided into two parts, whereon the temporally earlier half of M/(2**2) data is transferred to the output port a with the temporally later half of M/(2**2) data being transferred to the output port b .
  • M/(2**1) data inputted through the input port y is divided by two, whereon the temporally earlier half of M/(2**2) data is transferred to the output port a with the temporally later half of M/(2**2) data being transferred to the output port b .
  • data permutation is effected such that the first M/(2**2) data inputted through the input port x is firstly divided by two, whereon the temporally earlier half of M/(2**3) data is transferred to the output port a with the temporally later half of M/(2**3) data being transferred to the output port b . Thereafter, the first M/(2**2) data inputted through the input port y is divided by two, whereon the temporally earlier half of M/(2**3) data is transferred to the output port a with the temporally later half of M/(2**3) data being transferred to the output port b .
  • the succeeding remaining M/(2**2) data from the input port x is divided by two, whereon the temporally earlier half of M/(2**3) data are transferred to the output port a with the temporally later half of M/(2**3) data being transferred to the output port b .
  • the succeeding remaining M/(2**2) data from the input part y are divided by two, whereon the temporally earlier half of M/(2**3) data is transferred to the output port a with the temporally later half of M/(2**3) data being transferred to the output port b .
  • the fifth stage et seq. data are divided finely to be permutated.
  • the data making appearance at the output ports a and b , respectively, of the first stage are time-serially separated just by M/(2**1) samples.
  • the M/(2**1) contiguous data are divided by two to be fed to the output ports a and b , respectively. Accordingly, the data making appearance at the output ports a and b are separated or distanced by M/(2**2) samples which is a half of M/(2**1) samples.
  • the M/(2**2) contiguous data are divided by two to be transferred to the output ports a and b , respectively. Accordingly, the data making appearance at the output ports a and b are separated by M/(2**3) samples which is a half of M/(2**2) samples.
  • the Fourier transform point number i.e., the number of data for Fourier transform
  • the data supplied to the pipeline FFT of the preceding stage may be fetched ⁇ by ⁇ every M-th data to be supplied to the pipeline FFT on a ⁇ -by- ⁇ basis.
  • the data permutating module of the preceding stage of the present invention described hereinbefore is used the columns of individual groups of the output data ⁇ X 1 (n) ⁇ from the pipeline FFT of the preceding stage are virtually partitioned into M/ ⁇ sets on an ⁇ /2-column basis and the output sequence is utterly same as that of the pipeline FFT of the preceding stage of the (M ⁇ M)-point pipeline FFT.
  • the data to be inputted to the pipeline FFT of the succeeding stage may be fetched one by one from the corresponding positions of the M groups, respectively, (i.e., M data in total are fetched), which is nothing but the data permutation performed in the succeeding stage described previously.
  • the bypass function is applied up to the last arithmetic operation in the preceding stage
  • the very input data strings for the preceding stage pipeline FFT are sequentially outputted intactly. Accordingly, after the data permutation in the data permutating module of the succeeding stage, there can be obtained the original time-serially contiguous M-point based data.
  • the results of the M-point FFTs can be obtained sequentially.
  • results of the FFT are obtained for the number of points less than M/2 points inclusive.
  • the Fourier transform apparatus having a function capable of performing the Fourier transform for N/2 . . . 2 points by adopting the radix 2 pipeline FFTs having the function to bypass the arithmetic operation itself in the preceding and succeeding stages.
  • This multiplication module 107 includes a complex multiplication circuit 105 and a coefficient memory 106 .
  • the order in which the data undergone the data permutation are outputted as the transform proceeds will be described below.
  • the input data y(k) is rearranged or permutated as shown in the table 15 by the second half part 103 b of the data permutating module 103 (see FIG. 16 for details).
  • the read address generating circuits 103 a - 1 and 103 b - 1 correspond to those shown in FIGS. 6 and 7 , respectively.
  • the intra-cluster column number counter is deleted, since the count number of the intra-cluster column number counter is one.
  • the sequence of the data Y(k) is such as shown in the undermentioned table 16.
  • the read address generating circuit 104 - 1 shown in the figure corresponds to the read address circuit shown in FIG. 7 .
  • the intra-cluster column number counter is omitted from illustration, because the count number of the intra-cluster column number counter is one.
  • each stage includes M (power of 2)-point radix 2 pipeline FFT circuits each having two-parallel inputs/outputs in a number of a (divisor of M) for which the numbers of transform points are equal and the data permutating means for data supply to the transform means in each stage.
  • M power of 2
  • the pipeline width of the apparatus can be made to be independent of the transform point numbers of the individual pipeline FFT circuits in each stage.

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