US7301842B2 - Synchronous pseudo static random access memory - Google Patents

Synchronous pseudo static random access memory Download PDF

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US7301842B2
US7301842B2 US11/326,177 US32617705A US7301842B2 US 7301842 B2 US7301842 B2 US 7301842B2 US 32617705 A US32617705 A US 32617705A US 7301842 B2 US7301842 B2 US 7301842B2
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signal
latency
output
precharge
control circuit
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US20070002651A1 (en
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Yin-Jae Lee
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Definitions

  • the present invention relates to a synchronous pseudo random access memory (PSRAM); and, more particularly, to a synchronous PSRAM for improving an operation efficiency by varying the latency according to the refresh operation.
  • PSRAM synchronous pseudo random access memory
  • a semiconductor memory device includes a plurality of memory cells, a plurality of sense amplifiers for driving the memory cells, a row decoder, and a column decoder.
  • a data stored in a predetermined memory cell is selected by using the row decoder and the column decoder and, then, amplified by the sense amplifier.
  • the memory cell of a dynamic random access memory is provided with one cell transistor performing a switching operation and one capacitor storing the data. Meanwhile, the data stored in the capacitor is discharged because of a leakage current occurring at a PN junction of the cell transistor. Therefore, a refresh operation is performed to thereby maintain the original data level by recharging the capacitor.
  • DRAM dynamic random access memory
  • the refresh operation is similar to a read/write operation of the DRAM. That is, the refresh operation is performed by amplifying the data stored in the memory cell and, then, restoring the data into the memory cell.
  • the refresh operation should be performed more frequently to maintain the data.
  • a refresh period becomes smaller, the performance degradation of the memory device occurs because an external device is not able to access to the memory device while the refresh operation is performed.
  • a pseudo static random access memory PSRAM is used.
  • the PSRAM is a kind of DRAM which is operated like an SRAM.
  • the PSRAM continuously performs a usual read/write operation and a refresh operation during one memory access cycle. Therefore, the PSRAM can be operated just like the SRAM though it is a DRAM actually.
  • the PSRAM performs a paging operation asynchronously.
  • a normal address for enabling a corresponding word line is activated and, then, after a predetermined time, i.e., a memory access time tRC, a page address for enabling a corresponding page is activated.
  • the memory access time tRC includes an address active cycle for a read/write operation and a cell refresh cycle for the refresh operation.
  • the memory access time tRC usually is about 75 ns to about 80 ns.
  • a synchronous PSRAM has an initial latency in order to obtain the memory access time tRC.
  • the initial latency corresponds to the number of clocks from a timing of starting a burst operation to a timing of outputting a data.
  • FIG. 1 is block diagram showing a conventional latency control circuit for use in a conventional PSRAM.
  • the conventional latency control circuit includes a latency decoder 1 .
  • the latency decoder 1 decodes a latency set signal BCR ⁇ 13 : 11 > and outputs a fixed latency signal LT ⁇ 2 : 6 > determining a latency of a fixed length.
  • FIG. 2 is a timing diagram demonstrating a read operation of the conventional PSRAM.
  • the initial latency is always fixed. For example, when a clock period CLK is about 20 ns and the memory access time tRC is about 70 ns, the initial latency is fixed to 4. Further, when the memory access time tRC is about 85 ns, the initial latency is fixed to 5.
  • the synchronous PSRAM includes a wait pin WAIT monitoring an input/output timing of a valid data in order to reduce a data collision. Therefore, an external system transmits the data in response to a signal outputted from the wait pin WAIT.
  • the refresh operation is not performed for every memory access cycle but performed for a predetermined period. Nevertheless, the conventional PSRAM always includes a latency for the refresh operation because the initial latency is fixed. Therefore, an operation performance of the conventional PSRAM is degraded.
  • an object of the present invention to provide a latency control circuit for use in a synchronous PSRAM for improving an operation efficiency.
  • a latency control circuit for use in a semiconductor memory device including: a precharge unit for outputting a precharge reset signal based on a refresh signal and a normal active signal, wherein the precharge reset signal is used for extending a latency during a burst read period which includes a refresh cycle; a refresh cycle detector for detecting the refresh cycle in response to a latency setting signal and the precharge reset signal to thereby output a latency extension signal; a latency decoder for decoding an external address to thereby output a plurality of preliminary latency signals; and a latency controller for outputting a plurality of latency signals in response to the preliminary latency signal and the latency extension signal.
  • FIG. 1 is block diagram showing a conventional latency control circuit for use in a conventional PSRAM
  • FIG. 2 is a timing diagram demonstrating a read operation of the conventional PSRAM
  • FIG. 3 is a block diagram describing the latency control circuit for use in a synchronous PSRAM in accordance with a embodiment of the present invention
  • FIG. 4 is a schematic circuit diagram depicting a precharge unit shown in FIG. 3 ;
  • FIG. 5 is a schematic circuit diagram describing a refresh cycle detector shown in FIG. 3 ;
  • FIG. 6 is a schematic circuit diagram showing a latency controller shown in FIG. 3 ;
  • FIG. 7 is a timing diagram demonstrating an operation of the latency control circuit of the present invention shown in FIG. 3 ;
  • FIG. 8 is a timing diagram describing a burst read operation of the synchronous PSRAM including the latency control circuit shown in FIG. 3 .
  • FIG. 3 is a block diagram describing the latency control circuit for use in a synchronous PSRAM in accordance with an embodiment of the present invention.
  • the latency control circuit includes a precharge unit 10 , a refresh cycle detector 20 , a latency decoder 30 , and a latency controller 40 .
  • the precharge unit 10 receives a refresh signal REFb, an upper and a lower address detection signals ATD_U and ATD_L, a sense signal SEN, a normal active signal NATV, a chip selection signal CS_P, and a first write enable signal WEB_P to thereby output a precharge signal PCG and a precharge reset signal PCG_E_RE.
  • the chip selection signal CS_P is activated as a logic high level and the write enable signal WEB_P is pulse signal generated when a write enable pin /WE transit from a logic low level to a logic high level.
  • the refresh cycle detector 20 detects a refresh cycle based on the precharge reset signal PCG_E_RE, a latency setting signal BCR ⁇ 14 >, a refresh start signal REF_S, a power-up signal PWRUP, and a second write enable signal WEB to thereby output a latency extension signal LT_E.
  • the latency setting signal BCR ⁇ 14 > corresponding to an address A 14 is a mode register set (MRS) signal for a read operation and determines a latency length.
  • MRS mode register set
  • the refresh cycle detector 20 outputs the latency extension signal LT_E of a logic high level during a burst read period which including the refresh cycle and outputs the latency extension signal LT_E of a logic low level after the precharge reset signal, which denotes a termination of the burst read period, is activated.
  • the latency decoder 30 decodes a latency setting signal BCR ⁇ 13 : 11 > to output a preliminary latency signal LT_PRE ⁇ 2 : 6 >.
  • the latency setting signal BCR ⁇ 13 : 11 > is generated based on external addresses A 11 to A 13 .
  • the latency controller 40 selectively activates a latency signal LT ⁇ 2 : 6 > based on the latency extension signal LT_E and the preliminary latency signal LT_PRE ⁇ 2 : 6 > in order to determine a latency length. That is, the latency controller 40 outputs the first or the second latency signal LT ⁇ 2 > and LT ⁇ 3 > during the burst read period which does not include the refresh cycle and outputs the third or the fourth latency signal LT ⁇ 4 > and LT ⁇ 6 > during the burst read period which includes the refresh cycle. Therefore, it is possible for the present invention to have latency of various lengths.
  • FIG. 4 is a schematic circuit diagram depicting the precharge unit 10 shown in FIG. 3 .
  • the precharge unit 10 contains a precharge signal generator 11 , a precharge reset signal generator 12 , and a first and a second drivers 13 and 14 .
  • the precharge signal generator 11 is implemented with a plurality of inverters IV 1 to IV 7 , a plurality of NAND gates ND 1 to ND 3 , a first PMOS transistor P 1 , a first NMOS transistor N 1 , and a first and a second delays D 1 and D 2 .
  • the first NAND gate ND 1 receives an inverted refresh signal REFb inverted by the first inverter IV 1 and a delayed sense signal SEN.
  • the first driver voltage generator provided with a first PMOS transistor P 1 and the first NMOS transistor N 1 transmits a first drive voltage to a first latch R 1 in response to outputs of the first delay D 1 and the second inverter IV 2 .
  • the first latch R 1 provided with the third and the fourth inverters IV 3 and IV 4 latches the first drive voltage from a common node of the first PMOS transistor P 1 and the first NMOS transistor N 1 and outputs a refresh set signal REF_SET.
  • the second NAND gate ND 2 receives the refresh set signal REF_SET and a precharge set signal PCG_SET outputted from the precharge reset signal generator 12 .
  • the fifth inverter IV 5 inverts an output of the second NAND gate ND 2 .
  • the second delay D 2 delays an output of the fifth inverter IV 5 for a predetermined time.
  • the third NAND gate ND 3 receives outputs of the second and a fourth delays D 2 and D 4 .
  • the sixth inverter IV 6 inverts an output of the third NAND gate ND 3 and outputs to the first delay D 1 .
  • the seventh inverter IV 7 inverts the output of the sixth inverter IV 6 to thereby output the precharge signal PCG.
  • the precharge reset signal generator 12 includes a plurality of inverters IV 8 to IV 14 , a fourth NAND gate ND 4 , a second PMOS transistor P 2 , a second NMOS transistor N 2 , and two delays D 3 and D 4 .
  • the third delay D 3 delays the sense signal SEN for a predetermined time.
  • the eighth inverter IV 8 inverts and outputs the delayed sense signal SEN to the first NAND gate ND 1 in the precharge signal generator 11 .
  • the second driver voltage generator provided with a second PMOS transistor P 2 and the second NMOS transistor N 2 transmits a second drive voltage to a second latch R 2 in response to outputs of the first delay D 1 and the eighth inverter IV 8 .
  • the second latch R 2 provided with the ninth and the tenth inverters IV 9 and IV 10 latches the second drive voltage from a common node of the second PMOS transistor P 2 and the second NMOS transistor N 2 to thereby output the precharge set signal PCG_SET.
  • the fourth NAND gate ND 4 receives the precharge set signal PCG_SET and a precharge wait signal PCG_STB outputted from the first driver 13 .
  • the eleventh inverter IV 11 inverts an output of the fourth NAND gate ND 4 .
  • the fourth delay D 4 delays an output of the eleventh inverter IV 11 for a predetermined time.
  • the output of the fourth delay D 4 is outputted to the third NAND gate ND 3 of the precharge signal generator 11 .
  • the three inverters IV 12 to IV 14 invert and delay the output of the fourth delay D 4 to thereby output the precharge reset signal PCG_E_RE.
  • the first driver 13 includes a plurality of inverters IV 15 to IV 17 , a fifth NAND gate ND 5 , a third PMOS transistor P 3 , and a third NMOS transistor N 3 .
  • the fifth NAND gate ND 5 receives the output of the first delay D 1 and the normal active signal NATV.
  • the third driver voltage generator provided with a third PMOS transistor P 3 and the third NMOS transistor N 3 transmits a third drive voltage to a third latch R 3 in response to outputs of the first delay D 1 and the fifteenth inverter IV 15 .
  • the third latch R 3 provided with the sixteenth and the seventeenth inverters IV 16 and IV 17 latches the third drive voltage from a common node of the third PMOS transistor P 3 and the third NMOS transistor N 3 to thereby output the precharge wait signal PCG_STB.
  • the second driver 14 includes two NAND gates ND 6 and ND 7 and two NMOS transistors N 4 and N 5 .
  • the sixth NAND gate ND 6 receives the chip selection signal CS_P and the first write enable signal WEB_P.
  • the seventh NAND gate ND 7 receives the upper and the lower address detection signals ATD_U and ATD_L for detecting a transition of the normal address signal NATV.
  • the fourth and the fifth NMOS transistors N 4 and N 5 transmit a ground voltage VSS to the third NMOS transistor N 3 in response to outputs of the sixth and the seventh NAND gates ND 6 and ND 7 , respectively.
  • FIG. 5 is a schematic circuit diagram describing the refresh cycle detector 20 shown in FIG. 3 .
  • the refresh cycle detector 20 includes a plurality of inverters IV 18 to IV 27 , three PMOS transistors P 4 to P 6 , a sixth NMOS transistor N 6 , a transmission gate T 1 , and a NOR gate NR 1 .
  • the fourth and the fifth PMOS transistor P 4 and P 5 parallel connected to each other respectively controlled by an inverted precharge reset signal PCG_E_RE and the power-up signal PWRUP.
  • the fourth latch R 4 provided with two inverters IV 19 and IV 20 latches a voltage loaded at a common node of the fourth and the fifth PMOS transistors P 4 and P 5 and the sixth NMOS transistor N 6 .
  • the sixth NMOS transistor N 6 is controlled by the refresh start signal REF_S which has information about a start timing of the refresh operation.
  • the NOR gate NR 1 receives the latency setting signal BCR ⁇ 14 > and an inverted write enable signal WEB.
  • the twenty fourth inverter IV 24 inverts an output of the NOR gate NR 1 .
  • the transmission gate T 1 transmits an output of the twenty first IV 21 in response to outputs of the inverters IV 22 and IV 24 .
  • the sixth PMOS transistor P 6 connected to the power supply voltage VDD terminal provides the transmission gate T 1 with the power supply voltage VDD in order to precharge an output node of the transmission gate T 1 .
  • the inverters IV 25 to IV 27 inverts and delays an output of the transmission gate T 1 to thereby output the latency extension signal LT_E.
  • FIG. 6 is a schematic circuit diagram showing the latency controller 40 shown in FIG. 3 .
  • the latency controller 40 includes a plurality of NAND gates ND 8 to ND 15 and a plurality of inverters IV 28 to IV 30 .
  • the eighth NAND gate ND 8 receives the first preliminary latency signal LT_PRE ⁇ 2 > and an inverted latency extension signal LT_E inverted by the twenty eighth inverter IV 28 .
  • the inverters IV 30 to IV 32 invert and delay an output of the eighth NAND gate ND 8 to thereby output the first latency signal LT ⁇ 2 >.
  • the ninth NAND gate ND 9 receives the third preliminary latency signal LT_PRE ⁇ 4 > and the inverted latency extension signal LT_E.
  • the tenth NAND gate ND 10 receives the first preliminary latency signal LT_PRE ⁇ 2 > and the latency extension signal LT_E.
  • the fourteenth NAND gate ND 14 receives outputs of the ninth and the tenth NAND gates ND 9 and ND 10 .
  • the inverters IV 33 and IV 34 delay an output of the fourteenth NAND gate ND 14 to thereby output the third latency signal LT ⁇ 4 >.
  • the eleventh NAND gate ND 11 receives the second preliminary latency signal LT_PRE ⁇ 3 > and an inverted latency extension signal LT_E inverted by the twenty ninth inverter IV 29 .
  • the inverters IV 35 to IV 37 invert and delay an output of the eleventh NAND gate ND 11 to thereby output the second latency signal LT ⁇ 3 >.
  • the twelfth NAND gate ND 12 receives the fourth preliminary latency signal LT_PRE ⁇ 6 > and the inverted latency extension signal LT_E.
  • the thirteenth NAND gate ND 13 receives the second preliminary latency signal LT_PRE ⁇ 3 > and the latency extension signal LT_E.
  • the fifteenth NAND gate ND 15 receives outputs of the twelfth and the thirteenth NAND gates ND 12 and ND 13 .
  • the inverters IV 38 and IV 39 delay an output of the fifteenth NAND gate ND 15 to thereby output the fourth latency signal LT ⁇ 6 >.
  • FIG. 7 is a timing diagram demonstrating an operation of the latency control circuit of the present invention shown in FIG. 3 .
  • a length of a normal latency is 2 and a length of a refresh latency is 4 in response to the first and the third latency signals LT ⁇ 2 > and LT ⁇ 4 >.
  • the normal latency and the refresh latency refer to latencies which are occurred during burst read period which does not include the refresh cycle and during burst read period which includes the refresh cycle.
  • the precharge signal generator 10 outputs the precharge wait signal PCG_STB in response to activations of the normal active signal NATV, the chip selection signal CS_P, the write enable signal WEB_P, the upper and the lower address detection signals ATD_U and ATD_L.
  • the normal active signal NATV is activated as a logic high level in response to an activation of an external active signal and deactivated as a logic low level when the precharge signal PCG becomes a logic high level.
  • the chip selection signal CS_P is activated when an external chip selection signal /CS becomes a logic high level.
  • the write enable signal WEB_P is activated when an external write signal /WE becomes a logic high level.
  • the upper and the lower address detection signals ATD_U and ATD_L are activated in response to an address transition.
  • the sense signal SEN which shows that a sense amplifier is finishes its operation is activated.
  • the precharge set signal PCG_SET is activated as a logic high level in response to an activation of the sense signal SEN.
  • the precharge signal PCG becomes a logic high level in response to the precharge set signal PCG_SET and the precharge wait signal PCG_STB of logic high levels.
  • the refresh signal REFb maintains a logic high level during a read/write operation.
  • the refresh signal REFb is activated as a logic low level and the precharge reset signal generator 12 activates the precharge reset signal PCG_E_RE during the refresh operation. Accordingly, the latency extension signal LT_E maintains an activation state during a time from starting the burst read period which includes the refresh cycle to activating the precharge reset signal.
  • the transmission gate T 1 in the refresh cycle detector 20 is turned off when the latency setting signal BCR ⁇ 14 > is a logic high level or when the latency setting signal BCR ⁇ 14 > is a logic low level and the external write enable signal /WE is a logic low level.
  • sixth PMOS transistor P 6 is turned on to thereby output the latency extension signal LT_E of a logic low level.
  • the transmission gate T 1 is turned on during a burst read period where the latency setting signal BCR ⁇ 14 > is a logic low level and the external write enable signal /WE is a logic high level. Then, when the refresh start signal REF_S is enabled, the latency extension signal LT_E becomes a logic high level.
  • the latency controller 40 extends the latency for predetermined clocks in response to the latency extension signal LT_E during the burst read period which includes the refresh cycle.
  • the latency controller 40 when the latency extension signal LT_E is a logic low level, the latency controller 40 outputs the preliminary latency signals LT_PRE ⁇ 2 > and LT_PRE ⁇ 4 > as the latency signals LT ⁇ 2 > and LT ⁇ 4 >. That is, the first latency signal LT ⁇ 2 > has a logic high level and the third latency signal LT ⁇ 4 > has a logic low level. Therefore, the latency becomes 2 during burst read period which does not include the refresh cycle.
  • the latency controller 40 when the latency extension signal LT_E is a logic high level, the latency controller 40 outputs the first latency signal LT ⁇ 2 > of a logic low level and the third latency signal LT ⁇ 4 > of a logic high level. Therefore, the latency becomes 4 during burst read period which includes the refresh cycle.
  • the latency control circuit controls the latency length in response to the latency extension signal LT_E in order to improve an operation speed.
  • FIG. 8 is a timing diagram describing a burst read operation of the synchronous PSRAM including the latency control circuit shown in FIG. 3 .
  • the latency in case of the burst read period which does not include the refresh cycle is set 2 of about 40 ns to about 45 ns. Also, the latency in case of the burst read period which includes the refresh cycle is set 4 of about 70 ns to about 85 ns.
  • the latency control circuit improves an operation efficiency by varying the latency according to the refresh operation.

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TWI703563B (zh) * 2019-02-25 2020-09-01 華邦電子股份有限公司 偽靜態隨機存取記憶體及其操作方法
TWI777847B (zh) * 2021-11-08 2022-09-11 華邦電子股份有限公司 虛擬靜態隨機存取記憶體

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