US20140182897A1 - Circuit board and method of manufacturing the same - Google Patents

Circuit board and method of manufacturing the same Download PDF

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Publication number
US20140182897A1
US20140182897A1 US14/143,682 US201314143682A US2014182897A1 US 20140182897 A1 US20140182897 A1 US 20140182897A1 US 201314143682 A US201314143682 A US 201314143682A US 2014182897 A1 US2014182897 A1 US 2014182897A1
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United States
Prior art keywords
insulating layer
build
inorganic material
circuit board
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/143,682
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English (en)
Inventor
Doo Hwan Lee
Yul Kyo Chung
Yee Na Shin
Seung Eun Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD. reassignment SAMSUNG ELECTRO-MECHANICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHUNG, YUL KYO, LEE, DOO HWAN, LEE, SEUNG EUN, SHIN, YEE NA
Publication of US20140182897A1 publication Critical patent/US20140182897A1/en
Priority to US15/074,209 priority Critical patent/US9788433B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
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    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K1/00—Printed circuits
    • H05K1/02—Details
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    • H05K1/115—Via connections; Lands around holes or via connections
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    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/156—Material
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10015—Non-printed capacitor
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469—Circuit made after mounting or encapsulation of the components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Definitions

  • Embodiments of the present invention relate to a circuit board and a method of manufacturing the same.
  • multi-layered substrate techniques in which a plurality of interconnection layers are formed on a printed circuit board (PCB) are developed, and further, a technique of mounting electronic components such as an active device or a passive device into a multi-layered substrate is also developed.
  • PCB printed circuit board
  • one of important tasks in a multi-layered substrate field may be that built-in electronic components effectively transmit and receive a signal including a voltage or current to/from an external circuit or other devices.
  • a bending phenomenon of the substrate becomes a serious problem.
  • Such a bending phenomenon may be referred to as warpage, which becomes serious as the electronic components-built-in substrate is formed of various materials having different thermal expansion coefficients.
  • Document 1 cited below discloses a multi-layered substrate constituted by an insulating layer formed on a glass ceramic material only
  • Document 2 cited below discloses a conventional multi-layered substrate in which a core substrate is formed by coating or impregnating a glass core or a glass fiber with resin.
  • the insulating layer is implemented by the glass ceramic material only like in Document 1, since a process of processing a via and a circuit pattern is very difficult, it is difficult to implement a fine and highly integrated circuit pattern, and it is difficult to secure adhesion reliability between layers.
  • an aspect of the present invention is to provide a circuit board and a method of manufacturing the same that are capable of reducing warpage of the circuit board and improving manufacturing efficiency thereof.
  • a circuit board including: an inorganic material insulating layer; a first circuit pattern layer formed on a surface of the inorganic material insulating layer; a first build-up insulating layer formed on the inorganic material insulating layer and formed of an organic material; and a second circuit pattern layer formed on a surface of the first build-up insulating layer.
  • the inorganic material insulating layer may be a glass sheet or a plate glass.
  • the circuit board may further include a recess section formed at one region of the inorganic material insulating layer, and an electronic component at least partially inserted into the recess section and having an external electrode at at least one surface thereof, wherein the first build-up insulating layer covers the electronic components.
  • the first build-up insulating layer may include a first upper build-up insulating layer formed on the inorganic material insulating layer and a first lower build-up insulating layer formed under the inorganic material insulating layer.
  • the number of build-up layers formed on the first upper build-up insulating layer may be different from the number of build-up layers formed on the first lower build-up insulating layer.
  • the external electrode may be disposed in a direction of the first upper build-up insulating layer, and the number of build-up layers formed on the first upper build-up insulating layer may be larger than that of the build-up layers formed on the first lower build-up insulating layer.
  • the first circuit pattern layers may be formed on both surfaces of the inorganic material insulating layer, and may be electrically connected to each other by a via passing through the inorganic material insulating layer.
  • circuit board may further include at least one build-up layer on the first build-up insulating layer.
  • the inorganic material insulating layer may include a first inorganic material insulating layer having a cavity; an adhesive layer adhered to a lower surface of the first inorganic material insulating layer; and a second inorganic material insulating layer adhered to a lower surface of the adhesive layer.
  • the circuit board may further include a cavity passing through the inorganic material insulating layer and formed in one region of the inorganic material insulating layer, and an electronic component at least partially inserted into the cavity and having an external electrode formed at at least one surface thereof, wherein the first build-up insulating layer covers the electronic component.
  • the electronic component may be a capacitor.
  • a circuit board includes an inorganic material insulating layer having a cavity or a recess section; an identification mark formed on a surface of the inorganic material insulating layer; an electronic component partially inserted into the cavity or the recess section and having an external electrode at at least one surface thereof; a first build-up insulating layer formed on the inorganic material insulating layer and formed of an organic material; and a second circuit pattern layer formed on a surface of the first build-up insulating layer.
  • the inorganic material insulating layer may be a glass sheet or plate glass.
  • the first build-up insulating layer may include a first upper build-up insulating layer formed on the inorganic material insulating layer and a first lower build-up insulating layer formed on the inorganic material insulating layer
  • the second circuit pattern layer may include a second upper circuit pattern layer formed on an upper surface of the first upper build-up insulating layer and a second lower circuit pattern layer formed on an upper surface of the first lower build-up insulating layer
  • the second upper circuit pattern layer and the second lower circuit pattern layer may be electrically connected by a via passing through the first build-up insulating layer and the inorganic material insulating layer.
  • the via may pass through the identification mark.
  • the external electrode may be electrically connected to any one of the second upper circuit pattern layer and the second lower circuit pattern layer by the via.
  • the external electrode may be disposed in a direction of the first upper build-up insulating layer, and the number of build-up layers formed on the first upper build-up insulating layer may be larger than that of build-up layers formed on the first lower build-up insulating layer.
  • the electronic component may be a capacitor.
  • a method of manufacturing a circuit board includes: forming a first circuit pattern layer on a surface of an inorganic material insulating layer; forming a recess section or a cavity in the inorganic material insulating layer; inserting at least a portion of an electronic component having an external electrode into the recess section or the cavity; forming a first build-up insulating layer formed of an organic material on the inorganic material insulating layer; forming a via-hole passing the first build-up insulating layer and configured to expose a surface of at least one of the first circuit pattern layer and the external electrode; and forming a conductive material in the via-hole and forming a second circuit pattern layer on a surface of the first build-up insulating layer.
  • forming a recess section or a cavity in the inorganic material insulating layer may include forming a resist pattern configured to expose a region at which the recess section or the cavity is to be formed on the inorganic material insulating layer; and wet-etching the exposed region to form the recess section or the cavity and then removing the resist pattern.
  • the first build-up insulating layer may include a first upper build-up insulating layer formed on the inorganic material insulating layer and a first lower build-up insulating layer formed under the inorganic material insulating layer
  • the method may further include forming at least one build-up layer on the first upper build-up insulating layer and the first lower build-up insulating layer, and wherein the number of build-up layers formed on the first upper build-up insulating layer is different from the number of build-up layers formed on the first lower build-up insulating layer.
  • inserting at least the portion of the electronic component having the external electrode into the recess section or the cavity may be performed by making the lower surface of the electronic components in contact with the adhesive layer and adhering an added inorganic material insulating layer to the adhesive layer lower surface in a state in which an adhesive layer is adhered to the lower surface of the inorganic material insulating layer having the cavity.
  • the method may further include performing at least one pre-treatment process selected from surface etching, hardening and opaque processing to the inorganic material insulating layer.
  • a method of manufacturing a circuit board includes forming an identification mark on a surface of an inorganic material insulating layer; forming a recess section or a cavity in the inorganic material insulating layer; inserting at least a portion of an electronic component having an external electrode into the recess section or the cavity; forming a first build-up insulating layer formed of an organic material on the inorganic material insulating layer; forming a via-hole passing through the first build-up insulating layer and configured to expose a surface of the external electrode; and forming a conductive material in the via-hole and forming a second circuit pattern layer on a surface of the first build-up insulating layer.
  • forming the recess section or the cavity in the inorganic material insulating layer may include patterning a predetermined region with respect to the identification mark.
  • inserting at least the portion of the electronic component having the external electrode into the recess section or the cavity may be performed by mounting the electronic component on a predetermined position with respect to the identification mark.
  • forming the via-hole passing through the first build-up insulating layer and configured to expose a surface of the external electrode may include forming a via-hole passing through the first build-up insulating layer, the identification mark and the inorganic material insulating layer.
  • the first build-up insulating layer may include a first upper build-up insulating layer formed on the inorganic material insulating layer and a first lower build-up insulating layer formed under the inorganic material insulating layer
  • the method may further include forming at least one build-up layer on the first upper build-up insulating layer and the first lower build-up insulating layer, wherein the number of build-up layers formed on the first upper build-up insulating layer is different from the number of build-up layers formed on the first lower build-up insulating layer.
  • a circuit board in another aspect of the invention, includes: a core substrate comprised of a glass sheet or a plate glass; and, on the core substrate, at least one build-up insulating layer formed of organic material and through which a via connecting circuit patterns at opposite respective ends of the via is disposed
  • FIG. 1 is a cross-sectional view schematically showing a circuit board according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view schematically showing a circuit board according to another embodiment of the present invention.
  • FIGS. 3A to 3D are cross-sectional process views schematically showing a method of manufacturing the circuit board according to the embodiment also illustrated in FIG. 2 , FIG. 3A showing a process of forming a first circuit pattern layer on an inorganic material insulating layer, FIG. 3B showing a process of forming a recess section in the inorganic material insulating layer, FIG. 3C showing a process of mounting electronic components and forming a first build-up insulating layer, and FIG. 3D showing a process of further forming a build-up layer;
  • FIG. 4 is a cross-sectional view schematically showing a circuit board according to another embodiment of the present invention.
  • FIG. 5 is a cross-sectional view schematically showing a circuit board according to another embodiment of the present invention.
  • FIG. 6 is a cross-sectional view schematically showing a circuit board according to a another embodiment of the present invention.
  • FIG. 7 is a cross-sectional view schematically showing a circuit board according to another embodiment of the present invention.
  • FIG. 8 is a cross-sectional view schematically showing a circuit board according to another embodiment of the present invention.
  • FIGS. 9A to 9D are cross-sectional process views schematically showing the circuit board according to the embodiment also illustrated in FIG. 8 , FIG. 9A showing a process of forming an identification mark on an inorganic material insulating layer, FIG. 9B showing a process of forming a recess section in the inorganic material insulating layer, FIG. 9C showing a process of mounting electronic components and forming a first build-up insulating layer, and FIG. 9D showing a process of further forming a build-up layer.
  • FIG. 1 is a cross-sectional view schematically showing a circuit board 100 according to an embodiment of the present invention.
  • the circuit board 100 may include an inorganic material insulating layer 110 , a first circuit pattern layer P 1 , a first build-up insulating layer 120 and a second circuit pattern layer P 2 .
  • the inorganic material insulating layer 110 may be formed of glass.
  • the glass may be a glass plate such as a glass sheet or a plate glass produced by a glass manufacturer.
  • the glass may be formed of various kinds of glass materials such as a willow, Gorilla (which are trademarks, manufactured by Corning Corporation), Lime Soda, a plate glass used in a liquid crystal display (LCD), or the like.
  • impurities or additives may be partially mixed with the glass to improve properties.
  • the inorganic material insulating layer 110 may function as a core substrate.
  • the core substrate since good stiffness, modulus, and tensile strength can be secured in comparison with the case in which a conventional resin or a resin impregnated with glass fiber is used as the core substrate, a warpage phenomenon of the circuit board can be basically solved.
  • glass materials such as willow, LCD, Gorilla, Lime Soda, or the like, may be applied as the glass.
  • the first circuit pattern layer P 1 may be directly formed on a surface of the inorganic material insulating layer 110 .
  • the first circuit pattern layer P 1 , P 1 ′ may be formed at both surfaces of the inorganic material insulating layer 110 , and the first circuit pattern layer P 1 formed on one surface of the inorganic material insulating layer 110 may be electrically connected to the first circuit pattern layer P 1 ′ formed on the other surface of the inorganic material insulating layer 110 through a through-via Vt passing through the inorganic material insulating layer 110 .
  • the first build-up insulating layer 120 may be formed of an organic material.
  • the first build-up insulating layer 120 may be formed of epoxy resin.
  • the first build-up insulating layer 120 may include ABF.
  • the organic material does not exclude that an additive such as filler is included in an organic composition such as resin.
  • a second circuit pattern layer P 2 may be directly formed on a surface of the first build-up insulating layer 120 .
  • the warpage of the circuit board 100 is basically blocked by the inorganic material insulating layer 110 , even when an insulating material including a core material such as prepreg is not used as a build-up insulating layer, sufficient mechanical and physical characteristics of the circuit board can be secured. Accordingly, as the organic material is used as the build-up insulating layer, a circuit pattern having a finer pitch or line width can be formed.
  • the first build-up insulating layer 120 , 120 ′ may also be formed on and under the inorganic material insulating layer 110 , a layer formed on the inorganic material insulating layer 110 may be referred to as a first upper build-up insulating layer 120 , and a layer formed under the inorganic material insulating layer 110 may be referred to as a first lower build-up insulating layer 120 ′.
  • the circuit board 100 includes the inorganic material insulating layer 110 to enable reduction in warpage in comparison with the conventional art and effective implement of a via and circuit pattern on the first build-up insulating layer 120 formed of an organic material.
  • the circuit board 100 according to the embodiment of the present invention can solve the problem.
  • FIG. 2 is a cross-sectional view schematically showing a circuit board 200 according to another embodiment of the present invention.
  • the circuit board 200 includes an electronic component 10 mounted therein.
  • a recess section 211 recessed in a groove shape is formed in one region of an inorganic material insulating layer 210 such that the electronic component 10 is seated in the recess section 211 .
  • the entire electronic component 10 should not be inserted into the recess section 211 .
  • the electronic component 10 may be an active device such as a semiconductor chip or a passive device such as a capacitor, and an external electrode 11 is installed at the outside thereof.
  • a surface the electrode 10 at which the external electrode 11 is formed may be disposed in a direction opposite to a bottom surface of the recess section 211 such that the external electrode 11 of the electronic component 10 forms electrical connection to the outside of the circuit board 200 .
  • the first build-up insulating layer 220 formed of the organic material may be provided on the inorganic material insulating layer 210 to cover the inorganic material insulating layer 210 , the first circuit pattern layer P 1 and the electronic component 10 .
  • the first build-up insulating layer 220 may be formed only on the inorganic material insulating layer 210 or only under the inorganic material insulating layer 210 .
  • the second circuit pattern layer P 2 may be formed on the surface of the first build-up insulating layer 220 , and the second circuit pattern layer P 2 may be electrically connected to the first circuit pattern layer P 1 and the external electrode 11 via a first via V 1 .
  • the process of implementing the circuit pattern on the first build-up insulating layer 220 formed of the organic material has high process efficiency and a fine circuit pattern in comparison with the process of implementing the circuit pattern on the inorganic material insulating layer 210 .
  • fine vias can be relatively easily and precisely formed.
  • At least one build-up layer may be further formed on the first build-up insulating layer 220 .
  • the build-up layer may include a build-up insulating layer and a circuit pattern layer formed on a surface of the build-up insulating layer.
  • a second build-up insulating layer 230 may be further provided in an upward direction of the inorganic material insulating layer 210 , and build-up layers may be further provided in a downward direction of the inorganic material insulating layer 210 in a similar manner.
  • solder resist SR and a solder ball SB may be further provided at the outermost side of the circuit board 100 .
  • the circuit board 200 can effectively implement the fine circuit pattern on the first build-up insulating layer 220 formed of the organic material while sufficiently reducing the warpage using the inorganic material insulating layer 210 .
  • FIGS. 3A to 3D are process cross-sectional views schematically showing a method of manufacturing the circuit board 200 according to the aforementioned embodiment of the present invention.
  • an inorganic material 210 ′ formed of glass is pre-treated to prepare the inorganic material insulating layer 210 .
  • the pre-treatment may be a process of treating surface through a process such as surface etching, or the like, or a process of hardening the surface to further improve strength thereof.
  • the inorganic material insulating layer 210 may be transparently treated, and the opaque treatment may also be included in the pre-treatment process.
  • the first circuit pattern layers P 1 may be formed on the surface of the inorganic material insulating layer 210 .
  • the first circuit pattern layer P 1 may be formed at both surfaces of the inorganic material insulating layer 210 , and a through-via Vt may be formed to electrically connect the first circuit pattern layers P 1 , P 1 ′ formed on both surfaces thereof.
  • a conductive material may be provided in the via-hole to form the through-via Vt, and the first circuit pattern layers P 1 , P 1 ′ can be electrically connected by the through-via Vt.
  • the recess section 211 may be formed on the inorganic material insulating layer 210 .
  • a resist pattern PR configured to expose a region in which the recess section 211 is to be formed is formed on the inorganic material insulating layer 210 .
  • the resist pattern PR may be a photo resist pattern, but not limited thereto.
  • the wet etching is performed using etchant, and as a result, the recess section, which is partially recessed, may be formed in the inorganic material insulating layer 210 .
  • the resist pattern PR may be formed such that the resist pattern PR covers both of the first circuit pattern layers P 1 to prevent damage to the first circuit pattern layers P 1 due to the etchant.
  • the electronic component 10 is inserted into the recess section 211 .
  • the electronic component 10 can be relatively securely fixed by applying an adhesive agent 12 to a lower surface of the electronic component 10 or applying the adhesive agent 12 to the upper surface of the recess section 211 and then mounting the electronic component 10 .
  • a first build-up insulating layer 220 is formed, and a via-hole VH passing through the first build-up insulating layer 220 is formed at a place requiring via connection, for example, an upper region of the external electrode 11 of the electronic component 10 or the first circuit pattern layer P 1 , by laser or wet etching.
  • the via-hole VH may be filled with a conductive material, and the second circuit pattern layer P 2 may be formed on a surface of the first build-up insulating layer 220 .
  • the plurality of build-up layers, the solder resist SR and the solder ball SB may be formed on the first build-up insulating layer 220 to manufacture the circuit board 200 .
  • FIG. 4 is a cross-sectional view schematically showing a circuit board 300 according to another embodiment of the present invention.
  • the number of build-up layers provided on the inorganic material insulating layer 210 is larger than that of the build-up layers provided under the inorganic material insulating layer 210 .
  • the inorganic material insulating layer 210 is symmetrically formed at upper and lower sides thereof to reduce the warpage in the conventional multi-layered substrate, the interconnection cannot be sufficiently formed on the electronic component 10 to increase an area of the substrate or add unnecessary layers under the electronic component 10 , increasing a thickness of the substrate.
  • the circuit board 300 according to the present invention can efficiently implement the fine circuit pattern on the first build-up insulating layer 220 formed of the organic material while sufficiently reducing the warpage using the inorganic material insulating layer 210 , the number of build-up layers may be different on and under the inorganic material insulating layer 210 from each other, and thus, the problems of the conventional art can be solved.
  • FIG. 5 is a cross-sectional view schematically showing a circuit board 400 according to another embodiment of the present invention.
  • the circuit board 400 may include a cavity 412 instead of the recess section so that the electronic component 10 is inserted into the cavity 412 .
  • FIG. 6 is a cross-sectional view schematically showing a circuit board 500 according to a another embodiment of the present invention.
  • the circuit board 500 may include an inorganic material insulating layer constituted by a first inorganic material insulating layer 510 , an adhesive layer 515 and a second inorganic material insulating layer 513 .
  • the adhesive layer 515 can be adhered to a lower surface of the first inorganic material insulating layer 510 , and in a state in which the electronic component 10 is inserted into the cavity 512 of the first inorganic material insulating layer 510 , the lower surface of the electronic component 10 can be securely adhered to the upper surface of the adhesive layer 515 .
  • the second inorganic material insulating layer 513 is further adhered to the lower surface of the adhesive layer 515 , strength of the inorganic material insulating layer can be further improved to more stably support the electronic component 10 .
  • the first inorganic material insulating layer 510 and the second inorganic material insulating layer 513 are entitled merely for the convenience of description, the first inorganic material insulating layer 510 may be referred to as an inorganic material insulating layer, and the second inorganic material insulating layer 513 may be referred to as an added inorganic material insulating layer.
  • FIG. 7 is a cross-sectional view schematically showing a circuit board 600 according to another embodiment of the present invention.
  • an electronic component 20 inserted into a cavity 612 is a capacitor such as MLCC or the like.
  • vias may be formed at the lower surface of an external electrode 21 as well as the upper surface of the external electrode 21 to be electrically connected to the build-up layers
  • FIG. 8 is a cross-sectional view schematically showing a circuit board 700 according to another embodiment of the present invention.
  • the circuit board 700 may include an inorganic material insulating layer 210 , an identification mark F, an electronic component 10 , a first build-up insulating layer 220 and a second circuit pattern layer P 2 .
  • the inorganic material insulating layer 210 may be glass.
  • the second circuit pattern layer P 2 on the inorganic material insulating layer 210 may be needed to be connected to the second circuit pattern layer P 2 under the inorganic material insulating layer 210 .
  • the through-via Vt passing through the first build-up insulating layer 220 may be formed to electrically connect the second circuit pattern layers P 2 .
  • the through-via Vt formed at this time can pass through the identification mark F. That is, in forming the through-via Vt, in order to process the via-hole at a precise position, the identification mark F can be used as a kind of reference index.
  • the identification mark F may be used as a reference index in a process of forming the recess section 211 or the cavity in the inorganic material insulating layer 210 , and may be used as a reference index in a process of mounting the electronic component 10 .
  • the first circuit pattern layer P 1 is not formed on the surface of the inorganic material insulating layer 210 .
  • the process of forming the circuit pattern or the via on the surface of the inorganic material insulating layer 210 formed of glass has a relatively low yield or process efficiency.
  • the thickness for forming at least two layers can be reduced by forming the first circuit pattern layer P 1 on the surface of the inorganic material insulating layer 210 , an effect according to formation of the first circuit pattern layer P 1 could be diluted in consideration of the process efficiency and yield.
  • an appropriate one of the above-mentioned embodiment and the present embodiment may be applied to manufacture the circuit board.
  • FIGS. 9A to 9D are cross-sectional process views schematically showing a method of manufacturing the circuit board 700 according to the embodiment illustrated in FIG. 8 .
  • the inorganic material 210 ′ formed of glass is pre-treated to prepare the inorganic material insulating layer 210 .
  • the pre-treatment may mean that the surface is treated through surface etching, hardened to improve strength thereof, or the inorganic material insulating layer 210 is opaquely treated.
  • the identification mark F is provided at the circuit board 700 according to the embodiment of the present invention.
  • the identification mark F may be used as a reference index in the process of forming the recess section 211 or the cavity in the inorganic material insulating layer 210 , and it has been described that the identification mark F can be used s a reference index in the process of mounting the electronic component 10 .
  • the identification mark F may have a groove shape or a protrusion shape, and in the specification, a method of forming the identification mark F in the protrusion shape will be described.
  • a film F′ is formed on one surface of the inorganic material insulating layer 210 through sputtering or plating.
  • the resist pattern PR configured to cover a portion at which the identification mark F is to be formed and expose the other portion is formed.
  • the resist pattern PR may be a photo resist pattern.
  • the resist pattern PR may be removed to form the identification mark F having the protrusion shape.
  • the recess section 211 may be formed on the inorganic material insulating layer 210 .
  • the resist pattern PR configured to expose a region at which the recess section 211 is to be formed is formed on the inorganic material insulating layer 210 .
  • the resist pattern PR may be the photo resist pattern PR, but not limited thereto.
  • the recess section 211 which is partially recessed, may be formed in the inorganic material insulating layer 210 .
  • all of the resist pattern PR may be removed to form the recess section 211 in the inorganic material insulating layer 210 .
  • a cavity instead of the recess section 211 may be formed in the inorganic material insulating layer 210 , and as described above, the recess section 211 and the cavity may be formed through wet etching or laser drilling.
  • a laser is irradiated to a predetermined region with respect to the identification mark F to form the recess section 211 or the cavity, more precisely processing the recess section 211 or the cavity.
  • the electronic component 10 is inserted into the recess section 211 .
  • the electronic component 10 may be mounted to relatively securely fix the electronic component 10 .
  • the first build-up insulating layer 220 is formed, and the via-hole VH passing through the first build-up insulating layer 220 is formed in a place that requires via connection, for example, an upper region of the external electrode 11 of the electronic component 10 , through laser or wet etching.
  • a via-hole passing through the first build-up insulating layer 220 and the inorganic material insulating layer 210 may be formed, and in order to precisely process the via-hole, the via-hole may pass through the identification mark F also.
  • the identification mark F may be used as a reference index for processing the via-hole to form the through-via Vt.
  • the via-hole may be filled with a conductive material, and the second circuit pattern layer P 2 may be formed on a surface of the first build-up insulating layer 220 .
  • a plurality of build-up layer, a solder resist SR and a solder ball SB may be formed on the first build-up insulating layer 220 to manufacture the circuit board 700 .
  • the present invention includes the inorganic material insulating layer to provide useful effects of reducing the warpage in comparison with the conventional art, and effectively implementing the via and circuit pattern on the first build-up insulating layer formed of the organic material.

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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150156880A1 (en) * 2013-11-29 2015-06-04 Ibiden Co., Ltd. Printed wiring board and method for manufacturing printed wiring board
WO2016018237A1 (en) * 2014-07-28 2016-02-04 Intel Corporation A multi-chip-module semiconductor chip package having dense package wiring
US9263784B2 (en) * 2014-05-02 2016-02-16 Ibiden Co., Ltd. Package substrate
US20160351486A1 (en) * 2015-05-27 2016-12-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Substrate Including Embedded Component with Symmetrical Structure
US9545018B2 (en) * 2014-11-05 2017-01-10 Elite Material Co., Ltd. Multi-layer printed circuit boards with dimensional stability
US9743534B2 (en) * 2014-10-08 2017-08-22 Ibiden Co., Ltd. Wiring board with built-in electronic component and method for manufacturing the same
WO2018017246A1 (en) * 2016-07-21 2018-01-25 Qualcomm Incorporated Glass substrate including passive-on-glass device and semiconductor die
US10283439B2 (en) 2016-12-22 2019-05-07 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package including electromagnetic interference shielding layer
WO2019091728A1 (de) * 2017-11-10 2019-05-16 Lpkf Laser & Electronics Ag Verfahren und vorrichtung zur integration von halbleiter-wafern
US10396049B2 (en) 2016-06-21 2019-08-27 Samsung Electronics Co., Ltd. Fan-out semiconductor package
CN110839318A (zh) * 2018-08-16 2020-02-25 三星电子株式会社 具有埋入式无源组件的板
US10660202B1 (en) * 2018-11-16 2020-05-19 Unimicron Technology Corp. Carrier structure and manufacturing method thereof
CN112599493A (zh) * 2020-12-22 2021-04-02 珠海越亚半导体股份有限公司 一种两面嵌埋玻璃基板及其制造方法
WO2021098531A1 (zh) * 2019-07-07 2021-05-27 深南电路股份有限公司 线路板及其制作方法
CN112930596A (zh) * 2018-08-14 2021-06-08 美敦力公司 集成电路封装及其形成方法
US11079886B2 (en) * 2017-03-10 2021-08-03 Sharp Kabushiki Kaisha Display substrate and display device
US11622443B2 (en) * 2020-04-16 2023-04-04 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier and method of manufacturing the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6428164B2 (ja) * 2014-10-31 2018-11-28 日立化成株式会社 半導体装置及びその製造方法
KR20160090625A (ko) * 2015-01-22 2016-08-01 삼성전기주식회사 전자소자내장형 인쇄회로기판 및 그 제조방법
KR101952863B1 (ko) * 2016-06-21 2019-02-28 삼성전기주식회사 팬-아웃 반도체 패키지
KR102544563B1 (ko) * 2016-08-18 2023-06-16 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 제조방법
CN108076596B (zh) 2016-11-17 2020-06-23 华邦电子股份有限公司 线路板的制造方法
JP2018186258A (ja) * 2017-03-28 2018-11-22 大日本印刷株式会社 電子部品搭載基板およびその製造方法
KR102425754B1 (ko) * 2017-05-24 2022-07-28 삼성전기주식회사 전자부품 내장 인쇄회로기판
US10643936B2 (en) * 2017-05-31 2020-05-05 Dyi-chung Hu Package substrate and package structure
CN111867248A (zh) * 2019-04-24 2020-10-30 宏启胜精密电子(秦皇岛)有限公司 电路板及其制作方法
KR20240077905A (ko) * 2022-11-25 2024-06-03 엘지이노텍 주식회사 회로 기판 및 이를 포함하는 반도체 패키지

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110147055A1 (en) * 2009-12-17 2011-06-23 Qing Ma Glass core substrate for integrated circuit devices and methods of making the same
US20120188734A1 (en) * 2011-01-20 2012-07-26 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US20130194764A1 (en) * 2011-10-31 2013-08-01 Ibiden Co., Ltd. Wiring board and method for manufacturing the same

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232528A (ja) 1993-02-08 1994-08-19 Hitachi Ltd 混成集積回路基板及びその製法
JP3708133B2 (ja) * 1997-01-29 2005-10-19 大日本印刷株式会社 多層配線基板の製造方法、多層配線基板の製造装置、および多層配線基板
JP3672169B2 (ja) 1999-03-05 2005-07-13 日本特殊陶業株式会社 コンデンサ、コア基板本体の製造方法、及び、コンデンサ内蔵コア基板の製造方法
JP3813402B2 (ja) * 2000-01-31 2006-08-23 新光電気工業株式会社 半導体装置の製造方法
JP2004079736A (ja) * 2002-08-15 2004-03-11 Sony Corp チップ内蔵基板装置及びその製造方法
TW573444B (en) 2003-04-22 2004-01-21 Ind Tech Res Inst Substrate having organic and inorganic functional package
JP2005064446A (ja) * 2003-07-25 2005-03-10 Dainippon Printing Co Ltd 積層用モジュールの製造方法
US8101868B2 (en) 2005-10-14 2012-01-24 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
JP5114041B2 (ja) * 2006-01-13 2013-01-09 日本シイエムケイ株式会社 半導体素子内蔵プリント配線板及びその製造方法
TWI325745B (en) 2006-11-13 2010-06-01 Unimicron Technology Corp Circuit board structure and fabrication method thereof
KR100888561B1 (ko) * 2007-02-27 2009-03-12 대덕전자 주식회사 능동소자 내장형 인쇄회로기판 제조 방법
KR100905642B1 (ko) * 2007-12-13 2009-06-30 삼성전기주식회사 칩 내장형 인쇄회로기판 및 그 제조방법
JP2009295850A (ja) * 2008-06-06 2009-12-17 Hitachi Chem Co Ltd 多層回路基板の製造方法及びこれから得られる多層回路基板、半導体チップ搭載基板並びにこの基板を用いた半導体パッケージ
US20130003314A1 (en) * 2010-02-22 2013-01-03 Sanyo Electronic Co., Ltd. Multilayer printed circuit board and manufacturing method therefor
US20110290540A1 (en) * 2010-05-25 2011-12-01 Samsung Electro-Mechanics Co., Ltd. Embedded printed circuit board and method of manufacturing the same
KR101095161B1 (ko) * 2010-10-07 2011-12-16 삼성전기주식회사 전자부품 내장형 인쇄회로기판
JP2012186440A (ja) * 2011-02-18 2012-09-27 Ibiden Co Ltd インダクタ部品とその部品を内蔵しているプリント配線板及びインダクタ部品の製造方法
KR20120137201A (ko) 2011-10-27 2012-12-20 아페리오(주) 티에스브이 공법이 적용된 전자부품 내장형 인쇄회로기판 및 제조방법
US8890628B2 (en) * 2012-08-31 2014-11-18 Intel Corporation Ultra slim RF package for ultrabooks and smart phones

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110147055A1 (en) * 2009-12-17 2011-06-23 Qing Ma Glass core substrate for integrated circuit devices and methods of making the same
US20120188734A1 (en) * 2011-01-20 2012-07-26 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US20130194764A1 (en) * 2011-10-31 2013-08-01 Ibiden Co., Ltd. Wiring board and method for manufacturing the same

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150156880A1 (en) * 2013-11-29 2015-06-04 Ibiden Co., Ltd. Printed wiring board and method for manufacturing printed wiring board
US9263784B2 (en) * 2014-05-02 2016-02-16 Ibiden Co., Ltd. Package substrate
WO2016018237A1 (en) * 2014-07-28 2016-02-04 Intel Corporation A multi-chip-module semiconductor chip package having dense package wiring
US9743534B2 (en) * 2014-10-08 2017-08-22 Ibiden Co., Ltd. Wiring board with built-in electronic component and method for manufacturing the same
US9545018B2 (en) * 2014-11-05 2017-01-10 Elite Material Co., Ltd. Multi-layer printed circuit boards with dimensional stability
US9955569B2 (en) 2014-11-05 2018-04-24 Elite Material Co., Ltd. Multi-layer printed circuit boards with dimensional stability
US10236337B2 (en) * 2015-05-27 2019-03-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure
US20160351486A1 (en) * 2015-05-27 2016-12-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Substrate Including Embedded Component with Symmetrical Structure
US9837484B2 (en) * 2015-05-27 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure
US10665662B2 (en) * 2015-05-27 2020-05-26 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure
US20180053819A1 (en) * 2015-05-27 2018-02-22 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming Substrate Including Embedded Component with Symmetrical Structure
US20190172902A1 (en) * 2015-05-27 2019-06-06 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming Substrate Including Embedded Component with Symmetrical Structure
US10396049B2 (en) 2016-06-21 2019-08-27 Samsung Electronics Co., Ltd. Fan-out semiconductor package
WO2018017246A1 (en) * 2016-07-21 2018-01-25 Qualcomm Incorporated Glass substrate including passive-on-glass device and semiconductor die
US10044390B2 (en) 2016-07-21 2018-08-07 Qualcomm Incorporated Glass substrate including passive-on-glass device and semiconductor die
US10523253B2 (en) 2016-07-21 2019-12-31 Qualcomm Incorporated Glass substrate including passive-on-glass device and semiconductor die
CN109478545A (zh) * 2016-07-21 2019-03-15 高通股份有限公司 包括无源玻璃设备和半导体裸片的玻璃衬底
US10283439B2 (en) 2016-12-22 2019-05-07 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package including electromagnetic interference shielding layer
US11079886B2 (en) * 2017-03-10 2021-08-03 Sharp Kabushiki Kaisha Display substrate and display device
JP2021502706A (ja) * 2017-11-10 2021-01-28 エルペーカーエフ レーザー ウント エレクトロニクス アーゲー 半導体ウェハの集積方法及び装置
US11515259B2 (en) 2017-11-10 2022-11-29 Lpkf Laser & Electronics Ag Method and device for the integration of semiconductor wafers
JP7090153B2 (ja) 2017-11-10 2022-06-23 エルペーカーエフ レーザー ウント エレクトロニクス アーゲー 半導体ウェハの集積方法及び装置
WO2019091728A1 (de) * 2017-11-10 2019-05-16 Lpkf Laser & Electronics Ag Verfahren und vorrichtung zur integration von halbleiter-wafern
US11876026B2 (en) 2018-08-14 2024-01-16 Medtronic, Inc. Method of forming integrated circuit package
CN112930596A (zh) * 2018-08-14 2021-06-08 美敦力公司 集成电路封装及其形成方法
US11270920B2 (en) * 2018-08-14 2022-03-08 Medtronic, Inc. Integrated circuit package and method of forming same
CN110839318A (zh) * 2018-08-16 2020-02-25 三星电子株式会社 具有埋入式无源组件的板
US20200163215A1 (en) * 2018-11-16 2020-05-21 Unimicron Technology Corp. Carrier structure and manufacturing method thereof
US10660202B1 (en) * 2018-11-16 2020-05-19 Unimicron Technology Corp. Carrier structure and manufacturing method thereof
WO2021098531A1 (zh) * 2019-07-07 2021-05-27 深南电路股份有限公司 线路板及其制作方法
US11622443B2 (en) * 2020-04-16 2023-04-04 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier and method of manufacturing the same
CN112599493A (zh) * 2020-12-22 2021-04-02 珠海越亚半导体股份有限公司 一种两面嵌埋玻璃基板及其制造方法

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KR20140087745A (ko) 2014-07-09
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