TWM551788U

TWM551788U - Voltage level shifter

Info

Publication number: TWM551788U
Application number: TW105213400U
Authority: TW
Inventors: 余建政; 林振漢
Original assignee: 修平學校財團法人修平科技大學
Priority date: 2016-08-31
Filing date: 2016-08-31
Publication date: 2017-11-11

Description

電壓位準移位器 Voltage level shifter

本創作係有關一種電壓位準移位器，尤指利用一振幅轉換電路(1)、一電位控制電晶體(2)以及另一電位控制電晶體(3)所組成，以求獲得精確電壓位準轉換且有效地降低功率消耗之電子電路。 The present invention relates to a voltage level shifter, especially comprising an amplitude conversion circuit (1), a potential control transistor (2) and another potential control transistor (3) for obtaining a precise voltage level. An electronic circuit that is quasi-converted and effectively reduces power consumption.

電壓位準移位器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電壓位準移位器就負責將低電壓工作信號轉換成高電壓工作信號。 A voltage level shifter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when an application system needs to transfer a signal from a core logic with a lower voltage level to a peripheral device with a higher voltage level, the voltage level shifter is responsible for converting the low voltage operation signal to a high voltage operation. signal.

第1圖係顯示一先前技藝(prior art)之一閂鎖型電壓位準移位器電路，其係使用一第一PMOS(P-channel metal oxide semiconductor，P通道金屬氧化物半導體)電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS(N-channel metal oxide semiconductor，N通道金屬氧化物半導體)電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電壓位準移位器電路，其中，該反相器(INV)的偏壓是第二高電位電壓(VDDL)及地(GND)，而第一信號(V(IN))的電位亦在地(GND)與第二高電位電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電壓位準移位器的輸出(OUT)處於一個穩定的狀態時，閂鎖型的電壓位準移位器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 Figure 1 shows a prior art latch-type voltage level shifter circuit using a first PMOS (P-channel metal oxide semiconductor) transistor ( MP1), a second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and a reverse The phase converter (INV) constitutes a voltage level shifter circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and the ground (GND), and the first signal (V( The potential of IN)) is also between ground (GND) and the second high potential voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal outputted through the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is turned ON. In addition, due to the cross-coupled manner of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level shifter is in a stable state, There is no static current generated in the latch type voltage level shifter. In particular, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned "ON", the gate potential of the first PMOS transistor (MP1) is pulled down and Making the first PMOS transistor (MP1) turn on, so as to pull up the gate potential of the second PMOS transistor (MP2) to turn off the second PMOS transistor (MP2); further, when the first NMOS transistor When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS is pulled up. The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電壓位準移位器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當第一信號(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電位電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1) 及第二NMOS電晶體(MN2)達到完全導通或完全關閉，如此會造成在第一高電位電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, the above-described conventional voltage level shifter approaches the second PMOS transistor (MP2) approaching (or turning off) and the second NMOS transistor (MN2) approaching (turning off). There is a mutual contention between the pull-up and pull-down of the potential at the output (OUT) , so the second signal (V(OUT)) is slower when it is converted to a low potential. Furthermore, it is considered that when the first signal (V(IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be instantaneously converted to 1.8 volts, the lower first signal (V(IN)) during the conversion may not be able to make the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor (MN1) and the second NMOS transistor (MN2) are fully turned on or completely turned off, which causes a static current between the first high potential voltage (VDDH) and the ground (GND) (static current ), this quiescent current increases the power loss.

再者，閂鎖型的電壓位準移位器的性能是受到第一高電位電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電位電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電位電壓(VDDL)。因此，限制了可以使閂鎖型電壓位準移位器正常運作的第一高電位電壓(VDDH)的範圍。 Furthermore, the performance of the latch type voltage level shifter is affected by the first high potential voltage (VDDH) due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). The pole voltage is the first high potential voltage (VDDH), and the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch type voltage level shifter operate normally is limited.

第2圖係顯示另一先前技藝之一鏡像型電壓位準移位器電路，該電壓位準移位器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電壓位準移位器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電位電壓(VDDH)改變，電壓位準移位器的性能也不會有太大的改變。因此，鏡像型的電壓位準移位器可以適用在各種輸出電壓電路。 Figure 2 is a diagram showing a mirror type voltage level shifter circuit of another prior art, the voltage level shifter having a gate of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) The poles are connected together and connected to the drain of the first PMOS transistor (MP1) such that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) Is in the saturation region, and its gate voltage is such that the saturation current is equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is also equal. . Since the performance of the mirror type voltage level shifter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes The performance of the voltage level shifter will not change much. Therefore, the mirror type voltage level shifter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are electrically charged. The bit is pulled down so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. As such, a quiescent current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

有鑑於此，本創作之主要目的係提出一種電壓位準移位器，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地減少漏電流，進而降低功率消耗。 In view of this, the main purpose of the present invention is to propose a voltage level shifter that not only accurately and quickly converts the first signal into a second signal, but also effectively reduces leakage current, thereby reducing power consumption.

本創作提出一種電壓位準移位器，其係由一振幅轉換電路(1)、一電位控制電晶體(2)以及另一電位控制電晶體(3)所組成，其中，該振幅轉換電路(1)係用來做為電位轉換；該電位控制電晶體(2)係用以拉降該第一節點(N1)之電壓位準；而該電位控制電晶體(3)係用以拉降該第二節點(N2)之電壓位準。 The present invention proposes a voltage level shifter comprising an amplitude conversion circuit (1), a potential control transistor (2) and another potential control transistor (3), wherein the amplitude conversion circuit ( 1) is used as a potential conversion; the potential control transistor (2) is used to pull down the voltage level of the first node (N1); and the potential control transistor (3) is used to pull down the voltage The voltage level of the second node (N2).

由模擬結果證實，本創作所提出之電壓位準移位器，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少功率損耗。 It is confirmed by the simulation results that the voltage level shifter proposed by the present invention can not only accurately and quickly convert the first signal into a second signal, but also has the advantages of simple circuit structure and miniaturization of the device. At the same time, it can effectively reduce power loss.

1‧‧‧振幅轉換電路 1‧‧‧Amplitude conversion circuit

2‧‧‧電位控制電晶體 2‧‧‧potential control transistor

3‧‧‧電位控制電晶體 3‧‧‧potential control transistor

I1‧‧‧第一反相器 I1‧‧‧First Inverter

N1‧‧‧第一節點 N1‧‧‧ first node

N2‧‧‧第二節點 N2‧‧‧ second node

N3‧‧‧第三節點 N3‧‧‧ third node

N4‧‧‧第四節點 N4‧‧‧ fourth node

MP1‧‧‧第一PMOS電晶體 MP1‧‧‧First PMOS transistor

MP2‧‧‧第二PMOS電晶體 MP2‧‧‧second PMOS transistor

MP3‧‧‧第三PMOS電晶體 MP3‧‧‧ Third PMOS transistor

MP4‧‧‧第四PMOS電晶體 MP4‧‧‧fourth PMOS transistor

MN1‧‧‧第一NMOS電晶體 MN1‧‧‧First NMOS transistor

MN2‧‧‧第二NMOS電晶體 MN2‧‧‧Second NMOS transistor

MN3‧‧‧第三NMOS電晶體 MN3‧‧‧ Third NMOS transistor

MN4‧‧‧第四NMOS電晶體 MN4‧‧‧4th NMOS transistor

IN‧‧‧第一輸入端 IN‧‧‧ first input

V(IN)‧‧‧第一信號 V(IN)‧‧‧first signal

INB‧‧‧第二輸入端 INB‧‧‧ second input

OUT‧‧‧輸出端 OUT‧‧‧ output

GND‧‧‧地 GND‧‧‧

V(OUT)‧‧‧第二信號 V(OUT)‧‧‧second signal

VDDH‧‧‧第一高電位電壓 VDDH‧‧‧first high potential voltage

VDDL‧‧‧第二高電位電壓 VDDL‧‧‧ second high potential voltage

第1圖係顯示第一先前技藝中電壓位準移位器之電路圖；第2圖係顯示第二先前技藝中電壓位準移位器之電路圖；第3圖係顯示本創作較佳實施例之電壓位準移位器之電路圖；第4圖係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖； 1 is a circuit diagram showing a voltage level shifter in a first prior art; FIG. 2 is a circuit diagram showing a voltage level shifter in a second prior art; and FIG. 3 is a view showing a preferred embodiment of the present invention. a circuit diagram of a voltage level shifter; FIG. 4 is a timing diagram showing transient analysis of the first signal and the second signal of the preferred embodiment of the present invention;

根據上述之目的，本創作提出一種電壓位準移位器，如第3圖所示，其係由一振幅轉換電路(1)、一電位控制電晶體(2)以及另一電位控制電晶體(3)所組成，其中，該振幅轉換電路(1)係用來做為電位轉換；該電位控制電晶體(2)係用以拉降該第一節點(N1)之電壓位準；該電位控制電晶體(3)係用以拉降該第二節點(N2)之電壓位準；該振幅轉換電路(1)係耦接於該第一電源電壓以及地(GND)，用來做為電位轉換之用；其係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第三PMOS電晶體(MP3)、一第四PMOS電晶體(MP4)、一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至第一高電位電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；該第二PMOS電晶體(MP2)的源極連接至第一高電位電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；該第三PMOS電晶體(MP3)的源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；該第四PMOS電晶體(MP4)的源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；該第一NMOS電晶體(MN1)的源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；該第二NMOS電晶體(MN2)的源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；而該第一反相器(I1)係耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；該電位控制電晶體(2)係由一第三NMOS電晶體(MN3)所組成，其源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；該電位控制電晶體(3)係由一第四NMOS電晶體(MN4)所組成，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；該第一電源電壓係用以提供該電壓位準移位器所需之第一高電位電壓(VDDH)，該第二電源電壓係用以提供該電壓位準移位器所需之第二高電位電壓(VDDL)，該第二高電位電壓(VDDL)之位準係小於該第一高電位電壓(VDDH)之位準，該第一信號為介於0伏特及1.2伏特間的矩形波，而該第二信號則為介於0伏特及1.8伏特間的對應波形，該第一高電位電壓(VDDH)為1.8伏特，而該第二高電位電壓(VDDL)為1.2伏特，該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。。 According to the above object, the present invention proposes a voltage level shifter, as shown in Fig. 3, which is composed of an amplitude conversion circuit (1), a potential control transistor (2) and another potential control transistor ( 3) the composition, wherein the amplitude conversion circuit (1) is used for potential conversion; the potential control transistor (2) is used to pull down the voltage level of the first node (N1); The transistor (3) is configured to pull down the voltage level of the second node (N2); the amplitude conversion circuit (1) is coupled to the first power voltage and ground (GND) for potential conversion It is used by a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a fourth PMOS transistor (MP4), and a first NMOS. a transistor (MN1), a second NMOS transistor (MN2), and a first inverter (I1), wherein a source of the first PMOS transistor (MP1) is connected to a first high potential voltage ( VDDH), the gate thereof is connected to the fourth node (N4), and the drain thereof is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first high potential Voltage (VDDH) The gate is connected to the third node (N3), and the drain is connected to the second node (N2); the source of the third PMOS transistor (MP3) is connected to the first node (N1) a gate connected to the first input terminal (IN) and a drain connected to the third node (N3); a source of the fourth PMOS transistor (MP4) connected to the second node ( N2), the gate thereof is connected to the second input terminal (INB), and the drain thereof is connected to the fourth node (N4); the source of the first NMOS transistor (MN1) is connected to the ground (GND a gate connected to the first input terminal (IN) and a drain connected to the third node (N3); a source of the second NMOS transistor (MN2) connected to ground (GND) Its gate is connected to The second input terminal (INB) is connected to the fourth node (N4), and the first inverter (I1) is coupled to the first input terminal (IN) for Receiving the first signal (V(IN)) and providing a signal inverted from the first signal (V(IN)); the potential control transistor (2) is composed of a third NMOS transistor (MN3) The composition is connected to the ground (GND), the gate is connected to the first input terminal (IN), and the drain is connected to the first node (N1); the potential control transistor (3) Is composed of a fourth NMOS transistor (MN4) whose source is connected to ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the second node ( N2) is connected; the first power voltage is used to provide a first high potential voltage (VDDH) required by the voltage level shifter, and the second power voltage is used to provide the voltage level shifter The second high potential voltage (VDDL) is required, and the level of the second high potential voltage (VDDL) is less than the level of the first high potential voltage (VDDH), and the first signal is between 0 volts and 1.2 volts. a rectangular wave between the two, and the second signal is between 0 Corresponding waveform between 1.8 volts, the first high potential voltage (VDDH) is 1.8 volts, and the second high potential voltage (VDDL) is 1.2 volts, and the first signal (V(IN)) is between 0 A rectangular wave between volts and 1.2 volts, the second signal (V(OUT)) being a corresponding waveform between 0 volts and 1.8 volts. .

請再參閱第3圖，現在考慮第一信號(V(IN))為低電位(0伏特)時，電壓位準移位器的穩態操作情形：第一輸入端(IN)上的低電位同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)、該第三NMOS電晶體(MN3)以及該第三PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)和該第三NMOS電晶體(MN3)都關閉、該第三PMOS電晶體(MP3)導通，而該第一反相器(I1)傳送第二高電位電壓(VDDL)到該第二NMOS電晶體(MN2)、該第四NMOS電晶體(MN4)和該第四PMOS電晶體(MP4)的閘極，使得該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都導通、該第四PMOS電晶體(MP4)關閉，此時，由於該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都導通，因此，該第二節點(N2)和該第四節點(N4)的電位會被拉降至一低電位(0伏特)，再者，該第四節點(N4)上的低電位傳送到該第一PMOS電晶體(MP1)的閘極，使得該第一PMOS電晶體(MP1)導通，由於該第一PMOS電晶體(MP1)和該第三PMOS電晶體(MP3)都導通，該第一NMOS電晶體(MN1)關閉，因此，該第一節點(N1)和該第三節點(N3)的電位會被拉升至一第一高電位電壓(VDDH)，此時，該第三節點(N3)的高電位電壓使得該第二PMOS電晶體(MP2)關閉，而由於該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都導通，該第二PMOS電晶體(MP2)和該第四PMOS電晶體(MP4)都關閉，因此，該第二節點(N2)的電位將維持在低電位(0伏特)，因此，輸出端(OUT)的電位會維持在一低電位(0伏特)的穩態值。質言之，第一信號(V(IN))為低電位(0伏特)時，經過電壓位準移位器轉換成具低電位(0伏特)的第二信號(V(OUT))，由輸出端(OUT)輸出。 Please refer to Figure 3 again. Now consider the steady-state operation of the voltage level shifter when the first signal (V(IN)) is low (0 volts): low potential at the first input (IN) Simultaneously transmitted to the input terminal of the first inverter (I1), the first NMOS transistor (MN1), the third NMOS transistor (MN3), and the gate of the third PMOS transistor (MP3), so that The first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned off, the third PMOS transistor (MP3) is turned on, and the first inverter (I1) transmits a second high potential voltage ( VDDL) to the gates of the second NMOS transistor (MN2), the fourth NMOS transistor (MN4), and the fourth PMOS transistor (MP4) such that the second NMOS transistor (MN2) and the fourth The NMOS transistor (MN4) is turned on, and the fourth PMOS transistor (MP4) is turned off. At this time, since the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on, the first The potentials of the two nodes (N2) and the fourth node (N4) are pulled down to a low potential (0 volts), and the low potential at the fourth node (N4) is transferred to the first PMOS transistor. The gate of (MP1) makes the first PMOS transistor (MP1) Turning on, since the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned on, the first NMOS transistor (MN1) is turned off, and therefore, the first node (N1) and the third The potential of the node (N3) is pulled up to a first high potential voltage (VDDH), at which time the high potential voltage of the third node (N3) causes the second PMOS transistor (MP2) to be turned off, and The second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on, and the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are both turned off, and therefore, the second node ( The potential of N2) will remain at a low potential (0 volts), so the potential at the output (OUT) will remain at a low potential (0 volts) steady state value. In a word, when the first signal (V(IN)) is low (0 volts), it is converted into a second signal (V(OUT)) with a low potential (0 volts) by a voltage level shifter. Output (OUT) output.

再考慮第一信號(V(IN))為第二高電位電壓(1.2伏特)時，電壓位準移位器的穩態操作情形：第一輸入端(IN)上的第二高電位電壓(VDDL)同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)、該第三NMOS電晶體(MN3)以及該第三PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)和該第三NMOS電晶體(MN3)都導通、該第三PMOS電晶體(MP3)關閉，由於該第一NMOS電晶體(MN1)和該第三NMOS電晶體(MN3)都導通，因此，該第一節點(N1)和該第三節點(N3)的電位會被拉降至一低電位(0伏特)，該第三節點(N3)上的低電位傳送到該第二PMOS電晶體(MP2)的閘極，使得該第二PMOS電晶體(MP2)導通，因此，該第二節點(N2)的電位會被拉升至一高電位；再者，該第一反相器(I1)傳送一低電位到該第二NMOS電晶體(MN2)、該第四NMOS電晶體(MN4)和該第四PMOS電晶體(MP4)的閘極，使得該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都關閉、該第四PMOS電晶體(MP4)導通，此時由於該第二PMOS電晶體(MP2)和該第四PMOS電晶體(MP4)都導通，該第四節點(N4)的電位被拉升至一高電位；而該第四節點(N4)的高電位使得該第一PMOS電晶體(MP1)關閉，此時，由於該第一NMOS電晶體(MN1)導通，而該第一PMOS電晶體(MP1)和該第三PMOS電晶體(MP3)都關閉，因此，該第三節點(N3)的電位會維持在一低電位(0伏特)的穩態值，而由於該第二PMOS電晶體(MP2)和該第四PMOS電晶體(MP4)都導通，該第二NMOS電晶體(MN2)關閉，因此，第二節點(N2)的電位將維持在第一高電位電壓(VDDH)，而該第三節點(N3)的電位維持在低電位(0伏特)，因此，輸出端(OUT)的電位會維持在一第一高電位電壓(VDDH)的穩態值。質言之，第一信號(V(IN))為第二高電位電壓(1.2伏特)時，經過電壓位準移位器轉換成具第一高電位電壓(VDDH)的第二信號(V(OUT))，由輸出端(OUT)輸出。 Considering the steady state operation of the voltage level shifter when the first signal (V(IN)) is the second high potential voltage (1.2 volts): the second high potential voltage on the first input (IN) ( VDDL) is simultaneously transmitted to the input terminal of the first inverter (I1), the gate of the first NMOS transistor (MN1), the third NMOS transistor (MN3), and the gate of the third PMOS transistor (MP3) So that the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned on, and the third PMOS transistor (MP3) is turned off due to the first NMOS transistor (MN1) and the third NMOS. The transistor (MN3) is turned on, so the potential of the first node (N1) and the third node (N3) is pulled down to a low potential (0 volts), which is low on the third node (N3) The potential is transmitted to the gate of the second PMOS transistor (MP2) such that the second PMOS transistor (MP2) is turned on, and therefore, the potential of the second node (N2) is pulled up to a high potential; The first inverter (I1) transmits a low potential to the gates of the second NMOS transistor (MN2), the fourth NMOS transistor (MN4), and the fourth PMOS transistor (MP4), such that a second NMOS transistor (MN2) and the fourth NMOS device The body (MN4) is turned off, and the fourth PMOS transistor (MP4) is turned on. At this time, since the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are both turned on, the fourth node (N4) The potential is pulled up to a high potential; and the high potential of the fourth node (N4) causes the first PMOS transistor (MP1) to be turned off, at which time, since the first NMOS transistor (MN1) is turned on, The first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned off, so the potential of the third node (N3) is maintained at a low potential (0 volt) steady state value, and The second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are both turned on, the second NMOS transistor (MN2) is turned off, and therefore, the potential of the second node (N2) is maintained at the first high potential voltage. (VDDH), while the potential of the third node (N3) is maintained at a low potential (0 volts), and therefore, the potential of the output terminal (OUT) is maintained at a steady state value of a first high potential voltage (VDDH). In other words, when the first signal (V(IN)) is the second high potential voltage (1.2 volts), it is converted into a second signal with a first high potential voltage (VDDH) through the voltage level shifter (V( OUT)) , output by the output (OUT).

綜上所述，第一信號(V(IN))為低電位(0伏特)時，第二信號(V(OUT))亦為低電位(0伏特)；而第一信號(V(IN))為第二高電位電壓(1.2伏特)時，第二信號(V(OUT))為第一高電位電壓(VDDH)。如此，電壓位準轉換的目的便實現。 In summary, when the first signal (V(IN)) is low (0 volts), the second signal (V(OUT)) is also low (0 volts); and the first signal (V(IN)) When the second high potential voltage (1.2 volts) is, the second signal (V(OUT)) is the first high potential voltage (VDDH) . Thus, the purpose of voltage level conversion is achieved.

本創作所提出之電壓位準移位器之Spice暫態分析模擬結果，如第4圖所示，由該模擬結果可証實，本創作所提出之電壓位準移位器，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且能有效地降低功率的損耗。 The Spice transient analysis simulation of the voltage level shifter proposed by this creation As shown in Fig. 4, it can be confirmed from the simulation results that the voltage level shifter proposed by the present invention can not only quickly and accurately convert the first signal into a second signal, but also can effectively Ground reduces power loss.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although the present invention has been particularly described and described in detail, it is understood by those skilled in the art that the present invention may be modified in any form or detail without departing from the spirit and scope of the present invention. Therefore, all changes in the relevant technical scope are included in the scope of the patent application of this creation.

1‧‧‧振幅轉換電路 1‧‧‧Amplitude conversion circuit

2‧‧‧電位控制電晶體 2‧‧‧potential control transistor

3‧‧‧電位控制電晶體 3‧‧‧potential control transistor

I1‧‧‧第一反相器 I1‧‧‧First Inverter

N1‧‧‧第一節點 N1‧‧‧ first node

N2‧‧‧第二節點 N2‧‧‧ second node

N3‧‧‧第三節點 N3‧‧‧ third node

N4‧‧‧第四節點 N4‧‧‧ fourth node

MP1‧‧‧第一PMOS電晶體 MP1‧‧‧First PMOS transistor

MP2‧‧‧第二PMOS電晶體 MP2‧‧‧second PMOS transistor

MP3‧‧‧第三PMOS電晶體 MP3‧‧‧ Third PMOS transistor

MP4‧‧‧第四PMOS電晶體 MP4‧‧‧fourth PMOS transistor

MN1‧‧‧第一NMOS電晶體 MN1‧‧‧First NMOS transistor

MN2‧‧‧第二NMOS電晶體 MN2‧‧‧Second NMOS transistor

MN3‧‧‧第三NMOS電晶體 MN3‧‧‧ Third NMOS transistor

MN4‧‧‧第四NMOS電晶體 MN4‧‧‧4th NMOS transistor

IN‧‧‧第一輸入端 IN‧‧‧ first input

V(IN)‧‧‧第一信號 V(IN)‧‧‧first signal

INB‧‧‧第二輸入端 INB‧‧‧ second input

OUT‧‧‧輸出端 OUT‧‧‧ output

GND‧‧‧地 GND‧‧‧

V(OUT)‧‧‧第二信號 V(OUT)‧‧‧second signal

VDDH‧‧‧第一高電位電壓 VDDH‧‧‧first high potential voltage

VDDL‧‧‧第二高電位電壓 VDDL‧‧‧ second high potential voltage

Claims

一種電壓位準移位器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括：一第一節點(N1)，用以將一第一PMOS電晶體(MP1)的汲極、一第三NMOS電晶體(MN3)的汲極以及一第三PMOS電晶體(MP3)的源極連接在一起；一第二節點(N2)，用以將一第二PMOS電晶體(MP2)的汲極、一第四NMOS電晶體(MN4)的汲極以及一第四PMOS電晶體(MP4)的源極連接在一起；一第三節點(N3)，用以將一第三PMOS電晶體(MP3)的汲極、一第二PMOS電晶體(MP2)的閘極以及一第一NMOS電晶體(MN1)的汲極連接在一起；一第四節點(N4)，用以將一第四PMOS電晶體(MP4)的汲極、一第一PMOS電晶體(MP1)的閘極以及一第二NMOS電晶體(MN2)的汲極連接在一起；一第一輸入端(IN)，耦接於該第三NMOS電晶體(MN3)、該第三PMOS電晶體(MP3)以及該第一NMOS電晶體(MN1)的閘極，用以提供一第一信號(V(IN))；一第二輸入端(INB)，耦接於該第四NMOS電晶體(MN4)、該第四PMOS電晶體(MP4)以及該第二NMOS電晶體(MN2)的閘極，用以提供該第一信號(V(IN))的反相信號；一輸出端(OUT)，耦接於該第二節點(N2)，用以輸出該第二信號(V(OUT))；一第一電源電壓，耦接於該第一PMOS電晶體(MP1)以及該第二PMOS電晶體(MP2)的源極，用以提供電壓位準移位器所需之第一高電位電壓(VDDH)；一第二電源電壓，耦接於一第一反相器(I1)，用以提供電壓位準移位器所需之第二高電位電壓(VDDL)，該第二高電位電壓(VDDL)之電位係小於該第一高電位電壓(VDDH)之電位；一振幅轉換電路(1)，耦接於該第一電源電壓以及地(GND)，用來做為電位轉換；一電位控制電晶體(2)，耦接於該第一輸入端(IN)，用以拉降該第一節點(N1)之電壓位準；以及一電位控制電晶體(3)，耦接於該第二輸入端(INB)，用以拉降該第二節點(N2)之電壓位準。 A voltage level shifter for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: a first node (N1) for a drain of a PMOS transistor (MP1), a drain of a third NMOS transistor (MN3), and a source of a third PMOS transistor (MP3) are connected together; a second node (N2) is used Connecting a drain of a second PMOS transistor (MP2), a drain of a fourth NMOS transistor (MN4), and a source of a fourth PMOS transistor (MP4); a third node (N3) For connecting a drain of a third PMOS transistor (MP3), a gate of a second PMOS transistor (MP2), and a drain of a first NMOS transistor (MN1); a fourth node (N4) for connecting the drain of a fourth PMOS transistor (MP4), the gate of a first PMOS transistor (MP1), and the drain of a second NMOS transistor (MN2); a first input terminal (IN) coupled to the third NMOS transistor (MN3), the third PMOS transistor (MP3), and the gate of the first NMOS transistor (MN1) for providing a first a signal (V(IN)); a second input terminal (INB) coupled to the fourth NMOS transistor (MN4 is), the fourth PMOS transistor (MP4) and a second NMOS transistor (the MN2) of the gate, for providing the first signal (V (IN)) of the inverted signal; An output terminal (OUT) coupled to the second node (N2) for outputting the second signal (V(OUT)); a first power supply voltage coupled to the first PMOS transistor (MP1) And a source of the second PMOS transistor (MP2) for providing a first high potential voltage (VDDH) required by the voltage level shifter; a second power supply voltage coupled to the first inverter (I1), for providing a second high potential voltage (VDDL) required by the voltage level shifter, the potential of the second high potential voltage (VDDL) being less than the potential of the first high potential voltage (VDDH); An amplitude conversion circuit (1) coupled to the first power supply voltage and ground (GND) for potential conversion; a potential control transistor (2) coupled to the first input terminal (IN), a voltage level for pulling down the first node (N1); and a potential control transistor (3) coupled to the second input terminal (INB) for pulling down the second node (N2) Voltage level.

如申請專利範圍第1項所述的電壓位準移位器，其中該振幅轉換電路(1)包括：一第一PMOS電晶體(MP1)，其源極連接至第一高電位電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；一第二PMOS電晶體(MP2)，其源極連接至第一高電位電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；一第三PMOS電晶體(MP3)，其源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；一第四PMOS電晶體(MP4)，其源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；一第一NMOS電晶體(MN1)，其源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；一第二NMOS電晶體(MN2)，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；以及一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。 The voltage level shifter according to claim 1, wherein the amplitude conversion circuit (1) comprises: a first PMOS transistor (MP1) whose source is connected to the first high potential voltage (VDDH) a gate connected to the fourth node (N4) and a drain connected to the first node (N1); a second PMOS transistor (MP2) having a source connected to the first high potential voltage (VDDH), whose gate is connected to the third node (N3), and its drain is connected to the second node (N2); a third PMOS transistor (MP3) having a source connected to the first node (N1), a gate connected to the first input (IN), and a drain connected to the third node (N3) Connected; a fourth PMOS transistor (MP4) having a source connected to the second node (N2), a gate connected to the second input (INB), and a drain connected to the fourth node (N4) connected; a first NMOS transistor (MN1) having a source connected to ground (GND), a gate connected to the first input (IN), and a drain connected to the third node (N3) is connected; a second NMOS transistor (MN2) having a source connected to ground (GND), a gate connected to the second input (INB), and a drain connected to the fourth node a (N4) phase connection; and a first inverter (I1) coupled to the first input terminal (IN) for accepting the first signal (V(IN)) and providing a first Signal (V(IN)) inverted signal.

如申請專利範圍第2項所述的電壓位準移位器，其中該電位控制電晶體(2)係由一第三NMOS電晶體(MN3)所組成，其源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接。 The voltage level shifter according to claim 2, wherein the potential control transistor (2) is composed of a third NMOS transistor (MN3), and the source thereof is connected to the ground (GND). Its gate is connected to the first input (IN) and its drain is connected to the first node (N1).

如申請專利範圍第3項所述的電壓位準移位器，其中該電位控制電晶體(3)係由一第四NMOS電晶體(MN4)所組成，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接。 The voltage level shifter according to claim 3, wherein the potential control transistor (3) is composed of a fourth NMOS transistor (MN4), and the source thereof is connected to the ground (GND). Its gate is connected to the second input (INB) and its drain is connected to the second node (N2).

如申請專利範圍第1項所述的電壓位準移位器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電位電壓(VDDL)之間。 The voltage level shifter of claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high potential voltage (VDDL).

如申請專利範圍第5項所述的電壓位準移位器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電位電壓(VDDH)之間。 The voltage level shifter of claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high potential voltage (VDDH).

如申請專利範圍第6項所述的電壓位準移位器，其中該第一反相器(I1)的電壓源為該第二高電位電壓(VDDL)。 The voltage level shifter of claim 6, wherein the voltage source of the first inverter (I1) is the second high potential voltage (VDDL).