TWM538183U - Voltage level converter - Google Patents

Voltage level converter Download PDF

Info

Publication number
TWM538183U
TWM538183U TW105215106U TW105215106U TWM538183U TW M538183 U TWM538183 U TW M538183U TW 105215106 U TW105215106 U TW 105215106U TW 105215106 U TW105215106 U TW 105215106U TW M538183 U TWM538183 U TW M538183U
Authority
TW
Taiwan
Prior art keywords
pmos transistor
gate
signal
voltage
high potential
Prior art date
Application number
TW105215106U
Other languages
Chinese (zh)
Inventor
余建政
湯雲欽
何孟芬
劉家宏
Original Assignee
修平學校財團法人修平科技大學
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 修平學校財團法人修平科技大學 filed Critical 修平學校財團法人修平科技大學
Priority to TW105215106U priority Critical patent/TWM538183U/en
Publication of TWM538183U publication Critical patent/TWM538183U/en

Links

Landscapes

  • Logic Circuits (AREA)

Description

電壓位準轉換器 Voltage level converter

本創作係有關一種電壓位準轉換器，尤指利用一電位拉升電路(1)、一模式控制開關(2)以及一輸入電路(3)所組成，以求獲得精確電壓位準轉換且有效地降低功率消耗之電子電路。 This creation is related to a voltage level converter, especially composed of a potential pull-up circuit (1), a mode control switch (2) and an input circuit (3) for obtaining accurate voltage level conversion and effective An electronic circuit that reduces power consumption.

電壓位準轉換器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電壓位準轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 A voltage level converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when an application system needs to transfer a signal from a core logic with a lower voltage level to a peripheral device with a higher voltage level, the voltage level converter is responsible for converting the low voltage operation signal into a high voltage operation signal. .

第1圖係顯示一先前技藝(prior art)之一閂鎖型電壓位準轉換器電路，其係使用一第一PMOS(P-channel metal oxide semiconductor，P通道金屬氧化物半導體)電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS(N-channel metal oxide semiconductor，N通道金屬氧化物半導體)電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電壓位準轉換器電路，其中，該反相器(INV)的偏壓是第二高電位電壓(VDDL)及地(GND)，而第一信號(V(IN))的電位亦在地(GND)與第二高電位電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因 此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電壓位準轉換器的輸出端(OUT)處於一個穩定的狀態時，閂鎖型的電壓位準轉換器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 Figure 1 shows a prior art latch-type voltage level converter circuit using a first PMOS (P-channel metal oxide semiconductor) transistor (MP1). a second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverting phase The inverter (INV) constitutes a voltage level converter circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and the ground (GND), and the first signal (V(IN) The potential is also between ground (GND) and the second high potential voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal outputted through the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . because Thus, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is turned ON. In addition, due to the cross-coupled manner of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output terminal (OUT) of the voltage level converter is in a stable state, There is no static current generated in the latch type voltage level converter. In particular, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned "ON", the gate potential of the first PMOS transistor (MP1) is pulled down and Making the first PMOS transistor (MP1) turn on, so as to pull up the gate potential of the second PMOS transistor (MP2) to turn off the second PMOS transistor (MP2); further, when the first NMOS transistor When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS is pulled up. The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電壓位準轉換器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當第一信號(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電位電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1) 及第二NMOS電晶體(MN2)達到完全導通或完全關閉，如此會造成在第一高電位電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, the above-described conventional voltage level converter is in the process of approaching (or turning off) the second PMOS transistor (MP2) and approaching (or turning on) the second NMOS transistor (MN2), The pull-up and pull-down of the potential at the output (OUT) have a contention, so the second signal (V(OUT)) is slower when it transitions to a low potential. Furthermore, it is considered that when the first signal (V(IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be instantaneously converted to 1.8 volts, the lower first signal (V(IN)) during the conversion may not be able to make the first PMOS transistor (MP1), the second PMOS transistor (MP2), First NMOS transistor (MN1) And the second NMOS transistor (MN2) is fully turned on or completely turned off, which causes a static current between the first high potential voltage (VDDH) and the ground (GND), and the quiescent current increases the power. Loss.

再者，閂鎖型的電壓位準轉換器的性能是受到第一高電位電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電位電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電位電壓(VDDL)。因此，限制了可以使閂鎖型電壓位準轉換器正常運作的第一高電位電壓(VDDH)的範圍。 Furthermore, the performance of the latch type voltage level converter is affected by the first high potential voltage (VDDH) due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). The voltage is the first high potential voltage (VDDH), and the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch type voltage level converter operate normally is limited.

第2圖係顯示另一先前技藝之一鏡像型電壓位準轉換器電路，該電壓位準轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電壓位準轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電位電壓(VDDH)改變，電壓位準轉換器的性能也不會有太大的改變。因此，鏡像型的電壓位準轉換器可以適用在各種輸出電壓電路。 Figure 2 is a diagram showing another prior art mirror type voltage level converter circuit for connecting the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) Connected to the drain of the first PMOS transistor (MP1) together such that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is The saturation region, and its gate voltage, causes the saturation current to be equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror type voltage level converter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, The performance of the voltage level converter will not change much. Therefore, the mirror type voltage level converter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電 位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are electrically charged. The bit is pulled down so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. As such, a quiescent current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

有鑑於此，本創作之主要目的係提出一種電壓位準轉換器，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地減少漏電流，進而降低功率消耗。 In view of this, the main purpose of the present invention is to propose a voltage level converter that not only accurately and quickly converts a first signal into a second signal, but also effectively reduces leakage current, thereby reducing power consumption.

本創作提出一種電壓位準轉換器，其係由一電位拉升電路(1)、一模式控制開關(2)以及一輸入電路(3)所組成，其中，該電位拉升電路(1)係用來將該第二信號(V(OUT))拉升到第一高電位電壓(VDDH)；該模式控制開關(2)係設計成可因應不同操作模式而控制該第一節點(N1)和該第二節點(N2)之電壓位準，亦即該模式控制開關(2)於對應之該致能控制端(EN)的輸入信號為邏輯高位準時代表主動(active)模式，而輸入信號為邏輯低位準時則為待機(standby)模式，俾藉此以於待機模式時，可有效降低功率的損耗；而該輸入電路(3)係用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號；該第一電源電壓係用以提供該電壓位準轉換器所需之第一高電位電壓(VDDH)，而該第二電源電壓係用以提供該電壓位準轉換器所需之第二高電位電壓(VDDL)，該第二高電位電壓(VDDL)之位準係小於該第一高電位電壓(VDDH)之位準，該第一信號為介於0伏特及1.2伏特間的矩形波，而該第二信號則為介於0伏特及1.8伏特間的對應波形。 The present invention proposes a voltage level converter which is composed of a potential pull-up circuit (1), a mode control switch (2) and an input circuit (3), wherein the potential pull-up circuit (1) is Used to pull the second signal (V(OUT)) to a first high potential voltage (VDDH); the mode control switch (2) is designed to control the first node (N1) and according to different operating modes The voltage level of the second node (N2), that is, the mode control switch (2) represents an active mode when the input signal corresponding to the enable control terminal (EN) is a logic high level, and the input signal is The logic low level is in standby mode, so that in the standby mode, the power loss can be effectively reduced; and the input circuit (3) is used to provide the first signal (V(IN)) and the An inverted signal of the first signal (V(IN)); the first power voltage is used to provide a first high potential voltage (VDDH) required by the voltage level converter, and the second power voltage is used to Providing a second high potential voltage (VDDL) required by the voltage level converter, the second high potential voltage (VDDL) having a level smaller than the first High potential voltage (the VDDH) of the level, the first rectangular wave signal is interposed between 0 volts and 1.2 volts, and the second signal corresponding to the waveform was interposed between 0 volts and 1.8 volts.

由模擬結果證實，本創作所提出之電壓位準轉換器，不但能 精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少功率損耗。 It is confirmed by the simulation results that the voltage level converter proposed by this creation can not only The first signal is converted into a second signal accurately and quickly, and has multiple functions such as simple circuit structure and miniaturization of the device, and can effectively reduce power loss.

1‧‧‧電位拉升電路 1‧‧‧ potential pull-up circuit

2‧‧‧模式控制開關 2‧‧‧Mode Control Switch

3‧‧‧輸入電路 3‧‧‧Input circuit

EN‧‧‧致能控制端 EN‧‧‧Enable control terminal

N1‧‧‧第一節點 N1‧‧‧ first node

N2‧‧‧第二節點 N2‧‧‧ second node

MP1‧‧‧第一PMOS電晶體 MP1‧‧‧First PMOS transistor

MP2‧‧‧第二PMOS電晶體 MP2‧‧‧second PMOS transistor

MP3‧‧‧第三PMOS電晶體 MP3‧‧‧ Third PMOS transistor

MP4‧‧‧第四PMOS電晶體 MP4‧‧‧fourth PMOS transistor

MP5‧‧‧第五PMOS電晶體 MP5‧‧‧ Fifth PMOS transistor

MP6‧‧‧第六PMOS電晶體 MP6‧‧‧6th PMOS transistor

MN1‧‧‧第一NMOS電晶體 MN1‧‧‧First NMOS transistor

MN2‧‧‧第二NMOS電晶體 MN2‧‧‧Second NMOS transistor

IN‧‧‧第一輸入端 IN‧‧‧ first input

V(IN)‧‧‧第一信號 V(IN)‧‧‧first signal

INB‧‧‧第二輸入端 INB‧‧‧ second input

OUT‧‧‧輸出端 OUT‧‧‧ output

GND‧‧‧地 GND‧‧‧

V(OUT)‧‧‧第二信號 V(OUT)‧‧‧second signal

VDDH‧‧‧第一高電位電壓 VDDH‧‧‧first high potential voltage

VDDL‧‧‧第二高電位電壓 VDDL‧‧‧ second high potential voltage

I1‧‧‧第一反相器 I1‧‧‧First Inverter

第1圖 係顯示第一先前技藝中電壓位準轉換器之電路圖；第2圖 係顯示第二先前技藝中電壓位準轉換器之電路圖；第3圖 係顯示本創作較佳實施例之電壓位準轉換器之電路圖；第4圖 係顯示本創作較佳實施例於主動模式時之輸入電壓信號及輸出電壓信號之暫態分析時序圖。 1 is a circuit diagram showing a voltage level converter in a first prior art; FIG. 2 is a circuit diagram showing a voltage level converter in a second prior art; and FIG. 3 is a voltage level showing a preferred embodiment of the present invention. The circuit diagram of the quasi-converter; FIG. 4 is a timing diagram showing the transient analysis of the input voltage signal and the output voltage signal in the active mode of the preferred embodiment of the present invention.

根據上述之目的，本創作提出一種電壓位準轉換器，如第3圖所示，其係由一電位拉升電路(1)、一模式控制開關(2)以及一輸入電路(3)所組成，其中，該電位拉升電路(1)係用來將該第二信號(V(OUT))拉升到第一高電位電壓(VDDH)之用；其係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第三PMOS電晶體(MP3)以及一第四PMOS電晶體(MP4)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至該第一高電位電壓(VDDH)，其閘極連接至該第二節點(N2)，而其汲極則與該第三PMOS電晶體(MP3)的源極相連接；該第二PMOS電晶體(MP2)的源極連接至該第一高電位電壓(VDDH)，其閘極連接至該第一節點(N1)，而其汲極則與該第四PMOS電晶體(MP4)的源極相連接；該第三PMOS電晶體(MP3)的源極連接 至該第一PMOS電晶體(MP1)的汲極，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；而該第四PMOS電晶體(MP4)，其源極連接至該第二PMOS電晶體(MP2)的汲極，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；該模式控制開關(2)係用以控制該電壓位準轉換器之不同操作模式；其係由一第五PMOS電晶體(MP5)、一第六PMOS電晶體(MP6)以及一致能控制端(EN)所組成，其中，該第五PMOS電晶體(MP5)的源極連接至該第一高電位電壓(VDDH)，其閘極與該第六PMOS電晶體(MP6)的閘極相連接，而其汲極則與該第一節點(N1)相連接；該第六PMOS電晶體(MP6)的源極連接至該第一高電位電壓(VDDH)，其閘極與該第五PMOS電晶體(MP5)的閘極相連接，而其汲極則與該第二節點(N2)相連接；而該致能控制端(EN)係耦接至該第五PMOS電晶體(MP5)和該第六PMOS電晶體(MP6)的閘極，用以提供一致能信號；該輸入電路(3)係用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號；其係由一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成，其中，該第一NMOS電晶體(MN1)的源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；該第二NMOS電晶體(MN2)的源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；而該第 一反相器(I1)係耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；該第一電源電壓係用以提供該電壓位準轉換器所需之第一高電位電壓(VDDH)，該第二電源電壓係用以提供該電壓位準轉換器所需之第二高電位電壓(VDDL)，該第二高電位電壓(VDDL)之位準係小於該第一高電位電壓(VDDH)之位準，該第一信號為介於0伏特及1.2伏特間的矩形波，而該第二信號則為介於0伏特及1.8伏特間的對應波形，該第一高電位電壓(VDDH)為1.8伏特，而該第二高電位電壓(VDDL)為1.2伏特，該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above purpose, the present invention proposes a voltage level converter, as shown in FIG. 3, which is composed of a potential pull-up circuit (1), a mode control switch (2) and an input circuit (3). The potential pull-up circuit (1) is used to pull the second signal (V(OUT)) to the first high potential voltage (VDDH); it is composed of a first PMOS transistor (MP1) a second PMOS transistor (MP2), a third PMOS transistor (MP3), and a fourth PMOS transistor (MP4), wherein the source of the first PMOS transistor (MP1) is connected to The first high potential voltage (VDDH) has a gate connected to the second node (N2) and a drain connected to a source of the third PMOS transistor (MP3); the second PMOS transistor a source of (MP2) is connected to the first high potential voltage (VDDH), a gate thereof is connected to the first node (N1), and a drain thereof is connected to a source of the fourth PMOS transistor (MP4) Connection; source connection of the third PMOS transistor (MP3) a drain to the first PMOS transistor (MP1) having a gate connected to the first input terminal (IN) and a drain connected to the first node (N1); and the fourth PMOS capacitor a crystal (MP4) having a source connected to the drain of the second PMOS transistor (MP2), a gate connected to the second input (INB), and a drain connected to the second node (N2) Connected; the mode control switch (2) is used to control different operating modes of the voltage level converter; it is composed of a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), and a uniform energy a control terminal (EN), wherein a source of the fifth PMOS transistor (MP5) is connected to the first high potential voltage (VDDH), and a gate thereof and a gate of the sixth PMOS transistor (MP6) Connected to the first node (N1); the source of the sixth PMOS transistor (MP6) is connected to the first high potential voltage (VDDH), and the gate and the fifth The gate of the PMOS transistor (MP5) is connected, and the drain of the PMOS transistor (MP5) is connected to the second node (N2); and the enable control terminal (EN) is coupled to the fifth PMOS transistor (MP5) And the gate of the sixth PMOS transistor (MP6), Providing a uniform energy signal; the input circuit (3) is for providing the first signal (V(IN)) and the inverted signal of the first signal (V(IN)); a crystal (MN1), a second NMOS transistor (MN2), and a first inverter (I1), wherein the source of the first NMOS transistor (MN1) is connected to ground (GND), and its gate a pole is connected to the first input terminal (IN), and a drain is connected to the first node (N1); a source of the second NMOS transistor (MN2) is connected to a ground (GND), and a gate thereof Connected to the second input (INB), and its drain is connected to the second node (N2); An inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)) and providing an inversion with the first signal (V(IN)) The first supply voltage is used to provide a first high potential voltage (VDDH) required by the voltage level converter, and the second supply voltage is used to provide a second required voltage level converter a high potential voltage (VDDL), the level of the second high potential voltage (VDDL) being less than a level of the first high potential voltage (VDDH), the first signal being a rectangular wave between 0 volts and 1.2 volts And the second signal is a corresponding waveform between 0 volts and 1.8 volts, the first high potential voltage (VDDH) is 1.8 volts, and the second high potential voltage (VDDL) is 1.2 volts, the first The signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is a corresponding waveform between 0 volts and 1.8 volts.

請再參閱第3圖，茲依電壓位準轉換器之工作模式說明圖3之工作原理如下： Please refer to Figure 3 again. According to the working mode of the voltage level converter, the working principle of Figure 3 is as follows:

(I)主動模式(Active mode) (I) Active mode

在主動模式下，亦即，當該致能控制端(EN)是在高電位狀態時，該第五PMOS電晶體(MP5)和第六PMOS電晶體(MP6)均呈關閉(OFF)狀態。 In the active mode, that is, when the enable control terminal (EN) is in the high potential state, the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are both in an OFF state.

現在考慮第一信號(V(IN))為低電位(0伏特)時，電壓位準轉換器的穩態操作情形：第一輸入端(IN)上的低電位同時傳送到第一反相器(I1)的輸入端、第一NMOS電晶體(MN1)的閘極以及第三PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)關閉、第三PMOS電晶體(MP3)導通，而該第一反相器(I1)傳送第二高電位電壓(VDDL)到第二NMOS電晶體(MN2)、第四PMOS電晶體(MP4)的閘極，使得第二NMOS電晶體(MN2)導通、第四PMOS電晶體(MP4)關閉，此時，由於第二NMOS電晶體(MN2)導通，因此， 該第二節點(N2)的電位會被拉降至一低電位(0伏特)，再者，該第二節點(N2)上的低電位傳送到第一PMOS電晶體(MP1)的閘極，使得第一PMOS電晶體(MP1)導通，由於第一PMOS電晶體(MP1)和第三PMOS電晶體(MP3)都導通，第一NMOS電晶體(MN1)關閉，因此，第一節點(N1)的電位會被拉升至一第一高電位電壓(VDDH)，該第一節點(N1)的第一高電位電壓(VDDH)使得第二PMOS電晶體(MP2)關閉，此時由於第二NMOS電晶體(MN2)導通，第二PMOS電晶體(MP2)和第四PMOS電晶體(MP4)都關閉，因此，第二節點(N2)的電位將維持在低電位(0伏特)，因此，輸出端(OUT)的電位會被拉降至一低電位(0伏特)的穩態值。質言之，第一信號(V(IN))為低電位(0伏特)時，經過電壓位準轉換器轉換成具低電位(0伏特)的第二信號(V(OUT))，由輸出端(OUT)輸出。 Now consider the steady state operation of the voltage level converter when the first signal (V(IN)) is low (0 volts): the low potential at the first input (IN) is simultaneously transmitted to the first inverter The input terminal of (I1), the gate of the first NMOS transistor (MN1), and the gate of the third PMOS transistor (MP3), such that the first NMOS transistor (MN1) is turned off, and the third PMOS transistor (MP3) Turning on, and the first inverter (I1) transmits a second high potential voltage (VDDL) to the gates of the second NMOS transistor (MN2) and the fourth PMOS transistor (MP4), so that the second NMOS transistor (MN2) is turned on, and the fourth PMOS transistor (MP4) is turned off. At this time, since the second NMOS transistor (MN2) is turned on, The potential of the second node (N2) is pulled down to a low potential (0 volts), and the low potential at the second node (N2) is transferred to the gate of the first PMOS transistor (MP1). The first PMOS transistor (MP1) is turned on, and since the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned on, the first NMOS transistor (MN1) is turned off, and therefore, the first node (N1) The potential is pulled up to a first high potential voltage (VDDH), and the first high potential voltage (VDDH) of the first node (N1) causes the second PMOS transistor (MP2) to be turned off, at this time due to the second NMOS The transistor (MN2) is turned on, and the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are both turned off, so the potential of the second node (N2) is maintained at a low potential (0 volt), and therefore, the output The potential of the terminal (OUT) is pulled down to a steady state value of a low potential (0 volts). In a word, when the first signal (V(IN)) is low (0 volts), it is converted into a second signal (V(OUT)) with a low potential (0 volt) by a voltage level converter, and the output is output. End (OUT) output.

再考慮第一信號(V(IN))為第二高電位電壓(VDDL)時，電壓位準轉換器的穩態操作情形：第一輸入端(IN)上的第二高電位電壓(VDDL)同時傳送到第一反相器(I1)的輸入端、第一NMOS電晶體(MN1)的閘極以及第三PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)導通、第三PMOS電晶體(MP3)關閉，此時由於第一NMOS電晶體(MN1)導通，因此，該第一節點(N1)的電位會被拉降至一低電位(0伏特)，該第一節點(N1)上的低電位傳送到第二PMOS電晶體(MP2)的閘極，使得第二PMOS電晶體(MP2)導通；而該第一反相器(I1)傳送一低電位到第二NMOS電晶體(MN2)和第四PMOS電晶體(MP4)的閘極，使得第二NMOS電晶體(MN2)關閉、第四PMOS電晶體(MP4)導通，此時由於第二PMOS電晶體(MP2)和第四PMOS電晶體(MP4)都導通，該第二節 點(N2)的電位會被拉升至一高電位；而該第二節點(N2)的高電位使得第一PMOS電晶體(MP1)關閉，此時由於第一NMOS電晶體(MN1)導通，第一PMOS電晶體(MP1)和第三PMOS電晶體(MP3)都關閉，該第一節點(N1)的電位會維持在低電位(0伏特)，而該第二節點(N2)的電位將維持在第一高電位電壓(VDDH)，因此，輸出端(OUT)的電位會被拉升至一第一高電位電壓(VDDH)的穩態值。質言之，第一信號(V(IN))為第二高電位電壓(VDDL)時，經過電壓位準轉換器轉換成具第一高電位電壓(VDDH)的第二信號(V(OUT))，由輸出端(OUT)輸出。 Considering the steady state operation of the voltage level converter when the first signal (V(IN)) is the second high potential voltage (VDDL): the second high potential voltage (VDDL) on the first input terminal (IN) Simultaneously transmitting to the input end of the first inverter (I1), the gate of the first NMOS transistor (MN1), and the gate of the third PMOS transistor (MP3), so that the first NMOS transistor (MN1) is turned on. The third PMOS transistor (MP3) is turned off. At this time, since the first NMOS transistor (MN1) is turned on, the potential of the first node (N1) is pulled down to a low potential (0 volt). The low potential on one node (N1) is transferred to the gate of the second PMOS transistor (MP2), so that the second PMOS transistor (MP2) is turned on; and the first inverter (I1) transmits a low potential to the first The gates of the two NMOS transistors (MN2) and the fourth PMOS transistors (MP4) are such that the second NMOS transistor (MN2) is turned off and the fourth PMOS transistor (MP4) is turned on, at this time due to the second PMOS transistor ( Both MP2) and the fourth PMOS transistor (MP4) are turned on, the second section The potential of the point (N2) is pulled up to a high potential; and the high potential of the second node (N2) causes the first PMOS transistor (MP1) to be turned off, at which time the first NMOS transistor (MN1) is turned on, The first PMOS transistor (MP1) and the third PMOS transistor (MP3) are both turned off, the potential of the first node (N1) is maintained at a low potential (0 volts), and the potential of the second node (N2) will be The first high potential voltage (VDDH) is maintained, so the potential of the output terminal (OUT) is pulled up to a steady state value of a first high potential voltage (VDDH). In other words, when the first signal (V(IN)) is the second high potential voltage (VDDL), it is converted into a second signal (V(OUT)) with a first high potential voltage (VDDH) through a voltage level converter. ), output by the output (OUT).

綜上所述，第一信號(V(IN))為低電位(0伏特)時，第二信號(V(OUT))亦為低電位(0伏特)；而第一信號(V(IN))為第二高電位電壓(VDDL)時，第二信號(V(OUT))為第一高電位電壓(VDDH)。如此，電壓位準轉換的目的便實現。 In summary, when the first signal (V(IN)) is low (0 volts), the second signal (V(OUT)) is also low (0 volts); and the first signal (V(IN)) When the second high potential voltage (VDDL) is the second high voltage (VDD), the second signal (V(OUT)) is the first high potential voltage (VDDH). Thus, the purpose of voltage level conversion is achieved.

(II)待機模式(Standby mode) (II) Standby mode

請再參考圖3。在待機狀態下，亦即，當該致能控制端(EN)是在低電位狀態時，該第五PMOS電晶體(MP5)和第六PMOS電晶體(MP6)均呈導通(ON)狀態，此時，該第一節點(N1)和該第二節點(N2)的電位被設定在第一高電位電壓(VDDH)，並且該第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都關閉，使得該電位拉升電路(1)停止動作。因此，任何第一信號(V(IN))的輸入均不會影響到已被拴鎖住的第二信號(V(OUT))值。其工作原理於此不再累述。 Please refer to Figure 3 again. In the standby state, that is, when the enable control terminal (EN) is in the low potential state, the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are both in an ON state. At this time, the potentials of the first node (N1) and the second node (N2) are set at a first high potential voltage (VDDH), and the first PMOS transistor (MP1) and the second PMOS transistor (MP2) ) are turned off, causing the potential pull-up circuit (1) to stop operating. Therefore, the input of any first signal (V(IN)) does not affect the value of the second signal (V(OUT)) that has been locked. The working principle of this is not repeated here.

本創作所提出之電壓位準轉換器之Spice暫態分析模擬結果，如第4圖所示，由該模擬結果可証實，本創作所提出之電壓位準轉換器， 其不但仍能快速且精確地將第一信號轉換為一第二信號，並且能有效地降低功率的損耗。 The result of the Spice transient analysis of the voltage level converter proposed by the author, as shown in Fig. 4, can be confirmed by the simulation result, the voltage level converter proposed by the present invention, It not only can quickly and accurately convert the first signal into a second signal, but also can effectively reduce the power loss.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although the present invention has been particularly described and described in detail, it is understood by those skilled in the art that the present invention may be modified in any form or detail without departing from the spirit and scope of the present invention. Therefore, all changes in the relevant technical scope are included in the scope of the patent application of this creation.

1‧‧‧電位拉升電路 1‧‧‧ potential pull-up circuit

2‧‧‧模式控制開關 2‧‧‧Mode Control Switch

3‧‧‧輸入電路 3‧‧‧Input circuit

EN‧‧‧致能控制端 EN‧‧‧Enable control terminal

N1‧‧‧第一節點 N1‧‧‧ first node

N2‧‧‧第二節點 N2‧‧‧ second node

MP1‧‧‧第一PMOS電晶體 MP1‧‧‧First PMOS transistor

MP2‧‧‧第二PMOS電晶體 MP2‧‧‧second PMOS transistor

MP3‧‧‧第三PMOS電晶體 MP3‧‧‧ Third PMOS transistor

MP4‧‧‧第四PMOS電晶體 MP4‧‧‧fourth PMOS transistor

MP5‧‧‧第五PMOS電晶體 MP5‧‧‧ Fifth PMOS transistor

MP6‧‧‧第六PMOS電晶體 MP6‧‧‧6th PMOS transistor

MN1‧‧‧第一NMOS電晶體 MN1‧‧‧First NMOS transistor

MN2‧‧‧第二NMOS電晶體 MN2‧‧‧Second NMOS transistor

IN‧‧‧第一輸入端 IN‧‧‧ first input

V(IN)‧‧‧第一信號 V(IN)‧‧‧first signal

INB‧‧‧第二輸入端 INB‧‧‧ second input

OUT‧‧‧輸出端 OUT‧‧‧ output

GND‧‧‧地 GND‧‧‧

V(OUT)‧‧‧第二信號 V(OUT)‧‧‧second signal

VDDH‧‧‧第一高電位電壓 VDDH‧‧‧first high potential voltage

VDDL‧‧‧第二高電位電壓 VDDL‧‧‧ second high potential voltage

I1‧‧‧第一反相器 I1‧‧‧First Inverter

Claims (7)

一種電壓位準轉換器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括：一第一節點(N1)，用以將一第二PMOS電晶體(MP2)的閘極、一第三PMOS電晶體(MP3)的汲極、一第一NMOS電晶體(MN1)的汲極以及一第五PMOS電晶體(MP5)的汲極連接在一起；一第二節點(N2)，用以將一第一PMOS電晶體(MP1)的閘極、一第四PMOS電晶體(MP4)的汲極、一第二NMOS電晶體(MN2)的汲極以及一第六PMOS電晶體(MP6)的汲極連接在一起；一第一輸入端(IN)，耦接於該第三PMOS電晶體(MP3)的閘極、該第一NMOS電晶體(MN1)的閘極以及一第一反相器(I1)的輸入端，用以提供一第一信號(V(IN))；一第二輸入端(INB)，耦接於該第四PMOS電晶體(MP4)的閘極、該第二NMOS電晶體(MN2)的閘極以及該第一反相器(I1)的輸出端，用以提供該第一信號(V(IN))的反相信號；一輸出端(OUT)，耦接於該第二節點(N2)，用以輸出該第二信號(V(OUT))；一第一電源電壓，用以提供電壓位準轉換器所需之第一高電位電壓(VDDH)；一第二電源電壓，用以提供電壓位準轉換器所需之第二高電位電壓(VDDL)，該第二高電位電壓(VDDL)之電位係小於該第一高電位電壓(VDDH)之電位； 一電位拉升電路(1)，用來將該第二信號(V(OUT))拉升到第一高電位電壓(VDDH)；一模式控制開關(2)，用以控制該電壓位準轉換器之不同操作模式；以及一輸入電路(3)，用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號。 A voltage level converter for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: a first node (N1) for placing a second The gate of the PMOS transistor (MP2), the drain of a third PMOS transistor (MP3), the drain of a first NMOS transistor (MN1), and the drain of a fifth PMOS transistor (MP5) are connected Together, a second node (N2) is used to connect the gate of a first PMOS transistor (MP1), the drain of a fourth PMOS transistor (MP4), and the gate of a second NMOS transistor (MN2). a drain of the sixth PMOS transistor (MP6) is coupled together; a first input terminal (IN) coupled to the gate of the third PMOS transistor (MP3), the first NMOS transistor ( a gate of MN1) and an input of a first inverter (I1) for providing a first signal (V(IN)); a second input terminal (INB) coupled to the fourth PMOS a gate of the crystal (MP4), a gate of the second NMOS transistor (MN2), and an output of the first inverter (I1) for providing an inversion of the first signal (V(IN)) An output (OUT) coupled to the second node (N2) for outputting the second signal (V(OUT)) a first supply voltage for providing a first high potential voltage (VDDH) required by the voltage level converter; and a second supply voltage for providing a second high potential voltage (VDDL) required by the voltage level converter The potential of the second high potential voltage (VDDL) is less than the potential of the first high potential voltage (VDDH); a potential pull-up circuit (1) for pulling the second signal (V(OUT)) to a first high potential voltage (VDDH); a mode control switch (2) for controlling the voltage level conversion Different operating modes of the device; and an input circuit (3) for providing the first signal (V(IN)) and the inverted signal of the first signal (V(IN)). 如申請專利範圍第1項所述的電壓位準轉換器，其中該電位拉升電路(1)包括：一第一PMOS電晶體(MP1)，其源極連接至該第一高電位電壓(VDDH)，其閘極連接至該第二節點(N2)，而其汲極則與該第三PMOS電晶體(MP3)的源極相連接；一第二PMOS電晶體(MP2)，其源極連接至該第一高電位電壓(VDDH)，其閘極連接至該第一節點(N1)，而其汲極則與該第四PMOS電晶體(MP4)的源極相連接；一第三PMOS電晶體(MP3)，其源極連接至該第一PMOS電晶體(MP1)的汲極，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；以及一第四PMOS電晶體(MP4)，其源極連接至該第二PMOS電晶體(MP2)的汲極，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接。 The voltage level converter according to claim 1, wherein the potential pull-up circuit (1) comprises: a first PMOS transistor (MP1) whose source is connected to the first high potential voltage (VDDH) a gate connected to the second node (N2) and a drain connected to the source of the third PMOS transistor (MP3); a second PMOS transistor (MP2) having a source connection Up to the first high potential voltage (VDDH), the gate is connected to the first node (N1), and the drain is connected to the source of the fourth PMOS transistor (MP4); a third PMOS a crystal (MP3) having a source connected to the drain of the first PMOS transistor (MP1), a gate connected to the first input (IN), and a drain connected to the first node (N1) Connected; and a fourth PMOS transistor (MP4) having a source connected to the drain of the second PMOS transistor (MP2), a gate connected to the second input terminal (INB), and a drain Then connected to the second node (N2). 如申請專利範圍第2項所述的電壓位準轉換器，其中該模式控制開關(2)包括： 一第五PMOS電晶體(MP5)，其源極連接至該第一高電位電壓(VDDH)，其閘極與該第六PMOS電晶體(MP6)的閘極相連接，而其汲極則與該第一節點(N1)相連接；一第六PMOS電晶體(MP6)，其源極連接至該第一高電位電壓(VDDH)，其閘極與該第五PMOS電晶體(MP5)的閘極相連接，而其汲極則與該第二節點(N2)相連接；以及一致能控制端(EN)，係耦接至該第五PMOS電晶體(MP5)和該第六PMOS電晶體(MP6)的閘極，用以提供一致能信號。 The voltage level converter of claim 2, wherein the mode control switch (2) comprises: a fifth PMOS transistor (MP5) having a source connected to the first high potential voltage (VDDH), a gate connected to the gate of the sixth PMOS transistor (MP6), and a drain The first node (N1) is connected; a sixth PMOS transistor (MP6) whose source is connected to the first high potential voltage (VDDH), and the gate thereof and the fifth PMOS transistor (MP5) The pole is connected, and the drain is connected to the second node (N2); and the uniform energy control terminal (EN) is coupled to the fifth PMOS transistor (MP5) and the sixth PMOS transistor ( The gate of MP6) is used to provide a consistent energy signal. 如申請專利範圍第3項所述的電壓位準轉換器，其中輸入電路(3)包括：一第一NMOS電晶體(MN1)，其源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；一第二NMOS電晶體(MN2)，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；以及一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。 The voltage level converter according to claim 3, wherein the input circuit (3) comprises: a first NMOS transistor (MN1) whose source is connected to ground (GND), the gate of which is connected to the gate a first input terminal (IN), the drain of which is connected to the first node (N1); a second NMOS transistor (MN2) whose source is connected to ground (GND), the gate of which is connected to the gate a second input terminal (INB), wherein the drain is connected to the second node (N2); and a first inverter (I1) coupled to the first input terminal (IN) for receiving The first signal (V(IN)) and provides a signal that is inverted from the first signal (V(IN)). 如申請專利範圍第4項所述的電壓位準轉換器，其中該第一反相器(I1)的電壓源為該第二高電位電壓(VDDL)。 The voltage level converter of claim 4, wherein the voltage source of the first inverter (I1) is the second high potential voltage (VDDL). 如申請專利範圍第1項所述的電壓位準轉換器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電位電壓(VDDL)之間。 The voltage level converter of claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high potential voltage (VDDL). 如申請專利範圍第6項所述的電壓位準轉換器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電位電壓(VDDH)之間。 The voltage level converter of claim 6, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high potential voltage (VDDH).
TW105215106U 2016-10-05 2016-10-05 Voltage level converter TWM538183U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW105215106U TWM538183U (en) 2016-10-05 2016-10-05 Voltage level converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW105215106U TWM538183U (en) 2016-10-05 2016-10-05 Voltage level converter

Publications (1)

Publication Number Publication Date
TWM538183U true TWM538183U (en) 2017-03-11

Family

ID=58774849

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105215106U TWM538183U (en) 2016-10-05 2016-10-05 Voltage level converter

Country Status (1)

Country Link
TW (1) TWM538183U (en)

Similar Documents

Publication Publication Date Title
TWM616390U (en) Low power voltage level shifter
TWM586017U (en) Low power level shifter circuit
TWM598009U (en) Voltage level shifter having output control circuit
TWM565921U (en) Voltage level shifter
TWM576366U (en) Level conversion circuit with auxiliary circuit
TWM576365U (en) Low power voltage level converter
TWM531694U (en) Voltage level converter
TWM517481U (en) Voltage level converter
TWM538183U (en) Voltage level converter
TWM628446U (en) Contention-free level converting circuit for data receiving circuit
TWM598007U (en) High performance voltage level converter
TWM625120U (en) Voltage level converter with leakage current reduction
TWM628475U (en) Low power and high performance voltage level converting circuit
TWM626414U (en) Voltage level converter with stack transistors
TWM626307U (en) Contention-reduced level converting circuit
TWM626417U (en) High-speed low-power level shifter circuit
TWM618862U (en) Voltage level shifter with low power consumption
TWM629696U (en) High performance voltage level shifting circuit
TWM565919U (en) Voltage level converter
TWM569528U (en) Voltage level converter
TWM576363U (en) Potential converter to reduce competition
TWM528555U (en) Voltage level converter
TWM643260U (en) High performance level shifting circuit
TWM587403U (en) Voltage level converter with low-power consumption
TWM551788U (en) Voltage level shifter

Legal Events

Date Code Title Description
MM4K Annulment or lapse of a utility model due to non-payment of fees