TWI654770B - Two-dimensional extendable and flexible device and method of manufacturing same - Google Patents

Two-dimensional extendable and flexible device and method of manufacturing same

Info

Publication number
TWI654770B
TWI654770B TW106107273A TW106107273A TWI654770B TW I654770 B TWI654770 B TW I654770B TW 106107273 A TW106107273 A TW 106107273A TW 106107273 A TW106107273 A TW 106107273A TW I654770 B TWI654770 B TW I654770B
Authority
TW
Taiwan
Prior art keywords
substrate
extensible
flexible
dimensional
receiving surface
Prior art date
Application number
TW106107273A
Other languages
Chinese (zh)
Other versions
TW201735380A (en
Inventor
約翰Ａ 羅傑斯
馬修 梅特
孫玉剛
高興助
安卓 卡森
崔元文
馬克 史托科維奇
簡寒坤
永剛 黃
Original Assignee
美國伊利諾大學理事會
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美國伊利諾大學理事會 filed Critical 美國伊利諾大學理事會
Publication of TW201735380A publication Critical patent/TW201735380A/en
Application granted granted Critical
Publication of TWI654770B publication Critical patent/TWI654770B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B81B3/0064—Constitution or structural means for improving or controlling the physical properties of a device
    • B81B3/0067—Mechanical properties
    • B81B3/0078—Constitution or structural means for improving mechanical properties not provided for in B81B3/007 - B81B3/0075
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1602—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/0283—Stretchable printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1446—Devices controlled by radiation in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0271—Mechanical force other than pressure, e.g. shearing or pulling
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/201—Integrated devices having a three-dimensional layout, e.g. 3D ICs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Mathematical Physics (AREA)
  • Materials Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Led Device Packages (AREA)
  • Thin Film Transistor (AREA)
  • Micromachines (AREA)
  • Optical Integrated Circuits (AREA)
  • Light Receiving Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Mechanical Light Control Or Optical Switches (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Pressure Sensors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

在一態樣中，本發明提供可延伸且視情況可印刷之半導體及電子電路，其能夠在延伸、壓縮、折曲或以其他方式變形時提供良好效能。對於一些應用為較佳之可延伸半導體及電子電路，除可延伸以外亦為可撓性的，且因此能夠顯著伸長、折曲、撓曲或進行沿一或多個軸之其他變形。另外，本發明之可延伸半導體及電子電路可調適成寬廣範圍之設備組態，以提供具有充分可撓性之電子及光電子設備。 In one aspect, the present invention provides extensible and optionally printable semiconductor and electronic circuits that can provide good performance when stretched, compressed, bent, or otherwise deformed. Extensible semiconductors and electronic circuits that are preferred for some applications are also flexible in addition to being extensible, and therefore can significantly elongate, flex, flex, or otherwise deform along one or more axes. In addition, the extensible semiconductor and electronic circuits of the present invention can be adapted to a wide range of device configurations to provide electronic and optoelectronic devices with sufficient flexibility.

Description

二維可延伸且可撓曲設備及其製造方法 Two-dimensional extensible and flexible equipment and manufacturing method thereof

自1994年對印刷全聚合物電晶體之首次論證以來，將大量關注針對於包含處於塑膠基板上之可撓性整合式電子設備的潛在之新類別的電子系統。[Garnier,F.，Hajlaoui,R.，Yassar,A.及Srivastava,P.,Science，第265卷，第1684至1686頁]近來，大量研究已針對開發用於用於可撓性塑膠電子設備之導體、介電質及半導體元件之新的溶液可處理材料。然而，可撓性電子元件領域之進步不僅係由新的溶液可處理材料之開發所驅動，而且亦由可應用於可撓性電子系統之新的設備組件幾何形狀、有效之設備及設備組件處理方法及高解析度圖案化技術所驅動。預期該等材料、設備組態及製造方法將在快速新興之新類別的可撓性整合式電子設備、系統及電路中起根本作用。 Since the first demonstration of printed all-polymer transistors in 1994, a lot of attention has been paid to potential new types of electronic systems that include flexible integrated electronic devices on plastic substrates. [Garnier, F., Hajlaoui, R., Yassar, A., and Srivastava, P., Science, Vol. 265, pages 1684 to 1686] Recently, a lot of research has been directed to the development of flexible plastic electronic devices New solutions of conductors, dielectrics and semiconductor components can handle materials. However, advances in the field of flexible electronic components are driven not only by the development of new solution-processable materials, but also by new equipment component geometries, effective equipment and equipment component processing that can be applied to flexible electronic systems Driven by methods and high-resolution patterning techniques. It is expected that these materials, equipment configuration and manufacturing methods will play a fundamental role in the rapidly emerging new class of flexible integrated electronic equipment, systems and circuits.

對可撓性電子元件領域之關注起因於此技術所提供之若干重要優勢。舉例而言，此等基板材料之固有可撓性允許將其整合為許多形狀，從而提供對於脆性習知矽基電子設備而言為不可能之大量有用設備組態。另外，溶液可處理組份材料與可撓性基板之組合致能藉由連續高速印刷技術進行之製造，該等技術能夠以較低成本於較大基板區上產生電子設備。 The focus on the field of flexible electronic components stems from several important advantages provided by this technology. For example, the inherent flexibility of these substrate materials allows their integration into many shapes, thereby providing a large number of useful device configurations that are not possible with brittle, conventional silicon-based electronic devices. In addition, the combination of solution-processable component materials and flexible substrates enables manufacturing by continuous high-speed printing techniques that can produce electronic devices on a larger substrate area at a lower cost.

然而，顯示出良好電子效能的可撓性電子設備之設計及製造提出許多重大挑戰。第一，製造習知矽基電子設備之成熟方法與多數可撓性材料 不相容。舉例而言，諸如單晶矽或鍺半導體之傳統高品質無機半導體組件通常藉由在大大超過多數塑膠基板之熔融或分解溫度的溫度(>攝氏1000度)下使薄膜生長而加以處理。另外，多數無機半導體本質上不可溶於將允許基於溶液之處理及輸送之習知溶劑中。第二，雖然許多非晶矽、有機或混合有機-無機半導體適於併入可撓性基板中且可以相對較低之溫度加以處理，但此等材料不具有能夠提供具有良好電子效能之整合式電子設備的電子特性。舉例而言，具有由此等材料製成之半導體元件之薄膜電晶體顯示出比基於互補單晶矽之設備小約三個數量級之場效遷移率。由於此等限制，可撓性電子設備目前限於不需要高效能之特定應用，諸如用於開關元件(用於具有非發射性像素之主動式矩陣平板顯示器)中及用於發光二極體中。 However, the design and manufacture of flexible electronic devices that exhibit good electronic performance pose many major challenges. First, mature methods for manufacturing conventional silicon-based electronic devices and most flexible materials incompatible. For example, traditional high-quality inorganic semiconductor devices such as single crystal silicon or germanium semiconductors are usually processed by growing thin films at temperatures (> 1000 degrees Celsius) that greatly exceed the melting or decomposition temperature of most plastic substrates. In addition, most inorganic semiconductors are inherently insoluble in conventional solvents that will allow solution-based processing and delivery. Second, although many amorphous silicon, organic or hybrid organic-inorganic semiconductors are suitable for incorporation in flexible substrates and can be processed at relatively low temperatures, these materials do not have an integrated type that can provide good electronic performance Electronic characteristics of electronic equipment. For example, thin-film transistors with semiconductor devices made of these materials show field-effect mobilities that are about three orders of magnitude smaller than devices based on complementary monocrystalline silicon. Due to these limitations, flexible electronic devices are currently limited to specific applications that do not require high performance, such as in switching elements (for active matrix flat panel displays with non-emissive pixels) and in light emitting diodes.

可撓性電子電路為包括可撓性顯示器、具有任意形狀之電活性表面(諸如電子織物及電子皮膚)的許多領域中之研究之活躍區。此等電路經常由於傳導組件不能夠回應於構形改變而延伸而不能夠充分與其環境相一致。因此，彼等可撓性電路易於受損、電子降級，且在嚴苛及/或重複之構形改變下可能不可靠。可撓性電路需要在經由延伸及鬆弛而循環時仍保持完好之可延伸且可撓曲之互連。 Flexible electronic circuits are active areas of research in many fields including flexible displays, electroactive surfaces with arbitrary shapes (such as electronic fabrics and electronic skins). These circuits are often unable to fully conform to their environment because the conductive components cannot extend in response to configuration changes. Therefore, their flexible circuits are susceptible to damage, electronic degradation, and may be unreliable under severe and / or repeated configuration changes. Flexible circuits require extensible and flexible interconnects that remain intact while cycling through extension and relaxation.

能夠撓曲且具有彈性之導體一般藉由在諸如聚矽氧之彈性體中嵌入金屬粒子而製成。彼等傳導橡膠為具有機械彈性且導電的。傳導橡膠之缺點包括高電阻率及在延伸時之顯著電阻變化，由此導致整體較差之互連效能及可靠性。 Flexible and elastic conductors are generally made by embedding metal particles in an elastomer such as polysiloxane. Their conductive rubbers are mechanically elastic and electrically conductive. Disadvantages of conductive rubber include high resistivity and significant resistance changes during extension, thereby resulting in overall poor interconnect performance and reliability.

Gray等人論述了藉由使用封閉於能夠進行高達54%之線性應變同時保持傳導性之聚矽氧彈性體中的微製造曲折導線來建構彈性體電子元件。 在彼研究中，將導線形成為螺旋彈簧形狀。與在較低應變(例如，2.4%)下斷裂之直線導線相比，曲折導線在顯著較高之應變(例如，27.2%)下仍保持傳導。該導線幾何形狀依賴於導線藉由撓曲而非延伸而伸長之能力。彼系統在以不同形狀及在額外平面中進行可控及精確圖案化之能力上受到限制，由此限制使系統適應於不同應變及撓曲狀態之能力。 Gray et al. Discussed the construction of elastomeric electronic components by using microfabricated tortuous wires enclosed in polysiloxane elastomers capable of linear strain up to 54% while maintaining conductivity. In his research, the wire was formed into the shape of a coil spring. Compared to a straight wire that breaks at a lower strain (eg, 2.4%), the tortuous wire remains conductive at a significantly higher strain (eg, 27.2%). The wire geometry depends on the ability of the wire to elongate by flexing rather than extending. The other system's ability to perform controllable and precise patterning in different shapes and in additional planes is limited, thereby limiting the ability of the system to adapt to different strains and flexure states.

研究提示，彈性可延伸金屬互連經歷電阻隨機械應變之增加。(Mandlik等人，2006年)。Mandlik等人嘗試藉由於錐形奈米圖案化表面上沈積金屬膜而最小化此電阻改變。然而，彼研究依賴於產生賦予薄金屬線延伸能力之微裂縫之起伏特徵。微裂縫藉由平面外扭曲及變形而促進金屬彈性變形。然而，彼等金屬裂縫與厚金屬膜不相容，而替代地與沈積於圖案化彈性體之頂部的相當窄範圍之薄金屬膜(例如，約小於30nm)相容。 Research suggests that elastically extensible metal interconnects experience an increase in resistance with mechanical strain. (Mandlik et al., 2006). Mandlik et al. Attempted to minimize this resistance change by depositing a metal film on the tapered nano-patterned surface. However, his research relied on the generation of undulating features of micro-cracks that impart thin metal wire extension capabilities. Micro-cracks promote the elastic deformation of metals by twisting and deforming out of plane. However, their metal cracks are not compatible with thick metal films, but are instead compatible with a relatively narrow range of thin metal films (eg, less than about 30 nm) deposited on top of the patterned elastomer.

向金屬互連賦予可延伸性之一方式為在導體(例如，金屬)應用期間對基板預加應變(例如，15%至25%)，繼之以對預應變之自發解除，由此誘發金屬導體互連之波狀起伏(見(例如)Lacour等人(2003)；(2005)；(2004)，Jones等人(2004)；Huck等人(2000)；Bowden等人(1998))。Lacour等人(2003)報告藉由最初壓縮金條帶來產生自發起皺之金條帶，電連續性在高達22%之應變(與彈性基板上之金膜之數個百分比的斷裂應變相比)下得以保持。然而，彼研究使用相當薄之金屬膜之層(例如，約105nm)且相對有限，因為系統可潛在地製造可延伸約10%之電導體。 One way to impart extensibility to metal interconnects is to pre-strain the substrate (eg, 15% to 25%) during application of the conductor (eg, metal), followed by spontaneous relief of the pre-strain, thereby inducing metal Undulation of conductor interconnections (see, for example, Lacour et al. (2003); (2005); (2004), Jones et al. (2004); Huck et al. (2000); Bowden et al. (1998)). Lacour et al. (2003) reported that by initially compressing the gold strip, the self-initiated gold strip was produced, and the electrical continuity was up to 22% strain (compared to a few percent of the strain of the gold film on the elastic substrate ) Can be maintained. However, his research uses relatively thin layers of metal films (eg, about 105 nm) and is relatively limited because the system can potentially produce electrical conductors that can be extended by about 10%.

自前述內容顯而易見，存在對於具有改良之可延伸性、電特性之互連及設備組件及用於快速且可靠地製造多種不同組態之可延伸互連的相關製程之需要。預期可撓性電子元件領域中之進步在許多重要的新興及既定 之技術中起關鍵作用。然而，可撓性電子技術之此等應用的成功在很大程度上取決於對用於製造在折曲、變形及撓曲構形下顯示出良好電子、機械及光學特性之積體電子電路及設備的新型材料、設備組態及商業可行之製造途徑之持續開發。特定言之，需要高效能、機械可延展材料及設備組態在延伸或收縮構形下顯示出有用的電子及機械特性。 As is apparent from the foregoing, there is a need for interconnects and device components with improved extensibility, electrical characteristics, and related processes for quickly and reliably manufacturing extensible interconnects in many different configurations. Expect progress in the field of flexible electronic components in many important emerging and established Plays a key role in the technology. However, the success of these applications of flexible electronic technology depends to a large extent on the use of integrated electronic circuits that exhibit good electronic, mechanical, and optical properties under bending, deformation, and flexure configurations and Continuous development of new materials for equipment, equipment configuration and commercially viable manufacturing methods. In particular, high-performance, mechanically extensible materials and equipment configurations are required to exhibit useful electronic and mechanical properties in extended or contracted configurations.

本發明提供可延伸半導體及可延伸電子設備、設備組件及電路。需要可延伸、可撓曲且適型之電子設備及設備組件來製造適於印刷於多種彎曲表面上的電子元件。形狀符合之設備具有在自可撓性顯示器及電子織物至適型生物及物理感應器之範圍內的多種應用。因此，本發明之一實施例為具可撓性且可撓曲之電子設備、設備組件及用於製造具可撓性且可撓曲之設備的相關方法。藉由提供具有波狀或彎曲幾何形狀之互連或半導體薄膜而實現該可撓性及可撓曲性。該幾何形狀提供用於確保系統可延伸且可撓曲而不會有害地影響效能(即使在猛烈且重複之延伸及/或撓曲循環下)之手段。此外，該等方法提供精確且準確之幾何建構之能力，以使得可使設備及/或設備組件之物理特徵(例如，可延伸性、可撓曲性)適應於系統之操作條件。 The invention provides extensible semiconductor and extensible electronic equipment, equipment components and circuits. There is a need for extensible, flexible and conformable electronic devices and device components to manufacture electronic components suitable for printing on a variety of curved surfaces. Appropriately shaped devices have a variety of applications ranging from flexible displays and electronic fabrics to suitable biological and physical sensors. Therefore, one embodiment of the present invention is a flexible and flexible electronic device, a device component, and a related method for manufacturing a flexible and flexible device. This flexibility and flexibility are achieved by providing interconnections or semiconductor films with wavy or curved geometry. This geometry provides a means to ensure that the system is extensible and flexible without adversely affecting performance (even under violent and repeated cycles of extension and / or deflection). In addition, these methods provide the ability for precise and accurate geometric construction, so that the physical characteristics (eg, extensibility, flexibility) of the device and / or device components can be adapted to the operating conditions of the system.

舉例而言，可藉由彎曲互連而使一陣列設備組件彼此連接，以促進設備組件相對於彼此之獨立移動。然而，陣列內之局部區域可能具有與其他區域不同的撓曲或延伸要求。本發明之設備及方法促進可具有彎曲互連幾何形狀(包括(例如)互連尺寸、週期性、振幅、定向及一區中互連之總數目)之局部變化之可撓性系統的建構。產生具有可控制定向之多個互連 促進使互連適應於設備之操作條件。 For example, an array of device components can be connected to each other by bending interconnects to promote independent movement of the device components relative to each other. However, local areas within the array may have different flexion or extension requirements than other areas. The apparatus and method of the present invention facilitates the construction of flexible systems that can have local variations in curved interconnect geometry including, for example, interconnect size, periodicity, amplitude, orientation, and the total number of interconnects in a zone. Generate multiple interconnections with controllable orientation Promote adapting the interconnect to the operating conditions of the equipment.

在一實施例中，本發明提供用於建立與設備組件之電接觸之可延伸互連。互連具有第一末端、第二末端及安置於第一末端與第二末端之間的中央部分。該等末端結合至基板，諸如可撓性(例如，可延伸)基板、彈性體基板、剛性基板、不為彈性體之基板或者希望向其印刷電子設備、設備組件或其陣列之基板。互連之每一末端可附接至自身由基板支撐的不同設備組件。互連之中央部分處於撓曲組態且不與基板實體接觸(例如，不結合)。在一態樣中，此撓曲組態為中央部分處於應變之結果。在此態樣中，撓曲組態一般為彎曲的，以使得若以隔開設備組件之方式向一或多個設備組件(或下伏基板)施加力，則互連彎曲部分可至少部分地變直以適應設備組件之間的相對運動，同時保持設備組件之間的電接觸。 In one embodiment, the present invention provides an extensible interconnect for establishing electrical contact with device components. The interconnect has a first end, a second end, and a central portion disposed between the first end and the second end. The ends are bonded to a substrate, such as a flexible (eg, extensible) substrate, an elastomer substrate, a rigid substrate, a substrate that is not an elastomer, or a substrate to which electronic devices, device components, or arrays thereof are desired to be printed. Each end of the interconnect can be attached to a different device component that is itself supported by the substrate. The central portion of the interconnect is in a flexed configuration and is not in physical contact with the substrate (eg, not bonded). In one aspect, this flexure configuration is the result of strain at the center. In this aspect, the flexure configuration is generally curved, so that if a force is applied to one or more device components (or underlying substrates) in a manner that separates the device components, the interconnected curved portion can be at least partially Straighten to accommodate relative movement between equipment components while maintaining electrical contact between equipment components.

在一實施例中，互連中央部分為弧形，其具有一振幅，諸如在約100nm與約1mm之間的振幅。在一態樣中，不同互連結合區域之數目可大於二，諸如三、四或五。在此態樣中，在第一互連末端與第二互連末端之間的中央部分實際上經再分為許多撓曲組態區域，以使得形成不與基板實體接觸之複數個不同彎曲部分區域。在該組態中，振幅及/或週期性可為恆定或者可在互連之整個縱向長度上變化。互連自身可為任何形狀，諸如薄膜、線或織帶。在互連為織帶之態樣中，織帶可具有在約300nm與1mm之間的厚度。 In one embodiment, the central portion of the interconnect is arc-shaped, having an amplitude, such as an amplitude between about 100 nm and about 1 mm. In one aspect, the number of different interconnection bonding regions may be greater than two, such as three, four, or five. In this aspect, the central portion between the first interconnect end and the second interconnect end is actually subdivided into many flexure configuration areas, so that a plurality of different curved portions that are not in physical contact with the substrate are formed region. In this configuration, the amplitude and / or periodicity may be constant or may vary over the entire longitudinal length of the interconnect. The interconnect itself can be of any shape, such as film, wire or webbing. In the aspect that the interconnection is a webbing ribbon, the webbing ribbon may have a thickness between about 300 nm and 1 mm.

為了促進額外設備組件之置放，互連末端電連接至之設備組件可為接觸焊墊。在一態樣中，額外設備組件與接觸焊墊電接觸。 To facilitate placement of additional equipment components, the equipment components to which the interconnect ends are electrically connected may be contact pads. In one aspect, the additional equipment components are in electrical contact with the contact pads.

如所指出，支撐互連之基板可視互連所併入之設備而具有任何所要材料。在一實施例中，基板包含諸如聚二甲基矽氧烷(PDMS)之彈性體材 料。基板可可逆地變形(例如，PDMS)或不可逆地變形(例如，塑膠)。 As noted, the substrate supporting the interconnect may have any desired materials depending on the equipment into which the interconnect is incorporated. In one embodiment, the substrate includes an elastomer material such as polydimethylsiloxane (PDMS) material. The substrate may be reversibly deformed (for example, PDMS) or irreversibly deformed (for example, plastic).

在一實施例中，設備可基於其物理特徵來進一步加以描述。舉例而言，本文中提供能夠經受高達25%之應變同時保持電導率及與設備組件之電接觸的互連。此情況下的"保持"指代在應變適應期間電導率的小於20%、10%或5%之降低。 In an embodiment, the device may be further described based on its physical characteristics. For example, provided herein is an interconnect that can withstand strains of up to 25% while maintaining electrical conductivity and electrical contact with equipment components. "Keep" in this case refers to a decrease in conductivity of less than 20%, 10%, or 5% during strain adaptation.

在一實施例中，藉由將本文揭示之互連中之任一者併入具有複數個互連及兩個以上設備組件的設備陣列中來提供多軸延伸及撓曲。在此實施例中，每一互連提供一對設備組件之間的電接觸。視所要延伸、撓曲及/或壓縮操作條件而定，設備陣列可具有為柵格、花形、橋接或其任一組合(例如，一區域處於柵格組態中，另一區域處於橋接組態中)之幾何組態。另外，藉由將鄰近設備組件連接至一個以上之互連(諸如兩個、三個或四個互連)之能力而提供進一步的延伸及可撓曲性控制。舉例而言，係正方形或矩形之設備組件可鄰近於四個其他設備組件。若每一鄰近對藉由兩個互連而連接，則設備組件將具有自其延伸之八個互連。 In one embodiment, multi-axis extension and flexure are provided by incorporating any of the interconnects disclosed herein into a device array having multiple interconnects and more than two device components. In this embodiment, each interconnect provides electrical contact between a pair of device components. Depending on the desired extension, deflection, and / or compression operating conditions, the device array may have a grid, flower shape, bridge, or any combination thereof (eg, one area is in a grid configuration and the other area is in a bridge configuration Medium) geometric configuration. In addition, the ability to connect adjacent device components to more than one interconnect (such as two, three, or four interconnects) provides further extension and flexibility control. For example, a device component that is square or rectangular may be adjacent to four other device components. If each adjacent pair is connected by two interconnects, the device assembly will have eight interconnects extending from it.

在一實施例中，設備陣列具有定向於至少兩個不同方向上之互連之集合。舉例而言，在柵格組態中，互連可具有彼此垂直或正交之兩個定向以提供在兩個方向上延伸之能力。在另一實施例中，設備陣列可包含所有皆相對於彼此對準之互連。彼實施例在延伸或撓曲被限制於單一方向時(例如，將電子設備織物撓曲限制於圓柱形表面)可為有用的。藉由將互連定向於三個或三個以上方向(例如，三個方向或四個方向)上而提供額外撓曲及/或延伸能力。在一實施例中，藉由將設備陣列之互連置放於任一數目之不同層(諸如彼此鄰近之兩層)中而提供額外控制及穩定性。 In one embodiment, the device array has a collection of interconnects oriented in at least two different directions. For example, in a grid configuration, interconnects can have two orientations that are perpendicular or orthogonal to each other to provide the ability to extend in two directions. In another embodiment, the device array may include all interconnects that are aligned relative to each other. The other embodiment may be useful when the extension or deflection is limited to a single direction (for example, to limit the deflection of the electronic device fabric to a cylindrical surface). By orienting the interconnect in three or more directions (eg, three or four directions), additional flexibility and / or extension capabilities are provided. In one embodiment, additional control and stability are provided by placing the interconnection of the device array in any number of different layers, such as two layers adjacent to each other.

在一實施例中，設備陣列能夠經受高達約150%之應變而不斷裂。藉 由使互連幾何形狀、定向、振幅、週期性、數目適應於操作條件(例如，單軸對多軸延伸及/或撓曲)而最大化達到斷裂之應變。 In one embodiment, the device array can withstand up to about 150% strain without breaking. borrow The strain at which fracture is maximized is achieved by adapting the interconnection geometry, orientation, amplitude, periodicity, and number to operating conditions (eg, uniaxial to multiaxial extension and / or deflection).

支撐互連或設備陣列之基板可具有為彎曲(諸如，為凹入、凸起、半球形或其組合)之至少一部分。在一實施例中，互連所併入之設備為可延伸之光偵測器、顯示器、發光器、光伏打裝置、薄片掃描器、LED顯示器、半導體雷射、光學系統、大面積電子元件、電晶體或積體電路中之一或多者。 The substrate supporting the interconnect or device array may have at least a portion that is curved (such as concave, convex, hemispherical, or a combination thereof). In one embodiment, the devices incorporated into the interconnect are extensible photodetectors, displays, light emitters, photovoltaic devices, thin-film scanners, LED displays, semiconductor lasers, optical systems, large-area electronic components, One or more of transistors or integrated circuits.

在另一實施例中，本發明係關於用於製造能夠建立與設備組件之電接觸之彎曲互連之各種方法。在一態樣中，向彈性體基板表面、互連或兩者上施加結合位點之圖案。施加一力以使基板及與基板接觸之互連應變。結合位點之圖案提供特定互連位置與基板之間的結合。在使基板鬆弛之後(藉由移除力)，即產生彎曲互連。改變預加應變之量值、結合位點圖案化、幾何形狀及間距中之一或多者產生具有不同彎曲或波狀幾何形狀之互連。舉例而言，使結合位點之位置交錯以使得鄰近互連於不同位置處結合至基板提供"反相"之互連幾何形狀。結合位點圖案化係藉由此項技術中已知的任何手段而進行，諸如藉由向彈性體基板表面塗覆可固化光聚合物。視情況可藉由將互連之至少一部分囊封於諸如彈性體材料之囊封材料中來保護互連。彎曲互連可具有適於應用之任何形狀。在一實施例中，圖案為柵格組態、花形組態、橋接組態或其任一組合。 In another embodiment, the invention relates to various methods for manufacturing curved interconnects capable of establishing electrical contact with device components. In one aspect, a pattern of bonding sites is applied to the surface of the elastomeric substrate, the interconnect, or both. A force is applied to strain the substrate and interconnects in contact with the substrate. The pattern of bonding sites provides bonding between specific interconnection locations and the substrate. After the substrate is relaxed (by the removal force), a curved interconnection is created. Changing one or more of the amount of pre-strain, the patterning of bonding sites, the geometry and the spacing produces interconnects with different curved or wavy geometries. For example, staggering the positions of the bonding sites so that adjacent interconnects are bonded to the substrate at different locations provides "inverted" interconnect geometry. The bonding site patterning is performed by any means known in the art, such as by applying a curable photopolymer to the surface of the elastomeric substrate. Optionally, the interconnection can be protected by encapsulating at least a portion of the interconnection in an encapsulating material such as an elastomeric material. The curved interconnection can have any shape suitable for the application. In one embodiment, the pattern is a grid configuration, a flower configuration, a bridge configuration, or any combination thereof.

方法及設備可具有具任何尺寸之互連，諸如具有在數十奈米至約一毫米之範圍內的厚度或大於約300nm之厚度。在一態樣中，彎曲互連具有對應於互連自基板之最大豎直移位的振幅，且該振幅係選自100nm與1mm之間的範圍。對於具有長度及寬度之互連織帶，寬度、振幅或者寬度 及振幅視情況可沿互連之長度而變化。影響振幅之一因素為在互連結合之前施加至彈性體基板之預加應變。一般而言，應變愈高，振幅愈大。在一實施例中，施加之力在彈性體基板中產生一應變，其中該應變選自在20%與100%之間的範圍。 The method and apparatus may have interconnects of any size, such as having a thickness in the range of tens of nanometers to about one millimeter or a thickness greater than about 300 nm. In one aspect, the curved interconnect has an amplitude corresponding to the maximum vertical displacement of the interconnect from the substrate, and the amplitude is selected from the range between 100 nm and 1 mm. For interconnected webbing with length and width, width, amplitude or width And the amplitude may vary along the length of the interconnect as appropriate. One factor that affects the amplitude is the pre-strain applied to the elastomer substrate prior to interconnect bonding. Generally speaking, the higher the strain, the greater the amplitude. In one embodiment, the applied force produces a strain in the elastomeric substrate, where the strain is selected from the range between 20% and 100%.

在一實施例中，互連之一末端電連接至設備組件，且基板能夠延伸高達約100%，壓縮高達約50%或以低達5mm之曲率半徑而撓曲而無互連斷裂。互連由任何合適材料製成，諸如金屬或半導體，包括GaAs或Si。在一實施例中，該等方法提供彎曲互連自彈性體基板至諸如彎曲設備基板之設備基板的轉印。 In one embodiment, one end of the interconnect is electrically connected to the device component, and the substrate can extend up to about 100%, compress up to about 50% or flex with a radius of curvature as low as 5 mm without interconnect fracture. The interconnect is made of any suitable material, such as metal or semiconductor, including GaAs or Si. In one embodiment, these methods provide transfer of curved interconnections from an elastomer substrate to a device substrate such as a curved device substrate.

替代經由對彈性體基板預加應變而產生上推或彎曲互連，可藉由向具有波狀表面之聚合印模施加互連材料而製成可延伸且可撓曲之互連。 Instead of creating push-up or bending interconnects by pre-straining the elastomer substrate, extensible and flexible interconnects can be made by applying interconnect materials to a polymeric stamp with a wavy surface.

在一實施例中，為了製造可延伸且可撓曲之互連，使在表面上具有波狀特徵之基板平滑(諸如旋塗聚合物以部分填充凹入特徵)。該部分填充產生平滑波狀基板。接著視需要將金屬特徵沈積至平滑波狀基板上且對該等金屬特徵進行圖案化。平滑波狀基板上之金屬特徵可用於聚合印模抵靠平滑波狀金屬化基板之後續澆鑄。藉由自基板移除聚合印模而將金屬化基板(具有金屬特徵)轉移至聚合物基板來製造可延伸且可撓曲之互連。在一實施例中，金屬與基板之間的界面為Au/Su-8環氧樹脂光阻劑。金屬可為層化之(例如)Au/Al。基板可經類似地層化，例如玻璃層支撐Su-8層，金屬與基板之間的實際界面為Au/Su-8。 In one embodiment, in order to fabricate extensible and flexible interconnects, a substrate having wavy features on the surface is smoothed (such as spin-coating a polymer to partially fill the concave features). This partial filling produces a smooth wavy substrate. Then, if necessary, metal features are deposited on the smooth wavy substrate and the metal features are patterned. The metal features on the smooth wavy substrate can be used for subsequent casting of the polymerization stamp against the smooth wavy metallized substrate. The extensible and flexible interconnect is manufactured by removing the metalized stamp from the substrate and transferring the metalized substrate (with metal features) to the polymer substrate. In one embodiment, the interface between the metal and the substrate is Au / Su-8 epoxy resin photoresist. The metal may be layered (for example) Au / Al. The substrate can be similarly layered, for example, the glass layer supports the Su-8 layer, and the actual interface between the metal and the substrate is Au / Su-8.

在印模表面上製造上推互連之替代方法依賴於使彎曲基板表面變平，使互連與變平之表面接觸且允許基板表面鬆弛回至其彎曲幾何形狀。如本文所揭示，在一實施例中，該方法進一步提供在接觸之前對結合位點 進行空間圖案化。在此實施例中，該方法尤為適於將互連及設備組件轉移至第二相應彎曲基板表面。在一態樣中，諸如黏著劑或黏著前驅物之結合手段在第二彎曲基板與第一彎曲基板上之互連系統之間產生結合，其即使在移除彈性體印模之後亦足以允許互連系統向第二基板之轉移。 Alternative methods of making push-up interconnects on the stamp surface rely on flattening the curved substrate surface, bringing the interconnect into contact with the flattened surface and allowing the substrate surface to relax back to its curved geometry. As disclosed herein, in one embodiment, the method further provides for binding sites prior to contact Perform spatial patterning. In this embodiment, the method is particularly suitable for transferring interconnection and device components to the second corresponding curved substrate surface. In one aspect, a bonding means such as an adhesive or an adhesive precursor creates a bond between the interconnection system on the second curved substrate and the first curved substrate, which is sufficient to allow mutual interaction even after the elastomer stamp is removed Transfer of the system to the second substrate.

在一態樣中，本發明之方法及設備中之任一者具有為PDMS之印模或彈性體基板，其具有對於高達約40%之應變的線性及彈性回應。本發明之互連視情況可為可延伸電極、可延伸被動式矩陣LED顯示器或光偵測器陣列之部分。在一實施例中，本發明為具有藉由本發明之方法而製成之任何一或多個互連之可延伸電子設備，其中該電子設備為可延伸或可撓曲之電極、被動式矩陣LED、太陽能電池、集光器陣列、生物感應器、化學感應器、光電二極體陣列或半導體陣列。在一態樣中，電連接至彎曲互連之設備組件為薄膜、感應器、電路元件、控制元件、微處理器、傳感器或其組合。在一態樣中，藉由使互連之一末端電連接至設備組件而接取互連。 In one aspect, any of the methods and devices of the present invention has a stamp or elastomer substrate that is a PDMS that has a linear and elastic response to strains of up to about 40%. The interconnection of the present invention may optionally be part of an extensible electrode, an extensible passive matrix LED display, or a photodetector array. In one embodiment, the present invention is an extendable electronic device having any one or more interconnects made by the method of the present invention, wherein the electronic device is an extendable or flexible electrode, a passive matrix LED, Solar cell, concentrator array, biosensor, chemical sensor, photodiode array or semiconductor array. In one aspect, the device components electrically connected to the curved interconnect are thin films, sensors, circuit elements, control elements, microprocessors, sensors, or combinations thereof. In one aspect, the interconnect is accessed by electrically connecting one end of the interconnect to the device component.

在一實施例中，本發明係關於具有諸如波狀半導體奈米薄膜之波狀奈米薄膜之方法及結構。該波狀奈米薄膜促進可撓性在設備組件自身中之併入(與連接設備組件之互連之可撓性相比)。在一態樣中，本發明為製造將半導體奈米薄膜材料自第一基板轉移至第二變形基板之雙軸可延伸半導體薄膜之方法，其中在轉移之後，允許變形基板鬆弛回至其靜止組態。在一態樣中，半導體材料之厚度在約40nm與600nm之間。二維變形力之解除產生具有二維波狀結構之奈米薄膜。在一態樣中，藉由改變可撓性基板之溫度而產生變形力。 In one embodiment, the present invention relates to a method and structure having a corrugated nano film such as a corrugated semiconductor nano film. The corrugated nano-film facilitates the incorporation of flexibility in the device component itself (compared to the flexibility of interconnects connecting device components). In one aspect, the present invention is a method of manufacturing a biaxially extensible semiconductor film that transfers semiconductor nano-film materials from a first substrate to a second deformed substrate, wherein after the transfer, the deformed substrate is allowed to relax back to its stationary group state. In one aspect, the thickness of the semiconductor material is between about 40 nm and 600 nm. The release of the two-dimensional deformation force produces a nano-film with a two-dimensional wave structure. In one aspect, the deformation force is generated by changing the temperature of the flexible substrate.

10‧‧‧金屬特徵/SU-8/互連 10‧‧‧Metal Features / SU-8 / Interconnect

20‧‧‧基板 20‧‧‧ substrate

22‧‧‧波狀特徵 22‧‧‧Wave characteristics

24‧‧‧銳緣/銳緣谷 24‧‧‧Sharp Edge / Sharp Edge Valley

25‧‧‧分隔物(裂縫) 25‧‧‧ divider (crack)

26‧‧‧PR/光可固化環氧樹脂 26‧‧‧PR / light curable epoxy resin

30‧‧‧彈性體印模/基板/彈性體基板 30‧‧‧Elastomer impression / substrate / elastomer substrate

32‧‧‧波狀表面/波狀彈性體基板表面 32‧‧‧Wave surface / Wave elastomer surface

34‧‧‧彈性體印模/銳緣基板 34‧‧‧Elastomer impression / sharp edge substrate

36‧‧‧第二彈性體印模 36‧‧‧Second elastomer impression

40‧‧‧波狀或彎曲幾何形狀/電互連 40‧‧‧Wave or curved geometry / electrical interconnection

50‧‧‧Su-8 50‧‧‧Su-8

60‧‧‧設備組件 60‧‧‧Equipment components

70‧‧‧接觸焊墊/設備組件 70‧‧‧contact pad / equipment component

90‧‧‧中央部分 90‧‧‧Central part

92‧‧‧未結合區域 92‧‧‧Unbound area

100‧‧‧第一末端 100‧‧‧The first end

102‧‧‧結合區域 102‧‧‧Combined area

110‧‧‧第二末端 110‧‧‧The second end

112‧‧‧界面 112‧‧‧Interface

120‧‧‧橋接中央部分高峰 120‧‧‧ bridging the central peak

130‧‧‧橋接組態 130‧‧‧Bridge configuration

140‧‧‧單一柵格組態 140‧‧‧Single grid configuration

150‧‧‧花形組態 150‧‧‧Flower configuration

160‧‧‧互連 160‧‧‧Interconnect

200‧‧‧凸起 200‧‧‧ raised

210‧‧‧凹入表面 210‧‧‧recessed surface

250‧‧‧電極 250‧‧‧electrode

300‧‧‧外殼腔室 300‧‧‧Shell chamber

310‧‧‧腔室容積/外殼容積/腔室 310‧‧‧chamber volume / housing volume / chamber

圖1概述用於製造波狀或彎曲可延伸金屬互連之一方法。A為流程圖 概述且B說明流程圖步驟。 Figure 1 outlines one method for making wavy or curved extensible metal interconnects. A is a flowchart Outline and B illustrate flowchart steps.

圖2為可延伸波狀/彎曲電互連之相片，該電互連係藉由自剛性基板取至經預加應變之可延伸PDMS橡膠基板上，隨後解除應變以誘發彎曲而形成。 Fig. 2 is a photograph of an extensible wavy / bending electrical interconnection formed by taking a rigid substrate onto a pre-strained extensible PDMS rubber substrate and then releasing strain to induce bending.

圖3概述藉由在波狀結構之彈性體基板上沈積而製造波狀可延伸電極之一方法。 FIG. 3 outlines a method of manufacturing a wave-shaped extensible electrode by depositing on a wave-shaped elastomer substrate.

圖4提供關於用於製造平滑波狀彈性體基板之一方法的細節。A為流程圖概述且B說明流程圖步驟。 FIG. 4 provides details about one method for manufacturing a smooth wavy elastomer substrate. A is an overview of the flowchart and B illustrates the steps of the flowchart.

圖5提供藉由圖3至圖4中所概括之方法而產生之平滑波狀PDMS基板的影像。A中所展示之互連具有22.6%之可延伸性且具有約900nm厚(700nm Al/200nm Au)之金屬互連、約38微米之波長及約15.6微米之振幅(自峰至谷之距離)。B展示互連之一用於與設備組件建立電接觸之末端。可將設備組件定位於基板之平坦部分中。 FIG. 5 provides an image of a smooth wave PDMS substrate produced by the method outlined in FIGS. 3 to 4. FIG. The interconnect shown in A has 22.6% extensibility and has a metal interconnect of about 900nm thick (700nm Al / 200nm Au), a wavelength of about 38 microns and an amplitude of about 15.6 microns (distance from peak to valley) . B shows the end of one of the interconnects used to establish electrical contact with device components. The device component can be positioned in the flat portion of the substrate.

圖6A具有尖點之市售雙凸透鏡陣列(購自Edmund Optics)。B旋塗光可固化環氧樹脂以製造平滑波狀基板。C抵靠得自B之基板而澆鑄PDMS印模以產生具有平滑特徵之波狀彈性體印模。 Figure 6A A commercially available lenticular lens array (purchased from Edmund Optics) with sharp points. B spin-coating light-curable epoxy resin to manufacture smooth wavy substrates. C casts a PDMS stamp against the substrate from B to produce a wavy elastomer stamp with smooth features.

圖7藉由經由蔽蔭遮罩而蒸鍍至平滑波狀彈性體基板上而沈積之可延伸電極。電極在受張力而延伸至高達~10%期間保持傳導性及連接性。定標線條為約0.1mm。A為彈性體基板上之波狀起伏之橫截面圖。B為蒸鍍至波狀彈性體基板上之電極之俯視顯微相片。焦平面處於波狀起伏之峰上。C為蒸鍍至波狀彈性體基板上之電極之俯視顯微相片。焦平面處於波狀起伏之谷上。 FIG. 7 is an extensible electrode deposited by vapor deposition onto a smooth wavy elastomer substrate through a shadow mask. The electrode maintains conductivity and connectivity during tension up to ~ 10%. The calibration line is about 0.1 mm. A is a cross-sectional view of undulations on the elastomer substrate. B is a photomicrograph of a top view of the electrode deposited onto the corrugated elastomer substrate. The focal plane is on the undulating peak. C is a photomicrograph of a top view of the electrode deposited onto the corrugated elastomer substrate. The focal plane is on the undulating valley.

圖8為對用於使用可延伸電極製造可延伸被動式矩陣LED顯示器之製 程之示意性說明。 FIG. 8 is a diagram showing the manufacturing method of an extensible passive matrix LED display using extensible electrodes. Schematic description of Cheng.

圖9說明具有波狀電極之被動式矩陣LED顯示器之機械可延伸性。 FIG. 9 illustrates the mechanical extensibility of passive matrix LED displays with corrugated electrodes.

圖10說明分布於具有球形彎曲之透鏡上的無機光電二極體陣列。所展示的為各種透鏡形狀及角度 Figure 10 illustrates an array of inorganic photodiodes distributed on lenses with spherical curvature. Shown are various lens shapes and angles

圖11說明當圍繞球形表面而包繞平坦薄片時對於可延伸性之需要。 Figure 11 illustrates the need for extensibility when a flat sheet is wrapped around a spherical surface.

圖12概述用於製造能夠與球面彎曲之表面相符的可延伸彎曲半導體陣列之一機制。 FIG. 12 outlines a mechanism for manufacturing an extendable curved semiconductor array that can conform to a spherically curved surface.

圖13具有單一連接柵格組態(A及B)、多個(例如，兩個)連接柵格組態(C)及花形連接組態(D)之彎曲可延伸矽陣列之光學顯微影像。可延伸互連能夠於(例如)接觸焊墊區域處電連接光電二極體、光收集/偵測設備及其他設備組件。此等系統能夠與彎曲表面相符。圖13中描繪之組態處於PDMS基板上。 Fig. 13 Optical microscopic image of a curved extendable silicon array with a single connection grid configuration (A and B), multiple (for example, two) connection grid configurations (C) and a flower-shaped connection configuration (D) . Extensible interconnects can electrically connect photodiodes, light collection / detection devices, and other device components at, for example, contact pad areas. These systems can conform to curved surfaces. The configuration depicted in Figure 13 is on the PDMS substrate.

圖14採取柵格組態的能夠支撐設備組件且與彎曲表面相符之彎曲可延伸矽陣列之電子顯微影像。定標線條在A中為200μm且在B中為50μm。 FIG. 14 is an electron microscopic image of a curved extensible silicon array in a grid configuration capable of supporting device components and conforming to a curved surface. The calibration line is 200 μm in A and 50 μm in B.

圖15採取柵格組態之彎曲可延伸矽陣列之電子顯微影像，該等陣列具有藉由複數個(例如，兩個)互連彼此連接之鄰近接觸焊墊且能夠支撐設備組件且與彎曲表面相符。定標線條在A中為200μm且在B中為50μm。 Fig. 15 Electron microscopic images of curved extendable silicon arrays in a grid configuration with adjacent contact pads connected to each other by a plurality (for example, two) of interconnections and capable of supporting device components and with bending The surface matches. The calibration line is 200 μm in A and 50 μm in B.

圖16採取花形組態的能夠支撐設備組件且與彎曲表面相符之彎曲可延伸矽陣列之電子顯微影像。定標線條在A中為200μm且在B中為50μm。 16 is an electron microscopic image of a curved extensible silicon array in a flower-shaped configuration capable of supporting device components and conforming to a curved surface. The calibration line is 200 μm in A and 50 μm in B.

圖17採取橋接組態的能夠支撐設備組件且與彎曲表面相符之彎曲可延伸矽陣列之電子顯微影像。定標線條在A中為200μm且在B中為50 μm。 FIG. 17 is an electron microscopic image of a curved extensible silicon array in a bridge configuration capable of supporting device components and conforming to a curved surface. The calibration line is 200μm in A and 50 in B μm.

圖18 PDMS上之可延伸彎曲矽陣列上的採取柵格陣列組態之光電二極體之相片。 Figure 18 Photograph of a photodiode in a grid array configuration on a stretchable curved silicon array on PDMS.

圖19論證可延伸互連在延伸與鬆弛期間的可逆行為。在畫面1中使系統鬆弛。如藉由延伸箭頭所指示而在畫面2、3及4中使系統延伸。畫面4中之最大延伸為約10%且導致大體上平坦之互連(對於在延伸力之方向上對準之互連)。在畫面5至8中釋放系統，且畫面8具有與畫面1中所示之幾何形狀及組態等效的幾何形狀及組態。定標線條為0.2mm。 Figure 19 demonstrates the reversible behavior of extensible interconnects during extension and relaxation. Relax the system in screen 1. Extend the system in screens 2, 3, and 4 as indicated by the extension arrows. The maximum extension in picture 4 is about 10% and results in substantially flat interconnects (for interconnects aligned in the direction of extension force). The system is released in screens 5 to 8, and screen 8 has a geometry and configuration equivalent to those shown in screen 1. The calibration line is 0.2mm.

圖20能夠與彎曲基板以及平坦基板保形接觸之"氣泡印模"或"氣球印模"設備。 Figure 20 "Bubble impression" or "balloon impression" equipment capable of conformal contact with a curved substrate and a flat substrate.

圖21能夠與球面彎曲及平坦表面相符之另一設備為可延伸球面模製之印模。抵靠彎曲表面(在此實例中為凹入透鏡)澆鑄印模且將其移除。使印模延伸以使其表面大體上變平，可將互連轉移至該表面。 Fig. 21 Another device capable of conforming to the curved and flat surface of the spherical surface is a stamper for extensible spherical molding. The stamp is cast against the curved surface (in this example, the concave lens) and removed. By extending the stamp so that its surface is substantially flat, the interconnect can be transferred to that surface.

圖22在"氣泡"或"氣球"印模上之延伸循環期間之可延伸彎曲矽陣列。在此實例中，鄰近接觸焊墊之間的互連包含兩個波狀互連(厚度為290nm之Si)。延伸測試使用氣泡擴展來提供多向延伸。最右側畫面處於最大延伸中，且底部兩幅畫面展示當移除延伸力時，互連鬆弛回至左上部畫面所示的其延伸之前的組態。 Figure 22 Extendable curved silicon array during the extension cycle on the "bubble" or "balloon" stamp. In this example, the interconnection between adjacent contact pads includes two wavy interconnections (Si with a thickness of 290 nm). The extension test uses bubble expansion to provide multi-directional extension. The right-most picture is in the maximum extension, and the bottom two pictures show that when the extension force is removed, the interconnect relaxes back to the configuration shown in the upper left picture before its extension.

圖23經由氣球印模而印刷至塗佈有黏著劑(PDMS或SU-8)之玻璃透鏡上之矽。 Figure 23 Silicone printed on a glass lens coated with an adhesive (PDMS or SU-8) via a balloon stamp.

圖24概括用於設計半導體奈米織帶中之3維彎曲形狀之處理步驟。A製造UVO遮罩且使用其在PDMS基板上圖案化表面化學。B形成彎曲GaAs織帶且將其嵌入於PDMS中。C彎曲GaAs織帶對延伸及壓縮之回應。D使 用a及b中之程序而形成之樣本的SEM影像。用於產生此樣本之預加應變為60%，其中Wact=10μm且Win=400μm。 Figure 24 summarizes the processing steps used to design a 3-dimensional curved shape in a semiconductor nanoweb. A. Make a UVO mask and use it to pattern the surface chemistry on the PDMS substrate. B forms a curved GaAs webbing and embeds it in PDMS. C Bending GaAs webbing response to extension and compression. D SEM images of samples formed using the procedures in a and b. The pre-strain used to generate this sample was 60%, where W act = 10 μm and W in = 400 μm.

圖25藉由使用33.7%之預加應變且以(A)Wact=10μm及Win=190μm；及(B)Wact=100μm及Win=100μm而形成於PDMS基板上的彎曲之側視輪廓。兩個樣本均由於織帶自PDMS之分離而在非活性區域中顯示彎曲。具有較小峰之正弦波僅形成於活性區域中，其中Wact=100μm。此等兩個樣本之比較指示將Wact選擇為小於一臨界值避免較小波狀結構之形成。 FIG. 25 is a side view of a curve formed on a PDMS substrate by using 33.7% of pre-strain and (A) W act = 10 μm and W in = 190 μm; and (B) W act = 100 μm and W in = 100 μm profile. Both samples showed bending in the inactive area due to the separation of the webbing from the PDMS. A sine wave with a smaller peak is formed only in the active area, where W act = 100 μm. The comparison of these two samples indicates that W act is selected to be less than a critical value to avoid the formation of smaller wavy structures.

圖26嵌入於PDMS中之彎曲GaAs織帶在顯微切片之後的側視影像。此影像展示PDMS完全填充織帶與下伏基板之間的間隙。在此情況下之彎曲以60%之預加應變且以Wact=10μm及Win=300μm而形成。在此等彎曲織帶之表面上澆鑄之PDMS預聚物在烘箱中於65℃下固化4小時。 Fig. 26 is a side view image of a curved GaAs ribbon embedded in PDMS after microsectioning. This image shows that PDMS completely fills the gap between the ribbon and the underlying substrate. The bend in this case is formed with a pre-strain of 60% and with W act = 10 μm and W in = 300 μm. The PDMS prepolymer cast on the surface of these curved webbings was cured in an oven at 65 ° C for 4 hours.

圖27彎曲(A及D)GaAs及(B、C)Si織帶之側視輪廓的光學顯微相片。A形成於以Wact=10μm及Win=190μm，以不同預加應變：11.3%、25.5%、33.7%及56.0%(自頂部至底部)而經圖案化之PDMS上的GaAs織帶結構。對於εpre=33.7%及56.0%之虛線為以數學方法預測之互連幾何形狀。B形成於經預加應變至50%且以Wact=15μm及Win為350、300、250、250、300及350μm(自左向右)而經圖案化之PDMS基板上的Si織帶結構。藉由使樣本以45之角度傾斜而獲得影像。C形成於經預加應變至50%且以黏著位點之平行線(Wact=15μm且Win=250μm)而經圖案化之PDMS基板上的Si織帶結構，該等平行線以相對於織帶之長度成30之角度而定向。藉由使樣本以75之角度傾斜而獲得影像。D形成於經預加應變至60%，具有Wact=10μm及不同Win(100、200、300及400μm(自頂部至底部))之基 板上的GaAs織帶結構。 Figure 27 Optical micrograph of the side profile of curved (A and D) GaAs and (B, C) Si ribbons. A was formed on a GaAs ribbon structure on PDMS patterned with W act = 10 μm and W in = 190 μm with different pre-strains: 11.3%, 25.5%, 33.7%, and 56.0% (from top to bottom). The dotted lines for ε pre = 33.7% and 56.0% are mathematically predicted interconnect geometry. B is formed on a Si ribbon structure pre-strained to 50% and patterned on PDMS substrates with W act = 15 μm and W in 350, 300, 250, 250, 300 and 350 μm (from left to right). The image was obtained by tilting the sample at an angle of 45. C is formed on the Si ribbon structure on the PDMS substrate patterned with parallel lines (W act = 15 μm and W in = 250 μm) pre-strained to 50% and adhered to the sites. The length is oriented at an angle of 30. The image was obtained by tilting the sample at an angle of 75. D is formed on a GaAs ribbon structure on a substrate pre-strained to 60%, with W act = 10 μm and different W in (100, 200, 300, and 400 μm (from top to bottom)).

圖28嵌入於PDMS中之彎曲GaAs織帶的延伸及壓縮。A延伸至拉伸應變之不同水準(正%)的單一彎曲織帶之影像。斷裂在接近50%時發生。B壓縮至壓縮應變之不同水準(負%)的單一彎曲織帶之影像。對於大於~-15%之壓縮應變，小、短週期波狀幾何形狀出現於彎曲之高峰處。C壓縮至壓縮應變之不同水準的單一彎曲織帶之影像。此等情況下之彎曲係以60%之預加應變，以Wact=10μm且Win=400μm(A、B)及以Wact=10μm且Win=300μm(C)而形成。每一畫面中之紅線及箭頭指示同一織帶上之相同位置以突出顯示機械變形。插圖提供標有白框之區段的放大影像，其清楚展示在高壓縮應變下裂縫之形成。根據下式而計算對應於延伸或壓縮程度 之數字：。 Figure 28 Extension and compression of curved GaAs webbing embedded in PDMS. A Image of a single curved webbing extending to different levels (positive%) of tensile strain. Fracture occurs near 50%. B Image of a single bent webbing compressed to different levels of compression strain (negative%). For compressive strains greater than ~ -15%, small and short-period wavy geometries appear at the peak of bending. C Image of a single curved webbing compressed to different levels of compressive strain. The bending in these cases is formed with a pre-strain of 60%, W act = 10 μm and W in = 400 μm (A, B) and W act = 10 μm and W in = 300 μm (C). The red line and arrow in each picture indicate the same position on the same webbing to highlight the mechanical deformation. The illustration provides an enlarged image of the section marked with a white frame, which clearly shows the formation of cracks under high compressive strain. Calculate the number corresponding to the degree of extension or compression according to the following formula: .

圖29具有兩個彎曲GaAs織帶陣列之層之樣本的相片。以逐層機制來製造該結構。第一個GaAs織帶之層(以60%之預加應變且以Wact=10μm及Win=400μm而界定之彎曲幾何形狀)嵌入於PDMS中。第二個彎曲織帶之層藉由使用50%之預加應變且以Wact=10μm及Win=300μm而形成於此基板之表面上。 Figure 29 is a photograph of a sample with two layers of curved GaAs ribbon arrays. The structure is manufactured in a layer-by-layer mechanism. The first layer of GaAs webbing (bent geometry defined by 60% pre-strain and defined by W act = 10 μm and W in = 400 μm) is embedded in the PDMS. The second layer of curved webbing was formed on the surface of this substrate by using 50% pre-strained and with W act = 10 μm and W in = 300 μm.

圖30 PDMS之表面上及PDMS之基質中的彎曲織帶之撓曲。A-C為採用較低放大率之光學顯微影像(左上部圖框)及較高放大率之光學顯微影像(右側圖框)及對PDMS上之具有(A)凹入，(B)平坦及(C)凸起表面之彎曲GaAs織帶的示意性說明(左下部圖框)。c中之定標線條適用於a及b。d為嵌入於PDMS中之彎曲織帶在撓曲之前(左側)及之後(右側)的影像。頂部及底部圖框分別展示頂部及底部表面之彎曲。右側影像中之定標線條亦適用於左側影像。彎曲織帶以60%之預加應變且以Wact=10μm及Win=400 μm而形成。 Figure 30 Flexure of curved webbing on the surface of PDMS and in the matrix of PDMS. AC is an optical microscopic image with a lower magnification (upper left frame) and an optical microscopic image with a higher magnification (right frame) and has (A) concave, (B) flat and on the PDMS (C) A schematic illustration of the curved GaAs webbing on the convex surface (lower left frame). The calibration lines in c apply to a and b. d is the image of the curved webbing embedded in PDMS before (left side) and after (right side) deflection. The top and bottom frames show the curvature of the top and bottom surfaces, respectively. The calibration lines in the image on the right also apply to the image on the left. The curved webbing was formed with 60% pre-strain and W act = 10 μm and W in = 400 μm.

圖31可延伸金屬-半導體-金屬光偵測器(metal-semiconductor-metal photodetector,MSM PD)之表徵。A對彎曲PD之幾何形狀(頂部)、等效電路(中部)及彎曲PD在延伸之前及期間的光學影像(底部)之示意性說明。B自藉由IR燈以不同輸出強度而輻射之彎曲PD記錄的電流(I)-電壓(V)曲線。以恆定之亮度及不同程度的延伸(C)或壓縮(D)而說明PD之I-V特徵。 FIG. 31 can be extended to the characterization of a metal-semiconductor-metal photodetector (MSM PD). A is a schematic illustration of the geometric shape (top), equivalent circuit (middle), and optical image (bottom) of the curved PD before and during the extension. B Current (I) -Voltage (V) curve recorded from a curved PD radiated by an IR lamp at different output intensities. The I-V characteristics of PD are illustrated with constant brightness and varying degrees of extension (C) or compression (D).

圖32半球彈性體轉移"印模"可將互連之Si CMOS "小晶片"自習知晶圓起離，且接著將其幾何形狀變換為半球形。小晶片之間的"上推"互連適應與此平面至彎曲表面之變換相關聯的應變。 Figure 32 Hemispherical elastomer transfer "impression" can separate the interconnected Si CMOS "small chip" from the conventional wafer, and then transform its geometry into a hemispherical shape. The "push-up" interconnection between the small wafers accommodates the strain associated with this plane-to-curved surface transformation.

圖33互連之CMOS小晶片自半球印模向匹配的半球設備基板之轉移。光可固化黏著劑層使CMOS結合至設備基板且亦使表面平面化。 Figure 33 Transfer of interconnected CMOS wafers from a hemispherical die to a matching hemispherical device substrate. The photocurable adhesive layer bonds the CMOS to the device substrate and also planarizes the surface.

圖34具有夾具、致動器及視覺系統，與半球印模相容之印刷器裝置。 Figure 34 is a printer device with fixtures, actuators and vision system compatible with hemispherical impressions.

圖35半球印模上藉由"上推"織帶互連而電連接之單晶矽島狀物的可壓縮陣列。 Figure 35 A compressible array of single crystal silicon islands electrically connected by "push-up" ribbon interconnections on a hemispherical impression.

圖36經"塗墨"至具有~2cm之曲率半徑之半球印模之表面上的互連之單晶矽島狀物之陣列之光學影像。 Figure 36. Optical image of an array of interconnected single crystal silicon islands on the surface of a hemispherical stamp with a radius of curvature of ~ 2cm after being "painted".

圖37可用於半球印模之各種聚矽氧彈性體之應力/應變曲線。對小於20%之應變的線性、純彈性回應係重要的。 Figure 37 Stress / strain curves of various silicone elastomers that can be used in hemispherical impressions. Linear, purely elastic responses to strains less than 20% are important.

圖38對具有0.57mm之最初均勻厚度之半球印模中的球形至平面之變換之有限元模型化。 Figure 38 is a finite element model of the spherical-to-planar transformation in a hemispherical stamp with an initial uniform thickness of 0.57mm.

圖39對用於製造彈性體支撐物上之二維"波狀"半導體奈米薄膜之步驟的示意性說明。 Figure 39 is a schematic illustration of the steps used to fabricate a two-dimensional "wavy" semiconductor nanofilm on an elastomeric support.

圖40(a-f)矽奈米薄膜中之2維波狀結構在其形成期間之各個階段之光學顯微相片。插圖展示二維功率譜，(g)低放大率的完全形成之結構之影像。對於此樣本，矽之厚度為100nm，其具有約4×4mm2之橫向尺寸，基板為PDMS且熱誘發之預加應變為3.8%。(h)對應於圖框(a-f)之短波長之曲線，及(i)於得自圖框(g)之各個點處估計的長波長之直方圖。 Figure 40 (af) Optical micrographs of the two-dimensional wave-like structure in the silicon nanofilm at various stages during its formation. The illustration shows a two-dimensional power spectrum, (g) a low-magnification image of a fully formed structure. For this sample, the thickness of silicon is 100 nm, it has a lateral dimension of about 4 × 4 mm 2 , the substrate is PDMS and the thermally induced pre-strain is 3.8%. (h) The curve corresponding to the short wavelength of the frame (af), and (i) the histogram of the long wavelength estimated at each point obtained from the frame (g).

圖41 PDMS上之2維波狀Si奈米薄膜之AFM(a)及SEM(b-d)影像(傾斜角60)。矽之厚度為100nm，且熱預加應變為3.8%。此等影像突出顯示波狀圖案之高度週期性性質、如由在Si與PDMS之接近於Si中蝕刻之孔洞之邊緣處可見的密切接觸而顯見之Si與PDMS之間良好結合，及波紋結構與此等孔洞之位置之間相關性的缺失。 Figure 41 AFM (a) and SEM (b-d) images (tilt angle 60) of the 2D wavy Si nanofilm on PDMS. The thickness of silicon is 100 nm, and the thermal pre-strain is 3.8%. These images highlight the highly periodic nature of the wavy pattern, such as the good bonding between Si and PDMS, as shown by the close contact visible at the edges of Si and PDMS close to the holes etched in Si, and The lack of correlation between the locations of these holes.

圖42(a)PDMS上之以3.8%之熱預加應變形成、具有各種厚度(55nm、100nm、260nm、320nm)之2維波狀Si奈米薄膜之光學顯微相片，及(b)短波長及振幅對Si厚度之依賴性。 Fig. 42 (a) Optical micrograph of a 2-dimensional wave-shaped Si nanofilm with various thicknesses (55nm, 100nm, 260nm, 320nm) formed on PDMS with 3.8% thermal pre-strain, and (b) short The dependence of wavelength and amplitude on the thickness of Si.

圖43(a)在於三個不同定向上施加之不同單軸應變下的2維波狀Si奈米薄膜之光學顯微相片。此等樣本由PDMS上之以3.8%之熱預加應變形成、具有100nm之厚度的Si薄膜組成。於延伸前之鬆弛狀態(頂部圖框)、延伸後之鬆弛狀態(底部圖框)及在1.8%之單軸施加的拉伸應變下(頂部中部圖框)及3.8%之單軸施加之拉伸應變下(底部中部圖框)收集該等影像，(b)短波長對在三個不同方向上施加之應變之依賴性。 Fig. 43 (a) is an optical micrograph of a 2D wavy Si nanofilm under different uniaxial strains applied in three different orientations. These samples consisted of Si thin films formed on PDMS with a thermal pre-strain of 3.8% and a thickness of 100 nm. In the relaxed state before extension (top frame), the relaxed state after extension (bottom frame) and under 1.8% uniaxially applied tensile strain (top middle frame) and 3.8% uniaxially applied tension Collect these images under tensile strain (bottom middle frame), (b) the dependence of short wavelength on the strain applied in three different directions.

圖44 2維波狀Si奈米薄膜之不同區域之AFM影像，其展示接近薄膜之邊緣處的區域(頂部圖框)、稍稍遠離此邊緣區域之區域(中部圖框)及接近薄膜的中央之區域(底部圖框)之一維波狀幾何特徵。此等樣本由PDMS上之以3.8%之熱預加應變形成、具有100nm之厚度的Si薄膜組成。 Figure 44 AFM images of different areas of a 2-dimensional wave-shaped Si nanofilm showing the area near the edge of the film (top frame), the area slightly away from this edge area (middle frame) and the center of the film One-dimensional wavy geometric feature of the area (bottom frame). These samples consisted of Si thin films formed on PDMS with a thermal pre-strain of 3.8% and a thickness of 100 nm.

圖45具有1000μm之長度且具有100μm、200μm、500μm及1000μm之寬度的2維波狀Si奈米薄膜之光學顯微相片。此等薄膜均具有100nm之厚度且以(a)2.3%及(b)4.8%之熱預加應變而形成於同一PDMS基板上。(c)對於類似薄膜，邊緣效應長度對預加應變之依賴性。 FIG. 45 is an optical micrograph of a 2-dimensional wave-shaped Si nanofilm having a length of 1000 μm and widths of 100 μm, 200 μm, 500 μm, and 1000 μm. These thin films all have a thickness of 100 nm and are formed on the same PDMS substrate with (a) 2.3% and (b) 4.8% thermal pre-strain. (c) For similar films, the dependence of edge effect length on pre-strain.

圖46具有不同形狀之2維波狀Si奈米薄膜之光學顯微相片：(a)圓形、(b)橢圓形、(c)六邊形及(d)三角形。此等薄膜均具有100nm之厚度且以4.8%之熱預加應變而形成於PDMS上。 Fig. 46 Optical micrographs of 2D wavy Si nanofilms with different shapes: (a) circle, (b) ellipse, (c) hexagon and (d) triangle These thin films all have a thickness of 100 nm and are formed on PDMS with a thermal pre-strain of 4.8%.

圖47具有經設計以利用邊緣效應來在平坦島狀物之互連陣列中提供2維可延伸性之形狀的Si奈米薄膜之波狀結構之光學顯微相片。在此處說明之兩種情況中，Si為100nm厚，方塊為100μm×100μm且織帶連接為30μm×150μm之線。預加應變為2.3%(a、e)及15%(c、g)。展示(a、c、e、g)之織帶及方塊之選定區域的SEM影像(75之傾斜角)分別展示於(b、d、f、h)中。高放大率SEM影像之插圖展示b及d中之具有波紋的凸起區域。 FIG. 47 has an optical micrograph of a wave structure of a Si nano-film having a shape designed to use edge effects to provide 2-dimensional extensibility in an interconnect array of flat islands. In the two cases described here, Si is 100 nm thick, the square is 100 μm × 100 μm, and the webbing connection is a line of 30 μm × 150 μm. The pre-strain is 2.3% (a, e) and 15% (c, g). The SEM images (inclination angle of 75) showing the webbing of (a, c, e, g) and the selected area of the square are shown in (b, d, f, h), respectively. The high magnification SEM image illustration shows the raised areas with ripples in b and d.

圖48為PDMS基板波紋上之2維波狀Si奈米薄膜之樣本(100nm厚，4×5mm2及3.8%之熱預加應變)的相片(頂部圖框)，且(i)為邊緣處之1維波紋，(ii)為內部區域處之魚骨狀波紋且(iii)為中央處之無序魚骨狀波紋。定標線條為50μm。 Fig. 48 is a photograph (top frame) of a sample of a 2-dimensional wave-shaped Si nanofilm on a PDMS substrate ripple (100 nm thick, 4 × 5 mm 2 and 3.8% thermal pre-strain), and (i) is at the edge The 1D corrugation, (ii) is a fishbone corrugation at the inner area and (iii) is a disordered fishbone corrugation at the center. The calibration line is 50 μm.

圖49對魚骨狀波紋結構中之特徵性長度之示意性說明。 Figure 49 is a schematic illustration of the characteristic length in a fishbone corrugated structure.

圖50魚骨狀波紋及1維波紋處作為所施加之熱預加應變之函數的Si應變。在實驗中藉由εSi=(L-λ)/λ來量測Si應變，其中L及λ為AFM表面輪廓中之表面及水平距離。 Figure 50 Fishbone corrugation and 1D corrugation Si strain as a function of applied thermal pre-strain. In the experiment, Si strain is measured by ε Si = (L-λ) / λ, where L and λ are the surface and horizontal distance in the AFM surface profile.

圖51延伸測試(~εSt=4.0%)之循環後的魚骨狀波紋之光學顯微影像。以100nm厚之Si薄膜及3.8%之雙軸熱預加應變來製備測試樣本。魚骨狀 波紋在高達15次的延伸測試之循環之後恢復為具有與最初相當類似的結構，除了源自薄膜裂縫之一些缺陷。 Figure 51 Optical microscopic image of fishbone corrugations after the cycle of the extension test (~ ε St = 4.0%). Test samples were prepared with a 100 nm thick Si film and 3.8% biaxial thermal pre-strain. The fishbone corrugations recovered to a structure that was quite similar to the original after up to 15 cycles of extension testing, except for some defects originating from film cracks.

圖52對藉由應用單軸拉伸應變而進行的魚骨狀波紋之"展開"之示意性說明。壓縮應變εcp係歸因於在拉伸應變為εst之情況下的柏松效應(Poisson effect)。 Figure 52 is a schematic illustration of the "unfolding" of a fishbone corrugation by applying uniaxial tensile strain. The compressive strain ε cp is due to the Poisson effect in the case where the tensile strain is ε st .

圖53魚骨狀波紋在作為雙軸延伸測試之加熱及冷卻過程期間的形態改變之光學顯微影像。以100nm厚之Si薄膜及2.9%之雙軸熱預加應變來製備測試樣本。 Figure 53 Optical microscopic image of the morphological changes of the fishbone corrugations during the heating and cooling process as a biaxial extension test. The test sample was prepared with a 100 nm thick Si film and 2.9% biaxial thermal pre-strain.

圖54概述製造波狀可延伸電極之一方法，該方法係藉由於結構化波狀母體上沈積，隨後在彼母體上澆鑄一印模，使印模固化，且藉此在釋放後即將電極轉移至母體。 FIG. 54 outlines one method of manufacturing a corrugated extensible electrode by depositing on a structured corrugated body, and then casting a stamp on the other body to cure the stamp and thereby transferring the electrode after release To the mother.

圖55提供藉由圖4中之方法結合圖54中之方法而製備的在波狀PDMS上之可延伸金屬電極(Au，300nm厚)之影像。底部畫面為可延伸波狀金屬電極的作為所施加之拉伸應變(高達30%)之函數的量測得之電阻資料之圖。 FIG. 55 provides an image of an extensible metal electrode (Au, 300 nm thick) on a corrugated PDMS prepared by the method in FIG. 4 combined with the method in FIG. 54. The bottom panel is a graph of the measured resistance data of the extensible corrugated metal electrode as a function of the applied tensile strain (up to 30%).

圖56為本發明之方法用於製造可撓性可延伸iLED條帶照明燈之應用之實例。A為說明設備能夠大程度地撓曲之設備的顯微相片，且在此實例中撓曲半徑為0.85cm。B提供波狀PDMS基板上之可延伸金屬之橫截面圖(頂部畫面，定標線條為40μm)及俯視圖(底部畫面，定標線條為3mm)。金屬能夠延伸約30%而無物理特性之顯著降級。C為局部應變對PDMS上之正弦波狀金屬互連(展示於B中)之波長(方塊，左側軸)及振幅(圓形，右側軸)的影響之圖。隨著應變增大，存在金屬之波長之相應增大及金屬之振幅的相應減小。 Fig. 56 is an example of the application of the method of the present invention for manufacturing a flexible and extensible iLED strip lighting lamp. A is a photomicrograph of a device illustrating that the device can flex to a large extent, and in this example, the radius of deflection is 0.85 cm. B provides a cross-sectional view of the extensible metal on the corrugated PDMS substrate (top picture, calibration line is 40 μm) and top view (bottom picture, calibration line is 3 mm). The metal can extend about 30% without significant degradation of physical properties. C is a graph of the effect of local strain on the wavelength (square, left axis) and amplitude (circle, right axis) of sinusoidal metal interconnects (shown in B) on PDMS. As the strain increases, there is a corresponding increase in the wavelength of the metal and a corresponding decrease in the amplitude of the metal.

圖57對用以得到異質三維電子元件之基於印刷半導體奈米材料之方法的示意性說明。該製程涉及獨立地形成於源基板上之奈米管、奈米線、奈米織帶或其他活性奈米材料之集合向共用設備基板的重複轉印以產生超薄多層堆疊幾何形狀的互連電子元件。 FIG. 57 is a schematic illustration of a method of printing semiconductor nanomaterials used to obtain heterogeneous three-dimensional electronic components. This process involves the repeated transfer of a collection of nanotubes, nanowires, nanoribbons, or other active nanomaterials independently formed on the source substrate to a common device substrate to produce interconnected electrons of ultra-thin multilayer stack geometry element.

圖58(A)對於半導體使用印刷矽奈米織帶之單晶矽金屬氧化物場效電晶體(MOSFET)之陣列之三維多層堆疊的光學顯微相片。此影像之底部(標有第一)、中部(標有第二)及頂部(標有第三)部分分別對應於設備之具有一個、二個及三個層之區域。(B)示意性橫截面圖(頂部)及傾斜圖(底部)。S、D及G分別指代源極、汲極及閘極電極(均以金色而展示)。亮藍及暗藍區域對應於矽織帶之摻雜及未摻雜區域；紫色層為SiO2閘極介電質。(C)於如(A)及(B)中所示之設備基板的設備基板上藉由共焦顯微法而收集之三維影像(左側圖框：俯視圖；右側圖框：傾斜圖)。對層進行著色(金色：頂層；紅色：中部層；藍色：底層；矽：灰色)以易於觀察。(D)該等層中之每一者中的Si MOSFET之電流-電壓特徵，其展示極佳效能(470±30cm2/Vs之遷移率)及特性之良好均勻性。通道長度及寬度分別為19及200μm。 Fig. 58 (A) is an optical micrograph of a three-dimensional multilayer stack of a single crystal silicon metal oxide field effect transistor (MOSFET) array using printed silicon nanoribbons for semiconductors. The bottom (marked first), middle (marked second), and top (marked third) portions of this image correspond to areas of the device with one, two, and three layers, respectively. (B) Schematic cross-sectional view (top) and oblique view (bottom). S, D, and G refer to the source, drain, and gate electrodes, respectively (all shown in gold). The bright blue and dark blue regions correspond to the doped and undoped regions of the silicon ribbon; the purple layer is SiO 2 gate dielectric. (C) Three-dimensional images collected by confocal microscopy on the device substrate as shown in (A) and (B) (left frame: top view; right frame: oblique view). Color the layers (gold: top layer; red: middle layer; blue: bottom layer; silicon: gray) for easy observation. (D) The current-voltage characteristics of the Si MOSFET in each of these layers, which show excellent performance (mobility of 470 ± 30 cm 2 / Vs) and good uniformity of characteristics. The channel length and width are 19 and 200 μm, respectively.

圖59(A)三層堆疊之三維異質式電子設備的光學顯微相片，該等電子設備包括GaN奈米織帶HEMT、Si奈米織帶MOSFET及SWNT網路TFT。(B)藉由共焦顯微法而收集之三維影像。對層進行著色(金色：頂層，Si MOSFET；紅色：中部層，SWNT TFT；藍色：底層)以易於觀察。(C)第一層上之GaN設備(通道長度、寬度及閘極寬度分別為20μm、170μm及5μm)、第二層上之SWNT設備(通道長度及寬度分別為50μm及200μm)及第三層上之Si設備(通道長度及寬度分別為19μm及200μm)的電特徵。 (D)每一層中之設備的作為塑膠基板之撓曲半徑之函數的正規化轉導(gm/g0m)(黑色方塊：Si MOSFET；紅色圓形：SWNT TFT；綠色三角：GaN HEMT)(左側)。撓曲系統及探測裝置之影像(右側)。 Figure 59 (A) Optical micrographs of three-layer stacked three-dimensional heterogeneous electronic devices including GaN nanoribbon HEMT, Si nanoribbon MOSFET and SWNT network TFT. (B) Three-dimensional images collected by confocal microscopy. The layers are colored (gold: top layer, Si MOSFET; red: middle layer, SWNT TFT; blue: bottom layer) for easy observation. (C) GaN device on the first layer (channel length, width and gate width are 20μm, 170μm and 5μm respectively), SWNT device on the second layer (channel length and width are 50μm and 200μm respectively) and the third layer The electrical characteristics of the Si device (channel length and width are 19μm and 200μm respectively). (D) Normalized transduction ( gm / g0m ) of the devices in each layer as a function of the deflection radius of the plastic substrate (black square: Si MOSFET; red circle: SWNT TFT; green triangle: GaN HEMT) (left ). Images of the flexure system and detection device (right side).

圖60(A)聚醯亞胺基板上之3維矽NMOS反相器之印刷陣列之影像。反相器由藉由電通道結構互連之兩個不同級上之MOSFET(通道長度為4μm，負載與驅動器寬度比為6.7且驅動器寬度為200μm)組成。右上部之影像提供藉由左側圖框中之紅色框指示之區域的放大視圖。右下部之曲線圖展示典型反相器之轉移特徵。(B)使用p通道SWNT TFT(通道長度及寬度分別為30μm及200μm)及n通道Si MOSFET(通道長度及寬度分別為75μm及50μm)之印刷互補反相器之轉移特徵。插圖提供反相器之光學顯微相片(左側)及電路示意圖(右側)。(C)與Si MOSFET(通道長度及寬度分別為9μm及200μm)整合之GaAs MSM(通道長度及寬度分別為10μm及100μm)在藉由紅外光源以850nm而照射的自黑暗至11μW之不同位準處之電流-電壓回應。插圖展示光學影像及電路圖。 Figure 60 (A) Image of a printed array of 3D silicon NMOS inverters on a polyimide substrate. The inverter consists of two MOSFETs on different stages interconnected by an electrical channel structure (channel length is 4 μm, load to driver width ratio is 6.7 and driver width is 200 μm). The upper right image provides an enlarged view of the area indicated by the red box on the left. The lower right graph shows the transfer characteristics of a typical inverter. (B) Transfer characteristics of printed complementary inverters using p-channel SWNT TFT (channel length and width of 30 μm and 200 μm, respectively) and n-channel Si MOSFET (channel length and width of 75 μm and 50 μm, respectively). The illustration provides the optical micrograph of the inverter (left side) and the circuit schematic (right side). (C) GaAs MSM integrated with Si MOSFET (channel length and width of 9 μm and 200 μm, respectively) (channel length and width of 10 μm and 100 μm, respectively) at different levels from dark to 11 μW irradiated by infrared light source at 850 nm Current-voltage response. Illustrations show optical images and circuit diagrams.

圖61用於轉印、能夠重合至~1μm內的自動台之影像。 Figure 61 is an image of an automatic stage that can be transferred to ~ 1μm for transfer.

圖62(A)聚醯亞胺基板上之Si MOSFET及GaN HEMT之三維異質整合陣列的光學顯微相片。右側插圖展示橫截面示意圖。電極(金色)、SiO2(PEO；紫色)、Si(亮藍：未摻雜；暗藍：摻雜)、GaN(暗綠：歐姆接觸點；亮綠：通道)、聚醯亞胺(PI；褐色)及聚胺基甲酸酯(PU；淺棕色)均得以展示。(B)典型Si MOSFET(通道長度及寬度分別為19μm及200μm)及GaN HEMT(通道長度、寬度及閘極寬度分別為20μm、170μm及5μm)之電流-電壓特徵。分別在Vdd=0.1V及Vdd=2V下量測左側圖框中關於Si及GaN之資料。 Fig. 62 (A) Optical micrograph of a three-dimensional hetero-integrated array of Si MOSFET and GaN HEMT on a polyimide substrate. The illustration on the right shows a schematic cross-section. Electrode (gold), SiO 2 (PEO; purple), Si (bright blue: undoped; dark blue: doped), GaN (dark green: ohmic contact; bright green: channel), polyimide (PI ; Brown) and polyurethane (PU; light brown) were displayed. (B) Current-voltage characteristics of typical Si MOSFET (channel length and width are 19 μm and 200 μm) and GaN HEMT (channel length, width and gate width are 20 μm, 170 μm and 5 μm, respectively). Measure the data about Si and GaN in the left frame at V dd = 0.1V and V dd = 2V respectively.

圖63(A)聚醯亞胺基板上之Si MOSFET及SWNT TFT之三維異質整合陣列的光學顯微相片。右側插圖展示橫截面示意圖。電極(金色)、環氧樹脂(青色)、SiO2(PEO；紫色)、Si(亮藍：未摻雜；暗藍：摻雜)、SWNT(灰色)、聚醯亞胺(PI；褐色)及固化聚醯亞胺(淺棕色)均得以展示。(B)典型SWNT TFT(通道長度及寬度分別為75μm及200μm)及典型Si MOSFET(閘極長度及通道寬度分別為19μm及200μm)之電流-電壓特徵。分別在Vdd=-0.5V及Vdd=0.1V下量測左側圖框中關於SWNT及Si之資料。 Figure 63 (A) Optical micrograph of a three-dimensional hetero-integrated array of Si MOSFET and SWNT TFT on a polyimide substrate. The illustration on the right shows a schematic cross-section. Electrode (golden), epoxy resin (cyan), SiO 2 (PEO; purple), Si (bright blue: undoped; dark blue: doped), SWNT (gray), polyimide (PI; brown) And cured polyimide (light brown) were displayed. (B) Current-voltage characteristics of a typical SWNT TFT (channel length and width of 75 μm and 200 μm, respectively) and a typical Si MOSFET (gate length and channel width of 19 μm and 200 μm, respectively). Measure the data about SWNT and Si in the left frame at V dd = -0.5V and V dd = 0.1V respectively.

圖64(A)聚醯亞胺基板上之Si MOSFET、SWNT TFT及GaN HEMT之三維異質整合陣列的橫截面示意性說明。(B)Si MOSFET(通道寬度=200μm，黑線：通道長度=9μm，紅色：14μm，綠色：19μm，藍色：24μm)中之若干者的轉移特徵、有效遷移率及開關比，(C)SWNT TFT(通道寬度=200μm，黑線：通道長度=25μm，紅色：50μm，綠色：75μm，藍色：100μm)之轉移特徵、有效遷移率及開關比及(D)GaN HEMT(通道長度、寬度及閘極寬度分別為20μm、170μm及5μm)之轉移特徵、轉導及開關比。 Fig. 64 (A) is a schematic illustration of a cross-section of a three-dimensional hetero-integrated array of Si MOSFET, SWNT TFT, and GaN HEMT on a polyimide substrate. (B) Transfer characteristics, effective mobility and switching ratio of several of Si MOSFETs (channel width = 200 μm, black line: channel length = 9 μm, red: 14 μm, green: 19 μm, blue: 24 μm), (C) SWNT TFT (channel width = 200 μm, black line: channel length = 25 μm, red: 50 μm, green: 75 μm, blue: 100 μm) transfer characteristics, effective mobility and switching ratio and (D) GaN HEMT (channel length, width And gate width of 20μm, 170μm and 5μm respectively) transfer characteristics, transduction and switching ratio.

圖65(A)建立於矽晶圓基板上之SWNT-Si CMOS反相器的橫截面之示意結構。(B)形成CMOS反相器之n通道Si MOSFET及p通道SWNT TFT之轉移特徵及I-V特徵。(C)反相器之計算而得之轉移特徵及Si與SWNT電晶體之I-V特徵。 Figure 65 (A) Schematic structure of a cross-section of a SWNT-Si CMOS inverter built on a silicon wafer substrate. (B) Transfer characteristics and I-V characteristics of n-channel Si MOSFET and p-channel SWNT TFT forming a CMOS inverter. (C) The calculated transfer characteristics of the inverter and the I-V characteristics of Si and SWNT transistors.

圖66(A)建立於聚醯亞胺基板上之GaAs MSM-Si MOSFET IR偵測器的橫截面之示意結構及電路示意圖。(B)GaAs MSM IR偵測器(L=10μm，W=100μm)之電流-電壓特徵及Si MOSFET(L=9μm，w=200μm)在 3V電源的情況下之轉移特徵及I-V特徵。(C)GaAs MSM之計算而得之IV特徵及與Si MOSFET整合之GaAs MSM在3V電源的情況下之I-V回應。 Fig. 66 (A) Schematic structure and circuit diagram of the cross-section of a GaAs MSM-Si MOSFET IR detector built on a polyimide substrate. (B) Current-voltage characteristics of GaAs MSM IR detector (L = 10μm, W = 100μm) and Si MOSFET (L = 9μm, w = 200μm) Transfer characteristics and I-V characteristics in the case of 3V power supply. (C) The calculated IV characteristics of GaAs MSM and the I-V response of GaAs MSM integrated with Si MOSFET under 3V power supply.

"互連"指代能夠與組件建立電連接或在組件之間建立電連接之導電材料。特定言之，互連可在分離及/或可相對於彼此移動之組件之間建立電接觸。視所要設備規格、操作及應用而定，互連由合適材料製成。對於需要高傳導性之應用而言，可使用典型互連金屬，包括(但不限於)銅、銀、金、鋁及其類似物、合金。合適傳導材料可包括如矽、氧化銦錫或GaAs之半導體。"半導體"指代於非常低之溫度下為絕緣體，但在約300克耳文之溫度下具有明顯電導率之任何材料。在本描述中，對術語半導體之使用意欲與在微電子及電子設備之技術中對此術語之使用相一致。在本發明中有用之半導體可包含元素半導體，諸如矽、鍺及金剛石，以及化合物半導體，諸如：諸如SiC及SiGe之第IV族化合物半導體、諸如AlSb、AlAs、Aln、AlP、BN、GaSb、GaAs、GaN、GaP、InSb、InAs、InN及InP之第III-V族半導體、諸如AlxGa1-xAs之第III-V族三元化合物半導體合金、諸如CsSe、CdS、CdTe、ZnO、ZnSe、ZnS及ZnTe之第II-VI族半導體、第I-VII族半導體CuCl、諸如PbS、PbTe及SnS之第IV-VI族半導體、諸如Pbl2、MoS2及GaSe之層狀半導體及諸如CuO及Cu2O之氧化物半導體。術語半導體包括本徵半導體及非本徵半導體，該等非本徵半導體摻有一或多種選定材料(包括具有p型摻雜材料及n型摻雜材料之半導體)以提供對給定應用或設備有用之有益電子特性。術語半導體包括包含半導體及/或摻雜劑之混合物的複合材料。在本發明之一些應用中有用之特定半導體材料包括(但不限於)Si、Ge、SiC、AlP、AlAs、AlSb、GaN、GaP、 GaAs、GaSb、InP、InAs、GaSb、InP、InAs、InSb、ZnO、ZnSe、ZnTe、CdS、CdSe、ZnSe、ZnTe、CdS、CdSe、CdTe、HgS、PbS、PbSe、PbTe、AlGaAs、AlInAs、AlInP、GaAsP、GaInAs、GaInP、AlGaAsSb、AlGaInP及GaInAsP。多孔矽半導體材料對於本發明在感應器及發光材料(諸如發光二極體(LED)及固態雷射)之領域中的應用為有用的。半導體材料之雜質為除半導體材料自身或提供至半導體材料之任何摻雜劑以外之原子、元素、離子及/或分子。雜質為存在於半導體材料中的可能消極地影響半導體材料之電子特性之不合需要的材料，且包括(但不限於)氧、碳及包括重金屬之金屬。重金屬雜質包括(但不限於)週期表上處於銅與鉛之間的族之元素、鈣、鈉及其所有離子、化合物及/或錯合物。 "Interconnect" refers to a conductive material that can establish an electrical connection with components or between components. In particular, interconnects can establish electrical contact between components that are separate and / or can move relative to each other. Depending on the required equipment specifications, operation and application, the interconnection is made of suitable materials. For applications requiring high conductivity, typical interconnect metals can be used, including (but not limited to) copper, silver, gold, aluminum, and the like, alloys. Suitable conductive materials may include semiconductors such as silicon, indium tin oxide, or GaAs. "Semiconductor" refers to any material that is an insulator at a very low temperature, but has significant electrical conductivity at a temperature of about 300 grams. In this description, the use of the term semiconductor is intended to be consistent with the use of this term in the technology of microelectronics and electronic devices. Semiconductors useful in the present invention may include elemental semiconductors such as silicon, germanium and diamond, and compound semiconductors such as: Group IV compound semiconductors such as SiC and SiGe, such as AlSb, AlAs, Aln, AlP, BN, GaSb, GaAs , GaN, GaP, InSb, InAs, InN, and InP Group III-V semiconductors, such as Al x Ga 1-x As, Group III-V ternary compound semiconductor alloys, such as CsSe, CdS, CdTe, ZnO, ZnSe , Group II-VI semiconductors of ZnS and ZnTe, Group I-VII semiconductors CuCl, Group IV-VI semiconductors such as PbS, PbTe and SnS, layered semiconductors such as Pbl 2 , MoS 2 and GaSe and layered semiconductors such as CuO and Cu 2 O oxide semiconductor. The term semiconductor includes intrinsic semiconductors and extrinsic semiconductors, which are doped with one or more selected materials (including semiconductors with p-type doped materials and n-type doped materials) to provide usefulness for a given application or device Beneficial electronic properties. The term semiconductor includes composite materials including a mixture of semiconductors and / or dopants. Specific semiconductor materials useful in some applications of the present invention include (but are not limited to) Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs, AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP and GaInAsP. Porous silicon semiconductor materials are useful for the application of the invention in the field of sensors and light-emitting materials such as light-emitting diodes (LEDs) and solid-state lasers. Impurities in semiconductor materials are atoms, elements, ions, and / or molecules other than the semiconductor material itself or any dopants provided to the semiconductor material. Impurities are undesirable materials present in semiconductor materials that may negatively affect the electronic properties of the semiconductor materials, and include (but are not limited to) oxygen, carbon, and metals including heavy metals. Heavy metal impurities include (but are not limited to) elements of the group on the periodic table between copper and lead, calcium, sodium and all their ions, compounds and / or complexes.

"可延伸"之互連在本文中用以廣泛地指代能夠經受在一或多個方向上的諸如延伸、撓曲及/或壓縮之多種力及應變而不會有害地影響至設備組件之電連接或自設備組件之電導的互連。因此，可延伸互連可由諸如GaAs之相對脆性之材料形成，然而歸因於互連之幾何組態而即使在曝露於顯著變形力(例如，延伸、撓曲、壓縮)下時仍能夠持續起作用。在一例示性實施例中，可延伸互連可經受大於約1%、10%或約30%之應變而不斷裂。在一實例中，藉由使互連之至少一部分所結合至之下伏彈性體基板延伸而產生應變。 "Extensible" interconnection is used herein to broadly refer to the ability to withstand various forces and strains in one or more directions, such as extension, deflection, and / or compression, without adversely affecting equipment components Electrical connection or interconnection of conductance from equipment components. Therefore, extensible interconnects can be formed from relatively brittle materials such as GaAs, however, due to the geometric configuration of the interconnects, they can continue to sustain even when exposed to significant deformation forces (eg, extension, deflection, compression) effect. In an exemplary embodiment, the extensible interconnect can withstand strains greater than about 1%, 10%, or about 30% without breaking. In one example, strain is generated by extending at least a portion of the interconnect to the underlying elastomeric substrate.

使用"設備組件"以廣泛地指代電氣設備內之個別組件。組件可為光電二極體、LED、TFT、電極、半導體、其他光收集/偵測組件、電晶體、積體電路、能夠收納設備組件之接觸焊墊、薄膜設備、電路元件、控制元件、微處理器、傳感器及其組合中之一或多者。如諸如金屬蒸鍍、導 線結合、固體或導電膏之施加的技術中所已知，設備組件可連接至一或多個接觸焊墊。電氣設備一般指代併有複數個設備組件之設備，且包括較大面積之電子元件、印刷線路板、積體電路、設備組件陣列、生物及/或化學感應器、物理感應器(例如，溫度、光、輻射等等)、太陽能電池或光伏打陣列、顯示器陣列、集光器、系統及顯示器。 "Equipment components" are used to refer broadly to individual components within electrical equipment. Components can be photodiodes, LEDs, TFTs, electrodes, semiconductors, other light collection / detection components, transistors, integrated circuits, contact pads that can hold equipment components, thin film equipment, circuit components, control components, micro One or more of processors, sensors, and combinations thereof. Such as metal evaporation, guide Known in the art of wire bonding, solid or conductive paste application, device components can be connected to one or more contact pads. Electrical equipment generally refers to equipment that includes multiple equipment components and includes larger area electronic components, printed circuit boards, integrated circuits, equipment component arrays, biological and / or chemical sensors, physical sensors (eg, temperature , Light, radiation, etc.), solar cells or photovoltaic arrays, display arrays, light collectors, systems and displays.

"基板"指代具有能夠支撐包括設備組件或互連之組件之表面的材料。"結合"至基板之互連指代互連之與基板處於實體接觸且實質上不能夠相對於所結合至之基板表面移動的部分。相反，未結合之部分能夠相對於基板作顯著移動。互連之未結合部分一般對應於(諸如)藉由應變誘發之互連撓曲而具有"撓曲組態"之部分。 "Substrate" refers to a material having a surface capable of supporting components including device components or interconnects. Interconnect "bonded" to a substrate refers to the portion of the interconnect that is in physical contact with the substrate and is essentially unable to move relative to the surface of the substrate to which it is bonded. On the contrary, the unbonded part can move significantly relative to the substrate. The unbonded portion of the interconnect generally corresponds to, for example, a portion that has a "flex configuration" by strain-induced interconnect deflection.

在此描述之上下文中，"撓曲組態"指代具有由力之施加所導致之彎曲構形之結構。在本發明中，撓曲結構可具有一或多個摺疊區域、凸起區域、凹入區域及其任何組合。舉例而言，可以捲曲構形、起皺構形、彎曲構形及/或波狀(亦即，波紋狀)組態而提供在本發明中有用之撓曲結構。 In the context of this description, "flexure configuration" refers to a structure that has a curved configuration caused by the application of force. In the present invention, the flexure structure may have one or more folding regions, convex regions, concave regions, and any combination thereof. For example, a flexure structure useful in the present invention can be provided in a crimped configuration, a corrugated configuration, a curved configuration, and / or a wavy (ie, corrugated) configuration.

諸如可延伸撓曲互連之撓曲結構可以撓曲結構處於應變下之構形而結合至諸如聚合物及/或彈性基板之可撓性基板。在一些實施例中，諸如撓曲織帶結構之撓曲結構處於等於或小於約30%之應變下、等於或小於約10%之應變下、等於或小於約5%之應變下，且在對於一些應用為較佳之實施例中，處於等於或小於約1%之應變下。在一些實施例中，諸如撓曲織帶結構之撓曲結構處於自約0.5%至約30%之範圍中選擇之應變下、自約0.5%至約10%之範圍中選擇的應變下、自約0.5%至約5%之範圍中選擇之應變下。或者，可延伸撓曲互連可結合至係設備組件之基板的基板，該基板包括自身非可撓性之基板。基板自身可為平坦、大體上平坦、彎曲、具 有銳緣或其任何組合。可延伸撓曲互連可用於轉移至此等複雜基板表面形狀中之任何一或多者。 A flexure structure such as an extensible flexure interconnect may be bonded to a flexible substrate such as a polymer and / or elastic substrate in a configuration where the flexure structure is under strain. In some embodiments, a flexure structure such as a flexure webbing structure is under a strain equal to or less than about 30%, a strain equal to or less than about 10%, a strain equal to or less than about 5%, and In a preferred embodiment, the application is at a strain equal to or less than about 1%. In some embodiments, a flexure structure, such as a flexure web structure, is under a strain selected from the range of about 0.5% to about 30%, a strain selected from the range of about 0.5% to about 10%, from about Under strain selected in the range of 0.5% to about 5%. Alternatively, the extensible flex interconnect can be bonded to a substrate that is the substrate of the device assembly, the substrate including its own non-flexible substrate. The substrate itself can be flat, substantially flat, curved, There are sharp edges or any combination thereof. Extensible flex interconnects can be used to transfer to any one or more of these complex substrate surface shapes.

互連可具有任何數目之幾何形狀或形狀，只要該幾何形狀或形狀促進互連在不破裂之情況下的撓曲或延伸即可。可將一般互連幾何形狀描述為"彎曲"或"波狀"。在一態樣中，可由藉由對下伏可變形基板施加力以使得下伏基板之尺寸的改變在互連中產生彎曲或波紋(因為互連之部分結合至基板，且結合部分之間的區域未結合)而對互連施加力(例如，應變)來獲得彼幾何形狀。因此，可藉由結合至基板之末端及末端之間未與基板結合之彎曲中央部分來界定個別互連。"彎曲"指代相對複雜之形狀，諸如對於在中央部分具有一或多個額外結合區域之互連之情況。"弧狀"指代具有振幅之一般呈正弦之形狀，其中振幅對應於互連與基板表面之間的最大分離距離。 The interconnect may have any number of geometries or shapes as long as the geometry or shape promotes flexing or extension of the interconnect without breaking. The general interconnection geometry can be described as "curved" or "wavy". In one aspect, by applying a force to the underlying deformable substrate such that the change in the size of the underlying substrate produces bending or ripples in the interconnect (because the interconnected portion is bonded to the substrate, and the The areas are not joined) and apply a force (eg, strain) to the interconnect to obtain the other geometry. Therefore, individual interconnections can be defined by bonding to the ends of the substrate and the curved central portion between the ends that is not bonded to the substrate. "Curved" refers to relatively complex shapes, such as for interconnections with one or more additional bonding areas in the central portion. "Arc" refers to a generally sinusoidal shape with an amplitude, where the amplitude corresponds to the maximum separation distance between the interconnect and the substrate surface.

互連可具有任何橫截面形狀。一形狀之互連為織帶狀互連。"織帶"指代具有厚度及寬度的大體上呈矩形形狀之橫截面。特定尺寸視經由互連之所要傳導性、互連之組成及使鄰近設備組件電連接之互連的數目而定。舉例而言，使鄰近組件連接之橋接組態的互連可具有與使鄰近組件連接之單一互連不同之尺寸。因此，只要產生合適電導率，尺寸可具有任何合適值，諸如在約10μm與1cm之間的寬度及在約50nm與1nm之間的厚度，或者在約0.001與0.1之間的範圍內之寬度厚度比，或約為0.01之比。 The interconnect may have any cross-sectional shape. The interconnection of a shape is a ribbon-like interconnection. "Webbing" refers to a generally rectangular cross-section with thickness and width. The specific size depends on the desired conductivity through the interconnect, the composition of the interconnect, and the number of interconnects that electrically connect adjacent device components. For example, the interconnection of the bridge configuration connecting adjacent components may have a different size than the single interconnection connecting adjacent components. Therefore, as long as a suitable conductivity is produced, the size may have any suitable value, such as a width between about 10 μm and 1 cm and a thickness between about 50 nm and 1 nm, or a width thickness in the range between about 0.001 and 0.1 Ratio, or about 0.01 ratio.

"彈性體"指代可延伸或變形且至少部分地返回其原始形狀而無顯著永久變形之聚合材料。彈性體基板通常經受實質上之彈性變形。在本發明中有用之例示性彈性體基板包括(但不限於)彈性體及彈性體之複合材料或混合物，以及顯示出彈性之聚合物及共聚物。在一些方法中，經由沿一或 多個主軸提供彈性基板之擴展之機構來對彈性體基板預加應變。舉例而言，可藉由使彈性基板沿第一軸擴展(包括用以將半球形表面變換為平坦表面的在徑向方向上之擴展)而提供預加應變。或者，可沿複數個軸來擴展彈性基板(例如經由沿相對於彼此正交定位之第一與第二軸的擴展)。經由提供彈性基板之擴展之機構而對彈性基板預加應變的手段包括撓曲、捲繞、折曲、平整、擴展彈性基板或以其他方式使彈性基板變形。預加應變之手段亦包括藉由升高彈性基板之溫度，藉此提供彈性基板之熱膨脹而提供之預加應變。在本發明中有用之彈性體可包括(但不限於)熱塑性彈性體、苯乙烯類材料、烯烴材料、聚烯烴、聚胺基甲酸酯熱塑性彈性體、聚醯胺、合成橡膠、PDMS、聚丁二烯、聚異丁烯、聚(苯乙烯-丁二烯-苯乙烯)、聚胺基甲酸酯、聚氯丁烯及聚矽氧。 "Elastomer" refers to a polymeric material that can extend or deform and at least partially return to its original shape without significant permanent deformation. Elastomer substrates generally undergo substantial elastic deformation. Exemplary elastomer substrates useful in the present invention include, but are not limited to, elastomers and composite materials or mixtures of elastomers, as well as polymers and copolymers that exhibit elasticity. In some methods, the Multiple spindles provide an expansion mechanism for the elastic substrate to pre-strain the elastomer substrate. For example, the pre-strain can be provided by expanding the elastic substrate along the first axis (including expansion in the radial direction to transform the hemispherical surface into a flat surface). Alternatively, the elastic substrate may be expanded along multiple axes (eg, via expansion along first and second axes orthogonally positioned relative to each other). Means for pre-straining the elastic substrate by providing a mechanism for expansion of the elastic substrate include flexing, winding, bending, flattening, expanding the elastic substrate, or otherwise deforming the elastic substrate. The means of pre-straining also includes pre-straining provided by increasing the temperature of the elastic substrate, thereby providing thermal expansion of the elastic substrate. Elastomers useful in the present invention may include, but are not limited to, thermoplastic elastomers, styrenic materials, olefin materials, polyolefins, polyurethane thermoplastic elastomers, polyamides, synthetic rubbers, PDMS, poly Butadiene, polyisobutylene, poly (styrene-butadiene-styrene), polyurethane, polychloroprene and polysiloxane.

將對於長度自L(處於靜止)變為L+△L(在所施加之力下)之應變界定為：ε=△L/L，其中△L為自靜止之移位距離。軸向應變指代施加至基板之軸以產生移位△L之力。亦藉由在其他方向上施加之力來產生應變，諸如撓曲力、壓縮力、剪切力及其任何組合。亦可藉由將彎曲表面延伸為平坦表面或是相反過程來產生應變或壓縮。 The strain for changing the length from L (at rest) to L + △ L (under applied force) is defined as: ε = △ L / L, where △ L is the displacement distance from self-rest. Axial strain refers to the force applied to the axis of the substrate to produce a displacement of ΔL. Strain is also generated by forces applied in other directions, such as deflection force, compression force, shear force, and any combination thereof. Strain or compression can also be generated by extending the curved surface to a flat surface or vice versa.

"楊氏模數(Young's modulus)"為材料、設備或層之機械特性，其指代對於給定物質，應力與應變之比。楊氏模數可由以下表達式提供； "Young's modulus" is the mechanical property of a material, device, or layer, which refers to the ratio of stress to strain for a given substance. Young's modulus can be provided by the following expression;

其中E為楊氏模數，L0為平衡長度，△L為在所施加之應力下的長度改變，F為所施加之力且A為力所施加於之面積。亦可經由下式而以拉梅常數(Lame constant)來表達楊氏模數： Where E is the Young's modulus, L 0 is the equilibrium length, ΔL is the length change under the applied stress, F is the applied force and A is the area to which the force is applied. The Young's modulus can also be expressed in terms of Lame constant by the following formula:

其中λ及μ為拉梅彈性常數。高楊氏模數(或"高模數")及低楊氏模數(或"低模數")為對於給定材料、層或設備中之楊氏模數之量值的相對描述符。在本發明中，高楊氏模數大於低楊氏模數，對於一些應用較佳地大約10倍，對於其他應用更佳大約100倍且對於其他應用甚至更佳大約1000倍。藉由使具有空間變化之楊氏模數之彈性體聚合及/或藉由以在各個位置處具有不同彈性之多個層而使彈性體層化來獲得複雜表面形狀。 Where λ and μ are Lame elastic constants. High Young's modulus (or "high modulus") and low Young's modulus (or "low modulus") are relative descriptors for the magnitude of Young's modulus in a given material, layer, or device. In the present invention, the high Young's modulus is greater than the low Young's modulus, preferably about 10 times for some applications, about 100 times better for other applications and about 1000 times better for other applications. Complex surface shapes are obtained by polymerizing elastomers with spatially varying Young's modulus and / or by layering the elastomers with multiple layers having different elasticities at various locations.

壓縮在本文中以與應變類似之方式而使用，但特別指代用以減小基板之特徵性長度或體積之力，從而△L<0。 Compression is used in this article in a manner similar to strain, but specifically refers to the force used to reduce the characteristic length or volume of the substrate, such that ΔL <0.

"斷裂"指代互連中之實體破裂，其使得互連實質上不能夠導電。 "Fracture" refers to the rupture of an entity in an interconnect, which makes the interconnect substantially incapable of conducting electricity.

"結合位點之圖案"指代結合手段對支撐基板表面及/或對互連之空間應用，其使得所支撐之互連具有與基板之結合區域及未結合區域。舉例而言，於末端結合至基板且在中央部分未結合之互連。進一步之形狀控制藉由在中央部分中提供額外結合位點以使得未結合之區域被劃分為兩個不同的中央部分而為可能的。結合手段可包括黏著劑、黏著前驅物、熔接、光微影、光可固化聚合物。一般而言，結合位點可藉由多種技術而加以圖案化，且可在能夠提供基板與特徵(例如，互連)之間的強黏著力之表面活性(Wact)區域及黏著力相對較弱之表面非活性(Win)的方面加以描述。可在Wact與Win之尺寸方面描述以黏著方式圖案化成直線之基板。彼等變數連同預加應變之量值εpre影響互連幾何形狀。 The "pattern of bonding sites" refers to the application of bonding means to the surface of the supporting substrate and / or to the space of the interconnects, which enables the supported interconnects to have bonded and unbonded areas with the substrate. For example, an interconnect that is bonded to the substrate at the end and unbonded at the center. Further shape control is possible by providing additional binding sites in the central part so that the unbound area is divided into two different central parts. The bonding means may include adhesives, adhesive precursors, fusion bonding, photolithography, and photocurable polymers. Generally speaking, the binding site can be patterned by various techniques, and can be relatively strong in the surface active (W act ) region and adhesion that can provide strong adhesion between the substrate and the feature (eg, interconnection) Weak aspects of surface inactivity (W in ) are described. The substrate patterned into a straight line in an adhesive manner can be described in terms of the dimensions of W act and W in . These variables together with the magnitude of pre -strain ε pre affect the interconnect geometry.

藉由以下非限制性實例可進一步瞭解本發明。本文引用之所有參考文獻在不與隨附揭示內容不一致的程度上以引用方式併入本文中。雖然本文之描述含有許多特定細節，但此等特定細節不應解釋為限制本發明之範疇，而應解釋為僅僅提供對本發明之目前較佳的實施例中之一些之說明。 因此，本發明之範疇應由所附申請專利範圍及其等效物判定而非由給出之實例所判定。 The invention can be further understood by the following non-limiting examples. All references cited herein are incorporated by reference to the extent that they are inconsistent with the accompanying disclosure. Although the description herein contains many specific details, these specific details should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently preferred embodiments of the invention. Therefore, the scope of the present invention should be determined by the scope of the attached patent application and its equivalent rather than by the examples given.

圖1大體概述用於製造彎曲或波狀互連之一方法。在基板20上提供金屬特徵10(諸如將為互連之金屬特徵)。視情況可(諸如)藉由光微影或以蔽蔭遮罩而處理接觸金屬特徵及/或基板表面以減小黏著。諸如藉由微機械加工、蝕刻及/或機械雕合而在特徵10與基板20之間引入分隔物(裂縫)25。藉由柔性彈性體印模30取得金屬特徵10。印模30之後續變形在金屬特徵10中產生波狀或彎曲幾何形狀40。由在取得金屬特徵時處於應變下且隨後解除所施加之張力的印模30提供彎曲之產生，或藉由在取得金屬特徵之後壓縮印模30而提供彎曲之產生。 Figure 1 generally outlines one method for manufacturing curved or wavy interconnects. Metal features 10 (such as metal features that will be interconnected) are provided on the substrate 20. The contact metal features and / or substrate surface can be processed to reduce adhesion, such as by photolithography or with a shadow mask, as appropriate. A partition (crack) 25 is introduced between the feature 10 and the substrate 20, such as by micromachining, etching, and / or mechanical engraving. The metal feature 10 is obtained by the flexible elastomer stamp 30. The subsequent deformation of the stamp 30 produces a wavy or curved geometry 40 in the metal feature 10. The generation of bending is provided by the stamp 30 that is under strain when the metallic feature is acquired and then the applied tension is released, or by compressing the stamp 30 after acquiring the metallic feature.

圖2展示藉由圖1中所概述之方法而產生之彎曲或波狀金屬特徵之一實例。圖2為可延伸波狀/彎曲電互連40之相片，該電互連40係藉由自剛性基板取至經預加應變之可延伸PDMS橡膠基板30上，隨後解除應變，藉此誘發彎曲而形成。 FIG. 2 shows an example of curved or wavy metal features produced by the method outlined in FIG. 1. FIG. 2 is a photograph of an extensible corrugated / bent electrical interconnection 40, which is taken from a rigid substrate onto a pre-strained extensible PDMS rubber substrate 30, and then the strain is relieved to thereby induce bending While forming.

圖3中提供用於產生波狀可延伸電極及/或互連之方法。如圖3A所示，藉由(例如)微機械加工製程而在基板20上製備波狀特徵22。一表面具有波狀特徵22之基板20充當用於模製具有相應波狀表面32之彈性體印模30的母體。藉由(諸如)經由蔽蔭遮罩之蒸鍍及/或電鍍而在波狀表面32上沈積金屬特徵10。 A method for generating wavy extensible electrodes and / or interconnects is provided in FIG. 3. As shown in FIG. 3A, the wavy features 22 are prepared on the substrate 20 by, for example, a micro-machining process. A substrate 20 having a corrugated feature 22 on its surface serves as a matrix for molding an elastomer stamp 30 having a corresponding corrugated surface 32. The metal features 10 are deposited on the wavy surface 32 by, for example, evaporation and / or electroplating through a shadow mask.

圖4提供用於製造平滑波狀彈性體基板之一方法。各向異性Si(100)蝕刻提供具有銳緣24之基板20(圖4B-頂部畫面)。旋塗PR藉由在基板20之銳緣谷24中沈積PR 26而使銳緣谷平滑。抵靠基板20而澆鑄彈性體印模34。印模34具有銳緣凹入特徵。在印模34上澆鑄第二彈性體印模36以產生具 有銳緣峰之印模。以Su-8 50壓印印模36且在適當時使其固化。旋塗PR 26使50之銳緣谷平滑。抵靠具有平滑谷之50而澆鑄彈性體基板30。移除基板30以顯露波狀且平滑之表面32。 Figure 4 provides one method for manufacturing a smooth wavy elastomer substrate. Anisotropic Si (100) etching provides a substrate 20 with sharp edges 24 (FIG. 4B-top panel). Spin coating PR smoothes the sharp valley by depositing PR 26 in the sharp valley 24 of the substrate 20. The elastomer stamp 34 is cast against the substrate 20. The stamp 34 has a sharp edge concave feature. A second elastomer stamp 36 is cast on the stamp 34 to produce a tool There are impressions of sharp edge peaks. The stamp 36 is embossed with Su-8 50 and cured as appropriate. Spin coating PR 26 to smooth the sharp edge valley of 50. The elastomer substrate 30 is cast against the 50 with smooth valleys. The substrate 30 is removed to reveal the wavy and smooth surface 32.

圖54概述製造波狀可延伸電極之一方法：於波狀母體上沈積，隨後在彼母體上澆鑄一印模，使印模固化，且藉此在釋放後即將電極轉移至母體。圖55展示藉由圖4中之方法結合圖54中之方法而製備的在波狀PDMS上之可延伸金屬電極(Au，300nm厚)之影像。於金屬特徵10與基板20之間展示界面112。界面112可包含促進底部畫面中所說明的藉由印模30而進行的金屬特徵10之移除之材料。簡言之，一方法使用：於預清潔之2"×3"玻璃載片上旋塗SU-8 10之薄塗層以使得玻璃表面被完全覆蓋。使載片/SU-8與具有所要波狀表面特徵(平滑谷及陡峰)之PDMS印模接觸且輕柔施加壓力以使得所有氣穴經移除。在正面於UV燈下閃蒸固化印模/模結構歷時30秒，翻轉，且在背面固化額外之40秒。在固化之後，在熱板上於65℃下烘焙5分鐘。在烘焙之後，允許樣本冷卻至室溫，並將SU-8模自PDMS母體剝離。SU-8現將具有具有銳緣谷之波狀表面起伏。為了使此等谷趨於平滑，將一份SU-8 2與一份較薄之SU-8混合，且以高RPM而旋塗歷時90秒。曝露於UV燈下歷時20秒來固化且於65℃進行後烘焙歷時3分鐘。一旦冷卻，即經由電鍍、光微影及蝕刻/起離及/或經由蔽蔭遮罩之蒸鍍而沈積金屬線或接觸點。以MPTMS對SU-8上之金屬處理1小時，且接著抵靠其而澆鑄彈性體基板。在移除後，PDMS具有波狀表面起伏(其具有平滑之峰及谷)連同轉移之金屬結構。圖55為藉由圖54中概述之製程而製造之波狀可延伸電極之相片，且亦提供可延伸波狀金屬電極的作為所施加之拉伸應變(高達30%)之函數的量測而得之電阻資料。 Fig. 54 outlines one method of manufacturing a corrugated extensible electrode: depositing on a corrugated matrix, then casting a stamp on the matrix, curing the stamp, and transferring the electrode to the matrix after release. 55 shows an image of an extensible metal electrode (Au, 300 nm thick) on a corrugated PDMS prepared by the method in FIG. 4 combined with the method in FIG. 54. An interface 112 is shown between the metal feature 10 and the substrate 20. The interface 112 may include materials that facilitate the removal of the metal feature 10 by the stamp 30 as illustrated in the bottom panel. In short, one method is to use a thin coating of SU-8 10 on a pre-cleaned 2 "× 3" glass slide to completely cover the glass surface. The slide / SU-8 was brought into contact with a PDMS stamp with desired wavy surface features (smooth valleys and steep peaks) and gentle pressure was applied to allow all air pockets to be removed. The impression / mold structure was flash-cured under UV light on the front side for 30 seconds, turned over, and cured for an additional 40 seconds on the back side. After curing, it was baked on a hot plate at 65 ° C for 5 minutes. After baking, the sample was allowed to cool to room temperature, and the SU-8 mold was peeled from the PDMS matrix. SU-8 will now have undulating surface relief with sharp edge valleys. To smooth these valleys, one part of SU-8 2 was mixed with one part of thinner SU-8 and spin-coated at high RPM for 90 seconds. Exposure to UV lamp for 20 seconds to cure and post-baking at 65 ° C for 3 minutes. Once cooled, metal lines or contact points are deposited by electroplating, photolithography and etching / lifting and / or by vapor deposition of shadow masks. The metal on SU-8 was treated with MPTMS for 1 hour, and then an elastomer substrate was cast against it. After removal, the PDMS has undulating surface relief (which has smooth peaks and valleys) along with the transferred metal structure. FIG. 55 is a photograph of the wavy extensible electrode manufactured by the process outlined in FIG. 54 and also provides measurement of the extensible wavy metal electrode as a function of applied tensile strain (up to 30%) Obtained resistance information.

圖5提供藉由圖4中概述之方法而製造之平滑波狀PDMS基板30之一實例。設備組件60可於非波狀區域(例如，大體上平坦之部分)中支撐於波狀基板30且在需要時連接至互連10。 FIG. 5 provides an example of a smooth wave PDMS substrate 30 manufactured by the method outlined in FIG. 4. The device assembly 60 may be supported on the corrugated substrate 30 in a non-corrugated area (eg, a substantially flat portion) and connected to the interconnect 10 when needed.

圖6展示向銳緣谷或凹入特徵中旋塗平滑層之一實例。藉由旋塗光可固化環氧樹脂26而使銳緣基板34(圖6A)平滑來產生平滑波狀基板。藉由抵靠圖6B之基板澆鑄PDMS印模且隨後自基板34移除印模30而獲得具有平滑波狀表面32之彈性體(例如，PDMS)印模30。 Figure 6 shows an example of spin coating a smooth layer into a sharp valley or concave feature. A smooth wavy substrate is produced by smoothing the sharp-edged substrate 34 (FIG. 6A) by spin-coating the light-curable epoxy resin 26. An elastomer (eg, PDMS) stamp 30 having a smooth wavy surface 32 is obtained by casting a PDMS stamp against the substrate of FIG. 6B and then removing the stamp 30 from the substrate 34.

圖7為可延伸電極之相片。圖7A為具有波狀表面32之彈性體基板30的橫截面之相片。圖7B為藉由在波狀彈性體基板表面32上蒸鍍金屬10而製成之電極的俯視顯微相片。影像之焦平面處於波狀起伏之峰上。在圖7C中，焦平面處於波狀起伏之谷上且金屬互連10處於與電極250之電接觸中。藉由經由蔽蔭遮罩而蒸鍍至平滑波狀彈性體基板上來沈積可延伸電極。在此實例中，電極250在受張力而延伸至高達約10%的期間保持經由互連10之傳導性及連接性。 Figure 7 is a photograph of an extendable electrode. 7A is a photograph of a cross-section of an elastomer substrate 30 having a wavy surface 32. FIG. 7B is a top-view microphotograph of an electrode made by vapor-depositing metal 10 on the surface 32 of the corrugated elastomer substrate. The focal plane of the image is on the undulating peak. In FIG. 7C, the focal plane is on the undulating valley and the metal interconnection 10 is in electrical contact with the electrode 250. The extensible electrode is deposited by vapor deposition onto a smooth wavy elastomer substrate through a shadow mask. In this example, the electrode 250 maintains conductivity and connectivity through the interconnect 10 during the period of being stretched up to about 10% under tension.

本文揭示之方法及設備可用以製造多種電子設備，包括(例如)可延伸被動式矩陣LED顯示器(見圖8)。將波狀電極(例如，互連10及接觸焊墊70)圖案化於兩個彈性體基板30上。藉由轉印而將設備組件60(在此情況中為ILED像素)於接觸焊墊70處圖案化波狀電極上。相應地組裝兩個基板30以使得互連10以不同定向(在此實例中為垂直)而延行。圖9說明該被動式矩陣LED顯示器之2D機械可延伸性。除了能夠單軸及雙軸延伸以外，顯示器能夠顯著撓曲而不破裂。該多軸撓曲向彎曲表面提供模製電子設備之能力以製造彎曲電子設備且併入智慧電子織物或顯示器中。 The methods and devices disclosed herein can be used to manufacture a variety of electronic devices, including, for example, extendable passive matrix LED displays (see FIG. 8). The wavy electrodes (for example, the interconnect 10 and the contact pad 70) are patterned on the two elastomer substrates 30. The device component 60 (ILED pixel in this case) is patterned on the wavy electrode at the contact pad 70 by transfer. The two substrates 30 are assembled accordingly so that the interconnect 10 runs in different orientations (vertical in this example). FIG. 9 illustrates the 2D mechanical extensibility of the passive matrix LED display. In addition to being able to extend uniaxially and biaxially, the display can flex significantly without breaking. The multi-axis flexure provides the curved surface with the ability to mold electronic devices to manufacture curved electronic devices and is incorporated into smart electronic fabrics or displays.

彎曲電子設備之一該實例提供於圖10中。圖10說明包含分布於球面 彎曲透鏡上之無機光電二極體陣列之"人造眼"。展示人造陣列之四個不同視圖。圖11示意性地說明對於可延伸平坦電子設備之要求。為了圍繞球形表面而包繞平坦薄片，薄片必須在一個以上的方向上延伸。 One example of a curved electronic device is provided in FIG. Figure 10 illustrates the inclusion of distribution on the sphere The "artificial eye" of an inorganic photodiode array on a curved lens. Show four different views of the artificial array. Figure 11 schematically illustrates the requirements for extendable flat electronic devices. In order to wrap a flat sheet around a spherical surface, the sheet must extend in more than one direction.

圖12為用於製造能夠與彎曲表面相符之可延伸彎曲半導體陣列之製造機制。藉由在基板(諸如畫面(i)中所說明之"母晶圓")上之選擇性Au或Ti/Au沈積來製造薄Si元件。使Si結合至經預加應變(指示為L+△L)及UVO處理之PDMS(畫面(ii))。如所說明，在兩個方向上提供預加應變。該結合係藉由此項技術中已知之任何手段而進行，諸如(例如)塗覆至Si元件、基板或兩者之黏著劑。以選定圖案應用結合手段以使得Si具有將保持與基板之實體接觸(在變形之後)之結合區域及不與基板實體接觸之處於撓曲組態的其他區域(例如，相對於結合區域中之黏著力不結合或弱結合之區域)。自晶圓基板移除經預加應變之基板以顯露半導體陣列之平坦柵格(畫面(iii))。在將基板自L+△L鬆弛至L後，互連10即在弱結合之區域中彎曲(見畫面(iv))為撓曲組態，而設備組件60(例如，半導體Si接觸焊墊)仍保持結合至基板30。因此，彎曲互連10向整個陣列賦予可延伸性，且特定言之相對於其他組件60移動組件60之能力。不破壞組件60之間的電接觸而藉此向彎曲表面或可撓曲表面提供保形能力。 FIG. 12 is a manufacturing mechanism for manufacturing an extensible curved semiconductor array that can conform to a curved surface. Thin Si devices are manufactured by selective Au or Ti / Au deposition on a substrate such as the "mother wafer" illustrated in screen (i). Si is bonded to PDMS (picture (ii)) pre-strained (indicated as L + ΔL) and UVO treated. As illustrated, pre-strain is provided in both directions. The bonding is performed by any means known in the art, such as, for example, an adhesive applied to the Si device, substrate, or both. Apply bonding means in a selected pattern so that Si has bonding areas that will maintain physical contact with the substrate (after deformation) and other areas in a flexed configuration that do not physically touch the substrate (e.g., adhesion to the bonding area Areas where the force is not combined or weakly combined). The pre-strained substrate is removed from the wafer substrate to reveal the flat grid of the semiconductor array (picture (iii)). After the substrate is relaxed from L + ΔL to L, the interconnect 10 is bent in the weakly bonded area (see screen (iv)) into a flexure configuration, while the device component 60 (eg, semiconductor Si contact pad) remains Keep bonding to the substrate 30. Therefore, the curved interconnect 10 imparts extensibility to the entire array, and specifically the ability to move the component 60 relative to other components 60. The electrical contact between the components 60 is not disrupted thereby providing shape retention to the curved or flexible surface.

圖13提供採取單一柵格組態140(頂部兩幅畫面)、具有複數個連接之互連160的柵格組態(左下部畫面)及花形組態150(右下部畫面)之彎曲可延伸矽陣列之光學顯微影像。在此等實例中之每一者中，互連10在中央部分中彎曲，互連末端附接至接觸焊墊70。互連及接觸焊墊70支撐於PDMS基板30上。圖14至圖17進一步提供許多不同互連幾何形狀之特寫視圖。圖14提供電子顯微影像以展示具有中央部分90連同第一末端100及第二末端 110之基本彎曲或波狀互連10。中央部分採取撓曲組態。末端100及110連接至設備組件(在此情況下為接觸焊墊70)，從而能夠建立與設備組件之電接觸。互連10及接觸焊墊70支撐於諸如彈性體PDMS基板之基板30上。 Fig. 13 provides curved stretchable silicon with a single grid configuration 140 (top two pictures), a grid configuration with multiple interconnections 160 (lower left picture) and a flower configuration 150 (lower right picture) Optical microscopic image of the array. In each of these examples, the interconnect 10 is bent in the central portion, and the interconnect end is attached to the contact pad 70. The interconnection and contact pads 70 are supported on the PDMS substrate 30. Figures 14 to 17 further provide close-up views of many different interconnect geometries. FIG. 14 provides an electron microscopic image to show the central portion 90 together with the first end 100 and the second end 110 的 basically curved or wavy interconnection 10. The central part adopts the flexure configuration. The ends 100 and 110 are connected to the device component (in this case the contact pad 70), so that electrical contact with the device component can be established. The interconnect 10 and the contact pad 70 are supported on a substrate 30 such as an elastomer PDMS substrate.

圖15為藉由複數個(兩個)互連160彼此連接之鄰近設備組件(例如，接觸焊墊70)之電子顯微影像。圖15與圖14比較論證了可藉由一或多個互連10來使設備組件70彼此連接以向電子設備提供額外可撓性。舉例而言，具有相對較大之佔據面積之設備組件或接觸焊墊70視情況可藉由多個互連而連接至另一設備組件。 15 is an electron microscopic image of adjacent device components (eg, contact pads 70) connected to each other by a plurality (two) of interconnections 160. 15 and 14 demonstrate that the device components 70 can be connected to each other by one or more interconnects 10 to provide additional flexibility to electronic devices. For example, a device component or contact pad 70 having a relatively large footprint can optionally be connected to another device component through multiple interconnections.

圖16為採取花形組態150之互連之電子顯微影像。與柵格組態相比，花形組態具有在兩個以上之縱向方向上定向之互連。在此實例中，存在四個不同定向以使得諸如接觸焊墊70之設備組件能夠接觸對角鄰近之設備組件。在此實例中，互連10具有電連接至設備組件(未圖示)之互連末端100與110之間的可選結合區域102，藉此將中央部分90劃分為各具有撓曲組態之兩個未結合區域92。 Figure 16 is an electron micrograph of interconnections in a flower configuration 150. Compared with the grid configuration, the flower-shaped configuration has interconnections oriented in more than two longitudinal directions. In this example, there are four different orientations to enable device components such as contact pads 70 to contact device components that are diagonally adjacent. In this example, the interconnect 10 has an optional bonding area 102 that is electrically connected between the interconnect ends 100 and 110 of the device assembly (not shown), thereby dividing the central portion 90 into each having a flex configuration Two uncombined areas 92.

圖17為以橋接組態130配置之互連的電子顯微影像。在橋接組態中，存在橋接中央部分高峰120，三個或三個以上互連末端自其延伸。舉例而言，於未結合區域中相交之兩個互連導致高峰120，其具有自其延伸之四個互連末端。對於設備組件為交錯配置之情形，高峰120可具有自其延伸之三個末端。在設備組件之間存在多個互連連接之情況下，四個以上之末端可自高峰120延伸。 FIG. 17 is an electron micrograph of interconnections configured in a bridge configuration 130. In the bridge configuration, there is a peak 120 in the central part of the bridge from which three or more interconnecting ends extend. For example, two interconnections that intersect in the unbonded area result in a peak 120 that has four interconnect ends extending from it. For the case where the equipment components are in a staggered configuration, the peak 120 may have three ends extending therefrom. In the case of multiple interconnections between equipment components, more than four ends can extend from the peak 120.

雖然本文提供之圖式中之許多者展示係接觸焊墊70之設備組件，但本文主張的方法及設備能夠連接至大量設備組件以提供可延伸且因此形狀符合之電子設備。舉例而言，圖18展示設備組件60，其為藉由支撐於彈 性體基板30上之彎曲互連10而連接至採取陣列組態之其他光電二極體的光電二極體。 Although many of the drawings provided herein show device components that contact pads 70, the methods and devices claimed herein can be connected to a large number of device components to provide extensible and therefore conformable electronic devices. For example, FIG. 18 shows the device assembly 60, which is supported by the elastic The curved interconnection 10 on the body substrate 30 is connected to the photodiodes of other photodiodes in an array configuration.

圖19描繪彎曲矽陣列之一維延伸行為。畫面(i)為在未施加任何應變力之情況下的彎曲矽陣列之圖像。施加延伸力(如藉由畫面(i)上方之箭頭所指示)以使陣列在一方向上延伸。如畫面(2)至(4)所展示，彎曲互連變平。當於畫面(5)中解除延伸力時，陣列返回至其彎曲組態(見畫面(6)至(8))。畫面(1)與(8)之間的比較展示在延伸之前與延伸之後的彎曲組態相同，此指示該過程可逆。 Figure 19 depicts the one-dimensional extension behavior of a curved silicon array. Picture (i) is an image of a curved silicon array without any strain applied. Apply an extension force (as indicated by the arrow above the screen (i)) to extend the array in one direction. As shown in pictures (2) to (4), the curved interconnection flattens out. When the extension force is released in screen (5), the array returns to its curved configuration (see screens (6) to (8)). The comparison between pictures (1) and (8) shows that the bending configuration before and after the extension is the same, which indicates that the process is reversible.

設備組件之彎曲陣列可易於轉移至彎曲表面，包括剛性或非彈性彎曲表面。藉由圖20之氣泡或氣球印模400來提供用於促進對彎曲表面之保形接觸的一設備及製程之實例。彈性體基板30(在此實例中為約20μm厚之PDMS薄膜)固定於外殼腔室300中以提供由面向內部之基板壁及外殼腔室所界定之腔室容積310。施加正壓力(例如，腔室300中之壓力大於外部壓力)產生能夠與凹入狀收納基板保形接觸之凸起200基板表面。相反，負壓力產生能夠與凸起狀收納基板保形接觸之凹入表面210。對基板之局部彈性(例如，楊氏模數)之空間控制允許產生複雜彎曲幾何形狀。圖20之左下部畫面說明用於藉由引入氣體至腔室310或自腔室310移除氣體之注射器而控制外殼容積310中的壓力之一構件。圖式右側之影像為PDMS薄膜回應於正壓力之增加水準的不同彎曲。用於在彈性體基板上提供彎曲互連之方法及設備中之任一者可與用於轉印至彎曲基板的該等設備一起使用。 The curved array of device components can be easily transferred to curved surfaces, including rigid or inelastic curved surfaces. An example of an apparatus and process for promoting conformal contact to a curved surface is provided by the bubble or balloon stamp 400 of FIG. 20. An elastomer substrate 30 (in this example, a PDMS film of about 20 μm thickness) is fixed in the housing chamber 300 to provide a chamber volume 310 defined by the substrate wall facing the interior and the housing chamber. Applying a positive pressure (eg, the pressure in the chamber 300 is greater than the external pressure) generates a surface of the protrusion 200 substrate that can be in conformal contact with the concave storage substrate. In contrast, the negative pressure generates a concave surface 210 that can conformally contact the convex storage substrate. Spatial control of the local elasticity of the substrate (e.g., Young's modulus) allows complex bending geometries to be generated. The lower left screen of FIG. 20 illustrates a member for controlling the pressure in the housing volume 310 by introducing a gas into the chamber 310 or a syringe for removing the gas from the chamber 310. The image on the right side of the diagram shows the different bending of the PDMS film in response to the increased level of positive pressure. Any of the methods and devices for providing curved interconnects on elastomer substrates can be used with such devices for transfer to curved substrates.

圖21中概述用於在彎曲表面上產生彎曲或上推互連之另一構件。抵靠成形之表面澆鑄薄彈性體膜以產生具有至少一彎曲部分之彈性體基板。基板能夠延伸以使表面變平，從而使得基板能夠與彎曲及平坦表面相符。 將互連施加至平坦印模，且在解除延伸力之後，基板表面即鬆弛回至彎曲幾何形狀，從而在互連中產生應變，藉由互連中央部分之上推而適應該應變。 An overview of another component used to create a bend or push-up interconnection on a curved surface is shown in FIG. A thin elastomer film is cast against the shaped surface to produce an elastomer substrate with at least one curved portion. The substrate can be extended to flatten the surface so that the substrate can conform to curved and flat surfaces. The interconnect is applied to a flat stamp, and after the extension force is released, the substrate surface relaxes back to the curved geometry, thereby generating strain in the interconnect, which is adapted by pushing up the central portion of the interconnect.

圖22中提供由圖20所示之設備造成的彎曲矽陣列之"二維"延伸之實例。在此實例中，互連包含採取柵格組態之複數個彎曲互連連接，其中互連由290nm厚之Si製成。將最初為平坦之彎曲矽陣列(左上部影像)置放入外殼中，且施加正壓力以使陣列擴展為氣泡或氣球組態(例如，彎曲表面)。最右側影像中展示最大擴展，且隨後移除正壓力。類似於對於平坦基板之單軸延伸的結果，此"彎曲"延伸為可逆的。在最大化與彎曲表面之保形接觸的擴展之任一階段，可藉由此項技術中已知之任何手段來將陣列轉移至彎曲表面。圖23展示藉由氣球印模而進行的至塗佈有黏著劑(彈性體基板或SU-8)之玻璃透鏡上之矽印刷之實例。透鏡可為凹入或凸起的。在此實例中，R分別等於19.62mm及9.33mm。 Figure 22 provides an example of a "two-dimensional" extension of the curved silicon array caused by the device shown in Figure 20. In this example, the interconnection includes a plurality of curved interconnection connections in a grid configuration, where the interconnection is made of 290 nm thick Si. Place the initially flat curved silicon array (top left image) into the housing and apply positive pressure to expand the array into a bubble or balloon configuration (eg, curved surface). The largest expansion is shown in the rightmost image, and then the positive pressure is removed. Similar to the result of uniaxial extension for a flat substrate, this "bending" extension is reversible. At any stage of maximizing the conformal contact with the curved surface, the array can be transferred to the curved surface by any means known in the art. FIG. 23 shows an example of silicon printing performed by a balloon stamp onto a glass lens coated with an adhesive (elastomer substrate or SU-8). The lens can be concave or convex. In this example, R is equal to 19.62mm and 9.33mm, respectively.

實例1：半導體奈米織帶中之受控彎曲結構連同在可延伸電子元件中之應用實例 Example 1: Controlled bending structure in semiconductor nanoribbons and application examples in extensible electronic components

對半導體奈米結構之組成、形狀、空間位置及/或幾何組態之控制對於此等材料之幾乎所有應用均為重要的。雖然存在用於界定奈米線及奈米織帶之材料組成、直徑、長度及位置之方法，但存在相對較少用於控制其二維及三維(2D及3D)組態的方法。本文提供用於在奈米織帶中形成原本難以產生的特定類別之3D形狀之機械策略。此實例涉及對用以提供對黏著位點之空間控制之微影圖案化表面化學反應與用以誘發受到良好控制的局部移位之支撐基板之彈性變形的組合使用。可藉由力學分析模型而定量地描述以此方式及此等組態而產生於GaAs與Si之奈米織帶中的經精確設 計之彎曲幾何形狀。作為一應用實例，特定結構提供至具有極高可延伸性水準(高達~100%)、可壓縮性水準(高達~25%)及可撓曲性水準(具有低至~5mm之曲率半徑)之電子元件的途徑。 The control of the composition, shape, spatial position and / or geometric configuration of semiconductor nanostructures is important for almost all applications of these materials. Although there are methods for defining the material composition, diameter, length, and position of nanowires and nanoribbons, there are relatively few methods for controlling their two-dimensional and three-dimensional (2D and 3D) configurations. This article provides a mechanical strategy for forming a specific category of 3D shapes in nanoribbons that would otherwise be difficult to produce. This example involves the combined use of a lithographic patterned surface chemical reaction to provide spatial control of adhesion sites and an elastic deformation of a support substrate to induce well-controlled local displacement. It is possible to quantitatively describe the precise design produced in this way and these configurations in the nanoweb of GaAs and Si by the mechanical analysis model Take into account the curved geometry. As an application example, specific structures are provided to have extremely high levels of extensibility (up to ~ 100%), compressibility levels (up to ~ 25%) and flexibility levels (with curvature radius as low as ~ 5mm) Electronic components approach.

對奈米織帶及奈米線之2維及3維組態在其生長期間加以控制以避免諸如捲曲、環狀及分支布局之特定幾何形狀，或在其生長之後加以控制以(作為實例)藉由將此等元件耦接至受到應變之彈性體支撐物而產生正弦波狀結構或藉由使用成層系統中的內建殘餘應力而產生管狀(或螺旋)結構。具有波狀幾何形狀之半導體奈米織帶受到關注，此部分因為其使得高效能可延伸電子元件系統能夠用於潛在應用，諸如球面彎曲焦平面陣列、智慧型橡膠外科手套及適型結構保健監視器。電子設備自身可延伸之此方法與達成使用剛性設備島狀物連同可延伸金屬互連之此等相同應用之替代方法不同且可能為對其之補充。先前描述之波狀奈米織帶具有兩個主要劣勢：(i)其以由材料之模數及織帶之厚度所界定之固定週期及振幅以幾乎不提供對波紋的幾何形狀或相位之控制之方式而自發形成，及(ii)受到由此製程所導致的非最佳波狀幾何形狀之限制，其可適應之最大應變在20%至30%之範圍內。此處引入之程序使用微影界定之表面黏著位點連同支撐基板之彈性變形來達成彎曲組態(藉由對其幾何形狀之確定性控制)。週期性或非週期性設計對於該等結構之大規模、有組織陣列中的個別奈米織帶之任一選定集合為可能的。經設計以用於可延伸電子元件之專用幾何形狀致能高達接近150%之應變範圍(即使在諸如GaAs之脆性材料中)，此與力學分析模型一致且多達先前報告之結果的十倍。 Control the 2D and 3D configurations of nanoribbons and nanowires during their growth to avoid specific geometries such as curling, loops, and branching, or control them as they grow (as an example) Sinusoidal structures are created by coupling these elements to a strained elastomeric support or by using built-in residual stress in a layered system to produce a tubular (or spiral) structure. Semiconductor nanoribbons with corrugated geometry are of interest, in part because they enable high-performance extensible electronic component systems for potential applications, such as spherical curved focal plane arrays, smart rubber surgical gloves and conformable structural health monitors . This method of extending the electronic device itself is different from and may complement the alternative method of achieving these same applications using rigid device islands along with extensible metal interconnects. The previously described corrugated nanoribbon webbing has two main disadvantages: (i) it has a fixed period and amplitude defined by the modulus of the material and the thickness of the webbing in a way that provides little control over the geometry or phase of the ripple The spontaneous formation, and (ii) is limited by the non-optimal wavy geometry caused by this process, the maximum strain it can adapt is in the range of 20% to 30%. The procedure introduced here uses lithography-defined surface adhesion sites along with the elastic deformation of the supporting substrate to achieve a curved configuration (by deterministic control of its geometry). Periodic or aperiodic designs are possible for any selected set of individual nanowebs in a large-scale, organized array of such structures. The special geometry designed for extensible electronic components enables strain ranges up to nearly 150% (even in brittle materials such as GaAs), which is consistent with the mechanical analysis model and up to ten times the previously reported results.

圖24展示此程序中之步驟。製造始於對遮罩之製備，該遮罩用於對聚二甲基矽氧烷(PDMS)之彈性體基板上的表面化學黏著位點進行圖案 化。此過程涉及在稱作UVO遮罩的不常見類型之振幅光罩(經由步驟i製造)與PDMS保形接觸時經由該光罩而傳遞深紫外(UV)光(240-260nm)。UVO遮罩佔有透明區域中起伏之凹入特徵，使得向UV之曝露在接近PDMS之表面處產生臭氧之圖案化區。臭氧將以-CH3及-H端基支配之未改質疏水性表面轉換為以-OH及-O-Si-O-官能基終止的高度極性及反應性表面(亦即，活性表面)。未曝露之區保持未改質之表面化學(亦即，非活性表面)。此處引入之程序涉及於較大單軸預加應變(對於長度自L變為L+△L，εpre=△L/L)下在PDMS基板(厚度為~4mm)上之曝露(步驟ii)。對於具有簡單週期性線條圖案之遮罩，吾人在步驟(i)中將圖24A之步驟(iii)中的活性條帶(指示為標有"活性表面"之線條)與非活性條帶之寬度(例如，鄰近活性條帶之間的距離)表示為Wact與Win。活性區可強烈且不可逆地結合至在表面上具有曝露之-OH或-Si-O基團的其他材料。如下文所概括，利用此等圖案化黏著位點以在奈米織帶中形成經清楚界定之3D幾何形狀。或者，藉由在互連與基板接觸之前對互連類似地進行圖案化而提供類似的黏著結合位點圖案。 Figure 24 shows the steps in this procedure. Manufacturing begins with the preparation of a mask that is used to pattern the surface chemical adhesion sites on the polydimethylsiloxane (PDMS) elastomer substrate. This process involves passing deep ultraviolet (UV) light (240-260 nm) through the photomask when an unusual type of amplitude photomask (manufactured via step i) called UVO mask comes into conformal contact with PDMS. The UVO mask occupies the undulating concave features in the transparent area, so that the exposure to the UV generates ozone in the patterned area close to the surface of the PDMS. Ozone converts unmodified hydrophobic surfaces dominated by -CH 3 and -H end groups into highly polar and reactive surfaces (ie, active surfaces) terminated with -OH and -O-Si-O-functional groups. Unexposed areas maintain unmodified surface chemistry (ie, inactive surfaces). The procedure introduced here involves exposure on a PDMS substrate (thickness ~ 4mm) under a large uniaxial pre-strain (for a length from L to L + △ L, εpre = △ L / L) (step ii) . For a mask with a simple periodic line pattern, in step (i), we combined the width of the active strip (indicated as a line labeled "active surface") and the inactive strip in step (iii) of Figure 24A (For example, the distance between adjacent active bands) is expressed as W act and W in . The active region can be strongly and irreversibly bound to other materials having exposed -OH or -Si-O groups on the surface. As outlined below, these patterned adhesion sites are utilized to form a clearly defined 3D geometry in the nanoweb. Alternatively, a similar pattern of adhesive bonding sites is provided by similarly patterning the interconnect before the interconnect is in contact with the substrate.

在此實例中，奈米織帶由單晶Si及GaAs組成。藉由使用先前描述之程序(見Khang等人，Science 311,208-212(2006))而由絕緣體上矽(SOI)晶圓製備矽織帶。GaAs織帶包括藉由分子束磊晶法(molecular-beam epitaxy,MBE)在(100)SI-GaAs晶圓上形成的摻雜Si之n型GaAs(120nm；載體濃度為4×1017cm3)、半絕緣GaAs(SI-GaAs；150nm)及AlAs(200nm)之多層。藉由使用沿(0 1 1)結晶定向而光阻圖案化之線條作為蝕刻遮罩而在H3PO4及H2O2之水性蝕刻劑中化學蝕刻磊晶層，從而界定織帶。移除光阻劑且接著將晶圓浸泡於HF之乙醇溶液(乙醇與49%之水性HF的體積 為2：1)中移除AlAs層，藉此釋放具有由光阻劑判定之寬度(對於圖24D中之實例為100μm)的GaAs(n-GaAs/SI-GaAs)之織帶。乙醇向HF溶液之添加減小易碎織帶歸因於乾燥期間之毛細管力之作用而破裂的機率。較低表面張力(與水相比)亦最小化GaAs織帶之空間布局中的乾燥誘發之無序。在最後步驟中，沈積較薄SiO2層(~30nm)以提供必要-Si-OH表面化學以供與PDMS之活性區域結合。 In this example, the nano ribbon is composed of single crystal Si and GaAs. Silicon ribbons are prepared from silicon-on-insulator (SOI) wafers by using the previously described procedure (see Khang et al., Science 311, 208-212 (2006)). GaAs ribbons include Si-doped n-type GaAs (120 nm; carrier concentration 4 × 10 17 cm 3 ) formed on (100) SI-GaAs wafers by molecular-beam epitaxy (MBE) , Multilayer of semi-insulating GaAs (SI-GaAs; 150nm) and AlAs (200nm). The epitaxial layer is chemically etched in an aqueous etchant of H 3 PO 4 and H 2 O 2 by using lines oriented along the (0 1 1) crystal orientation and photoresist pattern as an etching mask to define the webbing. The photoresist is removed and the wafer is then immersed in an ethanol solution of HF (the volume of ethanol and 49% aqueous HF is 2: 1) to remove the AlAs layer, thereby releasing the width (for The example in FIG. 24D is a web of GaAs (n-GaAs / SI-GaAs) of 100 μm). The addition of ethanol to the HF solution reduces the chance that the fragile webbing will rupture due to capillary force during drying. The lower surface tension (compared to water) also minimizes the drying-induced disorder in the spatial layout of the GaAs ribbon. In the final step, a thinner SiO 2 layer (~ 30nm) is deposited to provide the necessary -Si-OH surface chemistry for bonding with the active area of PDMS.

抵靠經UVO處理、預延伸之PDMS基板(平行於預加應變之方向而定向之織帶)而層壓經處理之SOI或GaAs晶圓，將其在烘箱中於90℃下烘焙數分鐘，且移除晶圓，從而將所有織帶轉移至PDMS的表面(步驟iv)。加熱促進Si織帶上之原生SiO2層或GaAs織帶上之沈積的SiO2層與PDMS之主動區之間的保形接觸及該兩者之間的強矽氧烷鍵(亦即，-O-Si-O-)之形成。相對較弱之凡得瓦爾力(Waals force)使織帶結合至PDMS之非活性表面區域。使PDMS中之應變鬆弛經由織帶與PDMS之非活性區域的實體分離而產生彎曲(步驟v)。歸因於強化學鍵結，織帶保持在活性區域中繫栓至PDMS。所得3D織帶幾何形狀(亦即，彎曲之空間變化的圖案)視預加應變之量值及表面活性之圖案(例如，Win及Wact之形狀及尺寸)而定。(可經由織帶上之圖案化結合位點而達成類似結果)。對於簡單線條圖案之情況，Win及預加應變判定彎曲之寬度及振幅。當Wact>100μm時，歸因於產生"波狀"矽之類型的機械不穩定性，在相同織帶中亦形成具有比彎曲小得多的波長及振幅之正弦波(見圖25，以不同Wact形成之樣本之影像)。作為製造之最後步驟，可藉由澆鑄並固化液態預聚物而將3D織帶結構囊封於PDMS中(見圖24步驟vi)。歸因於液體之低黏度及低表面能，其流動且填充形成於織帶與基板之間的間隙(見圖26)。 Laminating the treated SOI or GaAs wafers against UVO-treated, pre-stretched PDMS substrates (webbing oriented parallel to the pre-strained direction) and baking them in an oven at 90 ° C for several minutes, and The wafer is removed, thereby transferring all the webbing to the surface of the PDMS (step iv). Heating promotes the conformal contact between the native SiO 2 layer on the Si ribbon or the deposited SiO 2 layer on the GaAs ribbon and the active region of PDMS and the strong siloxane bond between the two (ie, -O- Si-O-) formation. The relatively weak Waals force binds the webbing to the inactive surface area of PDMS. The strain relaxation in the PDMS causes bending through the physical separation of the webbing from the inactive area of the PDMS (step v). Due to strong chemical bonding, the webbing remains tethered to the PDMS in the active area. The resulting 3D geometry of the webbing (i.e., the bending of the spatially varying pattern) depends on the pre-strain magnitude and pattern of surfactants (e.g., W in and W act of shape and size) may be. (A similar result can be achieved through patterned binding sites on the webbing). For the case of a simple line pattern, W in and pre-determined bending strain of the width and amplitude. When W act > 100μm, due to the mechanical instability of the type that produces "wavy" silicon, a sine wave with a wavelength and amplitude much smaller than the bend is also formed in the same webbing (see Figure 25, with different Image of the sample formed by W act ). As the final step of manufacturing, the 3D webbing structure can be encapsulated in PDMS by casting and curing the liquid prepolymer (see step 24 in Figure 24). Due to the low viscosity and low surface energy of the liquid, it flows and fills the gap formed between the webbing and the substrate (see Figure 26).

圖24D展示PDMS上之彎曲GaAs織帶之斜視掃描電子顯微鏡(scanning electron microscope,SEM)影像，其中εpre=60%且Wact=10μm且Win=400μm。該影像顯示對於陣列中之所有織帶具有共有幾何形狀及空間相干相位之均勻週期性彎曲。將錨固點適當地對齊至微影界定之黏著位點。插圖展示結合區域之SEM影像；寬度為~10μm，其與Wact相一致。該等影像亦顯示PDMS之表面為平坦的，即使在結合位點處亦如此。與先前報告之強耦接之波狀結構大不相同的此行為提示，對於此處描述之情況，PDMS誘發移位，但並不密切涉及於彎曲製程中(亦即，其模數不影響織帶之幾何形狀)。在此意義上，PDMS表示用於經由施加於黏著位點處之力而控制織帶的柔軟、非破壞性工具。 FIG. 24D shows a scanning electron microscope (SEM) image of a curved GaAs ribbon on PDMS, where ε pre = 60% and W act = 10 μm and W in = 400 μm. The image shows a uniform periodic curvature with a common geometry and spatially coherent phase for all ribbons in the array. Align the anchor points appropriately to the adhesion sites defined by the lithography. The inset shows the SEM image of the bonded area; the width is ~ 10μm, which is consistent with W act . These images also show that the surface of PDMS is flat, even at the binding site. This behavior, which is very different from the previously reported strong coupling wave structure, suggests that for the situation described here, PDMS induces displacement, but it is not closely involved in the bending process (that is, its modulus does not affect the ribbon Geometry). In this sense, PDMS refers to a soft, non-destructive tool for controlling the webbing through the force applied at the adhesion site.

圖27A展示以不同εpre形成於PDMS上之彎曲織帶的側視光學顯微相片(Wact=10μm且Win=190μm)。彎曲之高度(例如，"振幅")隨著εpre而增加。非活性區域中之織帶在較低εpre處未充分分離(見以εpre=11.3%及25.5%而形成之樣本)。在較高εpre處，織帶(厚度h)與PDMS分離以形成具有由下式特徵化之豎直移位輪廓之彎曲： FIG. 27A shows a side view optical micrograph of a curved webbing formed on PDMS with different ε pre (W act = 10 μm and W in = 190 μm). The height of the bend (eg, "amplitude") increases with ε pre . The webbing in the inactive area is not sufficiently separated at the lower ε pre (see samples formed with ε pre = 11.3% and 25.5%). At the higher ε pre , the webbing (thickness h) is separated from the PDMS to form a bend with a vertically shifted profile characterized by:

其中： among them:

如藉由對均勻薄層中所形成之彎曲的非線性分析所判定，織帶中之最大拉伸應變近似為 As determined by nonlinear analysis of the bending formed in a uniform thin layer, the maximum tensile strain in the webbing is approximately

彎曲之寬度為2L1且週期為2L2。因為對於h<1μm，h2π2/(12L1 2)遠小於εpre(在此報告中亦即>10%)，所以振幅獨立於織帶之機械特性(例如，厚度、化學組成、楊氏模數等等)，且主要由黏著位點之布局及預加應變所判定。此結論提示如下方法之一般適用性：由任何材料製成之織帶均將形成類似彎曲幾何形狀。此預測與藉由此處所使用之Si與GaAs之織帶而獲得的結果相一致。在圖27A中繪製為虛線之對於33.7%及56.0%之預加應變而計算所得的輪廓與在GaAs織帶中的觀測結果良好地符合。另外，除了在低εpre處(表1及表2)，圖27A所示之彎曲之參數(包括週期、寬度及振幅)與分析計算相一致。此研究之一引起關注之結果在於織帶中之最大拉伸應變較小(例如，~1.2%)，即使對於較大εpre(例如，56.0%)亦如此。如隨後所論述，此定比致能可延伸性，即使對於諸如GaAs之脆性材料的情況亦如此。 The width of the bend is 2L 1 and the period is 2L 2 . Because for h <1μm, h 2 π 2 / (12L 1 2 ) is much smaller than ε pre (> 10% in this report), so the amplitude is independent of the mechanical properties of the webbing (eg, thickness, chemical composition, Young's Modulus, etc.), and is mainly determined by the layout of the adhesion site and pre-strain. This conclusion suggests the general applicability of the following method: a webbing made of any material will form a similar curved geometry. This prediction is consistent with the results obtained with the ribbon of Si and GaAs used here. The contours calculated for the pre-strain of 33.7% and 56.0% drawn as dashed lines in FIG. 27A are in good agreement with the observation results in the GaAs ribbon. In addition, except at the low ε pre (Table 1 and Table 2), the bending parameters (including period, width, and amplitude) shown in FIG. 27A are consistent with the analysis calculation. One of the results of concern in this study is that the maximum tensile strain in the webbing is small (eg, ~ 1.2%), even for large ε pre (eg, 56.0%). As discussed later, this scaling enables scalability, even for brittle materials such as GaAs.

微影界定之黏著位點可具有比與圖24中之結構相關聯之簡單格柵或柵格圖案複雜的幾何形狀。舉例而言，可在個別織帶中形成具有不同寬度及振幅之彎曲。作為實例，圖27B展示彎曲Si織帶(寬度及厚度分別為50μm及290nm)之SEM影像，該織帶以50%之預加應變及以Wact=15μm且Win沿織帶的長度等於350、300、250、250、300及350μm為特徵之黏著位點而形成。該影像清楚地展示織帶中之每一者中的鄰近彎曲之寬度及振幅之變化。彎曲織帶亦可以對於不同織帶之不同相位而形成。圖27C呈現以彎曲中隨垂直於織帶之長度的距離而線性變化之相位來設計的Si系統之實例。用於此樣本之UVO遮罩具有分別為15μm及250μm之Wact及Win。PDMS印模上之活性條帶與Si織帶之間的角度為30。歸因於對黏著位點之 簡單微影控制而可易於達成許多其他可能性，且一些可能性展示於(例如)圖13至圖17中。 Lithography-defined adhesion sites may have a more complex geometry than the simple grid or grid pattern associated with the structure in FIG. For example, bends with different widths and amplitudes can be formed in individual webbings. As an example, FIG. 27B shows an SEM image of a curved Si webbing (width and thickness of 50 μm and 290 nm, respectively) with a pre-strain of 50% and W act = 15 μm and W in the length of the webbing equal to 350, 300, 250, 250, 300, and 350 μm are characteristic adhesion sites. The image clearly shows the changes in the width and amplitude of adjacent bends in each of the webbing. The curved ribbon can also be formed for different phases of different ribbons. FIG. 27C presents an example of a Si system designed with a phase that changes linearly with the distance perpendicular to the length of the webbing in bending. The UVO mask used for this sample has W act and W in of 15 μm and 250 μm, respectively. The angle between the active strip on the PDMS stamp and the Si web is 30. Many other possibilities can be easily achieved due to simple lithography control of the adhesion site, and some possibilities are shown in, for example, FIGS. 13-17.

具有εpre=60%、Wact=10μm及不同Win的PDMS上之彎曲GaAs織帶之簡單實例(如圖27D中所示)說明對於可延伸電子元件中的應用為重要之態樣。與對力學之分析解良好符合之輪廓展示在Win=100μm(及更小)時，歸因於GaAs中之破裂而導致的失效。失效係由超過GaAs之屈服點(~2%)的拉伸應變(在此情況下為~2.5%)所導致。因此可藉由選擇與εpre成比例之Win(»Wact)來達成對延伸及壓縮之強健性的最佳組態。在此情形中，可適應高達及大於100%之預加應變。吾人藉由向PDMS支撐物施加力而直接論證此類型之可延伸性。織帶之區段的端至端距離(Lprojected)之改變提供根據下式而量化可延伸性及可壓縮性之手段： 其中表示斷裂之前的最大/最小長度，且為鬆弛狀態下之 長度。延伸及壓縮分別對應於大於及小於之。Wact=10μm且Win=400μm且εpre=60%的PDMS上之彎曲織帶顯示出60%之可延伸性(亦即εpre)及高達30%之可壓縮性。將織帶嵌入於PDMS中在機械上保護結構，且亦產生持續可逆回應，但在力學上存在微小改變。特定言之，可延伸性及可壓縮性分別減小至~51.4%(圖28A)與~18.7%(圖28B)。織帶頂部之PDMS基質部分歸因於下伏PDMS的固化誘發之收縮而使彎曲之峰微微變平。小週期波紋在較大壓縮應變下歸因於產生先前所述之波狀織帶結構之類型的自發力學而形成於此等區域中。如圖28B所說明，機械失效傾向於開始於此等區中，由此減小可壓縮性。Wact=10μm且Win=300μm之彎曲結構避免此類型之行為。雖然該等實例顯示出比圖28A所示之實例稍低 的可延伸性，但短週期波紋之缺少將可壓縮性增加至~26%。總體而言，形成於具有圖案化表面化學黏著位點之預延伸之PDMS基板上的具有彎曲之單晶GaAs奈米織帶顯示出高於50%之可延伸性及大於25%之可壓縮性，此對應於接近100%之滿標度應變範圍。此等數字藉由增加εpre及Win且藉由使用具有比PDMS高之伸長率的基板材料而得到進一步改良。對於更加精密之系統，亦可重複此等製造程序來產生具有多個彎曲織帶之層的樣本(見圖29)。 A simple example of a curved GaAs ribbon on a PDMS with ε pre = 60%, W act = 10 μm, and different W in (as shown in FIG. 27D) illustrates an important aspect for applications in extensible electronic components. The contours that are in good agreement with the analytical solutions of mechanics are shown at W in = 100 μm (and smaller), due to failure due to cracking in GaAs. The failure is caused by a tensile strain (~ 2.5% in this case) that exceeds the yield point of GaAs (~ 2%). Therefore, by selecting W in (»W act ) which is proportional to ε pre , the optimal configuration for the robustness of extension and compression can be achieved. In this case, pre-strains up to and above 100% can be accommodated. We directly demonstrate the extensibility of this type by applying force to the PDMS support. The change of the end-to-end distance (L projected ) of the webbing section provides a means to quantify extensibility and compressibility according to the following formula: among them Represents the maximum / minimum length before breaking, and It is the length in the relaxed state. Extension and compression correspond to greater than and less than Of . The curved webbing on PDMS with W act = 10 μm and W in = 400 μm and ε pre = 60% shows 60% extensibility (ie ε pre ) and compressibility up to 30%. Embedding the webbing in PDMS mechanically protects the structure and also produces a continuous reversible response, but there are minor mechanical changes. In particular, the extensibility and compressibility are reduced to ~ 51.4% (Figure 28A) and ~ 18.7% (Figure 28B), respectively. The PDMS matrix at the top of the webbing is partly due to the shrinkage induced by the curing of the underlying PDMS and the peak of bending is slightly flattened. Small period ripples are formed in these regions due to spontaneous mechanics that produce the type of wavy webbing structure described earlier under greater compressive strain. As illustrated in FIG. 28B, mechanical failure tends to start in these regions, thereby reducing compressibility. The curved structure with W act = 10 μm and W in = 300 μm avoids this type of behavior. Although these examples show slightly lower extensibility than the example shown in FIG. 28A, the lack of short-period ripple increases the compressibility to ~ 26%. In general, single-crystal GaAs nanoribbon ribbons with bends formed on pre-extended PDMS substrates with patterned surface chemical adhesion sites show extensibility greater than 50% and compressibility greater than 25%, This corresponds to a full-scale strain range close to 100%. These numbers are further improved by increasing ε pre and W in and by using substrate materials with higher elongation than PDMS. For more sophisticated systems, these manufacturing procedures can also be repeated to produce samples with multiple layers of curved webbing (see Figure 29).

此較大可延伸性/可壓縮性之直接結果為極大程度之機械可撓曲性。圖30A至圖30C呈現說明此特徵之撓曲組態的光學顯微相片。分別將PDMS基板(厚度為~4mm)撓曲為凹入(~5.7mm之半徑)、平坦及凸起(~6.1mm之半徑)的彎曲。該等影像說明輪廓如何改變以適應撓曲誘發之表面應變(對於此等情況為~20%至25%)。實際上，形狀類似於在壓縮(~20%)及張力(~20%)中所獲得之形狀。嵌入之系統歸因於中性機械平面效應而顯示出甚至更高水準之可撓曲性。當頂部與底部PDMS層具有類似厚度時，在撓曲期間不存在彎曲形狀上的改變(圖30D)。 The direct result of this greater extensibility / compressibility is a great degree of mechanical flexibility. 30A to 30C present optical micrographs illustrating the flexure configuration of this feature. The PDMS substrate (thickness ~ 4mm) was flexed into concave (~ 5.7mm radius), flat and convex (~ 6.1mm radius) bends respectively. These images illustrate how the contour changes to accommodate the deflection-induced surface strain (~ 20% to 25% for these cases). In fact, the shape is similar to that obtained in compression (~ 20%) and tension (~ 20%). The embedded system exhibits even higher levels of flexibility due to neutral mechanical plane effects. When the top and bottom PDMS layers have similar thicknesses, there is no change in bending shape during deflection (FIG. 30D).

為了論證功能電子設備中之此等機械特性，吾人使用具有類似於圖30所示之輪廓的輪廓之彎曲GaAs織帶，藉由將較薄金電極沈積至織帶之SI-GaAs側上以進行肖特基接觸(Schottky contact)而建立金屬-半導體-金屬光偵測器(MSM PD)。圖31A展示MSM PD在延伸~50%之前及之後的幾何形狀及等效電路及俯視光學顯微相片。在無光之情況下，幾乎無電流流過PD；電流隨著紅外光束(波長為~850nm)之增加的照射而增大(圖31B)。電流/電壓(I-V)之不對稱特徵可歸因於接觸點之電特性的差異。圖31C(延伸)及圖31D(壓縮)展示在不同程度之延伸及壓縮所量測之I-V。電 流在PD延伸高達44.4%時增大，且接著隨著進一步延伸而減小。因此光源之每單位面積的強度為恆定的，所以電流隨延伸之增大可歸因於彎曲GaAs織帶的投影面積(稱作有效面積，Seff)隨織帶變平之增大。使PD進一步延伸可能誘發GaAs織帶之表面上及/或晶格中的缺陷，其導致電流之減小且最終在斷裂時導致斷路。類似地，壓縮使Seff減小且因此使電流減小(圖31D)。此等結果指示，嵌入於PDMS基質中之彎曲GaAs織帶提供對於諸如耐磨監視器、彎曲成像陣列及其他設備之各種應用為有用的充分可延伸/可壓縮類型之光感應器。 To demonstrate these mechanical properties in functional electronic devices, we used curved GaAs webbing with a profile similar to that shown in Figure 30, by depositing thinner gold electrodes on the SI-GaAs side of the webbing for SCHOTT Based on Schottky contact to establish metal-semiconductor-metal photodetector (MSM PD). Figure 31A shows the geometry and equivalent circuit and top-view optical micrograph of the MSM PD before and after the extension by ~ 50%. In the absence of light, almost no current flows through the PD; the current increases as the infrared beam (wavelength is ~ 850nm) increases (Figure 31B). The asymmetry characteristic of current / voltage (IV) can be attributed to the difference in electrical characteristics of the contact points. Fig. 31C (extended) and Fig. 31D (compressed) show the measured IV for different degrees of extension and compression. The current increases when the PD extends up to 44.4%, and then decreases with further extension. Therefore, the intensity per unit area of the light source is constant, so the increase in current with extension can be attributed to the increase in the projected area of the curved GaAs webbing (called the effective area, S eff ) as the webbing flattens. Extending the PD further may induce defects on the surface of the GaAs ribbon and / or in the crystal lattice, which leads to a reduction in current and eventually a circuit break when broken. Similarly, compression reduces S eff and therefore the current (FIG. 31D). These results indicate that the curved GaAs ribbon embedded in the PDMS matrix provides a fully extensible / compressible type of light sensor that is useful for various applications such as wearable monitors, curved imaging arrays and other devices.

總之，此實例指示，具有以微影方式界定之黏著位點之柔軟彈性體作為用於在半導體奈米織帶中形成特定類型之3維組態的工具為有用的。可延伸電子元件提供此等類型之結構的許多可能應用領域之一實例。簡單PD設備論證一些能力。對結構之高水準控制及將高溫處理步驟(例如，歐姆接觸之形成)與彎曲製程及PDMS分離之能力指示較為複雜之設備(例如，電晶體及較小電路薄片)為可能的。鄰近織帶中之彎曲的受到良好控制之相位提供電互連多個元件之機會。又，雖然此處報告之實驗使用GaAs與Si奈米織帶，但其他材料(例如，GaN、InP及其他半導體)及其他結構(例如，奈米線、奈米薄膜)與此方法相容。 In summary, this example indicates that a soft elastomer with adhesive sites defined in a lithographic manner is useful as a tool for forming specific types of 3-dimensional configurations in semiconductor nanoribbons. Extensible electronic components provide one example of many possible application areas for these types of structures. A simple PD device demonstrates some capabilities. High-level control of the structure and the ability to separate high-temperature processing steps (eg, the formation of ohmic contacts) from the bending process and PDMS indicate more complex equipment (eg, transistors and smaller circuit sheets). The well-controlled phase of the bend in the adjacent webbing provides an opportunity to electrically interconnect multiple components. Also, although the experiments reported here use GaAs and Si nanoribbons, other materials (eg, GaN, InP, and other semiconductors) and other structures (eg, nanowires, nanofilms) are compatible with this method.

GaAs織帶之製造：具有定製磊晶層之GaAs晶圓(細節描述於本文中)係購自IQE Inc.,Bethlehem,PA。光微影及濕式化學蝕刻產生GaAs織帶。以5000rpm之速度將AZ光阻劑(例如AZ 5214)旋轉澆鑄於GaAs晶圓上歷時30秒，且接著於100℃下軟烘焙1分鐘。經由具有以沿GaAs之(011)結晶方向而定向之圖案化線的光罩之曝露繼之以顯影在光阻劑中產生線條圖案。溫和O2電漿(亦即，除渣製程)移除殘餘光阻劑。GaAs晶圓接著在 蝕刻劑(4mL H3PO4(85重量%)、52mL H2O2(30重量%)及48mL去離子水)中經各向異性蝕刻1分鐘，在冰水浴中經冷卻。以於乙醇中稀釋之HF溶液(Fisher® Chemicals)(在體積上為1：2)來溶解AlAs層。在通風櫃中使具有在母晶圓上之經釋放織帶的樣本乾燥。以藉由電子束蒸鍍沈積之30nm的SiO2來塗佈經乾燥之樣本。 Fabrication of GaAs webbing: GaAs wafers with customized epitaxial layers (details are described in this article) were purchased from IQE Inc., Bethlehem, PA. Photolithography and wet chemical etching produce GaAs ribbons. An AZ photoresist (eg, AZ 5214) was spin-cast on a GaAs wafer at 5000 rpm for 30 seconds, and then soft baked at 100 ° C for 1 minute. A line pattern is created in the photoresist through exposure of a photomask with patterned lines oriented in the (011) crystal direction of GaAs followed by development. A mild 02 plasma (ie, slag removal process) removes residual photoresist. The GaAs wafer was then anisotropically etched in an etchant (4 mL H 3 PO 4 (85% by weight), 52 mL H 2 O 2 (30% by weight) and 48 mL deionized water) for 1 minute, and cooled in an ice water bath . The AlAs layer was dissolved with HF solution (Fisher ® Chemicals) (1: 2 in volume) diluted in ethanol. The sample with the released webbing on the mother wafer is dried in a fume hood. The dried samples were coated with 30 nm SiO 2 deposited by electron beam evaporation.

Si織帶之製造：由絕緣體上矽(SOI)晶圓(Soitect,Inc.，頂部矽290nm，內埋氧化物400nm，p型)來製造矽織帶。使用AZ 5214光阻劑藉由習知光微影法對晶圓進行圖案化，且藉由SF6電漿(PlasmaTherm RIE，SF6 40sccm，50毫托，100W)對其進行蝕刻。在以丙酮將光阻劑洗淨之後，接著在HF(49%)中蝕刻內埋氧化物層。 Fabrication of Si ribbons: Silicon ribbons are manufactured from silicon-on-insulator (SOI) wafers (Soitect, Inc., top silicon 290 nm, buried oxide 400 nm, p-type). The wafer was patterned by conventional photolithography using AZ 5214 photoresist and etched by SF6 plasma (PlasmaTherm RIE, SF6 40sccm, 50 mTorr, 100W). After washing the photoresist with acetone, the buried oxide layer was then etched in HF (49%).

UVO遮罩之製造：於食人魚溶液(piranha solution)中清洗熔融石英載片(於60℃)15分鐘且以充足的水對其進行徹底沖洗。藉由氮氣吹掃來乾燥經清洗之載片，且將其置放於電子束蒸鍍器之腔室中以藉由5nm之Ti(作為黏著層)及100nm之Au(對於UV光之遮罩層)的連續層而塗佈。以3000rpm之速度將負性光阻劑(亦即，SU8 5)旋轉澆鑄於載片上歷時30秒來產生~5μm厚之膜。軟烘焙、曝露於UV光、後烘焙及顯影在光阻劑中產生圖案。溫和O2電漿(亦即，除渣製程)移除殘餘光阻劑。光阻劑充當遮罩以分別藉由金蝕刻劑(亦即，I2與KI之水性溶液)及鈦蝕刻劑(亦即，HCl之稀釋溶液)來蝕刻Au與Ti。 Manufacture of UVO mask: Wash the fused silica slide (at 60 ° C) in piranha solution for 15 minutes and rinse it thoroughly with sufficient water. The cleaned slides were dried by nitrogen purge and placed in the chamber of the electron beam vaporizer to pass 5nm of Ti (as an adhesive layer) and 100nm of Au (for UV light masking) Layer). A negative photoresist (ie, SU8 5) was spin-cast on a slide at 3000 rpm for 30 seconds to produce a ~ 5 μm thick film. Soft baking, exposure to UV light, post-baking, and development produce patterns in the photoresist. A mild 02 plasma (ie, slag removal process) removes residual photoresist. The photoresist acts as a mask to etch Au and Ti with a gold etchant (ie, an aqueous solution of I 2 and KI) and a titanium etchant (ie, a diluted solution of HCl), respectively.

PDMS印模之製造：藉由將預聚物(A：B=1：10，Sylgard 184，Dow Corning)傾注至皮氏培養皿中繼之以於65℃下烘焙4小時來製備具有~4mm之厚度的PDMS基板。自所得固化物件切割具有合適大小及矩形形狀之厚片且接著以異丙醇對其進行沖洗且藉由氮氣吹掃使其乾燥。使用特別 設計之台來將PDMS機械延伸至所要程度的應變。經由置放為與PDMS接觸之UVO遮罩使此等經延伸之基板受到短波長UV光(低壓汞燈，BHK，自240至260nm為173μW/cm2)的照射歷時5分鐘產生經圖案化之表面化學。 Manufacturing of PDMS impressions: by pouring a prepolymer (A: B = 1: 10, Sylgard 184, Dow Corning) into a petri dish and relaying to bake at 65 ° C for 4 hours to prepare a product with ~ 4mm The thickness of the PDMS substrate. From the obtained cured article, a thick sheet having a suitable size and a rectangular shape was cut and then rinsed with isopropyl alcohol and dried by nitrogen purge. A specially designed stage is used to extend the PDMS mechanically to the desired degree of strain. These extended substrates were exposed to short-wavelength UV light (low-pressure mercury lamp, BHK, 173 μW / cm 2 from 240 to 260 nm) through a UVO mask placed in contact with PDMS to produce a patterned pattern. Surface chemistry.

彎曲GaAs織帶之形成及嵌入：相對於具有經圖案化之表面化學的延伸之PDMS層壓具有塗佈有SiO2之經釋放之織帶的GaAs晶圓。在烘箱中於90℃下烘焙5分鐘，在空氣中冷卻至室溫且接著緩慢鬆弛PDMS中之應變沿每一織帶產生彎曲。嵌入彎曲織帶涉及泛光曝露於UV光下5分鐘且接著將液態PDMS預聚物澆鑄至~4mm之厚度。將樣本在烘箱中於65℃下固化4小時或在室溫下固化36小時使得預聚物固化來使彎曲織帶嵌入於PDMS之固體基質中。 Formation and embedding of curved GaAs webbing: A GaAs wafer with a released webbing coated with SiO 2 is laminated against a PDMS with an extended patterned surface chemistry. Bake in an oven at 90 ° C for 5 minutes, cool to room temperature in the air and then slowly relax the strain in PDMS to produce bending along each webbing. Embedding a curved webbing involves flooding exposure to UV light for 5 minutes and then casting the liquid PDMS prepolymer to a thickness of ~ 4mm. The samples were cured in an oven at 65 ° C for 4 hours or at room temperature for 36 hours to cure the prepolymer to embed the curved webbing in the solid matrix of PDMS.

彎曲織帶之表徵：藉由使樣本傾斜~90°(對於非嵌入之樣本)或~30°(對於嵌入之樣本)而以光學顯微鏡對織帶進行成像。在以較薄金層(厚度為~5nm)塗佈樣本之後將SEM影像記錄於Philips XL30場發射掃描電子顯微鏡上。使用用於預延伸PDMS印模之同一台來延伸及壓縮所得樣本。 Characterization of curved webbing: The webbing is imaged with an optical microscope by tilting the sample by ~ 90 ° (for non-embedded samples) or ~ 30 ° (for embedded samples). After coating the sample with a thinner gold layer (~ 5nm thickness), the SEM image was recorded on a Philips XL30 field emission scanning electron microscope. The same sample used for pre-extending PDMS impressions was used to extend and compress the resulting samples.

SMS PD之製造及表徵：PD之製造始於採取圖24B之底部圖框中所示之組態的樣本。輕柔地將~0.8mm寬之聚對苯二甲酸乙二酯(PET)薄片的條帶置放於PDMS上，其中條帶之縱軸與織帶之縱軸垂直。此條帶充當對於30nm厚之金膜之電子束蒸鍍(以形成肖特基電極)的蔽蔭遮罩。移除PET條帶且鬆弛預延伸之PDMS印模形成建有彎曲GaAs織帶之SMS PD。將液態PDMS預聚物澆鑄至織帶之無電極的區域上，且接著於烘箱中固化。金電極延伸越過頂部PDMS以致能藉由半導體參數分析器而進行之探 測。(Agilent 4155C)。在對光回應之量測中，藉由使用用於延伸及壓縮之機械台來控制PD。IR LED源(具有850nm之波長)提供照射。 Manufacturing and characterization of SMS PD: The manufacturing of PD begins with a sample of the configuration shown in the bottom frame of FIG. 24B. Gently place a strip of polyethylene terephthalate (PET) sheet ~ 0.8mm wide on the PDMS, where the longitudinal axis of the strip is perpendicular to the longitudinal axis of the webbing. This strip serves as a shadow mask for electron beam evaporation (to form a Schottky electrode) of a 30 nm thick gold film. Remove the PET tape and relax the pre-extended PDMS stamp to form an SMS PD with a curved GaAs webbing. The liquid PDMS prepolymer was cast onto the electrodeless area of the webbing and then cured in an oven. The gold electrode extends beyond the top PDMS to enable exploration by the semiconductor parameter analyzer Measurement. (Agilent 4155C). In the measurement of the response to light, the PD is controlled by using a mechanical table for expansion and compression. The IR LED source (having a wavelength of 850 nm) provides illumination.

實例2：轉印： Example 2: Transfer:

吾人之技術方法使用體現於先前描述之基於平坦印模的印刷方法中之某些思想。雖然此等基本技術提供有前途之起點，但如下文所述，必須引入許多根本上的新特徵來滿足用於成像之半球陣列偵測器(Hemispherical Array Detector for Imaging,HARDI)系統之挑戰。 My technical method uses certain ideas embodied in the flat stamp-based printing method described previously. Although these basic technologies provide a promising starting point, as described below, many fundamental new features must be introduced to meet the challenges of the Hemispherical Array Detector for Imaging (HARDI) system.

圖32及圖33說明與向彎曲表面之轉印相關之總策略。步驟之第一集合(圖32)涉及經設計以將互連之Si CMOS "小晶片(chiplet)"自晶圓之平坦表面起離且接著將幾何形狀變換為半球形狀之較薄球面彎曲彈性體印模的製造及控制。藉由抵靠經選擇具有所要曲率半徑之高品質光學元件(亦即，凸透鏡與凹透鏡之配對)澆鑄並固化液態預聚物以獲得諸如聚二甲基矽氧烷(PDMS)之彈性體而形成用於此製程之印模。印模具有模製之圓形輪緣。藉由使此輪緣上之模製槽(圖32中之虛線圓)配合至適當大小之剛性圓形固持環而徑向延伸此元件將此球形印模變換為延伸之平坦薄片。使此延伸之印模與支撐具有較薄互連之預成型且經底切蝕刻之Si CMOS "小晶片"的母晶圓接觸且接著剝離該印模以此等互連之"小晶片"對此元件"塗墨"。小晶片與柔軟彈性體元件之間的凡得瓦爾相互作用(Van der Waals interaction)對此製程提供充分黏著。 32 and 33 illustrate the general strategy related to the transfer to the curved surface. The first set of steps (Figure 32) involves thinner spherical curved elastomers designed to separate interconnected Si CMOS "chiplets" from the flat surface of the wafer and then transform the geometry into a hemispherical shape Manufacture and control of impressions. It is formed by casting and curing a liquid prepolymer against a high-quality optical element selected with a desired radius of curvature (ie, a pair of convex lens and concave lens) to obtain an elastomer such as polydimethylsiloxane (PDMS) The impression used for this process. The stamping mold has a molded round rim. By fitting the molding groove (dashed circle in FIG. 32) on this rim to a rigid circular retaining ring of appropriate size, this element is extended radially to transform this spherical impression into an extended flat sheet. This extended stamp is brought into contact with the mother wafer supporting the pre-formed and undercut etched Si CMOS "small chip" with thin interconnects, and then the stamp is peeled off to match the "small chip" This element is "inked". The Van der Waals interaction between the small chip and the flexible elastomer element provides sufficient adhesion for this process.

移除固持環使得PDMS鬆弛回其初始半球形狀，藉此實現小晶片陣列的平坦至球形之變換。此變換誘發印模之表面處的壓縮應變。藉由互連之局部分層及提昇而在CMOS小晶片陣列中適應此等應變(圖32之左下部)。此等"上推"互連以避免對小晶片之損害及其電特性之有害的應變誘發之改 變之方式來吸收應變。將小晶片中之應變保持於~0.1%以下實現此等兩個目標。互連所需之空間限制CMOS小晶片之最大填充因數。然而，光偵測器消耗幾乎全部像素面積，由此提供達到80%之填充因數目標的簡單途徑。 Removal of the retaining ring allows the PDMS to relax back to its original hemispherical shape, thereby achieving a flat to spherical transformation of the small wafer array. This transformation induces compressive strain at the surface of the stamp. These strains are accommodated in the CMOS chiplet array by partial layering and promotion of interconnections (lower left of FIG. 32). These "push-up" interconnects avoid damage to small chips and their harmful strain-induced changes in electrical characteristics Change the way to absorb strain. Keeping the strain in the small wafer below ~ 0.1% achieves these two goals. The space required for interconnection limits the maximum fill factor of small CMOS chips. However, the photodetector consumes almost the entire pixel area, thus providing a simple way to achieve the 80% fill factor goal.

在步驟之第二集合(圖33)中，使用經"塗墨"之半球印模來將此等元件轉印至具有匹配形狀之空腔的最終設備基板(例如，在此實例中為具有匹配半球狀空腔之玻璃基板)上。此轉移製程使用諸如光可固化BCB(Dow Chemical)或聚胺基甲酸酯(Norland Optical Adhesive)之紫外(UV)固化光聚合物作為黏著劑。將此等材料以薄(數十微米厚)液態膜之形式塗覆至設備基板。在與印模接觸之後，此液態層即流動以符合與小晶片及上推互連相關聯之起伏結構。穿過透明基板之UV光使光聚合物固化且將其變換為固體形式以在移除印模之後即產生平滑、平面化之頂部表面。用以形成功能系統之最終整合涉及電極及光偵測器材料之沈積及圖案化，及匯流排線至外部控制電路之微影界定。 In the second set of steps (Figure 33), the "inked" hemispherical stamp is used to transfer these elements to the final device substrate with a cavity of matching shape (for example, in this example, with matching Hemispherical cavity on the glass substrate). This transfer process uses ultraviolet (UV) curable photopolymers such as photocurable BCB (Dow Chemical) or polyurethane (Norland Optical Adhesive) as the adhesive. These materials are applied to the device substrate in the form of a thin (tens of microns thick) liquid film. After contact with the stamp, this liquid layer flows to conform to the relief structure associated with the small wafer and the push-up interconnect. UV light passing through the transparent substrate cures the photopolymer and transforms it into a solid form to produce a smooth, planar top surface after removing the stamp. The final integration used to form the functional system involves the deposition and patterning of electrode and photodetector materials, and the lithographic definition of the busbar to an external control circuit.

圖32及圖33之方法具有若干顯著特徵。第一，其利用最新平面電子技術來致能對半球基板之可靠、節省成本及高效能的操作。特定言之，小晶片由以0.13μm之設計規則加以處理之矽電晶體之集合組成來得到HARDI系統之局部像素級處理能力。使用習知處理連同絕緣體上矽晶圓以形成此等設備。內埋氧化物提供犧牲層(藉由HF而進行底切蝕刻)來製備用於印刷之小晶片。互連由窄且薄(~100nm)之金屬線組成。 The method of FIGS. 32 and 33 has several salient features. First, it utilizes the latest planar electronic technology to enable reliable, cost-saving, and efficient operation of the hemispherical substrate. In particular, the small chip is composed of a collection of silicon transistors processed with a design rule of 0.13 μm to obtain the local pixel-level processing capability of the HARDI system. These devices are formed using conventional processing along with silicon-on-insulator wafers. The buried oxide provides a sacrificial layer (undercut etching by HF) to prepare small wafers for printing. The interconnect consists of narrow and thin (~ 100nm) metal lines.

第二特徵在於該方法使用彈性體元件及機械設計以致能平面向半球之受到良好控制的變換。轉移印模及綜合機械模型化中之可逆線性力學如隨後所概括而實現此控制。第三個有吸引力之態樣在於，轉移製程及策略 之用以控制黏著之某些基本組件在平面應用中已得到論證。實際上，已經設計以用於彼等平面印刷應用之台可經調適以用於圖32及圖33之製程。圖34展示適用於此製程中的具有整合式視覺系統及氣壓致動器之自製印刷器。 The second feature is that the method uses elastomeric elements and mechanical design to enable a well-controlled transformation of the plane to the hemisphere. Reversible linear mechanics in transfer impressions and comprehensive mechanical modelling achieves this control as outlined later. The third attractive aspect is that the transfer process and strategy Some basic components used to control adhesion have been demonstrated in planar applications. In fact, the tables that have been designed for their flat printing applications can be adapted for the processes of FIGS. 32 and 33. Figure 34 shows a self-made printer with integrated vision system and pneumatic actuator suitable for this process.

使用此等類型之印刷器系統來論證圖32及圖33之製程的若干態樣。圖35展示以單晶矽島狀物之陣列而"塗墨"之半球印模之表面的掃描電子顯微相片影像，該等單晶矽島狀物在正方陣列中藉由重摻雜之矽織帶而互連。圖36展示光學影像。在平面至球形之變換期間，此等織帶互連以圖32中所描繪之方式上推。此等類型之互連之關鍵態樣在於，當與完全成形之小晶片的轉移組合時，其減小對於高解析度彎曲表面微影或直接對半球進行之其他形式之處理的需要。 These types of printer systems are used to demonstrate several aspects of the process of FIGS. 32 and 33. Figure 35 shows a scanning electron micrograph image of the surface of a hemispherical impression "inked" with an array of single crystal silicon islands, which are made of heavily doped silicon in a square array Webbing and interconnected. Figure 36 shows an optical image. During the plane-to-sphere transformation, these webbing interconnects are pushed up in the manner depicted in FIG. 32. The key aspect of these types of interconnects is that when combined with the transfer of fully formed small wafers, it reduces the need for high-resolution curved surface lithography or other forms of processing directly on the hemisphere.

除了材料及總處理策略以外，執行對半球印模、上推互連及與剛性設備島狀物之相互作用的彈性機械回應之全計算模型化。此等計算以促進設計控制及最佳化之水準顯示製程之物理現象。基於線性彈性板理論之簡單估計暗示與圖32之製程相關聯的應變水準對於2mm厚之印模及半徑為1cm之球面可達到10%或更高。因此，為了可靠設計控制，對於高達此值之兩倍(亦即，~20%)的應變在線性彈性狀態中操作印模為必要的。圖37展示PDMS之若干變體之實驗應力/應變曲線，關於該等變體，吾人在基於塊狀平坦印模之印刷的水準上具有經驗。184-PDMS看來似乎提供良好初始材料，因為其提供高達~40%之應變的高線性及彈性回應。 In addition to materials and overall processing strategies, perform full computational modeling of elastic mechanical responses to hemispherical impressions, push-up interconnects, and interaction with rigid device islands. These calculations display the physical phenomena of the process in order to promote design control and optimization. A simple estimate based on linear elastic plate theory implies that the strain level associated with the process of Figure 32 can reach 10% or more for a 2mm thick stamp and a 1cm radius spherical surface. Therefore, for reliable design control, it is necessary to operate the stamp in a linear elastic state for strains up to twice this value (ie, ~ 20%). Figure 37 shows the experimental stress / strain curves of several variants of PDMS. Regarding these variants, we have experience in the level of printing based on massive flat stamps. 184-PDMS seems to provide a good starting material because it provides a highly linear and elastic response of up to ~ 40% strain.

諸如此等之機械量測連同關於小晶片及織帶上推互連之模數及幾何形狀的文獻值提供對於模型化為必要之資訊。採用兩種計算方法。第一者為滿標度有限元模型化(finite element modeling,FEM)，在其中分析平坦 基板上之設備及互連幾何形狀(例如，大小、間距、多層)的細節。在分析中直接考慮不同材料(例如，印模、矽、互連)。外加側向壓力以使印模及電路變形為所要球形形狀。有限元分析給出應變分布(尤其是設備及互連中之最大應變)及經變換之設備之間的不均勻間距。該方法之優勢在於其俘獲設備幾何形狀及材料之所有細節，且因此可用以探察轉印製程之不同設計的效果以減小最大應變及不均勻性。然而，此方法為計算密集的且因此耗費時間，因為其涉及較廣範圍之長度標度及對印模上之大量結構設備之模型化。 Mechanical measurements such as these, along with literature values on the modulus and geometry of the small chip and webbing push-up interconnects, provide the information necessary for modeling. Two calculation methods are used. The first is full-scale finite element modeling (FEM), where the analysis is flat Details of equipment and interconnect geometry (eg size, pitch, multiple layers) on the substrate. Different materials are directly considered in the analysis (for example, impression, silicon, interconnect). Apply lateral pressure to deform the stamp and circuit into the desired spherical shape. Finite element analysis gives the strain distribution (especially the maximum strain in the equipment and interconnections) and the uneven spacing between the transformed equipment. The advantage of this method is that it captures all the details of the device geometry and material, and therefore can be used to explore the effects of different designs of the transfer process to reduce the maximum strain and unevenness. However, this method is computationally intensive and therefore time-consuming because it involves a wider range of length scales and the modeling of a large number of structural devices on the stamp.

第二種方法為設備(小晶片)之單胞模型，該模型分析該等設備在負載情況下之機械效能。每一設備藉由一單胞表示，且其在機械負載下之回應(例如，撓曲及張力)經由有限元方法而得到徹底研究。接著藉由以互連連接之單胞來替代每一設備。接著將此單胞模型併入至有限元分析中以替代對設備及互連之詳細模型化。此外，在遠離球面之邊緣處，應變相對均勻以使得許多單胞可經整合且其效能可由粗略水準之模型表示。在接近球面邊緣處，應變高度不均勻，使得對設備之詳細模型化仍為必要的。該方法之優勢在於其顯著減少計算量。使用第一種方法中之滿標度有限元模型化來驗證此單胞模型。一旦經驗證，單胞模型即提供強有力之設計工具，因為其適用於對設備、互連及其間距的不同設計之快速探察。 The second method is a unit cell model of devices (small wafers), which analyzes the mechanical performance of these devices under load. Each device is represented by a unit cell, and its response under mechanical load (eg, deflection and tension) has been thoroughly studied through finite element methods. Then replace each device with interconnected cells. This unit cell model is then incorporated into the finite element analysis to replace the detailed modeling of equipment and interconnections. In addition, at the edge away from the spherical surface, the strain is relatively uniform so that many unit cells can be integrated and their performance can be represented by a rough level model. Near the edge of the spherical surface, the strain height is not uniform, making detailed modeling of the device still necessary. The advantage of this method is that it significantly reduces the amount of calculation. Use the full-scale finite element modeling in the first method to verify this unit cell model. Once verified, the single-cell model provides a powerful design tool because it is suitable for rapid exploration of different designs of devices, interconnects, and spacing.

圖38呈現關於如圖32所概括，將半球印模延伸為平坦幾何形狀(且將其鬆弛回至其半球形狀)的初步FEM結果。頂部圖框展示具有如同圖32中所示意性說明之幾何形狀的幾何形狀之半球印模之橫截面圖。此等結果展示延伸薄膜之應變中的如由其不均勻厚度所顯見之微小空間不均勻性。經由適當選擇藉由澆鑄及固化而形成印模時所抵靠之結構來對印模之厚度輪 廓進行涉及可消除此等不均勻性。然而，值得注意的是，一些不均勻應變為可接受的，因為(i)上推互連固有地容許扭曲，且(ii)小晶片無需在每一像素位置處完全居中；較大光偵測器將以均勻背面電極填充像素區，該背面電極可獨立於小晶片在像素區內的位置而建立至其之電接觸。 Figure 38 presents preliminary FEM results regarding extending the hemispherical impression to a flat geometry (and relaxing it back to its hemispherical shape) as outlined in Figure 32. The top frame shows a cross-sectional view of a hemispherical stamp having a geometric shape as illustrated schematically in FIG. 32. These results show small spatial non-uniformities in the strain of the stretched film as evident by its non-uniform thickness. By appropriately selecting the structure against which the impression is made by casting and curing, the thickness of the impression is rounded Contouring can eliminate these non-uniformities. However, it is worth noting that some non-uniform strain is acceptable because (i) the push-up interconnect inherently allows distortion, and (ii) the small chip does not need to be completely centered at each pixel location; larger light detection The device will fill the pixel area with a uniform back electrode, which can establish electrical contact to the chiplet independently of its position within the pixel area.

模型化亦可判定Si CMOS小晶片中應變之水準。系統應經設計以將此等小晶片應變保持於~0.1%至0.2%以下來避免電特性之改變及(可能地)歸因於斷裂或分層之機械失效。此模型化促進對印模及處理條件之設計以避免小晶片曝露於在此範圍以上的應變。 Modeling can also determine the level of strain in Si CMOS small chips. The system should be designed to keep these small chip strains below ~ 0.1% to 0.2% to avoid changes in electrical characteristics and (possibly) mechanical failure due to fracture or delamination. This modeling facilitates the design of impressions and processing conditions to avoid exposure of small wafers to strains above this range.

實例3：雙軸可延伸"波狀"矽奈米薄膜 Example 3: Biaxially extendable "wavy" silicon nanofilm

此實例引入雙軸可延伸形式之單晶矽，其由彈性體支撐物上之二維彎曲或"波狀"矽奈米薄膜組成。描述用於此等結構之製造程序，且呈現該等結構之幾何形狀之各種態樣及對於沿各個方向之單軸及雙軸應變的回應。此等系統之力學分析模型提供用於定量理解該等系統之行為之構架。此等類別之材料提供得到具有充分的二維可延伸性之高效能電子元件之途徑。 This example introduces biaxially extensible form of single crystal silicon, which consists of a two-dimensional curved or "wavy" silicon nanofilm on an elastomeric support. Describe the manufacturing process used for these structures, and present the various aspects of the geometry of these structures and the response to uniaxial and biaxial strains in various directions. The mechanical analysis models of these systems provide a framework for quantitatively understanding the behavior of these systems. These types of materials provide a way to obtain high-performance electronic components with sufficient two-dimensional extensibility.

提供機械可撓曲性之電子元件對於資訊顯示器、X射線成像光伏打設備及其他系統中之應用為所關注的。可逆可延伸性為一不同且更具技術挑戰性之機械特徵，其將致能無法藉由諸如智慧型外科手套、電子眼攝影機及個人保健監視器之僅可撓曲之電子元件實現的設備可能性。在得到此類型之電子元件之一方法中，可延伸導線使剛性設備島狀物互連以對於不可延伸之設備組件提供電路級可延伸性。在替代策略中，某些結構形式之薄單晶半導體及其他電子材料允許設備自身之可延伸性。近來之論證涉及在矽及砷化鎵之奈米織帶(厚度在數十與數百奈米之間且寬度在微米範圍內) 中使用彎曲一維"波狀"幾何形狀以在金屬氧化物半導體場效電晶體(MOSFET)、金屬半導體場效電晶體(MESFET)、pn接合二極體及肖特基電極中達成單軸可延伸性。此實例展示類似材料之奈米薄膜可成形為二維(2D)波狀幾何形狀以提供充分的2D可延伸性。描述該等系統之製造程序連同對該等系統之機械回應的詳細實驗表徵及分析模型化。 Electronic components that provide mechanical flexibility are of interest for applications in information displays, X-ray imaging photovoltaic devices, and other systems. Reversible extensibility is a different and more technically challenging mechanical feature that will enable device possibilities that cannot be achieved with only flexible electronic components such as smart surgical gloves, electronic eye cameras and personal health monitors . In one method of obtaining electronic components of this type, extensible wires interconnect rigid device islands to provide circuit-level scalability for non-extensible device components. In alternative strategies, thin single crystal semiconductors and other electronic materials in certain structural forms allow the extensibility of the device itself. Recent demonstrations have involved nanoribbons in silicon and gallium arsenide (thicknesses between tens and hundreds of nanometers and widths in the micrometer range) Uses a curved one-dimensional "wavy" geometry to achieve uniaxiality in metal oxide semiconductor field effect transistors (MOSFETs), metal semiconductor field effect transistors (MESFETs), pn junction diodes, and Schottky electrodes Extensibility. This example shows that a nano-film of similar material can be shaped into a two-dimensional (2D) wave geometry to provide sufficient 2D extensibility. Describe the manufacturing process of these systems and detailed experimental characterization and analysis modeling of the mechanical responses to these systems.

圖39示意性地說明用於在彈性體支撐物上形成二維可延伸Si奈米薄膜之步驟。對於此實例，由絕緣體上矽(SOI)晶圓(Soitec,Inc.，p型)製造此等薄膜，其始於藉由以光微影界定光阻劑之合適圖案且接著以反應性離子蝕刻(Plasma Therm RIE，SF6 40sccm，50毫托，100W)移除曝露之矽而形成頂部矽中之孔洞(~2.5μm之直徑及~25μm之間距)之正方陣列。此相同步驟界定薄膜之整體橫向尺寸，該尺寸對於此處報告之樣本處於3-5平方毫米之範圍內。厚度處於55nm與320nm之間。將經蝕刻之樣本浸沒於濃縮氫氟酸(HF 49%)中移除SiO2內埋層(145至1000nm厚)；在丙酮中清洗移除光阻劑。抵靠經研磨之矽晶圓澆鑄並固化聚二甲基矽氧烷(PDMS)之預聚物產生平坦彈性體基板(~4mm厚)。曝露於藉由強烈紫外光(240-260nm)形成之臭氧環境中5分鐘將疏水性PDMS表面(-CH3及-H端基)轉換為親水性狀態(-OH及-O-Si-O端基)。在對流烘箱中於70至180℃下暫時加熱該活性PDMS基板誘發受控程度之各向同性熱膨脹。使此元件與經處理之SOI晶圓接觸且接著再次將其剝離將整個奈米薄膜轉移至PDMS。對流烘箱中歷時數分鐘之繼續加熱促進薄膜與PDMS之間強黏著結合之形成。在最後步驟中，將奈米薄膜/PDMS結構i冷卻至室溫(約25℃)以釋放熱誘發之預加應變(△L/L)。此製程導致Si奈米薄膜及PDMS之附近表面區域中的二維(2D)波狀結構之起伏之自發形成。此等結構在一維週 期性波起主要作用之接近邊緣處、通常觀測到二維魚骨狀布局之內部區域中及無序魚骨狀結構經常發生的接近中央處顯示出不同狀態。魚骨狀區域以波紋中鄰近峰之間的距離(吾人稱作短波長λ)、波紋之振幅A1(圖1中未展示)及與魚骨狀結構中之鄰近"凹凸"之間的間隔相關聯之較長距離2 π/k2(沿x2方向)(吾人稱作長波長)為特徵。其他特徵長度為"凹凸"波長2 π/k1(沿x1方向，與長波長方向x2垂直)、凹凸之振幅A2、凹凸角θ。圖39之底部圖框示意性地說明此等特徵。 FIG. 39 schematically illustrates a step for forming a two-dimensional stretchable Si nano film on an elastomer support. For this example, these films were fabricated from silicon-on-insulator (SOI) wafers (Soitec, Inc., p-type), which started by defining the appropriate pattern of photoresist by photolithography and then etching with reactive ions (Plasma Therm RIE, SF 6 40sccm, 50 mTorr, 100W) Remove the exposed silicon to form a square array of holes (~ 2.5μm diameter and ~ 25μm spacing) in the top silicon. This same step defines the overall lateral dimension of the film, which is within the range of 3-5 square millimeters for the sample reported here. The thickness is between 55nm and 320nm. Immerse the etched samples in concentrated hydrofluoric acid (HF 49%) to remove the SiO 2 buried layer (145 to 1000 nm thick); wash in acetone to remove the photoresist. Casting and curing a prepolymer of polydimethylsiloxane (PDMS) against a polished silicon wafer produces a flat elastomer substrate (~ 4mm thick). Exposure to an ozone environment formed by intense ultraviolet light (240-260nm) for 5 minutes to convert the hydrophobic PDMS surface (-CH 3 and -H end groups) to a hydrophilic state (-OH and -O-Si-O ends base). Heating the active PDMS substrate temporarily in a convection oven at 70 to 180 ° C induces a controlled degree of isotropic thermal expansion. This device is brought into contact with the processed SOI wafer and then peeled off again to transfer the entire nanofilm to PDMS. Continue heating for several minutes in a convection oven to promote the formation of a strong adhesive bond between the film and PDMS. In the final step, the nanofilm / PDMS structure i is cooled to room temperature (about 25 ° C) to release the heat-induced pre-strain (ΔL / L). This process results in the spontaneous formation of two-dimensional (2D) wave-like structures in the surface area of the Si nanometer film and PDMS. These structures show different states near the edge where the one-dimensional periodic waves play a major role, usually observed in the internal area of the two-dimensional fishbone layout and near the center where disordered fishbone structures often occur. The fishbone area is related to the distance between the adjacent peaks in the ripple (I call it short wavelength λ), the amplitude A 1 of the ripple (not shown in Figure 1) and the distance between the adjacent "bumps" in the fishbone It is characterized by a long distance of 2 π / k 2 (along the x 2 direction) (I call it long wavelength). Other characteristic lengths are the "concavo-convex" wavelength 2 π / k 1 (along the x 1 direction, perpendicular to the long wavelength direction x 2 ), the amplitude A 2 of the concavo-convex, and the concave-convex angle θ. The bottom frame of Figure 39 illustrates these features schematically.

圖40之部分a-f展示對於具有100nm之厚度(約4×4mm2之橫向尺寸)及~3.8%之熱預加應變(藉由加熱至150℃而界定)的奈米薄膜，於魚骨狀波紋之形成期間之不同階段收集的光學顯微相片。此等影像指示兩階段之結構形成，該等階段中之第一者涉及在較大區上起主要作用之一維波紋繼之以撓曲此等波紋結構以最終在完全冷卻時形成緊密魚骨狀布局(圖40 d-f)。圖40h展示兩個特徵波長之時間演進。短波長傾向於隨著冷卻導致矽上的逐漸較大之壓縮應變(歸因於PDMS之相對較大之熱收縮)而減小。特定言之，此值自初始階段中之17至18μm降至魚骨狀結構變得突出時之~14.7μm，且最終在完全冷卻之狀態下降至~12.7μm。此波長在較大區上為均勻的(~5%之變化)。相反地，如自圖40g中之影像所顯而易見的，與魚骨狀布局相關聯之長波長顯示出寬廣範圍之值。在跨越此樣本之~100個點處之量測得到值之分布，其概述於圖40g之直方圖中。可由面外位移w=A1cos[k1x1+k1A2cos(k2x2)]表示魚骨狀結構(圖49)。此處，係數：波紋之振幅A1、長波長2 π/k2、凹凸波長2 π/k1及凹凸之振幅A2藉由對特定薄膜厚度、膜的機械特性及基板之分析而判定。短波長λ為(2 π/k1)sin(θ/2)。模型化使用如由量測而得之等同長度及波狀結構之週期而 判定的Si應變替代熱預加應變來作為施加之預加應變(圖50)。使Si變形之實際應變可能歸因於Si於PDMS上之負載效應而通常稍小於估計之熱預加應變。舉例而言，Si應變在3.8%之熱預加應變下為2.4%。對於該位移w，Si膜中之應力、應變及位移場可在A1、k1、A2及k2之方面自馮卡門板理論(Von Karman plate theory)獲得。自3D彈性理論獲得PDMS基板中之場。最小化由Si膜中之薄膜能量及撓曲能量及PDMS基板中之彈性能量組成之總能量給出A1、k1、A2及k2。Si及PDMS之楊氏模數及柏松比為ESi=130GPa、vSi=0.27、EPDMS=1.8MPa且vPDMS=0.5。實驗與模型均給出凹凸角θ為約90°。理論給出之短波長在2.4%之雙軸預加應變下為12.4μm，此與以上之實驗結果良好地符合。長波長2 π/k2之較大變化亦由理論計算所預測到，其為30至60μm。 Part af of FIG. 40 shows that for a nano-film with a thickness of 100 nm (a lateral dimension of about 4 × 4 mm 2 ) and a thermal pre-strain of ~ 3.8% (defined by heating to 150 ° C.), the fishbone corrugations Optical micrographs collected at different stages during the formation. These images indicate the formation of a two-stage structure, the first of these stages involves one-dimensional corrugations that play a major role on a larger area followed by flexing these corrugated structures to eventually form a tight fish bone when fully cooled Layout (Figure 40 df). Figure 40h shows the time evolution of two characteristic wavelengths. Short wavelengths tend to decrease as the cooling causes progressively larger compressive strains on the silicon (due to the relatively large thermal shrinkage of PDMS). In particular, this value was reduced from 17 to 18 μm in the initial stage to ~ 14.7 μm when the fishbone structure became prominent, and finally dropped to ~ 12.7 μm in a completely cooled state. This wavelength is uniform over a large area (~ 5% change). In contrast, as is apparent from the image in FIG. 40g, the long wavelength associated with the fishbone layout shows a wide range of values. The distribution of measured values at ~ 100 points across this sample is summarized in the histogram of Figure 40g. The fishbone structure can be represented by the out-of-plane displacement w = A 1 cos [k 1 x 1 + k 1 A 2 cos (k 2 x 2 )] (Figure 49). Here, the coefficients: the amplitude A 1 of the ripple, the long wavelength 2 π / k 2 , the uneven wavelength 2 π / k 1 and the amplitude A 2 of the unevenness are determined by analyzing the specific film thickness, the mechanical properties of the film, and the substrate. The short wavelength λ is (2 π / k 1 ) sin (θ / 2). Modeling uses the Si strain as determined by measuring the equivalent length and the period of the wave structure instead of the thermal pre-strain as the applied pre-strain (Figure 50). The actual strain that deforms Si may be due to the loading effect of Si on the PDMS and is usually slightly less than the estimated thermal pre-strain. For example, Si strain is 2.4% at a thermal pre-strain of 3.8%. For this displacement w, the stress, strain and displacement fields in the Si film can be obtained from Von Karman plate theory in terms of A 1 , k 1 , A 2 and k 2 . The field in the PDMS substrate is obtained from 3D elasticity theory. Minimizing the total energy consisting of the film energy and flexural energy in the Si film and the elastic energy in the PDMS substrate gives A 1 , k 1 , A 2 and k 2 . The Young's modulus and Poisson's ratio of Si and PDMS are E Si = 130 GPa, v Si = 0.27, E PDMS = 1.8 MPa, and v PDMS = 0.5. Both the experiment and the model gave a bump angle θ of about 90 °. The short wavelength given by theory is 12.4μm under the biaxial pre-strain of 2.4%, which is in good agreement with the above experimental results. The large change of the long wavelength 2 π / k 2 is also predicted by theoretical calculations, which is 30 to 60 μm.

圖41呈現類似於圖40之完全冷卻狀態所說明之結構的結構之原子力顯微鏡(atomic force microscope,AFM)及掃描電子顯微鏡(SEM)影像。此等影像清楚地展示，魚骨狀圖案以鋸齒狀結構為特徵，該等結構界定兩個特徵性方向，即使壓縮應變完全為各向同性亦如此。魚骨狀結構表示最小彈性能量組態，其減小系統中之總平面內應力且減輕兩個方向上之雙軸壓縮。因此，此幾何形狀相較於"棋盤形"及1D波紋布局而言在較大區上為較佳的，因為魚骨狀模式為此等三個模式中在所有方向上使平面內應力鬆弛而不誘發顯著延伸能量之唯一一者。僅在緊接凹凸處誘發顯著延伸。1D模式僅在一個方向上使預加應力降低。棋盤形模式在所有方向上降低應力，但其產生伴隨撓曲之顯著延伸能量。 FIG. 41 presents atomic force microscope (AFM) and scanning electron microscope (SEM) images of structures similar to those illustrated in the fully cooled state of FIG. 40. FIG. These images clearly show that the fishbone pattern is characterized by zigzag structures that define two characteristic directions, even if the compressive strain is completely isotropic. The fishbone structure represents the minimum elastic energy configuration, which reduces the total in-plane stress in the system and reduces the biaxial compression in both directions. Therefore, this geometry is better in larger areas than the "checkerboard" and 1D corrugated layouts, because the fishbone mode is the relaxation of in-plane stress in all directions among these three modes. The only one that does not induce significant extensional energy. Only significant extensions are induced immediately next to the bumps. The 1D mode only reduces the pre-stress in one direction. The checkerboard pattern reduces stress in all directions, but it generates significant extensional energy with deflection.

自AFM影像提取之兩個線切圖指示沿凹凸方向(輪廓i)及垂直於波紋(輪廓ii)的週期性(但僅近似正弦)之起伏輪廓。波紋之由輪廓ii判定之λ及 A1分別為12.8μm及0.66μm。由理論分析給出之為12.4μm之λ類似於實驗資料；然而，得自理論分析的A1為0.90μm，其為稍高於實驗結果之值。SEM影像清楚地展示如由在波紋之凸起及凹入區域中接近矽中之小孔洞的樣本之狀態所顯見之薄膜與PDMS之間的密切結合。此等影像亦指示波紋結構與此等孔洞之位置完全不相關，因為2.5μm之孔洞大小遠小於吾人之實驗中的變形模式之特徵性波長。對於波狀結構之幾何形狀對矽之厚度之依賴性的研究可提供對物理現象之額外理解且進一步驗證力學模型。圖42展示一些結果，包括對於類似熱應變以不同厚度形成於薄膜中之波紋結構的光學顯微相片以及波長與振幅。對於100nm之厚度，波紋之λ及A1分別為12.6(±0.37)μm及0.64(±0.07)μm，且對於320nm之厚度，其為45.1(±1.06)μm及1.95(±0.18)μm。此等值相當良好地對應於理論計算，該等理論計算得到λ及A1對於100nm之情況為12.4μm及0.90μm且對於320nm之情況分別為45.1μm及3.29μm。 The two line cuts extracted from the AFM image indicate periodic (but only approximately sinusoidal) undulating contours along the concave-convex direction (profile i) and perpendicular to the ripple (profile ii). The λ and A 1 of the ripple determined by the profile ii are 12.8 μm and 0.66 μm, respectively. The λ given by the theoretical analysis of 12.4 μm is similar to the experimental data; however, A 1 obtained from the theoretical analysis is 0.90 μm, which is a value slightly higher than the experimental results. The SEM image clearly shows the close bond between the thin film and PDMS as seen by the state of the sample close to the small holes in the silicon in the convex and concave areas of the corrugation. These images also indicate that the corrugated structure is completely unrelated to the location of these holes, because the 2.5 μm hole size is much smaller than the characteristic wavelength of the deformation mode in our experiment. The study of the dependence of the geometry of the wave structure on the thickness of silicon can provide additional understanding of physical phenomena and further validate the mechanical model. Figure 42 shows some results, including optical micrographs and wavelengths and amplitudes of corrugated structures formed in thin films of similar thickness with different thermal strains. For a thickness of 100 nm, the lambda and A 1 of the ripple are 12.6 (± 0.37) μm and 0.64 (± 0.07) μm, respectively, and for a thickness of 320 nm, they are 45.1 (± 1.06) μm and 1.95 (± 0.18) μm. These values correspond quite well to theoretical calculations, which yield λ and A 1 for 12.4 μm and 0.90 μm for 100 nm and 45.1 μm and 3.29 μm for 320 nm, respectively.

此等波狀薄膜提供各個平面內方向上之對於應變的真實可延伸性，此與藉由先前描述之織帶幾何形狀所提供之一維可延伸性形成對比。為了研究此態樣，吾人藉由使用經校準機械台及以熱誘發之3.8%的預加應變而製備之2D可延伸薄膜執行沿不同方向之單軸抗張延伸測試。圖43提供一些影像。在情況i中，沿長波紋之方向施加之拉伸應變(εst)使得魚骨狀結構"展開"(εst為1.8%)，逐漸導致完全延伸狀態(εst為3.8%)下的1D波狀幾何形狀。此延伸藉由柏松效應而在正交方向上誘發具有粗略等於拉伸應變之一半的振幅之壓縮應變。可藉由在此方向上壓縮波狀結構而適應此壓縮應變。在解除所施加之拉伸應變之後，原始魚骨狀波紋即恢復而顯示出與最初相當類似之結構。(圖51展示在5、10、15個延伸循環之後收集之光學顯 微相片)。 These corrugated films provide true extensibility to strain in various in-plane directions, in contrast to the one-dimensional extensibility provided by the webbing geometry described previously. To study this aspect, we performed a uniaxial tensile elongation test in different directions by using a calibrated mechanical table and a 2D stretchable film prepared with a thermally induced pre-strain of 3.8%. Figure 43 provides some images. In case i, the tensile strain (ε st ) applied in the direction of the long wave makes the fishbone structure "unfold" (ε st is 1.8%), gradually leading to 1D in the fully extended state (ε st is 3.8%) Wavy geometric shapes. This extension induces a compressive strain in the orthogonal direction with an amplitude roughly equal to one-half of the tensile strain by the Bosson effect. This compressive strain can be accommodated by compressing the wavy structure in this direction. After releasing the applied tensile strain, the original fishbone corrugations recovered and showed a structure similar to the original. (Figure 51 shows optical micrographs collected after 5, 10, and 15 extension cycles).

在對角方向上施加之拉伸應變(情況ii)展示類似結構改變，但在完全延伸時，1D波紋結構沿由施加之應變所界定之方向對準而非為初始幾何形狀。對於垂直情況iii，在較小應變(εst為1.8%)處，樣本之某些部分完全失去魚骨狀布局而沿延伸方向產生新的1D波紋。隨著增加之應變，較多區域經歷此變換直至整個區由此等定向之1D波紋組成。此等新形成之1D波紋垂直於原始波紋之定向；在解除之後，其即簡單地撓曲以形成無序魚骨狀幾何形狀。對於圖43b中所示之全部情況，波長均隨拉伸應變而增大且在解除之後即恢復至其原始值，即使在正交方向上由柏松效應誘發壓縮應力亦如此。此行為由於由魚骨狀波紋之展開所誘發的λ之增大而產生，該增大大於由柏松效應引起之此波長的減小。(圖52)對於情況i，凹凸波長2 π/k1(圖52A)在施加之拉伸應變εst下歸因於柏松效應而減小至2 π/k'1(圖52B)，亦即，k'1>k1。然而，相應凹凸角θ'歸因於魚骨狀結構之展開而大於角θ。短波長λ=(2 π/k1)sin(θ/2)變為λ'=(2 π/k'1)sin(θ'/2)，其在角改變之效應克服柏松效應時可大於λ。吾人之理論模型給出對於εst=0、1.8%及3.8%，λ=12.4、14.6及17.2μm，此證實了如在實驗中所觀測的，短波長隨施加之應變而增大。對於情況iii，λ及2 π/k1均隨施加之延伸應變而增大，因為波紋沿延伸應變之方向而鬆弛，且凹凸角θ未因柏松效應而顯著改變。亦藉由熱誘發之拉伸應變來研究彎曲薄膜之雙軸可延伸性(圖53)。由熱應變產生之魚骨狀波紋隨著對樣本加熱而緩慢消失；其在冷卻之後即完全恢復。 The tensile strain applied in the diagonal direction (case ii) shows a similar structural change, but when fully extended, the 1D corrugated structure is aligned in the direction defined by the applied strain rather than the initial geometry. For vertical case iii, at small strains (ε st is 1.8%), some parts of the sample completely lose the fishbone layout and produce new 1D ripples along the extension direction. With increasing strain, more regions undergo this transformation until the entire region is composed of 1D ripples of such orientation. These newly formed 1D corrugations are oriented perpendicular to the original corrugations; after being released, they simply flex to form a disordered fishbone geometry. For all cases shown in Fig. 43b, the wavelength increases with tensile strain and returns to its original value after being released, even if the compressive stress is induced by the Bosson effect in the orthogonal direction. This behavior is due to the increase in λ induced by the expansion of the fish-bone corrugations, which is greater than the decrease in this wavelength caused by the cypress effect. (Figure 52) For case i, the concave-convex wavelength 2 π / k 1 (Figure 52A) is reduced to 2 π / k ' 1 (Figure 52B) due to the Bosson effect under the applied tensile strain ε st (Figure 52B), also That is, k ' 1 > k 1 . However, the corresponding concave-convex angle θ 'is larger than the angle θ due to the expansion of the fishbone structure. The short wavelength λ = (2 π / k 1 ) sin (θ / 2) becomes λ '= (2 π / k' 1 ) sin (θ '/ 2), which can be changed when the effect of angle change overcomes the pine effect Greater than λ. Our theoretical model gives that for ε st = 0, 1.8% and 3.8%, λ = 12.4, 14.6 and 17.2 μm, this confirms that as observed in the experiment, the short wavelength increases with the applied strain. For case iii, both λ and 2 π / k 1 increase with the extension strain applied, because the ripple relaxes in the direction of the extension strain, and the bump angle θ does not change significantly due to the Bosson effect. The biaxial extensibility of the curved film was also studied by thermally induced tensile strain (Figure 53). The fishbone corrugation caused by thermal strain slowly disappears as the sample is heated; it completely recovers after cooling.

此等觀測結果僅適用於薄膜之中央區域。如圖39之底部圖框中所指示，薄膜之邊緣展示1D波紋結構，其中波向量沿邊緣而定向。圖44中展 示邊緣區域、中央區域及其之間的過渡區之AFM影像及線切圖輪廓。起源於Si之邊緣附近之1D波紋(頂部圖框)逐漸變得撓曲(中部圖框)直至其變換為中央區域中之魚骨狀幾何形狀(底部圖框)。此等區域中之λ值分別為16.6μm、13.7μm及12.7μm(自頂部圖框起)，其中A1為0.52μm、0.55μm及0.67μm。與邊緣處之1D波紋相對比，2D魚骨狀波紋具有較小λ及A1，此提示Si之內部區比邊緣受到較強的壓縮應變之影響。邊緣附近之應力狀態在某距離範圍內，由於薄膜之無牽引力邊緣而近似為單軸壓縮。此單軸壓縮平行於此自由邊緣，且因此導致沿該邊緣之1D波紋。然而，應力狀態在魚骨狀結構產生之中央區域中變為等雙軸壓縮。對於1D波紋邊緣與魚骨狀波紋之間的過渡區，不平衡雙軸壓縮造成具有較大凹凸角之"半"魚骨狀波紋。吾人之模型得到對於1D波紋分別為16.9μm及0.83μm之λ及A1及對於魚骨狀結構分別為12.4μm及0.90μm之λ及A1。此等結果與實驗觀測值相當良好地符合。 These observations only apply to the central area of the film. As indicated in the bottom frame of Figure 39, the edges of the film show a 1D corrugated structure, where the wave vectors are oriented along the edges. Figure 44 shows the AFM image and line cut contour of the edge area, the central area and the transition area between them. The 1D ripple (top frame) originating near the edge of Si gradually becomes flexed (middle frame) until it transforms into a fishbone geometry in the central area (bottom frame). The λ values in these areas are 16.6 μm, 13.7 μm, and 12.7 μm (framed from the top figure), where A 1 is 0.52 μm, 0.55 μm, and 0.67 μm. Compared with the 1D corrugation at the edge, the 2D fishbone corrugation has smaller λ and A 1 , which suggests that the inner region of Si is affected by stronger compressive strain than the edge. The stress state near the edge is within a certain distance, and it is approximately uniaxial compression due to the non-traction edge of the film. This uniaxial compression is parallel to this free edge, and therefore results in 1D ripples along the edge. However, the stress state becomes equibiaxial compression in the central area where the fishbone structure is generated. For the transition zone between the 1D corrugated edge and the fishbone corrugations, unbalanced biaxial compression results in a "half" fishbone corrugation with a large bump angle. We obtained for the 1D model λ 16.9μm and the corrugations are of 0.83μm and A 1 and fishbone-like structure for λ 12.4μm and 0.90μm, respectively, and the A 1. These results are in good agreement with the experimental observations.

為了進一步研究此等邊緣效應，吾人製造具有1000μm之長度及100μm、200μm、500μm及1000μm之寬度的矩形薄膜，其均處於同一PDMS基板上。圖45展示此等結構對於兩個不同水準之熱預加應變之光學顯微相片。在較低熱預加應變(約2.3%，圖45a)處，100μm及200μm寬之薄膜顯示出自一側至另一側的完全1D波紋，其在末端具有平坦未變形之區域。500μm寬之薄膜展示類似之1D波紋及平坦區域，但波紋在結構之中部具有微微撓曲之幾何形狀，其具有大體上小於100μm及200μm之情況的整體有序性及定向上之均勻性。對於1000μm之方塊，1D波紋存在於邊緣之中央區域中，其在角落中具有平坦區。薄膜之中央部分展示完全形成之魚骨狀幾何形狀。對於角落平坦區域，歸因於兩個自由邊緣而存在近 似無應力之狀態。在該等角落附近無波紋形成。隨著增大之預加應變(4.8%，圖45b)，所有情況下之平坦區域在大小上均減小。1D波紋狀態在100μm及200μm之織帶中持續，但顯著魚骨狀形態在500μm之情況的中央區域中出現。在較高預加應變處，等雙軸壓縮應變存在於500μm寬之薄膜的內部區域中。對於1000μm之方塊薄膜，魚骨狀狀態延伸至接近邊緣之區域。可將界定平坦區域之空間延伸之特徵長度標度(吾人稱作邊緣效應長度)Ledge估計為薄膜大小及預加應變的函數。圖45c展示指示對於此處研究之情況，此長度以獨立於薄膜之大小之方式隨預加應變之線性縮放的結果。隨著預加應變變得較高，單軸應變區域之長度變得較小。因此，可在接近兩個自由邊緣處之無應力區域中觀測到較短範圍之1D波紋形式及類似狀態。 To further study these edge effects, we manufactured rectangular thin films with a length of 1000 μm and widths of 100 μm, 200 μm, 500 μm, and 1000 μm, all on the same PDMS substrate. Figure 45 shows optical micrographs of these structures for two different levels of thermal pre-strain. At the lower thermal pre-strain (approximately 2.3%, Figure 45a), the 100 μm and 200 μm wide films showed complete 1D ripples from one side to the other with flat, undeformed areas at the ends. The 500 μm wide film exhibits similar 1D ripples and flat areas, but the ripples have a slightly deflecting geometry in the middle of the structure, which has overall order and orientation uniformity in the case of generally less than 100 μm and 200 μm. For a 1000 μm square, 1D ripples exist in the central area of the edge, which has flat areas in the corners. The central part of the film shows the fully formed fishbone geometry. For a flat corner area, due to the two free edges, there is an almost unstressed state. No ripples are formed near these corners. With increasing pre-strain (4.8%, Figure 45b), the flat area in all cases decreases in size. The 1D corrugated state persisted in the webs of 100 μm and 200 μm, but significant fish-bone morphology appeared in the central area of the case of 500 μm. At higher pre-strains, equibiaxial compressive strain exists in the inner region of the 500 μm wide film. For a 1000 μm square film, the fish-bone shape extends to the area close to the edge. The characteristic length scale defining the spatial extension of the flat area (I call it the edge effect length) L edge can be estimated as a function of film size and pre-strain. Figure 45c shows the results indicating that for this study, this length scales linearly with the pre-strain in a manner independent of the size of the film. As the pre-strain becomes higher, the length of the uniaxial strain region becomes smaller. Therefore, a shorter range of 1D ripple patterns and similar states can be observed in the unstressed areas near the two free edges.

圖46展示在包括圓形、橢圓形、六邊形及三角形之其他薄膜幾何形狀中形成之波狀結構的光學顯微相片。該等結果定性地與圖45之織帶及方塊中之觀測結果相一致。特定言之，邊緣區域展示平行於邊緣而定向之1D波紋。具有正交定向之波紋僅出現於距邊緣距離大於Ledge處。對於圓形，1D波紋歸因於薄膜之形狀而以全面徑向定向出現於接近邊緣處，魚骨狀波紋出現於中央。橢圓形顯示出類似行為，但在長軸之邊緣處具有平坦區域(歸因於此等區域中之較小曲率半徑)。對於六邊形及三角形形狀，銳角隅角(分別為120°及60°之角度)導致平坦區域。魚骨狀幾何形狀出現於六邊形之中央。三角形之中央展示對於此處所示之預加應變的水準，1D波紋之合併。對於具有清角之形狀(例如，六邊形、三角形及橢圓形之尖端)，在隅角附近不存在波紋，因為兩個相交之自由邊緣(未必垂直)給出無應力狀態。對於三角形形狀，不存在足夠空間來產生魚骨狀結構，即 使是在中央區域中亦如此。 Figure 46 shows optical micrographs of wavy structures formed in other film geometries including circles, ellipses, hexagons, and triangles. These results are qualitatively consistent with the observations in the webbing and squares of Figure 45. In particular, the edge region exhibits 1D ripples oriented parallel to the edge. Ripples with orthogonal orientations only appear at distances greater than L edge from the edge. For round shapes, 1D ripples appear near the edges in a full radial orientation due to the shape of the film, and fish-bone ripples appear in the center. The ellipse shows similar behavior, but has flat areas at the edges of the long axis (due to the smaller radius of curvature in these areas). For hexagonal and triangular shapes, acute corners (angles of 120 ° and 60 °, respectively) result in flat areas. The fish-bone geometry appears in the center of the hexagon. The center of the triangle shows the combination of 1D ripples for the pre-strained level shown here. For shapes with clear corners (for example, the tips of hexagons, triangles, and ellipses), there are no ripples near the corners, because the two free edges that intersect (not necessarily perpendicular) give an unstressed state. For triangular shapes, there is not enough space to create a fishbone structure, even in the central area.

薄膜自身提供達成雙軸可延伸電子設備之途徑。可利用上文概述之邊緣效應來實現對於該等設備之特定類別可為有用之特定結果。特定言之，在成像系統中，於光偵測器之位置處保持平坦未變形區域以避免在此等設備具有波狀形狀時發生之非理想狀態可能具有價值。圖47呈現達成此結果之可延伸薄膜之一些代表性實例。此等結構由以30μm×150μm之織帶(對於正交織帶而言為30μm×210μm)在豎直及水平方向上(圖47a、圖47c)及在豎直、水平及對角方向上(圖47e、圖47g)連接的100μm×100μm之正方島狀物組成。織帶中之波紋之振幅及波長的改變提供以在較大程度上避免正方島狀物之區域中之變形的方式來適應所施加之應變之手段。吾人檢查此等結構在若干不同所施加應變下之行為。圖47之部分a及e展示在藉由於烘箱中加熱樣本而施加的較低應變(約2.3%)之狀態中之代表性情況。圖47之部分c及g展示在藉由使用機械台而施加之相對較高的雙軸應變(約15%)下之相同結構。如所顯而易見的，在低應變狀態下島狀物保持平坦；在足夠高之應變下，開始於此等區域中形成波紋結構。如傾斜角度之SEM影像(圖47b、圖47d、圖47f、圖47h)中所示，在所有應變下，PDMS與Si之間的良好黏著得以保持。圖47之部分b及d中之高放大率SEM影像的插圖亦證實Si與PDMS之強結合。 The film itself provides a way to achieve biaxially extendable electronic devices. The edge effects outlined above can be used to achieve specific results that may be useful for specific categories of such devices. In particular, in imaging systems, it may be valuable to maintain a flat, undeformed area at the location of the light detector to avoid non-ideal conditions that occur when these devices have a wavy shape. Figure 47 presents some representative examples of stretchable films that achieve this result. These structures consist of a webbing of 30 μm × 150 μm (30 μm × 210 μm for orthogonal webbing) in the vertical and horizontal directions (Fig. 47a, 47c) and in the vertical, horizontal and diagonal directions (Fig. 47e , Figure 47g) connected by a square island of 100μm × 100μm. Changes in the amplitude and wavelength of the ripples in the webbing provide a means to adapt to the applied strain in a manner that avoids deformation in the area of square islands to a greater extent. We examine the behavior of these structures under a number of different applied strains. Parts a and e of Fig. 47 show a representative situation in the state of lower strain (about 2.3%) applied by heating the sample in an oven. Parts c and g of FIG. 47 show the same structure under relatively high biaxial strain (about 15%) applied by using a mechanical table. As is obvious, the islands remain flat under low strain conditions; at sufficiently high strains, a corrugated structure starts to form in these areas. As shown in the SEM images of the tilt angle (Figure 47b, Figure 47d, Figure 47f, Figure 47h), under all strains, good adhesion between PDMS and Si is maintained. The insets of the high-magnification SEM images in parts b and d of Fig. 47 also confirmed the strong binding of Si to PDMS.

總而言之，矽之奈米薄膜可與預加應變之彈性體基板整合以產生具有幾何形狀之一範圍的2D "波狀"結構。此等系統之機械行為的許多態樣與理論預測之行為良好地一致。此等結果對於電子元件在使用期間或在安裝期間需要充分可延伸性之系統中之應用為有用的。 In summary, nano-silicon films of silicon can be integrated with pre-strained elastomeric substrates to produce 2D "wavy" structures with a range of geometric shapes. Many aspects of the mechanical behavior of these systems are in good agreement with theoretically predicted behavior. These results are useful for applications in systems where electronic components require sufficient scalability during use or during installation.

參考文獻 references

1. Duan, X. & Lieber, C. M. General synthesis of compound semiconductor nanowires. Adv. Mater. 12, 298-302 (2000)。 1. Duan, X. & Lieber, C. M. General synthesis of compound semiconductor nanowires. Adv. Mater. 12, 298-302 (2000).

2. Xiang, J., Lu, W., Hu, Y., Wu, Y., Yan, H. & Lieber, C. M. Ge/Si nanowire heterostructures as high-performance field-effect transistors. Nature 441, 489-493 (2006)。 2. Xiang, J., Lu, W., Hu, Y., Wu, Y., Yan, H. & Lieber, CM Ge / Si nanowire heterostructures as high-performance field-effect transistors. Nature 441, 489-493 (2006).

3. Wu, Y., Yan, H., Huang, M., Messer, B., Song, J. H. & Yang, P. Inorganic semiconductor nanowires: rational growth, assembly, and novel properties. Chem. Eur. J. 8, 1261-1268 (2002)。 3. Wu, Y., Yan, H., Huang, M., Messer, B., Song, JH & Yang, P. Inorganic semiconductor nanowires: rational growth, assembly, and novel properties. Chem. Eur. J. 8 , 1261-1268 (2002).

4. Pan, Z. W., Dai, Z. R. & Wang, Z. L. Nanobelts of semiconducting oxides. Science 291, 1947-1949 (2001)。 4. Pan, Z. W., Dai, Z. R. & Wang, Z. L. Nanobelts of semiconducting oxides. Science 291, 1947-1949 (2001).

5. Peng, X., Manna, L, Yang, W., Wickham, J., Scher, E., Kadavanich, A. & Alivisatos, A. P. Shape control of CdSe nanocrystals. Nature 404, 59-61 (2000)。 5. Peng, X., Manna, L, Yang, W., Wickham, J., Scher, E., Kadavanich, A. & Alivisatos, A. P. Shape control of CdSe nanocrystals. Nature 404, 59-61 (2000).

6. Wang, D., Chang, Y.-L, Lu, Z. & Dai, H. Oxidation resistant germanium nanowires: bulk synthesis, long chain alkanethiol functionalization, and Langmuir-Blodgett assembly. J. Am. Chem. Soc. 127, 11871-11875 (2005)。 6. Wang, D., Chang, Y.-L, Lu, Z. & Dai, H. Oxidation resistant germanium nanowires: bulk synthesis, long chain alkanethiol functionalization, and Langmuir-Blodgett assembly. J. Am. Chem. Soc. 127, 11871-11875 (2005).

7. Huang, M. H., Wu, Y., Feick, H., Tran, N., Weber, E. & Yang, P. Catalytic growth of zinc oxide nanowires by vapor transport. Adv. Mater. 13, 113-116 (2001)。 7. Huang, MH, Wu, Y., Feick, H., Tran, N., Weber, E. & Yang, P. Catalytic growth of zinc oxide nanowires by vapor transport. Adv. Mater. 13, 113-116 ( 2001).

8. Gudiksen, M. S., Wang, J. & Lieber, C. M. Synthetic control of the diameter and length of single crystal semiconductor nanowires. J. Phys. Chem. B 105, 4062-4064 (2001)。 8. Gudiksen, M. S., Wang, J. & Lieber, C. M. Synthetic control of the diameter and length of single crystal semiconductor nanowires. J. Phys. Chem. B 105, 4062-4064 (2001).

9. Yu, H., Li, J., Loomis, R. A., Wang, L.-W. & Buhro, W. E. Two-versus three-dimensional quantum confinement in indium phosphide wires and dots. Nat. Mater. 2, 517-520 (2003)。 9. Yu, H., Li, J., Loomis, RA, Wang, L.-W. & Buhro, WE Two-versus three-dimensional quantum confinement in indium phosphide wires and dots. Nat. Mater. 2, 517- 520 (2003).

10. Sun, Y. & Rogers, J. A. Fabricating semiconductor nano/microwires and transfer printing ordered arrays of them onto plastic substrates. Nano Lett. 4, 1953-1959 (2004)。 10. Sun, Y. & Rogers, J. A. Fabricating semiconductor nano / microwires and transfer printing ordered arrays of them onto plastic substrates. Nano Lett. 4, 1953-1959 (2004).

11. Yin, Y., Gates, B. & Xia, Y. A soft lithography approach to the fabrication of nanostructures of single crystalline silicon with well-defined dimensions and shapes. 12, 1426-1430 (2000)。 11. Yin, Y., Gates, B. & Xia, Y. A soft lithography approach to the fabrication of nanostructures of single crystalline silicon with well-defined dimensions and shapes. 12, 1426-1430 (2000).

12. Kodambaka, S., Hannon, J. B., Tromp, R. M. & Ross, F. M. Control of Si nanowire growth by oxygen. Nano Lett. 6, 1292-1296 (2006)。 12. Kodambaka, S., Hannon, J. B., Tromp, R. M. & Ross, F. M. Control of Si nanowire growth by oxygen. Nano Lett. 6, 1292-1296 (2006).

13. Shan, Y., Kalkan, A. K., Peng, C.-Y. & Fonash, S. J. From Si source gas directly to positioned, electrically contacted Si nanowires: the self-assembling "grow-in-place" approach. Nano Lett. 4, 2085-2089 (2004)。 13. Shan, Y., Kalkan, AK, Peng, C.-Y. & Fonash, SJ From Si source gas directly to positioned, electrically contacted Si nanowires: the self-assembling "grow-in-place" approach. Nano Lett . 4, 2085-2089 (2004).

14. He, R., Cao, D., Fan, R., Hochbaum, A. I., Carraro, C, Maboudian, R. & Yang, P. Si nanowire bridges in microtrenches: integration of growth into device fabrication. Adv. Mater. 17, 2098-2102 (2005)。 14. He, R., Cao, D., Fan, R., Hochbaum, AI, Carraro, C, Maboudian, R. & Yang, P. Si nanowire bridges in microtrenches: integration of growth into device fabrication. Adv. Mater . 17, 2098-2102 (2005).

15. Lee, K. J., Motala, M. J., Meitl, M. A., Childs, W. R., Menard, E., Shim, A. K., Rogers, J. A. & Nuzzo, R. G. Large-area, selective transfer of microstructured silicon: a printing-based approach to high- performance thin-film transistors supported on flexible substrates. Adv. Mater. 17, 2332-2336 (2005)。 15. Lee, KJ, Motala, MJ, Meitl, MA, Childs, WR, Menard, E., Shim, AK, Rogers, JA & Nuzzo, RG Large-area, selective transfer of microstructured silicon: a printing-based approach to high- performance thin-film transistors supported on flexible substrates. Adv. Mater. 17, 2332-2336 (2005).

16. Gao, P. X., Ding, Y., Mai, W., Hughes, W. L., Lao, C. & Wang, Z. L. Conversion of zinc oxide nanobelts into superlattice-structured nanohelices. Science 309, 1700-1704 (2005)。 16. Gao, P. X., Ding, Y., Mai, W., Hughes, W. L., Lao, C. & Wang, Z. L. Conversion of zinc oxide nanobelts into superlattice-structured nanohelices. Science 309, 1700-1704 (2005).

17. Kong, X. Y., Ding, Y., Yang, R. & Wang, Z. L. Single-crystal nanorings formed by epitaxial self-coiling of polar nanobelts. Science 303, 1348-1351 (2004)。 17. Kong, X. Y., Ding, Y., Yang, R. & Wang, Z. L. Single-crystal nanorings formed by epitaxial self-coiling of polar nanobelts. Science 303, 1348-1351 (2004).

18. Chen, P., Chua, S. J., Wang, Y. D., Sander, M. D. & Fonstad, C. G. InGaN nanorings and nanodots by selective area epitaxy. Appl. Phys. Lett. 87, 143111 (2005)。 18. Chen, P., Chua, S. J., Wang, Y. D., Sander, M. D. & Fonstad, C. G. InGaN nanorings and nanodots by selective area epitaxy. Appl. Phys. Lett. 87, 143111 (2005).

19. Manna, L, Milliron, D. J., Meisel, A., Scher, E. C. & Alivisatos, A. P. Controlled growth of tetrapod-branched inorganic nanocrystals. Nat. Mater. 2, 382-385 (2003)。 19. Manna, L, Milliron, D. J., Meisel, A., Scher, E. C. & Alivisatos, A. P. Controlled growth of tetrapod-branched inorganic nanocrystals. Nat. Mater. 2, 382-385 (2003).

20. Dick, K. A., Deppert, K., Larsson, M. W., Mårtensson, T., Seifert, W., Wallenberg, L. R. & Samuelson, L. Synthesis of branched 'nanotrees' by controlled seeding of multiple branching events. Nat. Mater. 3, 380-384 (2004)。 20. Dick, KA, Deppert, K., Larsson, MW, Mårtensson, T., Seifert, W., Wallenberg, LR & Samuelson, L. Synthesis of branched 'nanotrees' by controlled seeding of multiple branching events. Nat. Mater . 3, 380-384 (2004).

21. Khang, D.-Y., Jiang, H., Huang, Y. & Rogers, J. A. A stretchable form of single-crystal silicon for high-performance electronics on rubber substrates. Science 311, 208-212 (2006)。 21. Khang, D.-Y., Jiang, H., Huang, Y. & Rogers, J. A. A stretchable form of single-crystal silicon for high-performance electronics on rubber substrates. Science 311, 208-212 (2006).

22. Schmidt, O. G. & Eberl, K. Thin solid films roll up into nanotubes. Nature 410, 168-168 (2001)。 22. Schmidt, O. G. & Eberl, K. Thin solid films roll up into nanotubes. Nature 410, 168-168 (2001).

23. Zhang, L, Ruh, E., Grützmacher, D., Dong, L, Bell, D. J., Nelson, B. J. & Schönenberger, C. Anomalous coiling of SiGe/Si and SiGe/Si/Cr helical nanobelts. Nano Lett. 6, 1311 -1317 (2006)。 23. Zhang, L, Ruh, E., Grützmacher, D., Dong, L, Bell, DJ, Nelson, BJ & Schönenberger, C. Anomalous coiling of SiGe / Si and SiGe / Si / Cr helical nanobelts. Nano Lett. 6, 1311 -1317 (2006).

24. Jin, H.-C, Abelson, J. R., Erhardt, M. K. & Nuzzo, R. G. Soft lithographic fabrication of an image sensor array on a curved substrate. J. Vac. Sci. Technol. B 22, 2548-2551 (2004)。 24. Jin, H.-C, Abelson, JR, Erhardt, MK & Nuzzo, RG Soft lithographic fabrication of an image sensor array on a curved substrate. J. Vac. Sci. Technol. B 22, 2548-2551 (2004) .

25. Someya, T., Sekitani, T., Iba, S., Kato, Y., Kawaguchi, H. & Sakurai, T. A large-area, flexible pressure sensor matrix with organic field-effect transistors for artificial skin applications. Proc. Natl. Acad. Sic. U.S.A. 101, 9966-9970 (2004)。 25. Someya, T., Sekitani, T., Iba, S., Kato, Y., Kawaguchi, H. & Sakurai, T. A large-area, flexible pressure sensor matrix with organic field-effect transistors for artificial skin applications . Proc. Natl. Acad. Sic. USA 101, 9966-9970 (2004).

26. Nathan, A., Park, B., Sazonov, A., Tao, S., Chan, I., Servati, P., Karim, K., Charania, T., Striakhilev, D., Ma, Q. & Murthy, R. V. R. Amorphous silicon detector and thin film transistor technology for large-area imaging of X-rays. Microelectronics J. 31, 883-891 (2000)。 26. Nathan, A., Park, B., Sazonov, A., Tao, S., Chan, I., Servati, P., Karim, K., Charania, T., Striakhilev, D., Ma, Q . & Murthy, RVR Amorphous silicon detector and thin film transistor technology for large-area imaging of X-rays. Microelectronics J. 31, 883-891 (2000).

27. Lacour, S. P., Jones, J., Wagner, S., Li, T. & Suo, Z. Stretchable interconnects for elastic electronic surfaces. Proc. IEEE 93, 1459-1467 (2005)。 27. Lacour, S. P., Jones, J., Wagner, S., Li, T. & Suo, Z. Stretchable interconnects for elastic electronic surfaces. Proc. IEEE 93, 1459-1467 (2005).

28. Childs, W. R., Motala, M. J., Lee, K. J. & Nuzzo, R. G. Masterless soft lithography: patterning UV/Ozone-induced adhesion on poly(dimethylsiloxane) surfaces. Langmuir 21, 10096-10105 (2005)。 28. Childs, W. R., Motala, M. J., Lee, K. J. & Nuzzo, R. G. Masterless soft lithography: patterning UV / Ozone-induced adhesion on poly (dimethylsiloxane) surfaces. Langmuir 21, 10096-10105 (2005).

29. Sun, Y., Kumar, V., Adesida, I. & Rogers, J. A. Buckled and wavy ribbons of GaAs for high-performance electronics on elastomeric substrates. Adv. Mater, in press。 29. Sun, Y., Kumar, V., Adesida, I. & Rogers, J. A. Buckled and wavy ribbons of GaAs for high-performance electronics on elastomeric substrates. Adv. Mater, in press.

30. Sun, Y., Khang, D.-Y., Hua, F., Hurley, K. Nuzzo, R. G. & Rogers, J. A. Photolithographic route to the fabrication of micro/nanowires of III-V semiconductors. Adv. Funct. Mater. 15, 30-40 (2005)。 30. Sun, Y., Khang, D.-Y., Hua, F., Hurley, K. Nuzzo, RG & Rogers, JA Photolithographic route to the fabrication of micro / nanowires of III-V semiconductors. Adv. Funct. Mater. 15, 30-40 (2005).

32. Loo, Y.-L.; Someya, T., Baldwin, K. W., Bao, Z., Ho, P., Dodabalapur, A., Katz, H. E. & Rogers, J. A. Soft, conformable electrical contacts for organic semiconductors: high-resolution plastic circuits by lamination. Proc. Natl. Acad. Sci. U.S.A. 99, 10252-10256 (2002)。 32. Loo, Y.-L .; Someya, T., Baldwin, KW, Bao, Z., Ho, P., Dodabalapur, A., Katz, HE & Rogers, JA Soft, conformable electrical contacts for organic semiconductors: High-resolution plastic circuits by lamination. Proc. Natl. Acad. Sci. USA 99, 10252-10256 (2002).

33. Suo, Z., Ma, E. Y., Gleskova, H., Wagner, S. Mechanics of rollable and foldable film-on-foil electronics. Appl. Phys. Lett. 74, 1177-1179 (1999)。 33. Suo, Z., Ma, E. Y., Gleskova, H., Wagner, S. Mechanics of rollable and foldable film-on-foil electronics. Appl. Phys. Lett. 74, 1177-1179 (1999).

P. Mandlik, S. P. Lacour, J. W. Li, S. Y. Chou，及S. Wagner, leee Electron Device Letters 27, 650-652 (2006)。 P. Mandlik, S. P. Lacour, J. W. Li, S. Y. Chou, and S. Wagner, leee Electron Device Letters 27, 650-652 (2006).

D. S. Gray, J. Tien及C. S. Chen, Advanced Materials 16, 393-+ (2004)。 D. S. Gray, J. Tien and C. S. Chen, Advanced Materials 16, 393- + (2004).

S. P. Lacour, S. Wagner, Z. Y. Huang及Z. Suo, Applied Physics Letters 82, 2404-2406 (2003)。 S. P. Lacour, S. Wagner, Z. Y. Huang and Z. Suo, Applied Physics Letters 82, 2404-2406 (2003).

S. P. Lacour, J. Jones, S. Wagner, T. Li及Z. G. Suo, Proceedings of the leee 93, 1459-1467 (2005)。 S. P. Lacour, J. Jones, S. Wagner, T. Li and Z. G. Suo, Proceedings of the leee 93, 1459-1467 (2005).

J. Jones, S. P. Lacour, S. Wagner及Z. G. Suo, Journal of Vacuum Science & Technology A 22, 1723-1725 (2004)。 J. Jones, S. P. Lacour, S. Wagner and Z. G. Suo, Journal of Vacuum Science & Technology A 22, 1723-1725 (2004).

S. P. Lacour, J. Jones, Z. Suo及S. Wagner, leee Electron Device Letters 25, 179-181 (2004)。 S. P. Lacour, J. Jones, Z. Suo and S. Wagner, leee Electron Device Letters 25, 179-181 (2004).

W. T. S. Huck, N. Bowden, P. Onck, T. Pardoen, J. W. Hutchinson及G. M. Whitesides, Langmuir16, 3497-3501 (2000)。 W. T. S. Huck, N. Bowden, P. Onck, T. Pardoen, J. W. Hutchinson and G. M. Whitesides, Langmuir 16, 3497-3501 (2000).

N. Bowden, S. Brittain, A. G. Evans, J. W. Hutchinson及G. M. Whitesides, Nature 393, 146-149 (1998)。 N. Bowden, S. Brittain, A. G. Evans, J. W. Hutchinson and G. M. Whitesides, Nature 393, 146-149 (1998).

S. Wagner, S. P. Lacour, J. Jones, P. H. I. Hsu, J. C. Sturm, T. Li及Z. G. Suo, Physica E-Low-Dimensional Systems & Nanostructures 25, 326-334 (2004)。 S. Wagner, S. P. Lacour, J. Jones, P. H. I. Hsu, J. C. Sturm, T. Li and Z. G. Suo, Physica E-Low-Dimensional Systems & Nanostructures 25, 326-334 (2004).

H. Kudo, T. Sawada, E. Kazawa, H. Yoshida, Y. Iwasaki及K. Mitsubayashi, Biosensors & Bioelectronics 22, 558-562 (2006)。 H. Kudo, T. Sawada, E. Kazawa, H. Yoshida, Y. Iwasaki and K. Mitsubayashi, Biosensors & Bioelectronics 22, 558-562 (2006).

T. Li, Z. G. Suo, S. P. Lacour及S. Wagner, Journal of Materials Research 20, 3274-3277 (2005)。 T. Li, Z. G. Suo, S. P. Lacour and S. Wagner, Journal of Materials Research 20, 3274-3277 (2005).

S. P. Lacour, D. Chan, S. Wagner, T. Li及Z. G. Suo, Applied Physics Letters 88 (2006)。 S. P. Lacour, D. Chan, S. Wagner, T. Li and Z. G. Suo, Applied Physics Letters 88 (2006).

S. P. Lacour, C. Tsay及S. Wagner, leee Electron Device Letters 25, 792-794 (2004)。 S. P. Lacour, C. Tsay and S. Wagner, leee Electron Device Letters 25, 792-794 (2004).

S. P. Lacour, S. Wagner, R. J. Narayan, T. Li及Z. G. Suo, Journal of Applied Physics 100 (2006)。 S. P. Lacour, S. Wagner, R. J. Narayan, T. Li and Z. G. Suo, Journal of Applied Physics 100 (2006).

Reuss, R. H等人，Proc. IEEE 2005, 93, 1239。 Reuss, R. H and others, Proc. IEEE 2005, 93, 1239.

Jain, K.等人，Proc. IEEE 2005, 93, 1500。 Jain, K. et al., Proc. IEEE 2005, 93, 1500.

Nathan, A.等人，Microelectron. Reliab. 2002, 42, 735。 Nathan, A. et al., Microelectron. Reliab. 2002, 42, 735.

Someya, T等人，T. Proc. Natl. Acad. Sci. U.S.A. 2004, 101, 9966。 Someya, T et al., T. Proc. Natl. Acad. Sci. U.S.A. 2004, 101, 9966.

Hsu, P. H. I.等人，IEEE Trans. Electron. DeV. 2004, 51, 371。 Hsu, P. H. I. et al., IEEE Trans. Electron. DeV. 2004, 51, 371.

Jin, H. C.等人，Vac. Sci. Technol., B: Microelectron. Nanometer Struct.-Process., Meas., Phenom. 2004, 22, 2548。 Jin, H. C. et al., Vac. Sci. Technol., B: Microelectron. Nanometer Struct.-Process., Meas., Phenom. 2004, 22, 2548.

Nathan, A.；等人，Microelectron. J. 2000, 31, 883。 Nathan, A .; et al., Microelectron. J. 2000, 31, 883.

Someya, T.等人，Proc. Natl. Acad. Sci. U.S.A. 2005, 103, 12321。 Someya, T. et al., Proc. Natl. Acad. Sci. U.S.A. 2005, 103, 12321.

Lacour, S. P.等人，Proc. IEEE 2005, 93, 1459. (c)。 Lacour, S. P. et al., Proc. IEEE 2005, 93, 1459. (c).

Lacour, S. P.等人，Appl. Phys. Lett. 2003, 82, 2404。 Lacour, S. P. et al., Appl. Phys. Lett. 2003, 82, 2404.

Khang, D.-Y.等人，Science 2006, 311, 208。 Khang, D.-Y. et al. Science 2006, 311, 208.

Sun, Y.等人，Adv. Mater. 2006, 18, 2857。 Sun, Y. et al., Adv. Mater. 2006, 18, 2857.

Sun, Y.等人，Nat. Nanotechnol. 2007, 1, 201。 Sun, Y. et al., Nat. Nanotechnol. 2007, 1, 201.

Ouyang, M.等人，Chem. Mater. 2000, 12, 1591。 Ouyang, M. et al., Chem. Mater. 2000, 12, 1591.

Childs, W. R.; Nuzzo, R. G. J. Am. Chem. Soc. 2002, 124, 13583。 Childs, W. R .; Nuzzo, R. G. J. Am. Chem. Soc. 2002, 124, 13583.

Efimenko, K.等人，J. Colloid Interface Sci. 2002, 254, 306。 Efimenko, K. et al., J. Colloid Interface Sci. 2002, 254, 306.

Hillborg, H.等人，Langmuir 2004, 20, 785。 Hillborg, H. et al., Langmuir 2004, 20, 785.

Buma, T.等人，Appl. Phys. Lett. 2001, 79, 548。 Buma, T. et al., Appl. Phys. Lett. 2001, 79, 548.

Properties of Silicon; INSPEC: New York, 1998。The coefficients of thermal expansion are RPDMS) 3.1x10-4K-1及αSi) 2.6x10-6K-1 for PDMS substrate及Si nanomembrane, respectively. The thermal prestrain for the samples prepared at 150℃ was calculated by AαAT=(3.1x10-4-2.6x10-6)(150-25)=3.8%。 Properties of Silicon; INSPEC: New York, 1998. The coefficients of thermal expansion are RPDMS) 3.1x10 -4 K -1 and α Si ) 2.6x10 -6 K -1 for PDMS substrate and Si nanomembrane, respectively. The thermal prestrain for the samples prepared at 150 ℃ was calculated by AαAT = (3.1x10 -4 -2.6x10 -6 ) (150-25) = 3.8%.

Timoshenko, S. Theory of Plates及Shells; McGraw-Hill: New York, 1940。 Timoshenko, S. Theory of Plates and Shells; McGraw-Hill: New York, 1940.

Timoshenko, S.; Goodier, J. N. Theory of Elasticity, 3rd ed.; McGraw-Hill: New York, 1969。 Timoshenko, S .; Goodier, J. N. Theory of Elasticity, 3rd ed .; McGraw-Hill: New York, 1969.

Chen, X.; Hutchinson, J. W. J. Appl. Mech. Trans. ASME 2004, 71, 597。 Chen, X .; Hutchinson, J. W. J. Appl. Mech. Trans. ASME 2004, 71, 597.

Chen, X.; Hutchinson, J. W. Scr. Mater. 2004, 50, 797。 Chen, X .; Hutchinson, J. W. Scr. Mater. 2004, 50, 797.

Huang, Z. Y. et al. J. Mech. Phys. Solids 2005, 53, 2101。 Huang, Z. Y. et al. J. Mech. Phys. Solids 2005, 53, 2101.

Bietsch, A.; Michel, B. J. Appl. Phys. 2000, 88, 4310。 Bietsch, A .; Michel, B. J. Appl. Phys. 2000, 88, 4310.

Ohzono, T.; Shimomura, M. Phys. Rev. B 2004, 69, 132202。 Ohzono, T .; Shimomura, M. Phys. Rev. B 2004, 69, 132202.

Ohzono, T.; Shimomura, M. Langmuir 2005, 21, 7230。 Ohzono, T .; Shimomura, M. Langmuir 2005, 21, 7230.

實例4：藉由使用印刷半導體奈米材料而得到之異質整合式三維電子元件 Example 4: Heterogeneous integrated three-dimensional electronic components obtained by using printed semiconductor nanomaterials

吾人已開發一種簡單方法來將寬廣類別之相異材料組合至具有二維或三維(3D)布局之異質整合式(HGI)電子系統中。該製程始於不同半導體奈米材料(例如，單壁碳奈米管及氮化鎵、矽及砷化鎵之單晶奈米線/織帶)於單獨基板上之合成。對使用柔軟印模及此等基板作為供體的附加轉印製程繼之以設備及互連之形成之重複應用產生將此等(或其他)半導體奈米材料的任何組合併入於剛性或可撓性設備基板上之高效能3D-HGI電子元件。此通用方法可產生使用其他技術難以達成或不可能達成的寬廣範圍之不常見電子系統。 We have developed a simple method to combine a wide range of dissimilar materials into a heterogeneous integrated (HGI) electronic system with a two-dimensional or three-dimensional (3D) layout. The process begins with the synthesis of different semiconductor nanomaterials (eg, single-walled carbon nanotubes and single crystal nanowires / ribbons of gallium nitride, silicon, and gallium arsenide) on separate substrates. The repeated application of additional transfer processes that use flexible stamps and these substrates as donors, followed by the formation of equipment and interconnects results in the incorporation of any combination of these (or other) semiconductor nanomaterials in rigid or High-performance 3D-HGI electronic components on flexible device substrates. This general method can produce a wide range of uncommon electronic systems that are difficult or impossible to achieve using other technologies.

許多現有及新興電子設備受益於相異類別之半導體向二維或三維(2D或3D)布局的單一系統中之整體異質整合(HGI)。實例包括多功能射頻通信設備、紅外(IR)成像攝影機、可定址感應器陣列及混合CMOS/奈米線/奈米設備電路(3-7)。在一些代表性系統中，化合物半導體或其他材料提供高速操作、有效光偵測或感應能力，而矽CMOS在通常包括堆疊3D組態之電路中提供數位讀出及信號處理。晶圓結合(8)及磊晶成長(9、10)表 示用於達成此等類型之3D-HGI系統的兩種最為廣泛使用之方法。前者製程涉及藉由使用黏著劑或熱起始界面化學而進行的分別形成於不同半導體晶圓上之積體電路、光電二極體或感應器之實體結合。此方法在許多情況中適用，但其具有重要缺點，包括(i)縮放至較大區或第三(亦即，堆疊)維度中之數層的有限能力，(ii)與不常見材料(例如，奈米結構之材料)或低溫材料及基板之不相容性，(iii)對於貫穿晶圓之電互連的具有挑戰性之製造及對準，(iv)對於平坦、平面結合表面之高要求及(v)可因藉由全異材料之差異熱膨脹/收縮而產生的機械應變發生之曲折及破裂。磊晶成長提供一種不同方法，其涉及藉由分子束磊晶法或其他手段而進行的較薄半導體材料層於其他材料之晶圓之表面上的直接形成。雖然此方法避免前述問題中之一些，但對於磊晶法之要求對可成長之材料的品質及類型加以嚴格限制，即使是在使用緩衝層及其他進階技術時亦如此。相反地，諸如無機材料之奈米級線、織帶、薄膜或粒子或者諸如單壁碳奈米管(SWNT)或石墨薄片(graphene sheet)(11-14)的基於碳之系統之新興類別的半導體奈米材料可成長且接著懸浮於溶劑中，或以回避對於磊晶成長或晶圓結合之需要之方式而轉移至基板上。近來的工作展示(例如)藉由溶液澆鑄(15)而形成之交叉奈米線二極體以2D布局的整合。此處呈現之結果說明相異單晶無機半導體(例如，GaN、Si及GaAs之奈米線/織帶)可如何藉由使用可伸縮及確定性印刷技術而彼此組合及亦與其他類別之奈米材料(例如，SWNT)組合來產生2D或3D布局之複雜HGI電子系統。特定言之，整合至剛性無機及可撓性塑膠基板上之設備陣列、邏輯閘及活動可定址光偵測器中的高效能金屬氧化物半導體場效電晶體(MOSFET)、金屬半導體場效電晶體(MESFET)、薄膜電晶體(TFT)、光電二極體及其他組件之超薄多層堆疊 論證該等能力中之一些。 Many existing and emerging electronic devices benefit from the overall heterogeneous integration (HGI) of different types of semiconductors into a single system of two-dimensional or three-dimensional (2D or 3D) layout. Examples include multi-function radio frequency communication devices, infrared (IR) imaging cameras, addressable sensor arrays, and hybrid CMOS / nanowire / nanodevice circuits (3-7). In some representative systems, compound semiconductors or other materials provide high-speed operation, effective light detection or sensing capabilities, while silicon CMOS provides digital readout and signal processing in circuits that typically include stacked 3D configurations. Wafer bonding (8) and epitaxial growth (9, 10) table Shows the two most widely used methods for achieving these types of 3D-HGI systems. The former process involves physical bonding of integrated circuits, photodiodes, or sensors formed on different semiconductor wafers by using adhesives or thermally initiated interface chemistry. This method is applicable in many cases, but it has important disadvantages, including (i) limited ability to scale to a larger area or several layers in the third (ie, stacked) dimension, (ii) with unusual materials (e.g. , Nanostructured materials) or incompatibility of low temperature materials and substrates, (iii) challenging manufacturing and alignment for through-wafer electrical interconnection, (iv) high for flat, planar bonding surfaces Requirements and (v) can be tortuous and cracked due to mechanical strain generated by the differential thermal expansion / contraction of disparate materials. Epitaxial growth provides a different method that involves the direct formation of a thinner semiconductor material layer on the surface of a wafer of other materials by molecular beam epitaxy or other means. Although this method avoids some of the aforementioned problems, the requirements of the epitaxy method place strict restrictions on the quality and type of materials that can be grown, even when using buffer layers and other advanced technologies. Conversely, emerging classes of semiconductors such as inorganic materials such as nanowires, ribbons, films or particles or carbon-based systems such as single-walled carbon nanotubes (SWNT) or graphite sheets (11-14) Nanomaterials can be grown and then suspended in a solvent, or transferred to the substrate in a manner that avoids the need for epitaxial growth or wafer bonding. Recent work has demonstrated (for example) the integration of crossed nanowire diodes formed by solution casting (15) in a 2D layout. The results presented here illustrate how dissimilar single crystal inorganic semiconductors (e.g. nanowires / ribbons of GaN, Si and GaAs) can be combined with each other and also with other types of nanometers by using scalable and deterministic printing techniques Materials (eg, SWNT) are combined to produce complex HGI electronic systems in 2D or 3D layouts. In particular, high-performance metal oxide semiconductor field-effect transistors (MOSFETs) and metal semiconductor field-effects integrated in device arrays, logic gates and active addressable photodetectors integrated on rigid inorganic and flexible plastic substrates Ultra-thin multilayer stack of crystal (MESFET), thin film transistor (TFT), photodiode and other components Demonstrate some of these capabilities.

圖57說明用於製造此等3D-HGI系統之代表性步驟。該製程始於各處於自己的源基板上之半導體奈米材料之合成。此處呈現之設備整合藉由使用基於晶圓之源材料及微影蝕刻程序而形成之單晶Si、GaN及GaAs的奈米線及奈米織帶(16-21)與藉由化學氣相沈積而成長之SWNT之網路(13、21)。圖57之頂部的掃描電子顯微相片展示在自源基板移除之後的此等半導體奈米材料。對於電路製造，此等元件仍處於在製造或成長階段期間於晶圓上界定之組態：在Si、GaN及GaAs奈米線/織帶之情況下為對準陣列，且對於SWNT為亞單層隨機網路。可在源基板上執行用於實現與Si、GaN及GaAs之歐姆接觸之高溫摻雜及退火程序。下一步驟涉及使用先前描述之基於彈性體印模之印刷技術來將此等經處理之元件自源基板轉移至設備基板(諸如圖57中所說明的聚醯亞胺(PI)之薄片)。特定言之，抵靠源基板層壓聚二甲基矽氧烷(PDMS)之印模建立與半導體奈米材料元件之軟凡得瓦爾黏著接觸。使經"塗墨"之印模與在表面上具有液態預聚物(例如，聚醯胺酸)之薄旋轉澆鑄層之設備基板(例如，PI薄片)接觸，且接著使聚合物固化使得在印模經移除時此等半導體材料嵌埋於此層上且良好地黏附至此層(16-20)。類似程序對於基板(亦即，剛性或可撓性、有機或無機)之一範圍及半導體奈米材料之一範圍適用[此製程之一略經修改的版本用於SWNT(21)。]。中間層(在此情況下為PI)之厚度可小至500nm，且對於此處描述之系統通常為1至1.5μm。在包括閘極介電質、電極及互連之形成的某一額外處理之後，可重複轉印及設備製造步驟，其始於於先前完成之電路級之頂部旋塗新的預聚物中間層。經特別設計以用於轉印之自動台或習知遮罩對準器致能在數平方公分上~1μm之疊置重合精度。(22)(圖 61)。簡單地藉由在中間層中之由光圖案化及/或乾式蝕刻界定之開口上蒸鍍金屬線及將金屬線蒸鍍至該等開口中而形成層與層的互連(23)。此用以得到3D-HGI電子元件之不常見方法具有若干重要特徵。第一，設備基板上之所有處理均於低溫下發生，藉此避免可導致多層堆疊系統中之不合需要之變形的差異熱膨脹/收縮效應。此操作亦致能對低溫塑膠基板及中間層材料之使用，且其有助於確保下伏電路層不會因對上覆設備之處理而熱降級。第二，該方法可應用於寬廣類別之半導體奈米材料，包括諸如SWNT之薄膜的新興材料。第三，柔軟印模致能與下伏設備層之非破壞性接觸；此等印模連同超薄半導體材料亦可容許具有某構形之表面。第四，超薄設備幾何形狀(<1μm)及中間層(<1.5μm)允許層與層之電互連的簡單形成。克服習知方法之劣勢中之許多者的此等特徵說明於下文描述之若干電路論證中。 Figure 57 illustrates representative steps for manufacturing such 3D-HGI systems. The process begins with the synthesis of semiconductor nanomaterials on their own source substrates. The equipment presented here integrates nanowires and nanoribbons (16-21) of single crystal Si, GaN and GaAs formed by using wafer-based source materials and lithography etching processes and by chemical vapor deposition The growing SWNT network (13, 21). The scanning electron micrograph at the top of Figure 57 shows these semiconductor nanomaterials after removal from the source substrate. For circuit manufacturing, these devices are still in the configuration defined on the wafer during the manufacturing or growth stage: aligned arrays in the case of Si, GaN, and GaAs nanowires / ribbons, and sub-monolayers for SWNT Random network. High temperature doping and annealing procedures for achieving ohmic contact with Si, GaN, and GaAs can be performed on the source substrate. The next step involves the transfer of these processed components from the source substrate to the device substrate (such as a sheet of polyimide (PI) illustrated in FIG. 57) using the previously described printing technique based on elastomer stamps. In particular, the impression of laminated polydimethylsiloxane (PDMS) against the source substrate establishes an adhesive contact with the soft van der Waals of semiconductor nanomaterial components. The "inked" stamp is brought into contact with a device substrate (eg, PI sheet) having a thin spin-cast layer of liquid prepolymer (eg, polyamide) on the surface, and then the polymer is cured so that When the stamp is removed, these semiconductor materials are embedded on this layer and adhere well to this layer (16-20). Similar procedures apply to a range of substrates (ie, rigid or flexible, organic or inorganic) and a range of semiconductor nanomaterials [a slightly modified version of this process is used for SWNT (21). ]. The thickness of the intermediate layer (PI in this case) can be as small as 500 nm, and is usually 1 to 1.5 μm for the system described here. After some additional processing including the formation of gate dielectrics, electrodes and interconnects, the transfer and equipment manufacturing steps can be repeated, which begins with the spin-coating of a new prepolymer interlayer on top of the previously completed circuit level . A specially designed automatic stage for transfer or a conventional mask aligner enables overlay accuracy of ~ 1μm over several square centimeters. (22) (Figure 61). The layer-to-layer interconnection is formed simply by vapor-depositing metal lines on the openings in the intermediate layer defined by the light patterning and / or dry etching and vapor-depositing the metal lines into these openings (23). This unusual method for obtaining 3D-HGI electronic components has several important features. First, all processing on the device substrate occurs at low temperatures, thereby avoiding differential thermal expansion / contraction effects that can lead to undesirable deformations in the multilayer stack system. This operation also enables the use of low-temperature plastic substrates and interlayer materials, and it helps to ensure that the underlying circuit layer is not thermally degraded by the treatment of the overlying equipment. Second, the method can be applied to a wide range of semiconductor nanomaterials, including emerging materials such as SWNT thin films. Third, the soft stamp enables non-destructive contact with the underlying device layer; these stamps, along with ultra-thin semiconductor materials, can also allow surfaces with a certain configuration. Fourth, the ultra-thin device geometry (<1μm) and intermediate layer (<1.5μm) allow simple formation of layer-to-layer electrical interconnections. These characteristics of overcoming many of the disadvantages of conventional methods are illustrated in several circuit arguments described below.

圖58呈現藉由使用圖57中說明之總處理流程，使用具有摻雜接觸點(形成於源晶圓上)、電漿增強化學氣相沈積之SiO2介電質及用於源極、汲極及閘極之Cr/Au金屬化的單晶矽奈米織帶(24)而製造之三層3D堆疊陣列Si MOSFET。每一設備使用三個對準之奈米織帶，其具有分別為87μm、290nm及250μm之寬度、厚度及長度。圖2A展示系統之邊緣之俯視光學顯微相片，該邊緣具有經設計以分別顯示基板之支撐一個、兩個及三個MOSFET層之部分的布局。第二層之設備幾何形狀相對於第一層及第三層之九十度旋轉有助於闡明系統之布局。堆疊結構之示意性橫截面圖及傾斜圖出現於圖58B中。可使用共焦光學顯微法來在三維上觀察樣本。圖58C展示該等影像之俯視圖及傾斜圖，其經著色以易於觀察。(影像品質隨深度而稍有降級，此歸因於自上層之散射及吸收)。圖58D呈現對每一層中 之代表性設備[具有19μm之通道長度(L c )、由在摻雜源極/汲極區域上延伸之閘極電極的距離界定之5.5μm之通道重疊距離(Lo)及200μm之通道寬度(W)的頂部閘極MOSFET]之電量測結果。三層中之每一者上之形成於PI基板上的設備展示出極佳特性(470±30cm2/Vs之線性遷移率，>104之開關比及-0.1±0.2V之臨限電壓)，且在不同層中的設備之間不存在系統差異。可藉由重複相同程序來向此系統添加額外層。如圖59中所說明，除了具有單一半導體之3D電路以外，可在多層中使用各種半導體以形成完整3D-HGI系統。為了說明此能力，吾人分別使用GaN及Si奈米織帶與SWNT膜而在PI基板上製造MESFET(特定言之，高電子遷移率電晶體HEMT)、MOSFET及TFT之陣列。圖59A及圖59B分別展示所得設備之高放大率光學影像與共焦影像。第一層上之GaN HEMT對於源極及汲極使用歐姆接觸點(Ti/Al/Mo/Au，其於源晶圓上加以退火)，且對於閘極使用肖特基(Ni/Au)接觸點。通道長度與寬度及閘極寬度分別為20μm、170μm及5μm。每一設備使用具有分別為1.2μm、10μm及150μm之厚度、寬度及長度、藉由設備基板上之處理而電互連的GaN織帶(由AlGaN/GaN/AlN之多層堆疊構成)。第二層上之SWNT TFT對於閘極介電質使用SiO2/環氧樹脂，且對於源極、汲極及閘極使用Cr/Au，其具有分別為50μm及200μm之通道長度及寬度。Si MOSFET使用與圖58中所示之設計相同的設計。可藉由使用Si、SWNT及GaN之不同組合來建構各種其他3D-HGI設備(圖61及圖62)。圖59C呈現圖59A及圖59B之系統中的典型設備之電流-電壓特徵。在所有情況中，特性均類似於在源晶圓上製造的特性：GaN HEMT具有-2.4±0.2V之臨限電壓(Vth)、>106之開關比及0.6±0.5mS之轉導；SWNT TFT具有Vth=-5.3±1.5V、>105之開關比及5.9±2.0cm2/Vs之 線性遷移率；Si MOSFET具有Vth=0.2±0.3V、>104之開關比及500±30cm2/Vs之線性遷移率。此等設備之一受關注態樣(其係由對薄PI基板(25μm)、設備(2.4μm)及PI/PU中間層(5μm)之使用而得出)為其機械可撓曲性，此對於在可撓性電子元件中之應用為重要的。吾人將對於圖59A之3D-HGI系統中之Si、SWNT及GaN設備的有效轉導(g eff )評估為撓曲半徑之函數。展示如經正規化為未撓曲狀態下之轉導(g 0eff )的此等資料之圖59D說明對於低至3.7mm之撓曲半徑的穩定效能。 FIG. 58 presents the use of the SiO 2 dielectric with doped contacts (formed on the source wafer), plasma enhanced chemical vapor deposition and the source and drain by using the overall process flow illustrated in FIG. 57 Three-layer 3D stacked array Si MOSFET made of Cr / Au metallized single crystal silicon ribbon (24) of the gate and gate. Each device uses three aligned nanoribbons with widths, thicknesses, and lengths of 87 μm, 290 nm, and 250 μm, respectively. Figure 2A shows a top-view optical micrograph of the edge of the system with the layout designed to show the portion of the substrate supporting one, two, and three MOSFET layers, respectively. The 90-degree rotation of the device geometry of the second layer relative to the first and third layers helps to clarify the layout of the system. A schematic cross-sectional view and an oblique view of the stacked structure appear in FIG. 58B. The sample can be viewed in three dimensions using confocal optical microscopy. FIG. 58C shows a top view and an oblique view of these images, which are colored for easy observation. (Image quality degrades slightly with depth, which is due to scattering and absorption from the upper layer). 58D presents a representative device in each layer [with a channel length of 19 μm ( L c ), a channel overlap distance of 5.5 μm defined by the distance of the gate electrode extending over the doped source / drain region (Lo ) And the top gate MOSFET with a channel width (W) of 200 μm]. The devices formed on the PI substrate on each of the three layers exhibit excellent characteristics (470 ± 30cm 2 / Vs linear mobility,> 10 4 switching ratio and -0.1 ± 0.2V threshold voltage) , And there is no system difference between devices in different layers. Additional layers can be added to this system by repeating the same procedure. As illustrated in FIG. 59, in addition to a 3D circuit with a single semiconductor, various semiconductors can be used in multiple layers to form a complete 3D-HGI system. To illustrate this capability, we used GaN and Si nanoribbons and SWNT films to fabricate arrays of MESFETs (specifically, high electron mobility transistors HEMT), MOSFETs, and TFTs on PI substrates. 59A and 59B show high-magnification optical images and confocal images of the resulting device, respectively. GaN HEMT on the first layer uses ohmic contacts (Ti / Al / Mo / Au, which are annealed on the source wafer) for the source and drain, and Schottky (Ni / Au) contacts for the gate point. The channel length and width and gate width are 20 μm, 170 μm and 5 μm, respectively. Each device uses a GaN ribbon (consisting of a multilayer stack of AlGaN / GaN / AlN) having thicknesses, widths and lengths of 1.2 μm, 10 μm and 150 μm, respectively, electrically interconnected by processing on the device substrate. The SWNT TFT on the second layer uses SiO 2 / epoxy for the gate dielectric, and Cr / Au for the source, drain, and gate, which have channel lengths and widths of 50 μm and 200 μm, respectively. The Si MOSFET uses the same design as shown in Figure 58. Various other 3D-HGI devices can be constructed by using different combinations of Si, SWNT, and GaN (FIGS. 61 and 62). FIG. 59C presents the current-voltage characteristics of the typical equipment in the system of FIGS. 59A and 59B. In all cases, the characteristics are similar to those fabricated on the source wafer: GaN HEMT has a threshold voltage (V th ) of -2.4 ± 0.2V, a switching ratio of> 10 6 and a transduction of 0.6 ± 0.5mS; SWNT TFT has V th = -5.3 ± 1.5V, switching ratio> 10 5 and linear mobility of 5.9 ± 2.0cm 2 / Vs; Si MOSFET has V th = 0.2 ± 0.3V, switching ratio> 10 4 and 500 Linear mobility of ± 30cm 2 / Vs. One of the concerns of these devices (which is derived from the use of thin PI substrates (25 μm), devices (2.4 μm) and PI / PU intermediate layers (5 μm)) is their mechanical flexibility, which It is important for applications in flexible electronic components. We evaluated the effective transduction (g eff ) for Si, SWNT, and GaN devices in the 3D-HGI system of FIG. 59A as a function of the deflection radius. Figure 59D showing such data as normalized to transduction in the unflexed state (g 0eff ) illustrates the stability performance for deflection radii as low as 3.7 mm.

形成於此等3D-HGI設備中之不同級之間的電互連可產生引起關注之電路能力。較薄聚合物中間層使得此等互連能夠藉由在微影界定之開口上蒸鍍金屬線或將金屬線蒸鍍至該等開口中而簡單地形成。圖60呈現一些實例。圖60A中所示之第一者為3D NMOS反相器(邏輯閘)，其中驅動(L=4μm，W=200μm)與負載(L=4μm,W=30μm)Si MOSFET處於不同級上。在5V之電源電壓之情況下，此雙層反相器顯示出經良好界定的轉移特徵，其中增益為~2，此與使用類似電晶體之習知平面反相器(25)之效能相當。圖60B展示藉由使用整合之n通道Si MOSFET與p通道SWNT TFT而具有互補設計(CMOS)之反相器，其經設計以使上拉與下拉方向上之電流驅動能力均衡(圖65)。以至VDD端子之5V偏壓及自0V至5V之閘極電壓(輸入)而收集之轉移曲線出現於圖60A中。曲線形狀及增益(高達~7)定性地與數值電路模擬(圖65)相一致。作為第三實例，吾人建立與可撓性PI基板上之Si MOSFET整合的金屬-半導體-金屬(MSM)紅外(IR)偵測器(26)來論證用於製造可用於活性IR成像器中之單胞的能力。在此情況下，轉移至具有Si奈米織帶MOSFET之印刷陣列之基板上的GaAs之印刷奈米織帶(厚度、寬度及長度分別為270μm、100nm及400μm)形成MSM之基礎。沈 積於此等GaAs奈米織帶之末端上的電極(Ti/Au=5/70nm)形成背對背肖特基二極體，其中間隔為10μm。所得偵測器單元顯示出隨IR照射之強度而增大的電流增強(圖60C)，此與電路模擬(圖66)相一致。在不考慮自半導體之表面反射的光之情況下，在1V至5V觀測到於850nm之波長處約0.30A/W之回應率。該系統亦顯示出具有低於1cm之曲率半徑的可撓曲性，此對於諸如廣角IR夜視成像器之彎曲焦平面陣列之進階系統可為有用的。 The electrical interconnections formed between the different stages in these 3D-HGI devices can generate circuit capabilities that are of interest. The thinner polymer interlayer allows these interconnects to be formed simply by vaporizing metal lines on the openings defined by the lithography or by vaporizing the metal lines into the openings. Figure 60 presents some examples. The first one shown in FIG. 60A is a 3D NMOS inverter (logic gate), in which the driving (L = 4μm, W = 200μm) and load (L = 4μm, W = 30μm) Si MOSFETs are at different levels. At a supply voltage of 5V, this double-layer inverter shows well-defined transfer characteristics, with a gain of ~ 2, which is comparable to the performance of a conventional planar inverter (25) using a similar transistor. FIG. 60B shows an inverter with a complementary design (CMOS) by using integrated n-channel Si MOSFET and p-channel SWNT TFT, which is designed to balance the current driving capability in the pull-up and pull-down directions (FIG. 65). The transfer curve collected with the 5V bias to the VDD terminal and the gate voltage (input) from 0V to 5V appears in FIG. 60A. The curve shape and gain (up to ~ 7) are qualitatively consistent with numerical circuit simulation (Figure 65). As a third example, we established a metal-semiconductor-metal (MSM) infrared (IR) detector (26) integrated with a Si MOSFET on a flexible PI substrate to demonstrate that it can be used in an active IR imager The ability of a single cell. In this case, the printed nanoweb tape (thickness, width, and length of 270 μm, 100 nm, and 400 μm, respectively) of GaAs transferred to the substrate of the printed array with Si nanoweb MOSFETs formed the basis of MSM. sink The electrodes (Ti / Au = 5 / 70nm) accumulated on the ends of these GaAs nanoribbons form back-to-back Schottky diodes with a spacing of 10 μm. The resulting detector unit showed an increase in current that increased with the intensity of IR irradiation (Figure 60C), which was consistent with the circuit simulation (Figure 66). Without considering the light reflected from the surface of the semiconductor, a response rate of about 0.30 A / W at a wavelength of 850 nm was observed at 1V to 5V. The system also shows flexibility with a radius of curvature of less than 1 cm, which can be useful for advanced systems such as curved focal plane arrays such as wide-angle IR night vision imagers.

印刷半導體奈米材料提供得到3D-HGI系統之新方法且可在各種應用領域中具有重要應用，不僅是此處報告之系統所提示的應用領域，且有其他應用領域，包括具有整合式讀出及感應電子元件之微流體設備、將不常見感應材料與習知矽基電子元件合併之生化感應系統及將化合物半導體之發光器與矽驅動電子元件或微機電結構組合的光子/光電子系統。另外，此方法與較薄輕型塑膠基板之相容性可產生對於具有不常見形狀因數或機械可撓性作為關鍵特徵的設備之額外機會。 Printed semiconductor nanomaterials provide a new way to obtain 3D-HGI systems and can have important applications in a variety of applications, not only the applications suggested by the system reported here, but also other applications, including with integrated readout And microfluidic devices for sensing electronic components, biochemical sensing systems combining uncommon sensing materials with conventional silicon-based electronic components, and photonic / photoelectric subsystems combining compound semiconductor light emitters with silicon driving electronic components or microelectromechanical structures. In addition, the compatibility of this method with thinner and lighter plastic substrates may create additional opportunities for devices with unusual form factors or mechanical flexibility as key features.

材料及方法：設備製造：矽設備：製造始於藉由處理絕緣體上矽晶圓(SOI；具有290nm之頂部Si層之Soitec unibond，其具有6.0~9.4×1014/cm3之摻雜級)而進行的對單晶矽之接觸點摻雜薄織帶之界定。第一步驟涉及磷摻雜，其使用固源及旋塗式摻雜劑(Filmtronic,P509)且使用電漿增強化學氣相沈積(PECVD)之SiO2(Plasmatherm,300nm,900毫托，350sccm,2%之SiH4/He,795sccm NO2,250℃)的光微影界定之層作為遮罩來控制摻雜劑於何處擴散至矽中。在摻雜之後，經由光阻劑之圖案化層而進行的SF6電漿蝕刻界定織帶。藉由濃HF溶液(Fisher Chemicals)而進行的對內埋氧化物之底切蝕刻將織帶自晶圓釋放。此程序 完成單晶矽之接觸點摻雜織帶的製造。在下一步驟中，使聚二甲基矽氧烷(PDMS,A：B=1：10,Sylgard 184,Dow Corning)之平坦彈性體印模與光阻劑塗佈之織帶接觸，且接著剝離印模，從而將織帶自晶圓移除，且藉由疏水性PDMS與光阻劑之間的凡得瓦爾力使得織帶仍黏附至印模之表面。抵靠旋塗有較薄液態PI前驅物聚醯胺酸(Sigma_Aldrich Inc.)層(~1.5μm)之25μm的聚醯亞胺(PI)薄片來層壓如此以來自晶圓之s-Si織帶而經"塗墨"的印模。使前驅物固化，剝離PDMS印模且汽提光阻劑將織帶保留為嵌埋於PI基板之表面上且良好地黏附至該表面。閘極介電質層由藉由PECVD於相對較低之溫度，250℃下沈積之SiO2層(厚度為~100nm)組成。光微影及CF4電漿蝕刻界定對矽之摻雜源極/汲極區域之開口。在藉由光微影及濕式蝕刻而進行之單一步驟中界定Cr/Au(5/100nm，藉由電子束蒸鍍自底部至頂部而形成，Temescal FC-1800)之源極、汲極及閘極電極。 Materials and methods: Equipment manufacturing: Silicon equipment: manufacturing begins by processing silicon-on-insulator wafers (SOI; Soitec unibond with a top Si layer of 290 nm, which has a doping level of 6.0 ~ 9.4 × 10 14 / cm 3 ) And the definition of the doping of the thin ribbon of the contact point of the single crystal silicon is carried out. The first step involves phosphorus doping, which uses solid sources and spin-on dopants (Filmtronic, P509) and plasma enhanced chemical vapor deposition (PECVD) of SiO 2 (Plasmatherm, 300 nm, 900 mtorr, 350 sccm, The 2% SiH 4 / He, 795sccm NO 2 , 250 ℃) photolithography-defined layer serves as a mask to control where the dopant diffuses into the silicon. After doping, the SF 6 plasma etch through the patterned layer of photoresist defines the webbing. The undercut etching of the buried oxide by concentrated HF solution (Fisher Chemicals) releases the webbing from the wafer. This procedure completes the manufacture of contact doped webbing for single crystal silicon. In the next step, a flat elastomer stamp of polydimethylsiloxane (PDMS, A: B = 1: 10, Sylgard 184, Dow Corning) is brought into contact with the photoresist coated webbing, and then the stamp is peeled off Mold, thereby removing the webbing from the wafer, and by the van der Waals force between the hydrophobic PDMS and the photoresist, the webbing still adheres to the surface of the stamp. Laminated against a 25 μm polyimide (PI) sheet spin-coated with a thinner liquid PI precursor polyamic acid (Sigma_Aldrich Inc.) layer (~ 1.5 μm) so laminated with s-Si ribbon from wafer And after "impression" impression. The precursor is cured, the PDMS stamp is peeled off and the stripping photoresist retains the webbing to be embedded on the surface of the PI substrate and adheres well to the surface. The gate dielectric layer consists of a SiO 2 layer (thickness ~ 100nm) deposited by PECVD at a relatively low temperature at 250 ° C. Photolithography and CF 4 plasma etching define openings in the doped source / drain regions of silicon. In a single step by photolithography and wet etching, the source, drain and Gate electrode.

GaN設備：在具有異質結構[AlGaN(18nm)/GaN(0.6μm)/AlN(0.6μm)/Si]的GaN之塊狀晶圓上製造GaN微結構。歐姆接觸區由AZ 5214光阻劑界定且接著於RIE系統中以SiCl4電漿而加以清洗。Ti/Al/Mo/Au(15nm/60nm/35nm/50nm)金屬層接著藉由電子束蒸鍍(Ti/Al/Mo)及熱蒸鍍(Au)而沈積。洗掉完整之抗蝕劑使金屬接觸點保留於GaN上。在N2環境中於850℃下歷時30秒之熱退火形成歐姆接觸點。SiO2(Plasmatherm,300nm,900毫托，350sccm,2%之SiH4/He,795sccm NO2,250℃)及Cr金屬(電子束蒸鍍器，150nm)層經沈積作為對於隨後的感應耦合電漿(ICP)蝕刻之遮罩材料。光微影、濕式蝕刻及RIE處理(50毫托，40sccm CF4,100W,14分鐘)界定GaN之織帶幾何形狀。在以丙酮移除光阻劑之後，使用ICP乾式蝕刻(3.2毫托，15sccm Cl2,5sccm Ar,-100V偏壓，14分鐘)來 移除曝露之GaN且稍稍蝕刻至Si中(~1.5μm)以促進隨後的各向異性蝕刻。接著藉由使用四甲基銨氫氧化物(Aldrich,150℃，歷時4分30秒)而自GaN下方蝕刻掉Si。將樣本浸漬於BOE(6：1,NH4F：HF)中歷時30秒以移除PECVD SiO2，且將新的50nm之電子束蒸鍍之SiO2層沈積於GaN織帶的頂部上。接著抵靠塗佈有2μm之聚胺基甲酸酯(PU,Norland optical adhesive,No.73)的PI薄片層壓藉由來自母晶圓之GaN織帶而經"塗墨"之PDMS厚片。使樣本曝露於UV光(173μWcm-2)下15分鐘以使PU固化。剝離PDMS且藉由浸沒於BOE中20秒而移除電子束SiO2導致GaN元件向塑膠基板之轉移。使用負性光阻劑(AZ nLOF2020)來圖案化Ni/Au(80/180nm)之肖特基接觸點。藉由AZ汽提器(KWIK，歷時30分鐘)來移除光阻劑。 GaN equipment: GaN microstructures are fabricated on bulk wafers of GaN with heterostructures [AlGaN (18nm) / GaN (0.6μm) / AlN (0.6μm) / Si]. The ohmic contact area is defined by AZ 5214 photoresist and then cleaned with SiCl 4 plasma in the RIE system. The Ti / Al / Mo / Au (15nm / 60nm / 35nm / 50nm) metal layer is then deposited by electron beam evaporation (Ti / Al / Mo) and thermal evaporation (Au). The complete resist is washed away so that the metal contacts remain on the GaN. Ohmic contact points were formed by thermal annealing at 850 ° C for 30 seconds in N 2 environment. SiO 2 (Plasmatherm, 300 nm, 900 mtorr, 350 sccm, 2% SiH 4 / He, 795 sccm NO 2 , 250 ° C.) and Cr metal (electron beam vaporizer, 150 nm) layers are deposited as the Masking material etched by slurry (ICP). Photolithography, wet etching, and RIE processing (50 mTorr, 40 sccm CF 4 , 100 W, 14 minutes) define the ribbon geometry of GaN. After removing the photoresist with acetone, ICP dry etching (3.2 mtorr, 15 sccm Cl 2 , 5 sccm Ar, -100 V bias, 14 minutes) was used to remove the exposed GaN and etched slightly into Si (~ 1.5 μm ) To facilitate subsequent anisotropic etching. Then Si was etched away from under GaN by using tetramethylammonium hydroxide (Aldrich, 150 ° C, 4 minutes and 30 seconds). The sample was immersed in BOE (6: 1, NH 4 F: HF) for 30 seconds to remove PECVD SiO 2 , and a new 50 nm electron beam vaporized SiO 2 layer was deposited on top of the GaN webbing. Next, the PDMS slabs "inked" with GaN web tape from the mother wafer were laminated against PI sheets coated with 2 μm polyurethane (PU, Norland optical adhesive, No. 73). The sample was exposed to UV light (173 μWcm -2 ) for 15 minutes to cure the PU. The PDMS was stripped and the electron beam SiO 2 was removed by immersion in BOE for 20 seconds resulting in the transfer of the GaN device to the plastic substrate. A negative photoresist (AZ nLOF2020) was used to pattern the Schottky contacts of Ni / Au (80/180 nm). The photoresist was removed by AZ stripper (KWIK, 30 minutes).

SWNT設備：使用化學氣相沈積(CVD)來在SiO2/Si晶圓上生長個別單壁碳奈米管之隨機網路。使用連同甲醇而沈積於基板上之鐵蛋白(Sigma Aldrich)作為催化劑。饋入氣體為甲烷(1900sccm CH4連同300sccm H2)。藉由Ar氣之高流動來沖洗爐中之石英管以在生長之前進行清洗。在生長期間，使溫度保持於900℃歷時20分鐘。轉移涉及類似於如先前所描述之製程的印刷之程序或者將厚Au層及PI前驅物塗佈於具有管之SiO2/Si基板上的稍稍不同之方法。在使PI固化之後剝離Au/PI。相對於塗佈有薄環氧樹脂層(SU8,150nm)之經預圖案化之設備基板而層壓此層，且接著分別藉由氧反應性離子蝕刻及濕式蝕刻而移除PI及Au層完成轉移。在底部閘極設備之情況中，基板支撐經預圖案化之閘極電極及介電質。特定言之，藉由光微影而圖案化Cr/Au/Cr(2nm/10nm/10nm)之閘極電極，且接著使用PECVD將300nm之SiO2沈積於基板上。直接於管之頂部界定 Cr/Au(2nm/20nm)之源極及汲極電極。 SWNT equipment: Use chemical vapor deposition (CVD) to grow a random network of individual single-walled carbon nanotubes on SiO 2 / Si wafers. Ferritin (Sigma Aldrich) deposited on the substrate together with methanol was used as a catalyst. The feed gas was methane (1900 sccm CH 4 together with 300 sccm H 2 ). The quartz tube in the furnace was rinsed by high flow of Ar gas to be cleaned before growth. During the growth period, the temperature was maintained at 900 ° C for 20 minutes. The transfer involves a printing process similar to the process described previously or a slightly different method of coating a thick Au layer and PI precursor on a SiO 2 / Si substrate with a tube. After curing the PI, the Au / PI is peeled off. This layer was laminated against a pre-patterned device substrate coated with a thin epoxy layer (SU8, 150nm), and then the PI and Au layers were removed by oxygen reactive ion etching and wet etching, respectively Complete the transfer. In the case of bottom gate devices, the substrate supports pre-patterned gate electrodes and dielectrics. Specifically, the gate electrode of Cr / Au / Cr (2nm / 10nm / 10nm) was patterned by photolithography, and then 300nm of SiO 2 was deposited on the substrate using PECVD. The source and drain electrodes of Cr / Au (2nm / 20nm) are defined directly on the top of the tube.

3D電路：3D Si NMOS反相器：藉由重複應用相同製造程序來建構多層設備。特定言之，將PI前驅物旋轉澆鑄於設備之現有層之頂部，且將矽織帶轉印於頂部。接著使用相同製程來製造設備。對於豎直金屬互連，藉由在AZ4620光阻劑之層中光圖案化開口，且接著藉由於RIE系統中使用CF4及O2電漿蝕刻掉此曝露區中之SiO2及PI而界定電極區。向此區中沈積300nm之Al於底部建立接觸，且在藉由蝕刻之SiO2及PI而形成之階梯邊緣上提供電連續連接。 3D circuit: 3D Si NMOS inverter: build a multi-layer device by repeatedly applying the same manufacturing process. In particular, the PI precursor is spin cast on top of the existing layer of the device, and the silicon ribbon is transferred to the top. The same process is then used to manufacture the equipment. For the vertical metal interconnection, it is defined by photo-patterning the opening in the layer of AZ4620 photoresist, and then by etching away the SiO 2 and PI in this exposed area due to the use of CF 4 and O 2 plasma in the RIE system Electrode area. Depositing 300 nm of Al into this area establishes contact at the bottom and provides electrical continuous connections on the edge of the step formed by etching SiO 2 and PI.

SWNT及Si CMOS反相器：SWNT設備由藉由光微影在管網路上界定的Au(20nm)之源極/汲極接觸點組成。SiO2(100nm)/Si晶圓基板提供閘極介電質及閘極。接著在選擇性地以光阻劑(AZ5214)塗佈SWNT電晶體之後將環氧樹脂(SU8,500nm)旋塗至此基板上。在用於環氧樹脂之固化的UV曝露之後，抵靠基板而層壓以未摻雜Si織帶"塗墨"之PDMS厚片，且隨後藉由緩慢人工剝離來移除該厚片以完成轉印製程。使用Cr/Au(5nm/100nm)作為對於矽設備中之源極及汲極電極之肖特基接觸點。使用Al(100nm)以連接SWNT與Si電晶體。 SWNT and Si CMOS inverters: The SWNT device consists of the source / drain contacts of Au (20nm) defined on the pipe network by photolithography. The SiO 2 (100nm) / Si wafer substrate provides gate dielectric and gate. Then, after selectively coating the SWNT transistor with a photoresist (AZ5214), an epoxy resin (SU8, 500 nm) was spin-coated onto this substrate. After UV exposure for curing of the epoxy resin, a PDMS slab "laminated" with undoped Si ribbon is laminated against the substrate, and then the slab is removed by slow manual peeling to complete the transfer Printing process. Use Cr / Au (5nm / 100nm) as the Schottky contact point for the source and drain electrodes in silicon devices. Use Al (100nm) to connect SWNT and Si transistor.

整合有Si TFT之GaAs MSM IR偵測器：使用GaAs晶圓(IQE Inc.,Bethlehem,PA.)以產生背對背肖特基二極體。由具有多個磊晶層[摻雜Si之n型GaAs(120nm)/半絕緣(SI)-GaAs(150nm)/AlAs(200nm)/SI-GaAs]的GaAs之高品質塊狀晶圓產生織帶。n型GaAs之載體濃度為4×1017cm-3。在蝕刻劑(4mL H3PO4(85重量%)、52mL H2O2(30重量%)及48mL去離子水)中對具有光阻劑遮罩圖案之GaAs晶圓進行各向異性蝕刻。以乙醇中之稀HF溶液(在體積上為1：2)來蝕刻掉AlAs層。接著藉由電子束蒸鍍器沈 積2nm之Ti及28nm之SiO2之層。接著使以GaAs織帶塗墨之PDMS印模與塗佈有PI的Si電晶體之層(厚度為1.5μm)接觸。剝離PDMS且藉由BOE蝕刻劑移除Ti及SiO2完成GaAs向設備基板之轉移。藉由電子束蒸鍍而沈積用於肖特基接觸點之金屬(Ti/Au=5nm/70nm)。藉由首先圖案化AZ4620光阻劑之層，接著於RIE系統中使用CF4及O2電漿蝕刻穿開口且接著沈積300nm之Al來界定GaAs背對背肖特基二極體與Si MOSFET之間的電互連。 GaAs MSM IR detector with integrated Si TFT: GaAs wafer (IQE Inc., Bethlehem, PA.) Is used to generate back-to-back Schottky diodes. Ribbons are produced from high-quality bulk wafers of GaAs with multiple epitaxial layers [Si-doped n-type GaAs (120nm) / semi-insulating (SI) -GaAs (150nm) / AlAs (200nm) / SI-GaAs] . The carrier concentration of n-type GaAs is 4 × 10 17 cm -3 . The GaAs wafer with the photoresist mask pattern was anisotropically etched in an etchant (4 mL H 3 PO 4 (85 wt%), 52 mL H 2 O 2 (30 wt%), and 48 mL deionized water). The AlAs layer was etched away with a dilute HF solution in ethanol (1: 2 in volume). Then, a layer of Ti of 2 nm and SiO 2 of 28 nm is deposited by an electron beam vaporizer. Next, a PDMS stamp coated with GaAs webbing was brought into contact with a layer (thickness of 1.5 μm) of PI-coated Si transistors. The PDMS is stripped and Ti and SiO 2 are removed by BOE etchant to complete the transfer of GaAs to the device substrate. The metal used for Schottky contacts (Ti / Au = 5nm / 70nm) was deposited by electron beam evaporation. By first patterning the layer of AZ4620 photoresist, then using CF 4 and O 2 plasma to etch through the opening in the RIE system and then depositing 300 nm of Al to define the gap between the GaAs back-to-back Schottky diode and the Si MOSFET Electrical interconnection.

設備表徵：使用半導體參數分析器(Agilent,4155C)及習知探測台來進行二極體及電晶體之電表徵。在具有850nm之波長的IR LED源下量測IR回應。 Equipment Characterization: Use the semiconductor parameter analyzer (Agilent, 4155C) and the conventional detection platform to perform the electrical characterization of diodes and transistors. The IR response was measured under an IR LED source with a wavelength of 850nm.

電路模擬：為了比較CMOS反相器之量測而得之轉移曲線與一模擬，經驗地產生對於n通道Si MOSFET與p通道SWNT TFT之2級PSPICE模型。基於預設PSPICE MOSFET模型(MbreakN及MbreakP)而產生此等PSPICE模型，該預設PSPICE MOSFET模型具有提取之參數來配合圖65B所示之Si NMOS及SWNT PMOS之量測而得的四個曲線。藉由使用與Si MOSFET串連連接之背對背肖特基二極體而經驗地產生對於GaAs MSM光偵測器之PSPICE模型。 Circuit simulation: In order to compare the transfer curve measured by the CMOS inverter with a simulation, a 2-level PSPICE model for n-channel Si MOSFET and p-channel SWNT TFT is empirically generated. These PSPICE models are generated based on the preset PSPICE MOSFET models (MbreakN and MbreakP). The default PSPICE MOSFET model has the extracted parameters to match the four curves measured by the Si NMOS and SWNT PMOS shown in FIG. 65B. PSPICE models for GaAs MSM photodetectors are empirically generated by using back-to-back Schottky diodes connected in series with Si MOSFETs.

實例4之參考文獻： References for Example 4:

1. K. Banerjee, S. J. Souri, P. Kapur, K. C. Saraswat, Proc. IEEE, 89, 602 (2001)。 1. K. Banerjee, S. J. Souri, P. Kapur, K. C. Saraswat, Proc. IEEE, 89, 602 (2001).

2. S. F. Al-Sarawi, D. Abbott, P. D. Franzon, IEEE Trans. Components, Packaging, and Manufacturing Technology, Part B, 21, 2 (1998)。 2. S. F. Al-Sarawi, D. Abbott, P. D. Franzon, IEEE Trans. Components, Packaging, and Manufacturing Technology, Part B, 21, 2 (1998).

3. A. S. Brown, W. A. Doolittle, N. M. Jokerst, S. Kang, S. Huang, S. W. Seo Materials Science and Engineering B 87, 317 (2001)。 3. A. S. Brown, W. A. Doolittle, N. M. Jokerst, S. Kang, S. Huang, S. W. Seo Materials Science and Engineering B 87, 317 (2001).

4. Y.-C. Tseng, P. Xuan, A. Javey, R. Malloy, Q. Wang, J. Bokor, H. Dai, Nano letters 4, 123 (2004)。 4. Y.-C. Tseng, P. Xuan, A. Javey, R. Malloy, Q. Wang, J. Bokor, H. Dai, Nano letters 4, 123 (2004).

5. C. Joachim, J. K. Gimzewski, A. Aviram, Nature 408, 541 (2000)。 5. C. Joachim, J. K. Gimzewski, A. Aviram, Nature 408, 541 (2000).

6. G. Roelkens等人，Optics Express 13, 10102 (2005)。 6. G. Roelkens et al., Optics Express 13, 10102 (2005).

7. D. B. Strukov, K. K. Likharev, Nanotechnology 16, 888 (2005)。 7. D. B. Strukov, K. K. Likharev, Nanotechnology 16, 888 (2005).

8. K. Vanhollebeke, I. Moerman, P. Van Daele, P. Demeester, Prog. Cryst. Growth Charact. Mater. 41, 1 (2000)。 8. K. Vanhollebeke, I. Moerman, P. Van Daele, P. Demeester, Prog. Cryst. Growth Charact. Mater. 41, 1 (2000).

9. H. Amano, N. Sawaki, I. Akasaki, Y. Toyoda, Appl. Phys. Lett. 48, 353 (1986)。 9. H. Amano, N. Sawaki, I. Akasaki, Y. Toyoda, Appl. Phys. Lett. 48, 353 (1986).

10. T. Kuykendall, P. J. Pauzauskie, Y. Zhang, J. Goldberger, D. Sirbuly, J. Denlinger, P. Yang, Nature Materials 3, 524, (2004)。 10. T. Kuykendall, P. J. Pauzauskie, Y. Zhang, J. Goldberger, D. Sirbuly, J. Denlinger, P. Yang, Nature Materials 3, 524, (2004).

11. A. M. Morales, C. M. Lieber, Science 279, 208 (1998)。 11. A. M. Morales, C. M. Lieber, Science 279, 208 (1998).

12. M. Law, D. J. Sirbuly, J. C. Johnson, J. Goldberger, R. J. Saykally, P. Yang, Science 305, 1269 (2004)。 12. M. Law, D. J. Sirbuly, J. C. Johnson, J. Goldberger, R. J. Saykally, P. Yang, Science 305, 1269 (2004).

13. J. Kong, H. T. Soh, A. M. Cassell, C. F. Quate及H. Dai, Nature 395, 878 (1998)。 13. J. Kong, H. T. Soh, A. M. Cassell, C. F. Quate and H. Dai, Nature 395, 878 (1998).

14. K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V. Grigorieva, A. A. Firsov, Science 306, 666 (2004)。 14. K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V. Grigorieva, A. A. Firsov, Science 306, 666 (2004).

15. Y. Huang, X. Duan, C. M. Lieber, Small 1, 1 (2005)。 15. Y. Huang, X. Duan, C. M. Lieber, Small 1, 1 (2005).

16. M. A. Meitl, Z. Zhu, V. Kumar, K. Lee, X. Feng, Y. Huang, R. G. Nuzzo, J. A. Rogers, Nature Materials 5, 33 (2006)。 16. M. A. Meitl, Z. Zhu, V. Kumar, K. Lee, X. Feng, Y. Huang, R. G. Nuzzo, J. A. Rogers, Nature Materials 5, 33 (2006).

17. E. Menard, K. J. Lee, D. Y. Khang, R. G. Nuzzo, J. A. Rogers, Appl. Phys. Lett. 84, 5398 (2004)。 17. E. Menard, K. J. Lee, D. Y. Khang, R. G. Nuzzo, J. A. Rogers, Appl. Phys. Lett. 84, 5398 (2004).

18. Y. Sun, S. Kim, I. Adesida, J. A. Rogers, Appl. Phys. Lett. 87, 083501 (2005)。 18. Y. Sun, S. Kim, I. Adesida, J. A. Rogers, Appl. Phys. Lett. 87, 083501 (2005).

19. K. Lee, M. A. Meitl, V. Kumar, J.-H. Ahn, I. Adesida, J. A. Rogers, R. G. Nuzzo, Appl. Phys. Lett, accepted。 19. K. Lee, M. A. Meitl, V. Kumar, J.-H. Ahn, I. Adesida, J. A. Rogers, R. G. Nuzzo, Appl. Phys. Lett, accepted.

20. S.-H. Hur, D.-Y. Khang, C. Kocabas, J. A. Rogers, Appl. Phys. Lett. 85, 5730 (2004)。 20. S.-H. Hur, D.-Y. Khang, C. Kocabas, J. A. Rogers, Appl. Phys. Lett. 85, 5730 (2004).

21. Materials及Methods are available as supporting material on Science Online。 21. Materials and Methods are available as supporting material on Science Online.

22. J. Dong, M. A. Meitl, E. Menard, P. Ferreira及J. A. Rogers，未出版。 22. J. Dong, M. A. Meitl, E. Menard, P. Ferreira and J. A. Rogers, unpublished.

23. S. Linder, H. Baltes, F. Gnaedinger及E. Doering: Proc. IEEE Micro Eletro Mech. Systems 349, (1994)。 23. S. Linder, H. Baltes, F. Gnaedinger and E. Doering: Proc. IEEE Micro Eletro Mech. Systems 349, (1994).

24. J.-H. Ahn, H.-S. Kim, K. Lee, Z.-T. Zhu, E. Menard, R. G. Nuzzo, J. A. Rogers, IEEE Electron Devices Lett. 27, 460 (2006)。 24. J.-H. Ahn, H.-S. Kim, K. Lee, Z.-T. Zhu, E. Menard, R. G. Nuzzo, J. A. Rogers, IEEE Electron Devices Lett. 27, 460 (2006).

25. J.-H. Ahn, H.-S. Kim, K. Lee, Z.-T. Zhu, E. Menard, R. G. Nuzzo, J. A. Rogers，未出版。 25. J.-H. Ahn, H.-S. Kim, K. Lee, Z.-T. Zhu, E. Menard, R. G. Nuzzo, J. A. Rogers, unpublished.

26. J. B. D. Soole, H. Schumacher, IEEE J. Quantum Electron. 27, 737 (1991)。 26. J. B. D. Soole, H. Schumacher, IEEE J. Quantum Electron. 27, 737 (1991).

美國專利申請案第11/115,954號、第11/145,574號、第11/145,542 號、第60/863,248號、第11/465,317號、第11/423,287號、第11/423,192號及第11/421,654號在不與本發明之描述不一致的程度上以引用方式併入本文中。 U.S. Patent Application Nos. 11 / 115,954, 11 / 145,574, 11 / 145,542 No. 60 / 863,248, No. 11 / 465,317, No. 11 / 423,287, No. 11 / 423,192, and No. 11 / 421,654 are incorporated herein by reference to the extent that they are inconsistent with the description of the present invention.

遍及此申請案之所有參考文獻(例如包括經頒予或授予之專利或等效物之專利文件；專利申請公開案；及非專利文獻或其他源材料)在每一參考文獻至少部分不與本申請案之揭示內容不一致的程度上(例如，部分不一致之參考文獻藉由引用除了該參考文獻之部分不一致之部分以外的部分而併入)以全文引用之方式併入本文中，如同個別地以引用方式併入一般。 All references throughout this application (for example, patent documents including granted or granted patents or equivalents; patent application publications; and non-patent literature or other source materials) are not at least partially To the extent that the disclosure content of the application is inconsistent (for example, a partially inconsistent reference is incorporated by citing parts other than the partially inconsistent part of the reference), it is incorporated by reference in its entirety as if References are incorporated into the general.

本文已使用之術語及表達係用作描述之術語且非限制之術語，且在使用該等術語及表達中不欲排除所展示及描述的特徵之任何等效物或其部分，但應認識到，各種修改在所主張的本發明之範疇內為可能的。因此，應瞭解，雖然已藉由較佳實施例、例示性實施例及可選特徵而特別揭示本發明，但可由熟習此項技術者採用對本文揭示之概念的修改及變化，且應瞭解，將該等修改及變化視作處於由所附申請專利範圍界定之本發明之範疇內。本文提供之特定實施例為本發明之有用實施例的實例，且熟習此項技術者將易瞭解，可藉由使用本發明之描述中所闡述之設備、設備組件、方法步驟之大量變化來執行本發明。如對於熟習此項技術者為明顯的，對於本發明之方法有用之方法及設備可包括大量可選組成及處理元件及步驟。 The terms and expressions used herein are terms used for description and are not limiting, and in using these terms and expressions is not intended to exclude any equivalents or parts of the features shown and described, but it should be recognized Various modifications are possible within the scope of the claimed invention. Therefore, it should be understood that although the present invention has been specifically disclosed through preferred embodiments, exemplary embodiments, and optional features, modifications and changes to the concepts disclosed herein can be adopted by those skilled in the art, and it should be understood that Such modifications and changes are considered to be within the scope of the present invention defined by the scope of the attached patent application. The specific embodiments provided herein are examples of useful embodiments of the invention, and those skilled in the art will readily understand that it can be performed by using a large number of variations of the equipment, equipment components, and method steps described in the description of the invention this invention. As will be apparent to those skilled in the art, methods and equipment useful for the method of the present invention may include a large number of optional components and processing elements and steps.

除非另行規定，否則本文描述或舉例說明之組件的每一表述或組合可用以實踐本發明。 Unless otherwise specified, every expression or combination of components described or illustrated herein may be used to practice the invention.

在說明書中無論何時給出一範圍(例如，溫度範圍、時間範圍或者組 成或濃度範圍)時，所有中間範圍及子範圍以及所給出之範圍中包括的所有個別值均欲包括於揭示內容中。應瞭解，包括於本文之描述中的任何子範圍或者範圍或子範圍中之個別值可自本文之申請專利範圍排除。 Whenever a range is given in the specification (for example, temperature range, time range or group (Concentration or concentration range), all intermediate ranges and subranges and all individual values included in the ranges given are intended to be included in the disclosure. It should be understood that any sub-ranges or individual values included in the ranges or sub-ranges included in the description herein may be excluded from the patent application range herein.

說明書中提及之所有專利及公開案指示熟習與本發明有關之技術者之技術水準。本文引用之參考文獻以其全文引用之方式併入本文中以指示在其出版或申請日期時的技術狀態，且意欲此資訊可在需要時使用於本文中以排除處於先前技術中之特定實施例。舉例而言，在主張物質之組成時，應瞭解，在先於申請者之發明之前的技術中已知並可用之化合物(包括在本文引用之參考文獻中提供致能揭示案所關於的化合物)不欲包括於本文所主張的物質組成中。 All patents and publications mentioned in the specification indicate the technical level of those familiar with the technology related to the present invention. The references cited herein are incorporated by reference in their entirety to indicate the state of the technology at the time of its publication or application date, and it is intended that this information can be used herein as needed to exclude specific embodiments in the prior art . For example, when claiming the composition of a substance, it should be understood that the compounds known and available in the technology prior to the applicant's invention (including those in the references cited herein provide enabling disclosure) It is not intended to be included in the material composition claimed herein.

在用於本文中時，"包含"與"包括"、"含有"或"以......為特徵"同義且為包括性或開放式的，且不排除額外未敍述之元件或方法步驟。在用於本文中時，"由......組成"排除在所主張之元件中未規定的任何元件、步驟或成份。在用於本文中時，"本質上由......組成"不排除不在本質上影響申請專利範圍之基本及新穎特徵的材料或步驟。在本文之每一例子中，術語"包含"、"本質上由...組成"及"由...組成"中之任一者可由另兩個術語中之任一者替代。可在缺少未於本文中特別揭示之任何元件、限制的情況下實踐在本文中適當地以說明方式描述之本發明。 When used in this document, "including" is synonymous with "including", "containing" or "characterized by" and is inclusive or open-ended, and does not exclude additional elements or methods that are not described step. As used herein, "consisting of" excludes any element, step, or ingredient not specified in the claimed element. As used in this article, "essentially consisting of" does not exclude materials or steps that do not substantially affect the basic and novel features of the patent application. In each example herein, the terms "including", "essentially consisting of" and "consisting of" may be replaced by either of the other two terms. The present invention suitably described by way of illustration herein may be practiced in the absence of any elements or limitations not specifically disclosed herein.

一般熟習此項技術者將瞭解，可在實踐本發明時使用除特別舉例說明之內容以外的起始材料、生物材料、試劑、合成方法、純化方法、分析方法、檢定方法及生物學方法而無需採用過度實驗。該等材料及方法的所有技術已知之功能等效物意欲包括於本發明中。已使用之術語及表達係用作描述之術語且非限制之術語，且在使用該等術語及表達中不欲排除所展 示及描述的特徵之任何等效物或其部分，但應認識到，各種修改在所主張的本發明之範疇內為可能的。因此，應瞭解，雖然已藉由較佳實施例及可選特徵而特別揭示本發明，但可由熟習此項技術者採用對本文揭示之概念的修改及變化，且應瞭解，將該等修改及變化視作處於由所附申請專利範圍界定之本發明之範疇內。 Those of ordinary skill in the art will understand that starting materials, biological materials, reagents, synthetic methods, purification methods, analytical methods, assay methods, and biological methods other than those specifically exemplified can be used in the practice of the present invention without the need Use excessive experimentation. All technically known functional equivalents of these materials and methods are intended to be included in the present invention. Used terms and expressions are used as descriptive and non-limiting terms, and are not intended to exclude development in the use of these terms and expressions Any equivalents or parts of the features shown and described, but it should be recognized that various modifications are possible within the scope of the claimed invention. Therefore, it should be understood that although the present invention has been specifically disclosed through preferred embodiments and optional features, modifications and changes to the concepts disclosed herein may be adopted by those skilled in the art, and it should be understood that such modifications and The change is deemed to be within the scope of the invention as defined by the scope of the attached patent application.

Claims (59)

一種二維可延伸且可撓曲(bentable)設備，其包含：一可撓性(flexible)基板，其具有一支撐表面；一設備組件陣列(an array of device component)，其被支撐於該支撐表面上；複數個互連件(interconnects)，其等連接該設備組件陣列之個別設備組件；其中該等互連件具有一中央區域，該中央區域包含不與該可撓性基板實體結合(phisically bonded)之複數個不同(distinct)彎曲(curved)部分。A two-dimensional extensible and bendable device includes: a flexible substrate having a support surface; and an array of device component supported by the support On the surface; a plurality of interconnects (interconnects), which are connected to the individual device components of the device component array; wherein the interconnects have a central area, the central area includes not physically combined with the flexible substrate (phisically Bonded multiple distinct curved parts. 如請求項1之二維可延伸且可撓曲設備，其中該複數個不同彎曲部分之每一者具有一撓曲(bent)組態。The two-dimensional extensible and flexible device of claim 1, wherein each of the plurality of different curved portions has a bent configuration. 如請求項2之二維可延伸且可撓曲設備，其中該撓曲組態相對於該可撓性基板具有大於100nm並小於1mm之一振幅(amplitude)。The two-dimensional extensible and flexible device according to claim 2, wherein the flexure configuration has an amplitude greater than 100 nm and less than 1 mm relative to the flexible substrate. 如請求項1之二維可延伸且可撓曲設備，其中該複數個互連件係選自由下列組成之下列群組：一薄膜、一線(wire)或一織帶(ribbon)。The two-dimensional extensible and flexible device of claim 1, wherein the plurality of interconnections are selected from the following group consisting of: a film, a wire, or a ribbon. 如請求項1之二維可延伸且可撓曲設備，其中該複數個互連件之每一者具有大於300nm並小於1mm之一厚度。The two-dimensional extensible and flexible device of claim 1, wherein each of the plurality of interconnects has a thickness greater than 300 nm and less than 1 mm. 如請求項1之二維可延伸且可撓曲設備，其中該複數個互連件係由選自由下列組成之群組：一金屬、一半導體或一絕緣體。The two-dimensional extensible and flexible device of claim 1, wherein the plurality of interconnections are selected from the group consisting of: a metal, a semiconductor, or an insulator. 如請求項1之二維可延伸且可撓曲設備，其中該複數個互連件電連接該設備組件陣列中之設備組件。The two-dimensional extensible and flexible device according to claim 1, wherein the plurality of interconnects are electrically connected to the device components in the device component array. 如請求項1之二維可延伸且可撓曲設備，其中該複數個互連件之每一者具有一第一末端及一第二末端，其中該中央區域係於該第一末端與該第二末端之間，且該第一末端相對於該第一末端下方(underlying)之該可撓性基板並未移動，而該第二末端相對於該第二末端下方之該可撓性基板並未移動。The two-dimensional extensible and flexible device of claim 1, wherein each of the plurality of interconnects has a first end and a second end, wherein the central area is located between the first end and the first end Between the two ends, and the first end does not move relative to the flexible substrate under the first end, and the second end does not move relative to the flexible substrate under the second end mobile. 如請求項8之二維可延伸且可撓曲設備，其中該第一末端被連接至一第一設備島狀物(island)，而該第二末端被連接至一第二設備島狀物，且該第一設備島狀物及該第二設備島狀物被結合至該可撓性基板。As in the two-dimensional extensible and flexible device of claim 8, wherein the first end is connected to a first device island, and the second end is connected to a second device island, And the first device island and the second device island are bonded to the flexible substrate. 如請求項9之二維可延伸且可撓曲設備，其中該第一末端及該第二末端被結合至該可撓性基板。The two-dimensional extensible and flexible device of claim 9, wherein the first end and the second end are bonded to the flexible substrate. 如請求項1之二維可延伸且可撓曲設備，其中該中央區域之一部分被結合至該可撓性基板。The two-dimensional extensible and flexible device of claim 1, wherein a part of the central area is bonded to the flexible substrate. 如請求項1之二維可延伸且可撓曲設備，其中超過一互連件連接至相鄰的設備組件。The two-dimensional extensible and flexible device as in claim 1, wherein more than one interconnect is connected to adjacent device components. 如請求項1之二維可延伸且可撓曲設備，其中該設備組件係選自由下列組成之群組：一電子設備、一光學設備、一光電設備、一機械設備或一熱設備。The two-dimensional extensible and flexible device of claim 1, wherein the device component is selected from the group consisting of: an electronic device, an optical device, an optoelectronic device, a mechanical device, or a thermal device. 如請求項1之二維可延伸且可撓曲設備，其中該設備組件包含一接觸墊。The two-dimensional extensible and flexible device of claim 1, wherein the device component includes a contact pad. 如請求項1之二維可延伸且可撓曲設備，其中該可撓性基板藉由一彎曲表面(curved surface)所支撐並符合(conform to)該彎曲表面以形成一彎曲電子設備。The two-dimensional extensible and flexible device of claim 1, wherein the flexible substrate is supported by a curved surface and conforms to the curved surface to form a curved electronic device. 如請求項15之二維可延伸且可撓曲設備，其中該彎曲表面係凹入的、突起的、半球形的或其任何組合。The two-dimensional extensible and flexible device of claim 15, wherein the curved surface is concave, convex, hemispherical, or any combination thereof. 如請求項15之二維可延伸且可撓曲設備，其中該彎曲表面包含一球面彎曲透鏡。The two-dimensional extensible and flexible device according to claim 15, wherein the curved surface includes a spherical curved lens. 如請求項17之二維可延伸且可撓曲設備，其中該設備組件陣列包含分布於該球面彎曲透鏡之一表面上之一光二極體陣列。The two-dimensional extensible and flexible device of claim 17, wherein the device component array includes an array of photodiodes distributed on a surface of the spherical curved lens. 如請求項18之二維可延伸且可撓曲設備，其中該可撓性基板係位於該光二極體陣列與該球面彎曲透鏡之間。The two-dimensional extensible and flexible device according to claim 18, wherein the flexible substrate is located between the optical diode array and the spherical curved lens. 如請求項17之二維可延伸且可撓曲設備，其中該球面彎曲透鏡具有低至5mm之一曲率半徑。The two-dimensional extensible and flexible device as in claim 17, wherein the spherical curved lens has a radius of curvature as low as 5 mm. 如請求項1之二維可延伸且可撓曲設備，其中該等設備組件及該等互連件提供力相關感測。The two-dimensional extensible and flexible device of claim 1, wherein the device components and the interconnects provide force-related sensing. 如請求項21之二維可延伸且可撓曲設備，其中該等設備組件包含電容性耦合之一底電極及一頂電極，其中該頂電極位於該中央區域中，並與該底電極隔開一分離距離，其中因為在垂直方向之一力造成該分離距離之改變，導致該底電極與該頂電極之間之電容值之改變。The two-dimensional extensible and flexible device of claim 21, wherein the device components include a bottom electrode and a top electrode capacitively coupled, wherein the top electrode is located in the central region and is spaced from the bottom electrode A separation distance in which a change in the separation distance due to a force in the vertical direction causes a change in the capacitance between the bottom electrode and the top electrode. 如請求項22之二維可延伸且可撓曲設備，其中該複數個不同彎曲部分包含使該頂電極之一第一末端電連接至與該可撓性基板結合之一第一電極之一互連件，及使該頂電極之一第二末端電連接至與該可撓性基板結合之一第二電極之一互連件。The two-dimensional extensible and flexible device of claim 22, wherein the plurality of different curved portions include electrically connecting a first end of the top electrode to one of the first electrodes combined with the flexible substrate A connecting member, and an interconnecting member for electrically connecting a second end of the top electrode to a second electrode combined with the flexible substrate. 如請求項1之二維可延伸且可撓曲設備，其選自由下列所組成之群組：可撓性顯示器、電子織物(electronic fabric)、生物感應器及物理感應器。The two-dimensional extensible and flexible device of claim 1 is selected from the group consisting of flexible displays, electronic fabrics, biosensors, and physical sensors. 如請求項1之二維可延伸且可撓曲設備，其能夠延伸高達100%、壓縮高達50%，或以大於或等於5mm之一曲率半徑撓曲，而無互連件或設備組件斷裂。As in the two-dimensional extensible and flexible device of claim 1, it is capable of extending up to 100%, compressing up to 50%, or flexing with a radius of curvature greater than or equal to 5 mm without breakage of interconnects or device components. 一種製造一設備之一個或多個可延伸組件之方法，該方法包含以下步驟：提供具有一接收表面之一彈性體基板(elastomeric substrate)，其中該基板具有一第一應變位準(level of strain)；產生結合位點(bonding site)之一圖案於一個或多個組件上、該彈性體基板之該接收表面上，或該一個或多個組件及該彈性體基板之該接收表面兩者上；結合該一個或多個組件及一個或多個設備組件至具有該第一應變位準之該彈性體基板之該接收表面；及施加一力至該彈性體基板，於該基板之應變位準中產生一改變自該第一應變位準至不同於該第一應變位準之一第二應變位準，其中於該基板之該應變位準中自該第一應變位準至該第二應變位準的改變使得該一個或多個組件撓曲，從而產生該一個或多個可延伸組件，該一個或多個可延伸組件之每一者具有結合至該基板的一第一末端及一第二末端及以一撓曲組態被提供之一中央區域。A method of manufacturing one or more extensible components of an apparatus, the method comprising the steps of: providing an elastomeric substrate having a receiving surface, wherein the substrate has a first level of strain ); A pattern of bonding sites (bonding site) is generated on one or more components, the receiving surface of the elastomer substrate, or both the one or more components and the receiving surface of the elastomer substrate ; Combining the one or more components and one or more device components to the receiving surface of the elastomer substrate with the first strain level; and applying a force to the elastomer substrate, the strain level of the substrate A change occurs from the first strain level to a second strain level that is different from the first strain level, wherein the first strain level to the second strain is in the strain level of the substrate The change in level causes the one or more components to flex, thereby producing the one or more extensible components, each of the one or more extensible components having a first end bonded to the substrate and And the second end is provided with a central region of one of the flexure configuration. 一種製造一可延伸設備之方法，其包含：提供一基板，其具有波狀(wavy)之一接收表面；使該波狀表面平滑(smoothing)，其係藉由旋塗(spin-coating)一聚合物部分填充該波狀表面之一個或多個凹入特徵而產生一平滑波狀(smoothly-wavy)基板；沈積一設備組件以至少部分保形(conformally)接觸該接收表面；抵靠(against)被至少部分保形接觸之該基板而澆鑄(casting)一聚合印模(polymeric stamp)；及自該基板移除該聚合印模，藉此轉移該設備組件至該印模，其中轉移至該印模之該設備組件具有結合該設備組件至該印模之結合位點(bond sites)之一圖案。A method of manufacturing an extensible device, comprising: providing a substrate having a wavy receiving surface; smoothing the wavy surface by spin-coating a The polymer partially fills one or more concave features of the wavy surface to produce a smoothly-wavy substrate; depositing a device component to at least partially conformally contact the receiving surface; against ) Casting a polymeric stamp on the substrate that is at least partially conformally contacted; and removing the polymeric stamp from the substrate, thereby transferring the device assembly to the stamp, wherein the transfer to the The device component of the stamp has a pattern that bonds the device component to the bonding sites of the stamp. 一種製造一設備之方法，該方法包含以下步驟：提供以一或多個設備組件預圖案化的一基板，該基板該一或多個設備組件由該基板的一接收表面所支撐；組裝(assembling)複數個可印刷半導體元件於該基板上，其係藉由接觸印刷該等可印刷半導體元件至該基板之該接收表面上或提供於該基板之該接收表面上之一個或多個結構上，其中該等可印刷半導體元件之至少一部分經定位以使得該等可印刷半導體元件之該至少一部分在空間上對準、電接觸或在空間上對準並電接觸由該基板所支持之該一個或多個設備組件；及組裝額外可印刷半導體元件於該基板上，其係藉由接觸印刷該等額外可印刷半導體元件至提供於該基板之該接收表面上之該等半導體元件上，或接觸印刷該等額外可印刷半導體元件至提供於一個或多個中間(intermediate)結構上，從而產生一多層設備結構，該一個或多個中間結構係提供於該等半導體元件及該等額外半導體元件之間，該等半導體元件係提供於該基板之該接收表面上。A method of manufacturing a device, the method comprising the steps of: providing a substrate pre-patterned with one or more device components, the one or more device components being supported by a receiving surface of the substrate; assembling ) A plurality of printable semiconductor elements on the substrate by contact printing the printable semiconductor elements onto the receiving surface of the substrate or on one or more structures provided on the receiving surface of the substrate, Wherein at least a portion of the printable semiconductor elements are positioned such that the at least a portion of the printable semiconductor elements are spatially aligned, electrically contacted, or spatially aligned and electrically contacted with the one supported by the substrate or A plurality of device components; and assembling additional printable semiconductor elements on the substrate by printing the additional printable semiconductor elements by contact onto the semiconductor elements provided on the receiving surface of the substrate, or by contact printing These additional printable semiconductor elements are provided on one or more intermediate structures to produce a multilayer device Configuration, the one or more intermediate structure between those lines providing such additional semiconductor element and the semiconductor element, a semiconductor element such lines provided on the receiving surface of the substrate. 一種製造一多層設備結構之方法，該方法包含以下步驟：提供一基板，該基板以一或多個設備組件預圖案化，該一個或多個設備組件藉由該基板之一接收表面所支撐；組裝一第一組可印刷半導體元件於該基板上，其係藉由接觸印刷該等可印刷半導體元件於該基板之該接收表面上，或於基板之該接收表面上之一個或多個結構上，藉此產生一第一設備層；提供一中間層(interlayer)於該第一組可印刷半導體元件上，該中間層具有一接收表面；組裝一第二組可印刷半導體元件於該中間層上，其係藉由接觸印刷該等可印刷半導體元件於該中間層之該接收表面上或該中間層之該接收表面上之一個或多個結構上，藉此產生一第二設備層；及建立電接觸件於該第一設備層中的該等可印刷半導體元件的至少一部分及該第二設備層中該等可印刷半導體元件的至少一部分之間。A method of manufacturing a multi-layer device structure, the method comprising the following steps: providing a substrate, the substrate is pre-patterned with one or more device components, the one or more device components are supported by a receiving surface of the substrate Assemble a first set of printable semiconductor elements on the substrate by printing the printable semiconductor elements on the receiving surface of the substrate by contact, or one or more structures on the receiving surface of the substrate On this, a first device layer is produced; an interlayer is provided on the first set of printable semiconductor elements, the intermediate layer has a receiving surface; a second set of printable semiconductor elements is assembled on the intermediate layer On, it prints the printable semiconductor elements on the receiving surface of the intermediate layer or one or more structures on the receiving surface of the intermediate layer by contact printing, thereby generating a second device layer; and Establishing electrical contacts on at least a portion of the printable semiconductor elements in the first device layer and at least a portion of the printable semiconductor elements in the second device layer . 一種製造一可延伸設備組件之方法，該方法包含：提供一基板，其具有波狀之一接收表面；使該波狀表面平滑，其係藉由旋塗一聚合物以部分填充該波狀表面之一個或多個凹入特徵，以產生一平滑波狀基板；沈積一設備組件以至少部分保形接觸該接收表面；抵靠被至少部分保形接觸之該基板而澆鑄一聚合印模；及自該基板移除該聚合印模，藉此轉移該設備組件至該印模，其中轉移至該印模之該設備組件具有結合該設備組件至該印模之結合位點之一圖案。A method of manufacturing an extensible device assembly, the method comprising: providing a substrate having a wave-shaped receiving surface; smoothing the wave-shaped surface, which partially fills the wave-shaped surface by spin coating a polymer One or more concave features to produce a smooth wavy substrate; depositing a device component to at least partially conformally contact the receiving surface; casting a polymeric stamp against the substrate that is at least partially conformally contacted; and The polymerization stamp is removed from the substrate, thereby transferring the device component to the stamp, wherein the device component transferred to the stamp has a pattern that bonds the device component to the bonding site of the stamp. 一種製造一可延伸且可撓曲設備之方法，該方法包含以下步驟：提供具有一接收表面之一可撓性基板；結合複數個設備組件至該接收表面，其中藉由一個或多個互連件使至少一設備組件連接至另一設備組件，其中至少一互連件具有彎曲並自該可撓性基板實體分離之一區域。A method of manufacturing an extensible and flexible device, the method comprising the steps of: providing a flexible substrate having a receiving surface; combining a plurality of device components to the receiving surface, wherein by one or more interconnections The device connects at least one device component to another device component, wherein at least one interconnector has a region that is bent and physically separated from the flexible substrate. 如請求項31之方法，其中該互連件係一電互連件，且該設備組件係下列其中之一或多者：一接觸墊、一光電二極體、一發光二極體、一電極、一電晶體、一積體電路、一生物感應器、一化學感應器、一加速度計、一壓力感應器或一傳感器。The method of claim 31, wherein the interconnect is an electrical interconnect, and the device component is one or more of the following: a contact pad, a photodiode, a light-emitting diode, an electrode , A transistor, an integrated circuit, a biological sensor, a chemical sensor, an accelerometer, a pressure sensor or a sensor. 如請求項31之方法，其中彎曲之該區域與該可撓性基板之間具有介於100nm至1mm之一分離距離。The method of claim 31, wherein the bent region has a separation distance between 100 nm and 1 mm between the flexible substrate. 如請求項31之方法，其進一步包含以下步驟：對該可撓性基板之該接收表面之一應變位準產生自一第一應變位準至一第二應變位準的一改變；其中於該第一應變位準該設備組件被結合至該可撓性基板，而應變位準之該改變使得該設備組件之一部分被撓曲且自該可撓性基板分離。The method of claim 31, further comprising the steps of: generating a change in a strain level of the receiving surface of the flexible substrate from a first strain level to a second strain level; wherein in the The first strain level the device component is bonded to the flexible substrate, and the change in the strain level causes a portion of the device component to be flexed and separated from the flexible substrate. 如請求項31之方法，其中該複數個設備組件形成一二維設備陣列，其中至少兩個互連件電連接至至一第一設備組件；其中在該結合之步驟期間，該至少兩個互連件自該第一設備組件在該接收表面之一平面中沿至少兩個不同方向延伸以形成該二維設備陣列，且該等互連件之每一者具有一區域，該區域係彎曲並自該可撓性基板實體分離。The method of claim 31, wherein the plurality of device components form a two-dimensional device array, wherein at least two interconnections are electrically connected to a first device component; wherein during the step of combining, the at least two device components The connecting member extends from the first device component in at least two different directions in a plane of the receiving surface to form the two-dimensional device array, and each of the interconnecting members has an area that is curved and It is physically separated from the flexible substrate. 如請求項35之方法，其進一步包含以下步驟：對該可撓性基板之該接收表面之一應變位準產生在一第一方向及一第二方向中的一改變；其中於該第一應變位準該設備組件被結合至該可撓性基板，而應變位準之該改變使得一第一互連件之一部分被撓曲，且在該第一方向中自該可撓性基板分離，並使得一第二互連件之一部分被撓曲，且在該第二方向中自該可撓性基板分離。The method of claim 35, further comprising the steps of: generating a change in a first direction and a second direction of a strain level of the receiving surface of the flexible substrate; wherein the first strain The device component is bonded to the flexible substrate, and the change in strain level causes a portion of a first interconnect to be flexed and separated from the flexible substrate in the first direction, and A part of a second interconnect is flexed and separated from the flexible substrate in the second direction. 如請求項36之方法，其中每一互連件之彎曲之區域與該可撓性基板之間具有介於100nm至1mm之一分離距離。The method of claim 36, wherein the bent region of each interconnection has a separation distance between 100 nm and 1 mm between the flexible substrate. 如請求項35之方法，其中至少兩個互連件具有一第一末端及一第二末端，其中具有彎曲並自該基板分離之該區域係介於該第一末端及該第二末端之間之一中央部分，其中：可延伸之該至少兩個互連件之每一者之該第一末端係與該第一設備組件電通信；可延伸之該至少兩個互連件之每一者之每一中央部分包含至少兩個撓曲組態區域及至少一接觸點，該至少一接觸點置於該至少兩個撓曲組態區域之間；及該至少一接觸點之每一者係與該可撓性基板之該接收表面實體通信。The method of claim 35, wherein at least two interconnections have a first end and a second end, wherein the region having the bend and separated from the substrate is between the first end and the second end A central portion, wherein: the first end of each of the at least two interconnects that can be extended is in electrical communication with the first device assembly; each of the at least two interconnects that can be extended Each central portion includes at least two flexure configuration areas and at least one contact point, the at least one contact point is disposed between the at least two flexure configuration areas; and each of the at least one contact point is Physically communicate with the receiving surface of the flexible substrate. 如請求項38之方法，其中該至少一接觸點係結合至該可撓性基板之該接收表面。The method of claim 38, wherein the at least one contact point is bonded to the receiving surface of the flexible substrate. 如請求項35之方法，其中該設備組件包含選自下列組成之群組中的一或多個材料：一金屬、一半導體、一絕緣體、一壓電材料、一鐵電材料、一磁致伸縮(magnetostrictive)材料、一電致伸縮(electrostrictive)材料、一超導體、一鐵磁材料、及一熱電材料。The method of claim 35, wherein the device component comprises one or more materials selected from the group consisting of: a metal, a semiconductor, an insulator, a piezoelectric material, a ferroelectric material, a magnetostriction (magnetostrictive) material, an electrostrictive material, a superconductor, a ferromagnetic material, and a thermoelectric material. 如請求項35之方法，其中該設備組件係一電子設備、一光學設備、一光電設備、一機械設備、一微機電設備、一奈米機電設備、一微流體設備或一熱設備。The method of claim 35, wherein the device component is an electronic device, an optical device, an optoelectronic device, a mechanical device, a microelectromechanical device, a nanoelectromechanical device, a microfluidic device, or a thermal device. 如請求項41之方法，其中該至少兩個互連件係可調(tunable)設備組件，其每一者具有至少一電性質、光性質或機械性質選擇性地隨由該至少兩個撓曲組態區域所提供之該中央部分之一應變位準而改變。The method of claim 41, wherein the at least two interconnections are tunable device components, each of which has at least one electrical, optical, or mechanical property to selectively follow the at least two deflections A strain level of the central part provided by the configuration area changes. 如請求項38之方法，其中該至少兩個互連件係複數個可延伸互連，且其中該複數個可延伸互連件之至少一者包含與該接收表面實體通信之該至少一接觸點及延伸自該至少一接觸點之三個或三個以上之撓曲組態區域。The method of claim 38, wherein the at least two interconnections are a plurality of extensible interconnections, and wherein at least one of the plurality of extensible interconnections includes the at least one contact point in physical communication with the receiving surface And three or more flexure configuration areas extending from the at least one contact point. 如請求項38之方法，其中該至少兩個互連件之每一者進一步包含與該第一末端、該第二末端、或該第一末端及該第二末端兩者電接觸之一或多個接觸墊。The method of claim 38, wherein each of the at least two interconnects further comprises one or more electrical contacts with the first end, the second end, or both the first end and the second end Contact pads. 如請求項44之方法，其中該第一設備組件與該一個或多個接觸墊電接觸。The method of claim 44, wherein the first device component is in electrical contact with the one or more contact pads. 如請求項35之方法，其中該至少兩個可延伸互連件之每一者具有一捲曲構形(coiled conformation)、一起皺(wrinkled)構形、一彎曲(buckled)構形及/或一波狀組態。The method of claim 35, wherein each of the at least two extensible interconnects has a coiled conformation, a wrinkled configuration, a buckled configuration, and / or a Wave configuration. 如請求項35之方法，其中該至少兩個撓曲組態區域之每一者包含一摺疊(folded)區域、一凸起(convex)區域、一凹入(concave)區域或其任何組合。The method of claim 35, wherein each of the at least two flexure configuration regions includes a folded region, a convex region, a concave region, or any combination thereof. 如請求項31之方法，其中該可撓性基板包含一彈性體材料。The method of claim 31, wherein the flexible substrate comprises an elastomer material. 如請求項35之方法，其中該至少一個設備組件係複數個設備組件，且其中該至少兩個可延伸互連件係複數個可延伸互連件。The method of claim 35, wherein the at least one device component is a plurality of device components, and wherein the at least two extensible interconnects are a plurality of extensible interconnects. 如請求項49之方法，其中該二維設備陣列具有一柵格組態、一花形(floral)組態、一橋接組態或其任何組合。The method of claim 49, wherein the two-dimensional device array has a grid configuration, a floral configuration, a bridge configuration, or any combination thereof. 如請求項49之方法，其中該複數個設備組件之一或多者藉由該複數個可延伸互連件而連接至相鄰之若干個設備組件。The method of claim 49, wherein one or more of the plurality of equipment components are connected to adjacent plurality of equipment components through the plurality of extensible interconnects. 如請求項51之方法，其中該複數個可延伸互連件之至少一者係定向於與該複數個可延伸互連件之另一者不同之一方向。The method of claim 51, wherein at least one of the plurality of extensible interconnects is oriented in a different direction from the other of the plurality of extensible interconnects. 如請求項49之方法，其中該二維設備陣列之至少一部分包含該複數個可延伸互連件之二者或二者以上彼此在一方向上平行對準，或該複數個可延伸互連件之二者或二者以上在兩個或兩個以上的方向上定向。The method of claim 49, wherein at least a portion of the two-dimensional device array includes two or more of the plurality of extensible interconnects aligned parallel to each other in one direction, or the plurality of extensible interconnects Two or more are oriented in two or more directions. 如請求項49之方法，其中該二維設備陣列包含兩個或兩個以上之設備層，且其中每一設備層包含複數個該設備組件及複數個該可延伸互連件。The method of claim 49, wherein the two-dimensional device array includes two or more device layers, and wherein each device layer includes a plurality of the device components and a plurality of the extensible interconnects. 如請求項49之方法，其中該可撓性基板之該接收表面之至少一部份係彎曲狀、凹入、凸起或半球形的。The method of claim 49, wherein at least a portion of the receiving surface of the flexible substrate is curved, concave, convex, or hemispherical. 如請求項49之方法，其中該二維設備陣列包含下列之一或多者：一光偵測器、一光二極體陣列、一顯示器、一發光設備、一光伏打設備、一感測器陣列、一薄片掃描器(sheet scanner)、一LED顯示器、一半導體雷射陣列、一光學成像系統、一大面積電子設備、一電晶體陣列、一邏輯閘陣列、一微處理器、一積體電路或其任何組合。The method of claim 49, wherein the two-dimensional device array includes one or more of the following: a photodetector, a photodiode array, a display, a light emitting device, a photovoltaic device, and a sensor array , A sheet scanner, a LED display, a semiconductor laser array, an optical imaging system, a large area of electronic equipment, a transistor array, a logic gate array, a microprocessor, an integrated circuit Or any combination thereof. 如請求項49之方法，其中該二維設備陣列具有一花形組態，其中該至少兩個可延伸互連件係複數個可延伸互連件，且其中該複數個可延伸互連件之至少一者包含：至少一接觸點，其與該接收表面實體通聯；及延伸自該至少一接觸點之三個或三個以上之撓曲組態區域。The method of claim 49, wherein the two-dimensional device array has a flower-shaped configuration, wherein the at least two extensible interconnects are a plurality of extensible interconnects, and wherein at least the plurality of extensible interconnects One includes: at least one contact point that is in physical communication with the receiving surface; and three or more flexure configuration areas extending from the at least one contact point. 如請求項34之方法，其中該第一應變位準延伸該接收表面，且在該應變位準中產生該改變之步驟係經延伸之該接收表面之一至少一部分鬆弛(relaxation)。The method of claim 34, wherein the first strain level extends the receiving surface, and the step of generating the change in the strain level is relaxation of at least a portion of the extended receiving surface. 如請求項36之方法，其中在該第一方向中之該第一應變位準及在該第二方向中之該第二應變位準之每一者在該第一方向中及在該第二方向中延伸該接收表面，且在該應變位準中產生該改變之步驟係經延伸之該接收表面在該第一方向中及在該第二方向中之一至少一部分鬆弛。The method of claim 36, wherein each of the first strain level in the first direction and the second strain level in the second direction is in the first direction and in the second The receiving surface extends in the direction, and the step of generating the change in the strain level is that at least a portion of the extended receiving surface relaxes in one of the first direction and the second direction.
TW106107273A 2006-09-06 2007-09-06 Two-dimensional extendable and flexible device and method of manufacturing same TWI654770B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US82468306P 2006-09-06 2006-09-06
US60/824,683 2006-09-06
US94462607P 2007-06-18 2007-06-18
US60/944,626 2007-06-18

Publications (2)

Publication Number Publication Date
TW201735380A TW201735380A (en) 2017-10-01
TWI654770B true TWI654770B (en) 2019-03-21

Family

ID=39158048

Family Applications (3)

Application Number Title Priority Date Filing Date
TW106107273A TWI654770B (en) 2006-09-06 2007-09-06 Two-dimensional extendable and flexible device and method of manufacturing same
TW103117812A TWI587527B (en) 2006-09-06 2007-09-06 Two-dimensional device array
TW096133310A TWI485863B (en) 2006-09-06 2007-09-06 Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW103117812A TWI587527B (en) 2006-09-06 2007-09-06 Two-dimensional device array
TW096133310A TWI485863B (en) 2006-09-06 2007-09-06 Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics

Country Status (7)

Country Link
EP (1) EP2064710A4 (en)
JP (3) JP5578509B2 (en)
KR (5) KR101814683B1 (en)
CN (2) CN101681695B (en)
MY (2) MY172115A (en)
TW (3) TWI654770B (en)
WO (1) WO2008030960A2 (en)

Families Citing this family (172)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7557433B2 (en) 2004-10-25 2009-07-07 Mccain Joseph H Microelectronic device with integrated energy source
US7799699B2 (en) 2004-06-04 2010-09-21 The Board Of Trustees Of The University Of Illinois Printable semiconductor structures and related methods of making and assembling
US8217381B2 (en) 2004-06-04 2012-07-10 The Board Of Trustees Of The University Of Illinois Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics
US7521292B2 (en) 2004-06-04 2009-04-21 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
CN103646848B (en) 2004-06-04 2018-06-05 伊利诺伊大学评议会 The method of assembling printable semiconductor elements and manufacture electronic device
WO2008036837A2 (en) 2006-09-20 2008-03-27 The Board Of Trustees Of The University Of Illinois Release strategies for making transferable semiconductor structures, devices and device components
KR101610885B1 (en) 2007-01-17 2016-04-08 더 보오드 오브 트러스티스 오브 더 유니버시티 오브 일리노이즈 Optical systems fabricated by printing-based assembly
KR101755207B1 (en) 2008-03-05 2017-07-19 더 보드 오브 트러스티즈 오브 더 유니버시티 오브 일리노이 Stretchable and foldable electronic devies
US8470701B2 (en) 2008-04-03 2013-06-25 Advanced Diamond Technologies, Inc. Printable, flexible and stretchable diamond for thermal management
US7927976B2 (en) 2008-07-23 2011-04-19 Semprius, Inc. Reinforced composite stamp for dry transfer printing of semiconductor elements
WO2010036807A1 (en) 2008-09-24 2010-04-01 The Board Of Trustees Of The University Of Illinois Arrays of ultrathin silicon solar microcells
US9119533B2 (en) 2008-10-07 2015-09-01 Mc10, Inc. Systems, methods, and devices having stretchable integrated circuitry for sensing and delivering therapy
US8886334B2 (en) 2008-10-07 2014-11-11 Mc10, Inc. Systems, methods, and devices using stretchable or flexible electronics for medical applications
EP2349440B1 (en) 2008-10-07 2019-08-21 Mc10, Inc. Catheter balloon having stretchable integrated circuitry and sensor array
US8097926B2 (en) 2008-10-07 2012-01-17 Mc10, Inc. Systems, methods, and devices having stretchable integrated circuitry for sensing and delivering therapy
US8372726B2 (en) 2008-10-07 2013-02-12 Mc10, Inc. Methods and applications of non-planar imaging arrays
US8389862B2 (en) 2008-10-07 2013-03-05 Mc10, Inc. Extremely stretchable electronics
US9123614B2 (en) 2008-10-07 2015-09-01 Mc10, Inc. Methods and applications of non-planar imaging arrays
KR101041139B1 (en) * 2008-11-04 2011-06-13 삼성모바일디스플레이주식회사 Thin Film Transistor, The method for Using The Same and Organic Light Emitting Display Device Comprising the TFT
WO2010056857A2 (en) * 2008-11-12 2010-05-20 Mc10, Inc. Extremely stretchable electronics
EP2351068B1 (en) 2008-11-19 2020-11-04 X Display Company Technology Limited Printing semiconductor elements by shear-assisted elastomeric stamp transfer
JP2012515436A (en) * 2009-01-12 2012-07-05 エムシー１０ インコーポレイテッド Non-planar imaging array methods and applications
EP2392196B1 (en) 2009-01-30 2018-08-22 IMEC vzw Stretchable electronic device
KR101870690B1 (en) 2009-05-12 2018-06-25 더 보드 오브 트러스티즈 오브 더 유니버시티 오브 일리노이 Printed assemblies of ultrathin, microscale inorganic light emitting diodes for deformable and semitransparent displays
FR2947063B1 (en) 2009-06-19 2011-07-01 Commissariat Energie Atomique OVERHEAD PROJECTOR
US8261660B2 (en) 2009-07-22 2012-09-11 Semprius, Inc. Vacuum coupled tool apparatus for dry transfer printing semiconductor elements
KR101077789B1 (en) 2009-08-07 2011-10-28 한국과학기술원 Manufacturing method for LED display and LED display manufactured by the same
KR101113692B1 (en) 2009-09-17 2012-02-27 한국과학기술원 A manufacturing method for solar cell and GaN solar cell manufactured by the same
WO2011041727A1 (en) 2009-10-01 2011-04-07 Mc10, Inc. Protective cases with integrated electronics
JP6046491B2 (en) 2009-12-16 2016-12-21 ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ In vivo electrophysiology using conformal electronics
US10441185B2 (en) 2009-12-16 2019-10-15 The Board Of Trustees Of The University Of Illinois Flexible and stretchable electronic systems for epidermal electronics
US9936574B2 (en) 2009-12-16 2018-04-03 The Board Of Trustees Of The University Of Illinois Waterproof stretchable optoelectronics
WO2011087301A2 (en) 2010-01-15 2011-07-21 성균관대학교산학협력단 Graphene protective film serving as a gas and moisture barrier, method for forming same, and use thereof
US8450779B2 (en) * 2010-03-08 2013-05-28 International Business Machines Corporation Graphene based three-dimensional integrated circuit device
TWI556802B (en) 2010-03-12 2016-11-11 美國伊利諾大學理事會 Implantable biomedical devices on bioresorbable substrates
JP5751728B2 (en) 2010-03-17 2015-07-22 ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ Embedded biomedical devices on bioabsorbable substrates
CA2832795C (en) * 2010-04-12 2018-01-09 Tufts University Silk electronic components and the method for fabricating the same
EP2622219B1 (en) * 2010-09-27 2021-08-11 Techtonic Pty Ltd Undulatory structures
CN102001622B (en) * 2010-11-08 2013-03-20 中国科学技术大学 Method for preparing air bridge type nano device
US9442285B2 (en) 2011-01-14 2016-09-13 The Board Of Trustees Of The University Of Illinois Optical component array having adjustable curvature
EP2681538B1 (en) 2011-03-11 2019-03-06 Mc10, Inc. Integrated devices to facilitate quantitative assays and diagnostics
TWI455341B (en) * 2011-03-21 2014-10-01 Motech Ind Inc Method for manufacturing solar cells
JP6078528B2 (en) * 2011-04-18 2017-02-08 アディダス アーゲー Process and apparatus for continuously encapsulating elongated components, and the resulting encapsulated elongated component
US9765934B2 (en) 2011-05-16 2017-09-19 The Board Of Trustees Of The University Of Illinois Thermally managed LED arrays assembled by printing
KR102000302B1 (en) 2011-05-27 2019-07-15 엠씨10, 인크 Electronic, optical and/or mechanical apparatus and systems and methods for fabricating same
WO2012167096A2 (en) 2011-06-03 2012-12-06 The Board Of Trustees Of The University Of Illinois Conformable actively multiplexed high-density surface electrode array for brain interfacing
CN102244015B (en) * 2011-06-17 2012-12-19 华中科技大学 Method for performing flexible electronic patterning on pretensioning elastic base plate
US9757050B2 (en) 2011-08-05 2017-09-12 Mc10, Inc. Catheter balloon employing force sensing elements
DE112012003250T5 (en) 2011-08-05 2014-04-30 Mc10, Inc. Catheter Balloon method and apparatus using sensing elements
WO2013033724A1 (en) 2011-09-01 2013-03-07 Mc10, Inc. Electronics for detection of a condition of tissue
DE112012004146T5 (en) 2011-10-05 2014-11-06 Mc10, Inc. Cardiac catheter using surface-true electronics for imaging
KR101979354B1 (en) 2011-12-01 2019-08-29 더 보오드 오브 트러스티스 오브 더 유니버시티 오브 일리노이즈 Transient devices designed to undergo programmable transformations
FR2985371A1 (en) * 2011-12-29 2013-07-05 Commissariat Energie Atomique METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE ON A SUPPORT
US8492208B1 (en) 2012-01-05 2013-07-23 International Business Machines Corporation Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process
CN102610534A (en) * 2012-01-13 2012-07-25 华中科技大学 Stretchable RFID (Radio Frequency Identification) electronic tag and manufacturing method thereof
KR102034575B1 (en) * 2012-03-19 2019-10-21 루미리즈 홀딩 비.브이. Singulation of light emitting devices before and after application of phosphor
CN102610672A (en) * 2012-03-23 2012-07-25 合肥工业大学 Heterojunction type photoelectric detector and manufacturing method thereof
US9554484B2 (en) 2012-03-30 2017-01-24 The Board Of Trustees Of The University Of Illinois Appendage mountable electronic devices conformable to surfaces
US9226402B2 (en) 2012-06-11 2015-12-29 Mc10, Inc. Strain isolation structures for stretchable electronics
US9247637B2 (en) 2012-06-11 2016-01-26 Mc10, Inc. Strain relief structures for stretchable interconnects
US9295842B2 (en) 2012-07-05 2016-03-29 Mc10, Inc. Catheter or guidewire device including flow sensing and use thereof
JP2015521894A (en) 2012-07-05 2015-08-03 エムシー１０ インコーポレイテッドＭｃ１０，Ｉｎｃ． Catheter device including flow sensing
CN102903841B (en) * 2012-09-18 2015-09-09 中国科学院宁波材料技术与工程研究所 A kind of temperature controlled magnetic electron device, its preparation method and application
US9171794B2 (en) 2012-10-09 2015-10-27 Mc10, Inc. Embedding thin chips in polymer
JP2016500869A (en) 2012-10-09 2016-01-14 エムシー１０ インコーポレイテッドＭｃ１０，Ｉｎｃ． Conformal electronic circuit integrated with clothing
CN102983791A (en) * 2012-10-26 2013-03-20 苏州大学 Temperature difference alternating current power generation device and power generation method thereof
WO2014104267A1 (en) 2012-12-28 2014-07-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR102051519B1 (en) 2013-02-25 2019-12-03 삼성전자주식회사 Thin Film Transistor on Fiber and Manufacturing Method of the same
WO2014169218A2 (en) 2013-04-12 2014-10-16 The Board Of Trustees Of The University Of Illinois Materials, electronic systems and modes for active and passive transience
US9706647B2 (en) 2013-05-14 2017-07-11 Mc10, Inc. Conformal electronics including nested serpentine interconnects
EP3030873A4 (en) 2013-08-05 2017-07-05 Mc10, Inc. Flexible temperature sensor including conformable electronics
CN105705093A (en) 2013-10-07 2016-06-22 Mc10股份有限公司 Conformal sensor systems for sensing and analysis
CN103560157B (en) * 2013-11-19 2016-02-24 中国科学院上海微***与信息技术研究所 Strain structure and preparation method thereof
CN105813545A (en) 2013-11-22 2016-07-27 Mc10股份有限公司 Conformal sensor systems for sensing and analysis of cardiac activity
KR102396850B1 (en) 2014-01-06 2022-05-11 메디데이타 솔루션즈, 인코포레이티드 Encapsulated conformal electronic systems and devices, and methods of making and using the same
KR20160129007A (en) 2014-03-04 2016-11-08 엠씨10, 인크 Multi-part flexible encapsulation housing for electronic devices
CA2941248A1 (en) 2014-03-12 2015-09-17 Mc10, Inc. Quantification of a change in assay
CN103869607A (en) * 2014-03-18 2014-06-18 无锡中微掩模电子有限公司 Method for removing chromium metal film from binary mask
WO2015168273A1 (en) 2014-05-02 2015-11-05 Synopsys, Inc. 3d tcad simulation
US10207916B2 (en) 2014-05-28 2019-02-19 3M Innovative Properties Company MEMS devices on flexible substrate
SG11201610371TA (en) 2014-07-11 2017-01-27 Intel Corp Bendable and stretchable electronic devices and methods
US9434150B2 (en) * 2014-07-20 2016-09-06 X-Celeprint Limited Apparatus and methods for micro-transfer-printing
KR102161644B1 (en) 2014-08-20 2020-10-06 삼성디스플레이 주식회사 Stretchable display panel and display device having the same
CN104153128B (en) * 2014-08-26 2017-03-08 青岛大学 A kind of preparation method based on ordered arrangement distorted-structure flexible extensible device
US9899330B2 (en) 2014-10-03 2018-02-20 Mc10, Inc. Flexible electronic circuits with embedded integrated circuit die
US10297572B2 (en) 2014-10-06 2019-05-21 Mc10, Inc. Discrete flexible interconnects for modules of integrated circuits
USD781270S1 (en) 2014-10-15 2017-03-14 Mc10, Inc. Electronic device having antenna
US9398705B2 (en) * 2014-12-02 2016-07-19 Flextronics Ap, Llc. Stretchable printed electronic sheets to electrically connect uneven two dimensional and three dimensional surfaces
US9991326B2 (en) 2015-01-14 2018-06-05 Panasonic Intellectual Property Management Co., Ltd. Light-emitting device comprising flexible substrate and light-emitting element
KR102356697B1 (en) * 2015-01-15 2022-01-27 삼성디스플레이 주식회사 Stretchable display device and manufacturing method of the same
KR102456698B1 (en) 2015-01-15 2022-10-19 삼성디스플레이 주식회사 Stretchable display device
KR102320382B1 (en) 2015-01-28 2021-11-02 삼성디스플레이 주식회사 Electronic device
WO2016134306A1 (en) 2015-02-20 2016-08-25 Mc10, Inc. Automated detection and configuration of wearable devices based on on-body status, location, and/or orientation
US10398343B2 (en) 2015-03-02 2019-09-03 Mc10, Inc. Perspiration sensor
KR102335807B1 (en) * 2015-03-10 2021-12-08 삼성디스플레이 주식회사 Display device
KR102385327B1 (en) * 2015-04-06 2022-04-12 삼성디스플레이 주식회사 Flexible display device and method of manufacturing the same
BR112017025616A2 (en) 2015-06-01 2018-08-07 Univ Illinois alternative approach to uv capture
MX2017015586A (en) 2015-06-01 2018-08-23 Univ Illinois Miniaturized electronic systems with wireless power and near-field communication capabilities.
US9841548B2 (en) 2015-06-30 2017-12-12 Apple Inc. Electronic devices with soft input-output components
US10026721B2 (en) 2015-06-30 2018-07-17 Apple Inc. Electronic devices with soft input-output components
CN105049033B (en) * 2015-07-01 2017-11-24 东南大学 Nor gate based on GaAs base low-leakage current double cantilever beam switch
WO2017015000A1 (en) 2015-07-17 2017-01-26 Mc10, Inc. Conductive stiffener, method of making a conductive stiffener, and conductive adhesive and encapsulation layers
WO2017031129A1 (en) 2015-08-19 2017-02-23 Mc10, Inc. Wearable heat flux devices and methods of use
EP4079383A3 (en) 2015-10-01 2023-02-22 Medidata Solutions, Inc. Method and system for interacting with a virtual environment
EP3359031A4 (en) 2015-10-05 2019-05-22 Mc10, Inc. Method and system for neuromodulation and stimulation
DE102015014256B4 (en) 2015-11-05 2020-06-18 Airbus Defence and Space GmbH Microelectronic module for cleaning a surface, modular array and method for cleaning a surface
US10925543B2 (en) 2015-11-11 2021-02-23 The Board Of Trustees Of The University Of Illinois Bioresorbable silicon electronics for transient implants
WO2017085849A1 (en) * 2015-11-19 2017-05-26 三井金属鉱業株式会社 Production method for printed wiring board having dielectric layer
CN105405983B (en) * 2015-12-14 2017-05-10 吉林大学 Stretching organic electroluminescence device with periodically regular crease structure
CN106920800B (en) * 2015-12-25 2019-07-23 昆山工研院新型平板显示技术中心有限公司 Flexible display device and forming method thereof
EP3420732B8 (en) 2016-02-22 2020-12-30 Medidata Solutions, Inc. System, devices, and method for on-body data and power transmission
CN108781313B (en) 2016-02-22 2022-04-08 美谛达解决方案公司 System, apparatus and method for a coupled hub and sensor node to obtain sensor information on-body
KR102455039B1 (en) * 2016-03-18 2022-10-17 삼성디스플레이 주식회사 Stretchable display device
US11154235B2 (en) 2016-04-19 2021-10-26 Medidata Solutions, Inc. Method and system for measuring perspiration
ITUA20162943A1 (en) * 2016-04-27 2017-10-27 Pilegrowth Tech S R L Method for the industrial manufacture of a semiconductor structure with reduced bowing.
US10209602B2 (en) * 2016-05-31 2019-02-19 E Ink Corporation Stretchable electro-optic displays
US10002222B2 (en) * 2016-07-14 2018-06-19 Arm Limited System and method for perforating redundant metal in self-aligned multiple patterning
US10447347B2 (en) 2016-08-12 2019-10-15 Mc10, Inc. Wireless charger and high speed data off-loader
CN106229038B (en) * 2016-09-07 2017-10-24 东华大学 A kind of stretchable electrically conducting transparent method for producing elastomers based on multilevel hierarchy graphene
JP2018060932A (en) * 2016-10-06 2018-04-12 ローム株式会社 LED package
CA3040514A1 (en) 2016-10-20 2018-04-26 Quantum Diamond Technologies Inc. Methods and apparatus for magnetic particle analysis using wide-field diamond magnetic imaging
JP2018078272A (en) * 2016-10-31 2018-05-17 スリーエム イノベイティブ プロパティズ カンパニー Three-dimensionally shaped thermally conductive molded body, and manufacturing method thereof
CN106601933B (en) * 2016-12-12 2018-02-23 吉林大学 Preparation method of stretchable electronic device with regular fold structure
CA3046849A1 (en) 2016-12-23 2018-06-28 Quantum Diamond Technologies Inc. Methods and apparatus for magnetic multi-bead assays
DE102017100053A1 (en) 2017-01-03 2018-07-05 Infineon Technologies Ag Frame assembly after film expansion
US11127778B2 (en) 2017-02-24 2021-09-21 Flexucell Aps Light emitting transducer
JP2018179501A (en) * 2017-04-03 2018-11-15 日本精工株式会社 Proximity sensor
WO2018191495A1 (en) * 2017-04-12 2018-10-18 Sense Photonics, Inc. Beam shaping for ultra-small vertical cavity surface emitting laser (vcsel) arrays
US20180323239A1 (en) * 2017-05-03 2018-11-08 Innolux Corporation Display device
CN107248518B (en) * 2017-05-26 2020-04-17 京东方科技集团股份有限公司 Photoelectric sensor, manufacturing method thereof and display device
CN110753976B (en) * 2017-06-12 2021-06-08 3M创新有限公司 Stretchable conductor
WO2019012345A1 (en) * 2017-07-14 2019-01-17 King Abdullah University Of Science And Technology Flexible and stretchable imager, method of making a flexible and stretchable imager, and method of using an imaging device having a flexible and stretchable imager
WO2019027917A1 (en) 2017-07-31 2019-02-07 Quantum Diamond Technologies, Inc Methods and apparatus for sample measurement
CN107634054A (en) * 2017-09-18 2018-01-26 天津大学 Silicon nanometer film revolution word logic inverter and preparation method thereof in flexible substrate
US10205303B1 (en) * 2017-10-18 2019-02-12 Lumentum Operations Llc Vertical-cavity surface-emitting laser thin wafer bowing control
TWI788433B (en) * 2017-11-07 2023-01-01 日商大日本印刷股份有限公司 Stretchable circuit substrate and product
CN108009317A (en) * 2017-11-09 2018-05-08 武汉大学 A kind of conductivity studies emulation of composite material and modeling method
EP3709943A1 (en) * 2017-11-15 2020-09-23 Smith & Nephew PLC Integrated sensor enabled wound monitoring and/or therapy dressings and systems
CN109859623B (en) * 2017-11-30 2021-05-18 云谷（固安）科技有限公司 Array substrate, preparation method thereof and display screen
KR101974575B1 (en) * 2017-12-01 2019-05-02 포항공과대학교 산학협력단 Manufacturing method for microscopic multi-slope sturcutre using synchrotron x-ray
CN108417592A (en) * 2018-02-12 2018-08-17 中国科学院半导体研究所 Infrared imaging device and preparation method thereof, bionical infrared spherical surface camera
KR102077306B1 (en) * 2018-02-14 2020-02-13 광운대학교 산학협력단 Real-time Glucose Monitoring Sensor System and Method of Manufacturing Glucose Sensor Based on Low Temperature Solution Process
CN109346504B (en) * 2018-09-30 2021-06-29 云谷（固安）科技有限公司 Flexible display panel and display device
CN109437091A (en) * 2018-10-23 2019-03-08 中山大学 A method of preparing micro-nano structure in elastic substrate
CN111148364B (en) * 2018-11-05 2021-01-26 北京梦之墨科技有限公司 Flexible stretchable circuit and manufacturing method thereof
EP3684640B1 (en) * 2018-12-10 2021-09-29 Corning Incorporated Dynamically bendable automotive interior display systems
CN109671869B (en) * 2018-12-12 2020-06-16 武汉华星光电半导体显示技术有限公司 Manufacturing method of composite film layer and display device
CN109637366B (en) * 2018-12-28 2020-10-09 厦门天马微电子有限公司 Jig and bending method of display module
CN111724676B (en) * 2019-03-21 2022-09-02 昆山工研院新型平板显示技术中心有限公司 Stretchable wire, manufacturing method thereof and display device
CN110393507B (en) * 2019-08-01 2020-12-25 清华大学 Structural design of flexible extensible electronic device and manufacturing method thereof
CN110797148B (en) * 2019-10-08 2021-07-30 上海交通大学 Superconducting tape suitable for uninsulated coil, uninsulated coil and preparation method thereof
CN110683508B (en) * 2019-10-18 2023-05-23 北京元芯碳基集成电路研究院 Preparation method of carbon nano tube parallel array
CN110808295B (en) * 2019-11-11 2021-04-23 重庆中易智芯科技有限责任公司 Semiconductor detector of three-dimensional electrostriction collecting electrode and preparation method thereof
CN110697646A (en) * 2019-11-22 2020-01-17 上海幂方电子科技有限公司 Electronic skin and preparation method thereof
US11062936B1 (en) 2019-12-19 2021-07-13 X Display Company Technology Limited Transfer stamps with multiple separate pedestals
CN111063658B (en) * 2019-12-30 2020-09-29 清华大学 Method for producing flexible and extensible electronic device
US20230119125A1 (en) * 2020-02-12 2023-04-20 Rayleigh Solar Tech Inc. High performance perovskite solar cells, module design, and manufacturing processes therefor
GB2593864B (en) * 2020-02-28 2023-01-04 X Fab France Sas Improved transfer printing for RF applications
CN112967971B (en) * 2020-05-27 2023-04-18 重庆康佳光电技术研究院有限公司 Micro-LED transfer substrate and preparation method thereof
KR102393781B1 (en) * 2020-07-07 2022-05-04 서울대학교산학협력단 Flexible device
CN112133198B (en) * 2020-09-29 2022-04-22 厦门天马微电子有限公司 Stretchable display panel and stretchable display device
CN112606585B (en) * 2020-12-02 2022-05-31 潍坊歌尔微电子有限公司 Device transfer printing processing method and micro microphone dustproof device transfer printing processing method
KR102591096B1 (en) * 2020-12-15 2023-10-18 연세대학교 산학협력단 method of manufacturing photodetector by applying tensile strain, photodetector manufactured by the method, and apparatus for manufacturing the photodetector
KR102553142B1 (en) * 2021-06-25 2023-07-06 경희대학교 산학협력단 Pressure sensor using conductive polymer material including structure to improve sensitivity
KR102582188B1 (en) * 2021-07-22 2023-09-26 한국과학기술원 Stretchable oleds using laser patterned plastic substrate and method for manufacturing the same
CN113542755B (en) * 2021-07-27 2022-06-21 展讯通信（上海）有限公司 Method and system for generating two-dimensional wedge-shaped mask
WO2023023976A1 (en) * 2021-08-25 2023-03-02 京东方科技集团股份有限公司 Radio frequency microelectronic mechanical switch and radio frequency device
CN114286513B (en) * 2021-11-30 2024-02-06 通元科技(惠州)有限公司 Asymmetric prestress eliminating type LED backboard and manufacturing method thereof
CN114355489B (en) * 2022-01-13 2023-05-16 西华大学 Curved fly-eye lens based on DMD digital lithography and preparation method thereof
KR20230112256A (en) 2022-01-20 2023-07-27 공주대학교 산학협력단 Wave-shaped steretchable wiring and its manufacturing method
WO2023137539A1 (en) * 2022-01-21 2023-07-27 Decorby Raymond Monolithic optical pressure sensors and transducers
WO2023187834A1 (en) * 2022-03-30 2023-10-05 Council Of Scientific And Industrial Research Method for fabricating silicon chip carriers using wet bulk micromachining for ir detector applications

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5763864A (en) * 1980-09-29 1982-04-17 Messerschmitt Boelkow Blohm Solar battery mechanism
US4766670A (en) * 1987-02-02 1988-08-30 International Business Machines Corporation Full panel electronic packaging structure and method of making same
US5086785A (en) * 1989-08-10 1992-02-11 Abrams/Gentille Entertainment Inc. Angular displacement sensors
US5475514A (en) * 1990-12-31 1995-12-12 Kopin Corporation Transferred single crystal arrayed devices including a light shield for projection displays
US5375397B1 (en) * 1993-06-22 1998-11-10 Robert J Ferrand Curve-conforming sensor array pad and method of measuring saddle pressures on a horse
JPH08298334A (en) * 1995-04-26 1996-11-12 Mitsubishi Electric Corp Solar cell board
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
DE19637626A1 (en) * 1996-09-16 1998-03-26 Bosch Gmbh Robert Flexible interconnect connection
FR2786037B1 (en) * 1998-11-16 2001-01-26 Alstom Technology SHIELDED ELECTRICAL CONDUCTION BAR FOR HIGH VOLTAGE ELECTRICAL STATION
US6150602A (en) * 1999-05-25 2000-11-21 Hughes Electronics Corporation Large area solar cell extended life interconnect
AU7137800A (en) * 1999-07-21 2001-02-13 E-Ink Corporation Preferred methods for producing electrical circuit elements used to control an electronic display
JP2001352089A (en) * 2000-06-08 2001-12-21 Showa Shell Sekiyu Kk Thermal expansion strain preventing solar cell module
US6743982B2 (en) * 2000-11-29 2004-06-01 Xerox Corporation Stretchable interconnects using stress gradient films
GB0029312D0 (en) * 2000-12-01 2001-01-17 Philips Corp Intellectual Pty Flexible electronic device
WO2002071137A1 (en) * 2001-03-06 2002-09-12 Koninklijke Philips Electronics N.V. Display device
US7273987B2 (en) * 2002-03-21 2007-09-25 General Electric Company Flexible interconnect structures for electrical devices and light sources incorporating the same
JP3980918B2 (en) * 2002-03-28 2007-09-26 株式会社東芝 Active matrix substrate, method for manufacturing the same, and display device
JP2003323741A (en) 2002-04-30 2003-11-14 National Institute Of Advanced Industrial & Technology Optical memory
US7491892B2 (en) * 2003-03-28 2009-02-17 Princeton University Stretchable and elastic interconnects
US7465678B2 (en) * 2003-03-28 2008-12-16 The Trustees Of Princeton University Deformable organic devices
US20050227389A1 (en) * 2004-04-13 2005-10-13 Rabin Bhattacharya Deformable organic devices
GB0323285D0 (en) * 2003-10-04 2003-11-05 Koninkl Philips Electronics Nv Device and method of making a device having a patterned layer on a flexible substrate
WO2005098969A1 (en) * 2004-04-08 2005-10-20 Sharp Kabushiki Kaisha Solar battery and solar battery module
CN103646848B (en) * 2004-06-04 2018-06-05 伊利诺伊大学评议会 The method of assembling printable semiconductor elements and manufacture electronic device
US7521292B2 (en) * 2004-06-04 2009-04-21 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US7629691B2 (en) * 2004-06-16 2009-12-08 Honeywell International Inc. Conductor geometry for electronic circuits fabricated on flexible substrates
FR2875339B1 (en) * 2004-09-16 2006-12-08 St Microelectronics Sa MOS TRANSISTOR WITH DEFORMABLE GRID
US20060132025A1 (en) * 2004-12-22 2006-06-22 Eastman Kodak Company Flexible display designed for minimal mechanical strain
US20060160943A1 (en) * 2005-01-18 2006-07-20 Weir James P Water-based flock adhesives for thermoplastic substrates
CN2779218Y (en) * 2005-02-01 2006-05-10 广德利德照明有限公司 Connecting line of a tubular LED decorative lamp
TWI533459B (en) * 2005-06-02 2016-05-11 美國伊利諾大學理事會 Printable semiconductor structures and related methods of making and assembling
JP7099160B2 (en) 2018-08-10 2022-07-12 住友電気工業株式会社 Optical fiber manufacturing method
US11394720B2 (en) 2019-12-30 2022-07-19 Itron, Inc. Time synchronization using trust aggregation

Also Published As

Publication number Publication date
KR20150003308A (en) 2015-01-08
KR20180002083A (en) 2018-01-05
TW201434163A (en) 2014-09-01
KR20160140962A (en) 2016-12-07
KR20140043244A (en) 2014-04-08
KR20090086199A (en) 2009-08-11
MY172115A (en) 2019-11-14
JP2010503238A (en) 2010-01-28
JP5578509B2 (en) 2014-08-27
JP2015216365A (en) 2015-12-03
EP2064710A4 (en) 2011-05-04
EP2064710A2 (en) 2009-06-03
TW200836353A (en) 2008-09-01
WO2008030960A3 (en) 2008-07-24
KR101689747B1 (en) 2016-12-27
JP5735585B2 (en) 2015-06-17
MY149475A (en) 2013-08-30
CN101681695A (en) 2010-03-24
CN103213935A (en) 2013-07-24
KR101814683B1 (en) 2018-01-05
TWI587527B (en) 2017-06-11
KR102087337B1 (en) 2020-03-11
KR101453419B1 (en) 2014-10-23
CN101681695B (en) 2013-04-10
CN103213935B (en) 2017-03-01
TW201735380A (en) 2017-10-01
KR101612749B1 (en) 2016-04-27
JP2013239716A (en) 2013-11-28
TWI485863B (en) 2015-05-21
WO2008030960A2 (en) 2008-03-13

Similar Documents

Publication Publication Date Title
TWI654770B (en) Two-dimensional extendable and flexible device and method of manufacturing same
US10355113B2 (en) Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics
US11456258B2 (en) Stretchable form of single crystal silicon for high performance electronics on rubber substrates
TWI336491B (en) A stretchable form of single crystal silicon for high performance electronics on rubber substrates
Baca et al. Semiconductor wires and ribbons for high‐performance flexible electronics