TWI578460B - 半導體封裝組件及其形成方法 - Google Patents

半導體封裝組件及其形成方法 Download PDF

Info

Publication number
TWI578460B
TWI578460B TW105114086A TW105114086A TWI578460B TW I578460 B TWI578460 B TW I578460B TW 105114086 A TW105114086 A TW 105114086A TW 105114086 A TW105114086 A TW 105114086A TW I578460 B TWI578460 B TW I578460B
Authority
TW
Taiwan
Prior art keywords
semiconductor package
semiconductor
package
forming
die
Prior art date
Application number
TW105114086A
Other languages
English (en)
Other versions
TW201642406A (zh
Inventor
林子閎
蕭景文
彭逸軒
Original Assignee
聯發科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯發科技股份有限公司 filed Critical 聯發科技股份有限公司
Publication of TW201642406A publication Critical patent/TW201642406A/zh
Application granted granted Critical
Publication of TWI578460B publication Critical patent/TWI578460B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02317—Manufacturing methods of the redistribution layers by local deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02319—Manufacturing methods of the redistribution layers by using a preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08147—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area disposed in a recess of the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80801—Soldering or alloying
    • H01L2224/8082—Diffusion bonding
    • H01L2224/8083—Solid-solid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1205—Capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1206—Inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1207—Resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19011—Structure including integrated passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

半導體封裝組件及其形成方法
本發明涉及半導體封裝組件，特別涉及一種三維(3D)半導體封裝組件及其形成方法。
由於對電子產品之微型化及多功能性的需求，使得半導體工業經歷了持續快速的增長。整合密度已經提高，從而允許更多的晶片(chip)或晶粒(die)整合於半導體封裝中，例如2維(2D)半導體封裝。但是，2D半導體封裝存在物理限制。例如，當將2顆以上的具有不同功能的晶粒放置於2D半導體設備中時，對需要的更複雜的設計和佈局的開發變得更加困難。
儘管3D積體電路及堆疊的晶粒已開發並且被普遍使用，但是整合於傳統3D半導體封裝中的複數晶粒限制於具有相同的尺寸。另外，3D半導體封裝技術遭受各種可能導致製造良率下降的問題。
因此，需要開發一種半導體封裝組件及其形成方法，能夠緩解或消除上述的問題。
有鑒於此，本發明提供一種半導體封裝組件及其形成方法，可以提高設計靈活性。
根據本發明至少一個實施例，提供了一種半導體封裝組件，包括：一第一封裝，包括：一第一元件；以及一第一重分佈層結構，耦接至該第一元件并且包括：一第一導電線路；以及一第二封裝，接合至該第一封裝，其中，該第二封裝包括：一第二元件；以及一第二重分佈層結構，耦接至該第二元件以及包括：第二導電線路，其中該第一導電線路直接接觸該第二導電線路。
根據本發明至少一個實施例，提供了一種形成半導體封裝組件的方法，包括：形成一第一半導體封裝，其中該第一半導體封裝包括：一第一半導體晶粒；以及一第一重分佈層結構，耦接至該第一半導體晶粒并且包括：一第一導電線路；形成一第二半導體封裝，其中該第二半導體封裝包括：一第二半導體晶粒，其中該第二半導體晶粒的主動面朝向該第一半導體晶粒的主動面；以及一第二重分佈層結構，耦接至該第二半導體晶粒以及包括：一第二導電線路；以及將該第二半導體封裝接合至該第一半導體封裝，其中，該第一導電線路直接接觸該第二導電線路。
根據本發明至少一個實施例，提供了一種形成半導體封裝組件的方法，包括：形成一第一半導體封裝，其中該第一半導體封裝包括：一第一半導體晶粒；以及一第一重分佈層結構，耦接至該第一半導體晶粒并且包括：一第一導電線路；形成一第二封裝，其中該第二封裝包括：一被動設備；以及一第二重分佈層結構，耦接至該被動設備以及包括：一第二導電線路；以及將該第二封裝接合至該第一半導體封裝，其 中，該第一導電線路直接接觸該第二導電線路。
以上的半導體封裝組件及其形成方法，通過將兩個封裝(如半導體封裝)接合起來，並使兩個封裝的導電線路直接接觸，從而形成半導體封裝組件，因此該兩個封裝可以分別製造，從而提高了設計靈活性。
100A‧‧‧第一載體基底
110A‧‧‧第一元件(或第一半導體晶粒)
120A‧‧‧第一成型模料
130A‧‧‧第一RDL結構
A‧‧‧第一(半導體)封裝
140A、140B、220‧‧‧導電線路
150A、150B、230‧‧‧IMD層
100B‧‧‧第二載體基底
160‧‧‧通孔結構
110B‧‧‧第二元件(或第二半導體晶粒)
120B‧‧‧第二成型模料
130B‧‧‧第二RDL結構
B‧‧‧第二(半導體)封裝
190‧‧‧導電元件
200‧‧‧RDL結構
210‧‧‧導電結構
L‧‧‧切割道
300、400、500‧‧‧半導體封裝組件
通過閱讀接下來的詳細描述以及參考所附的圖式所做的示例，可以更全面地理解本發明，其中： 第1A~1C圖為根據本發明一些實施例的各個階段的形成半導體封裝的方法的剖面示意圖。
第2A~2C圖為根據本發明一些實施例的各個階段的形成半導體封裝的方法的剖面示意圖。
第3A~3E圖為根據本發明一些實施例的各個階段的形成半導體封裝組件的方法的剖面示意圖。
第4圖為根據本發明一些實施例的半導體封裝組件的剖面示意圖。
第5圖為根據本發明一些實施例的半導體封裝組件的剖面示意圖。
以下描述為實現本發明的一种可预期的模式。該描述用於說明本發明的一般原理的目的，並且不應當理解為具有限制性意義。通過參考所附的申請專利範圍可確定本發明的範圍。
本發明將參考特定實施例及參考確定的圖式來描述，但是本發明不限制於此，並且本發明僅由申請專利範圍來限制。描述的圖式僅是原理圖並且不作為限制。在圖式中，出於說明目的而夸大了某些元件的尺寸，並且該些元件的尺寸並非按比例繪製。尺寸和相對尺寸不對應本發明實踐中的真實尺寸。
本發明的實施例提供了一種3D系統封裝(System-In-Package，SIP)半導體封裝組件。該半導體封裝組件整合了2個以上的元件或晶粒，從而可以降低使用該半導體封裝組件的電子產品的尺寸。分別製造該些元件或晶粒，接著將該些元件或晶粒整合於半導體封裝組件中。如此，該些元件或晶粒不限制於具有相同的尺寸及/或功能。顯著地改善了半導體封裝組件的設計靈活性。另外，提前測量該些元件或晶粒，以確保半導體封裝組件僅包含合格元件或合格晶粒。如此，可以顯著地減輕或消除由於複數個缺陷元件或缺陷晶粒所導致的良率損失。因此，降低了半導體封裝組件的製造成本。
第1A~1C圖為本發明一些實施例的各個階段的形成半導體封裝的方法的剖面示意圖。在第1A~1C圖中描述的各個階段之前、期間和/或之後，可以提供附加的操作。對於不同實施例，可以替換或者省略上述各個階段中的一部分。附加的特徵可以添加至半導體封裝中。對於不同實施例，可以替換或者省略以下描述的特征中的一部分。
如第1A圖所示，提供了一第一載體基底100A。在一些實施例中，該第一載體基底100A可以是晶圓或者面板 (panel)。第一載體基底100A可以包括：玻璃或者其他合適的支撐材料。
如第1A圖所示，複數個第一元件110A接合在該第一載體基底100A之上。根據本發明一些實施例，該等第一元件110A均為已知合格(known-good)元件。換句話說，無缺陷元件接合(bond)在該第一載體基底100A之上。在一些實施例中，該等第一元件110A和該第一載體基底100A可以通過諸如膠水或其他合適的膠黏材料等的膠黏層膠黏在一起。
在一些實施例中，第一元件110A可以為主動設備並且可被稱為第一半導體晶粒(或晶片)110A。第一半導體晶粒110A可以包括：電晶體或者其他合適的主動元件。例如，第一半導體晶粒110A可以為邏輯晶粒，該邏輯晶粒包括：CPU(Central Processing Unit，中央處理單元)、GPU(Graphics Processing Unit，圖形處理單元)、DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)控制器或他們的任意組合。在其他一些實施例中，第一元件110A可以為諸如IPD(Integrated Passive Devices，整合被動設備)等的被動設備。第一元件110A可以包括：電容、電阻、電感、變容二極體或者其他合適的被動元件。
如第1B圖所示，在第一載體基底100A之上形成一第一成型模料(molding compound)120A。該第一成型模料120A圍繞第一元件110A的側壁，並且沒有覆蓋第一元件110A的頂面和底面。
在一些實施例中，第一成型模料120A由諸如環氧 樹脂、樹脂、可塑聚合物或者其他合適的模塑材料等非導電材料形成。在一些實施例中，第一成型模料120A在大致上為液體時應用，然後通過化學反應固化。在其他一些實施例中，第一成型模料是UV(紫外)或熱固化聚合物，並且作為膠體或可塑固體而應用，然後通過UV或熱固化製程進行固化。第一成型模料120A可以按照模型來固化。
在一些實施例中，沉積的第一成型模料120A覆蓋第一元件110A的頂面，接著執行研磨(grinding)製程以使該沉積的第一成型模料120A變薄。如此，變薄的第一成型模料120A露出第一元件110A的頂面。在一些實施例中，第一成型模料120A的頂面和底面分別與第一元件110A的頂面和底面共平面。
如第1C圖所示，在第一成型模料120A上形成一第一RDL(Redistribution Layer，重分佈層)結構130A，並且該第一RDL結構130A耦接至該第一元件110A，該第一RDL結構130A也稱為扇出(fan-out)結構。如此，形成一第一(半導體)封裝A。在一些實施例中，該第一(半導體)封裝A為晶圓級扇出封裝。
該第一RDL結構130A覆蓋第一成型模料120A並且直接接觸該第一成型模料120A。在一些實施例中，該第一RDL結構130A包括：一個或更多的導電線路140A，設置在一IMD(Inter-Metal Dielectric，金屬間介電)層150A內並由該IMD層150A圍繞。第一元件110A電性連接至第一RDL結構130A中的導電線路140A。IMD層150A可以包括：複數個次 介電層，依次地堆疊在第一成型模料120A及第一元件110A之上。例如，第一層位的導電線路140A設置在第一層位的次介電層上，並且由第二層位的次介電層覆蓋。第二層位的導電線路140A設置在第二層位的次介電層之上，並且由第三層位的次介電層覆蓋。
在一些實施例中，IMD層150A可以由有機材料或非有機材料形成，其中該有機材料包括：聚合物基(polymer base)材料，該非有機材料包括：氮化矽(SiNx)、氧化矽(SiOx)、石墨烯，等等。在一些實施例中，IMD層150A為高k值介電層(k為介電層的介電常數)。在其他一些實施例中，IMD層150A可以由光敏性材料形成，包括：乾膜光阻。
導電線路140A的接墊部分從第一RDL結構130A的頂面露出。例如，導電線路140A的接墊部分從IMD層150A的開口露出，並連接至接下來形成的導電元件。需要注意的是，圖式中所示的導電線路140A和IMD層150A的數量和組態僅是示例而不是對本發明的限制。在一些實施例中，導電線路140A包括：銅或者其他合適的具有良好擴散性的導電材料。
第2A~2C圖為根據本發明一些實施例的各個階段的形成半導體封裝的方法的剖面示意圖。在第2A~2C圖中描述的各個階段之前、期間和/或之後，可以提供附加的操作。針對不同實施例，可以替換或者省略描述的各個階段中的一部分。附加的特徵可以添加至半導體封裝中。對於不同實施例，可以替換或者省略以下描述的特徵中的一部分。
如第2A圖所示，提供了一第二載體基底100B。 在一些實施例中，該第二載體基底100B可以為晶圓或者面板。第二載體基底100B可以包括：玻璃或者其他合適的支撐材料。
如第2A圖所示，複數個通孔結構(vias)160形成在第二載體基底100B之上。該等通孔結構160可以是TIV(Through Interposer Vias，中介層通孔結構)。在一些實施例中，該等通孔結構160可以是銅柱或者其他合適的導電結構。在一些實施例中，通過電鍍製程或者其他合適的製程形成通孔結構160。
如第2A圖所示，複數個第二元件110B接合在第二載體基底100B之上。根據本發明一些實施例，第二元件110B為已知合格元件。換句話說，無缺陷元件接合在第二載體基底100B之上。在一些實施例中，第二元件110B及第二載體基底100B通過膠黏層(諸如膠水或者其他合適的膠黏材料)而膠黏在一起。在一些實施例中，每個第二元件110B設置在兩個通孔結構160之間。在一些實施例中，在兩個第二元件110B之間設置一個或更多的通孔結構160。
在一些實施例中，第二元件110B可以為主動設備並且可以被稱為第二半導體晶粒(或晶片)110B。第二半導體晶粒110B可以包括：電晶體或者其他合適的主動元件。例如，第二半導體晶粒110B可以是邏輯晶粒，該邏輯晶粒包括：CPU、GPU、DRAM控制器或者他們的任意組合。在其他一些實施例中，第二元件110B可以為被動設備，諸如IPD。第二元件110B可以包括：電容、電阻、電感、變容二極體和其他 合適的被動元件。
如第2B圖所示，在第二載體基底100B之上形成一第二成型模料120B。第二成型模料120B圍繞通孔結構160以及第二元件110B的側壁，並且沒有覆蓋第二元件110B的頂面和底面及通孔結構160的頂面和底面。也就是，通孔結構160穿透或者穿過第二成型模料120B。
在一些實施例中，第二成型模料120B由非導電材料形成，諸如環氧樹脂、樹脂、可塑聚合物或者其他合適的成型模料。在一些實施例中，第二成型模料120B在大致上為液體時應用，接著通過化學反應固化。在其他一些實施例中，第二成型模料120B為UV或熱固化聚合物，並且作為膠體或可塑固體而應用，然後通過UV或熱固化製程進行固化。第二成型模料120B可以按照模型固化。
在一些實施例中，沉積的第二成型模料120B覆蓋第二元件110B的頂面及通孔結構160的頂面，接著執行研磨製程薄化第二成型模料120B。如此，薄化後的第二成型模料120B露出第二元件110B的頂面及通孔結構160的頂面。在一些實施例中，第二成型模料120B的頂面和底面分別與第二元件110B的頂面和底面共平面。在一些實施例中，第二成型模料120B的頂面和底面分別與通孔結構160的頂面和底面共平面。
根據本發明一些實施例，在將第二元件110B接合至第二載體基底100B之前，預先薄化第二元件110B。如此，第二元件110B和通孔結構160大致上具有相同的厚度，從而 有利於第二元件110B和通孔結構160的露出。例如，薄化半導體晶圓並且接著將其切割成半導體晶粒(或晶片)，從而形成第二元件110B。第二元件110B可以通過機械研磨製程、化學機械磨光(polishing)製程、銑削(milling)製程或者其他合適製程而薄化。
如第2C圖所示，在第二成型模料120B上形成第二RDL結構130B，該第二RDL結構130B耦接至該第二元件110B和通孔結構160。如此，形成第二(半導體)封裝B。在一些實施例中，第二(半導體)封裝B為晶圓級扇出封裝。第二RDL結構130B覆蓋第二成型模料120B並且可以直接接觸第二成型模料120B。在一些實施例中，第二RDL結構130B包括：一個或更多的導電線路140B，設置在IMD層150B內並由IMD層150B圍繞。第二元件110B電性連接至第二RDL結構130B的導電線路140B。導電線路140B的接墊部分從第二RDL結構130B的頂面露出。第二RDL結構130B的結構類似或相同於第一RDL結構130A的結構，細節如前所述。需要注意的是，圖式中所示的導電線路140B和IMD層150B的數量和組態僅為示例而不是對本發明的限制。在一些實施例中，導電線路140B包括：銅或者其他合適的具有良好擴散性的導電材料。
第3A~3E圖為根據本發明一些實施例的各個階段的形成半導體封裝組件的方法的剖面示意圖。在第3A~3C圖中描述的各個階段之前、期間和/或之後，可以提供附加的操作。針對不同實施例，可以替換或者省略描述的各個階段中的 一部分。附加的特徵可以添加至半導體封裝組件中。對於不同實施例，可以替換或者省略以下描述的特徵中的一部分。
如第3A圖所示，第二封裝B接合至第一封裝A，使得第一RDL結構130A夾在第一元件110A和第二RDL結構130B之間。第一RDL結構130A的導電線路140A直接電性連接至第二RDL結構130B的導電線路140B。例如，導電線路140A和140B的接墊部分彼此直接接觸。第一RDL結構130A的IMD層150A和第二RDL結構130B的IMD層150B也彼此直接接觸。在一些實施例中，第一元件110A的主動面朝向第二元件110B的主動面。
根據本發明一些實施例，第一封裝A和第二封裝B使用熔融接合(fusion bonding)方式接合在一起。在一些實施例中，第一封裝A和第二封裝B使用銅熔融接合方式接合在一起。例如，導電線路140A和140B均包括銅，以便於第一封裝A和第二封裝B通過銅接合處接合在一起。第一封裝A和第二封裝B之間的接合處不包括焊錫。
第二封裝B放置在第一封裝A之上。導電線路140A直接貼近導電線路140B。在一些實施例中，導電線路140A大致對齊導電線路140B。在一些實施例中，導電線路140A與導電線路140B具有相同的佈局。導電線路140A與導電線路140B大致上完全重疊。在其他一些實施例中，導電線路140A與導電線路140B具有不同的佈局。導電線路140A與導電線路140B至少部分重疊，以便於建立第一封裝A和第二封裝B之間的電連接路徑。
然後，對第一封裝A和第二封裝B執行熱處理。如此，導電線路140A和導電線路140B中的熔化的金屬(銅)使得第二封裝B與第一封裝A連接。導電線路140A直接連接至導電線路140B，而無需接合結構(如導電柱、導電凸塊或者導電膏結構)。在一些實施例中，在150℃~250℃的溫度範圍內執行熱處理，但是本發明不限制於此。
在一些實施例中，在熱處理期間，將超聲能量應用至第一封裝A和第二封裝B。超聲能量有利於導電線路140A和導電線路140B之間的金屬擴散。如此，加強了第一封裝A和第二封裝B之間的接合處，使得第一封裝A和第二封裝B緊緊地接合在一起。
在一些實施例中，在將第二封裝B放置在第一封裝A上之前，對第一封裝A和/或第二封裝B執行平面化(planarization)製程。該平面化製程用於降低表面粗糙度並且提供具有平坦接合面的第一封裝A和/或第二封裝B。例如，在將第二封裝B放置在第一封裝A上之前，第一RDL結構130A和/或第二RDL結構130B的表面已經預先平面化。如此，第二封裝B可以緊密地接合至第一封裝A。
如第3B圖所示，從第二封裝B移除第二載體基底100B。如此，露出第二元件110B和通孔結構160。第二元件110B的側壁及通孔結構160仍然由第二成型模料120B圍繞。在一些實施例中，移除膠黏層的膠黏性能，以使第二載體基底100B脫膠，該膠黏層用於接合第二元件110B和第二載體基底100B。
如第3C圖所示，一導電元件190形成在第二封裝B上並且遠離第一封裝A。換句話說，導電元件190和第一封裝A設置在第二封裝B的兩相對側上。第二元件110B設置在第二RDL結構130B和導電元件190之間。
在一些實施例中，導電元件190通過通孔結構160和第二RDL結構130B電性連接或耦接至第二元件110B。在一些實施例中，導電元件190進一步通過通孔結構160、第二RDL結構130B及第一RDL結構130A電性連接至第一元件110A。
在一些實施例中，導電元件190由一RDL結構200及該RDL結構200上面的一導電結構210構成。在一些實施例中，該RDL結構200包括：一個或更多的導電線路220，設置在IMD層230中並由IMD層230圍繞。導電線路220的接墊部分從RDL結構200的頂面露出。RDL結構200的結構類似或者相同於RDL結構130A的結構，詳細如前所述。
導電結構210電性連接至導電線路220中露出的接墊部分。通孔結構160通過導電線路220電性連接或耦接至導電結構210。在一些實施例中，導電結構210為接合球(如焊錫球)，或者其他合適的導電結構。需要注意，圖式中所示的導電結構210和導電線路220的數量和組態僅是示例而不是對本發明的限制。
在其他一些實施例中，導電元件190由導電結構210構成。通孔結構160直接電性連接至導電結構210。通孔結構160可以通過一個或更多的導電層(諸如UBM(Under Bump Metallization，凸塊下金屬)層)電性連接至導電結構210。
如第3D圖所示，從第一封裝A移除第一載體基底100A。如此，露出第一元件110A。第一元件110A的側壁仍由第一成型模料120A圍繞。在一些實施例中，移除膠黏層的膠黏性能，以使第一載體基底100A脫膠，該膠黏層用於接合第一元件110A和第一載體基底100A。
然後，對已接合的封裝A和B執行切割(singulation)製程。沿切割道L切割已接合的封裝A和B，以將已接合的封裝A和B分為複數個半導體封裝組件300。該等半導體封裝組件300均為SIP半導體封裝組件，並且晶圓級扇出封裝集成於該等半導體封裝組件300中。
如第3E圖所示，每個半導體封裝組件300包括：一個第一元件110A和兩個第二元件110B。半導體封裝元件300可以包括：2個以上的第二元件110B。在一些實施例中，第一元件110A的尺寸不同於第二元件110B的尺寸。例如，第一元件110A的尺寸大於第二元件110B的尺寸。在一些實施例中，複數個第二元件110B具有相同的尺寸。在其他一些實施例中，該等第二元件110B具有不同的尺寸。
在一些實施例中，第一元件110A和第二元件110B具有相同的功能。因此，半導體封裝組件300為同質整合(homogeneous integration)。在其他一些實施例中，第一元件110A的功能不同於一個或複數個第二元件110B的功能。因此，半導體封裝組件300為異質整合(heterogeneous integration)。
在一些實施例中，第一元件110A和第二元件110B之一為SOC(system-on-chip，系統單晶片)，另一為被動設備。在一些實施例中，第一元件110A和第二元件110B之一為AP(Analog Processor，類比處理器)，另一為DP(Digital Processor，數位處理器)。在一些實施例中，第一元件110A和第二元件110B之一為BB(baseband，基帶)元件，另一為RF(Radio-Frequency，射頻)元件。
例如，在一些實施例中，第一元件110A為主動設備，同時該等第二元件110B為彼此具有相同或不同功能的被動設備。在一些實施例中，第二元件110B之一和第一元件110A為具有相同或不同功能的主動設備，同時另一第二元件110為被動設備。在其他一些實施例中，第一元件110A和第二元件110B為具有不同功能的主動設備。
可選地，在一些實施例中，第一元件110A為被動設備，同時該等第二元件110B為彼此具有相同或不同功能的主動設備。在一些實施例中，第二元件110B之一和第一元件110A為具有相同或不同功能的被動設備，同時另一第二元件110為主動設備。
可以對本發明實施例做出許多變形和/或修改。第4圖和第5圖均為根據本發明一些實施例的半導體封裝組件的剖面示意圖。第4圖和第5圖中相同於第3E圖的元件，採用與第3E圖相同的參考符號來標記，並且出於簡潔而不再描述。
參考第4圖，示出了一種半導體封裝組件400。該 半導體封裝組件400相似於第3E圖中所示的半導體封裝組件300。半導體封裝組件300和400之間的主要不同在於：半導體封裝組件300包括：一個第一元件110A，而半導體封裝組件400包括：兩個第一元件110A。半導體封裝組件400可以包括：超出兩個的第一元件110A。
在一些實施例中，複數個第一元件110A之間具有相同的尺寸。在其他一些實施例中，該等第一元件110A之間具有不同的尺寸。在一些實施例中，第一元件110A的尺寸不同於第二元件110B的尺寸。例如，第一元件110A的尺寸大於第二元件110B的尺寸。在一些實施例中，該等第一元件110A之間具有相同的功能。在其他一些實施例中，該等第一元件110A之間具有不同的功能。
參考第5圖，示出了一種半導體封裝組件500。該半導體封裝組件500類似於第3E圖所示的半導體封裝組件300。半導體封裝組件300和500之間的主要不同在於：半導體封裝組件300的通孔結構160形成於第二封裝B之中，而半導體封裝組件500的通孔結構160形成於第一封裝A之中。如此，半導體封裝組件300的導電元件形成在第二封裝B之上，而半導體封裝組件500的導電元件190形成在第一封裝A之上。
在第5圖中，通孔結構160穿透第一成型模料120A並且電性連接或耦接至第一RDL結構130A。導電元件190和第二封裝B設置在第一封裝A的兩相對側上。第一元件110A設置在第一RDL結構130A和導電元件190之間。
根據本發明實施例的半導體封裝組件及其形成方法提供了各種優勢。根據前述實施例，兩個以上的元件或晶粒可以整合於半導體封裝組件之中。該些元件或晶粒於不同的製程中製造，並且為已知合格元件或晶粒。如此，該些元件或晶粒的尺寸和/或功能不受限制，從而有利於改善設計靈活性。半導體封裝組件的製造良率更進一步顯著地增強。
另外，根據前述實施例，使用熔融接合方式將兩個封裝接合在一起，以形成半導體封裝組件。沒有必要形成附加的接合結構(諸如導電柱、導電凸塊或者導電膏結構)或者附加的膠黏層。相應地，簡化了半導體封裝組件的工藝流程，並且降低了製造成本。
由於兩個封裝沒有通過任何中介層而直接接合，因此顯著地縮短了兩個封裝之間的信號傳送路徑/距離。另外，可以進一步增強EM(Electrical Migration，電遷移)能力。另外，降低了半導體封裝組件的厚度。因此，顯著地改善了半導體封裝組件的設備性能。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
110A‧‧‧第一元件(或第一半導體晶粒)
120A‧‧‧第一成型模料
130A‧‧‧第一RDL結構
A‧‧‧第一(半導體)封裝
140A、140B、220‧‧‧導電線路
150A、150B、230‧‧‧IMD層
160‧‧‧通孔結構
110B‧‧‧第二元件(或第二半導體晶粒)
120B‧‧‧第二成型模料
130B‧‧‧第二RDL結構
B‧‧‧第二(半導體)封裝
190‧‧‧導電元件
200‧‧‧RDL結構
210‧‧‧導電結構
300‧‧‧半導體封裝組件

Claims (24)

  1. 一種半導體封裝組件，包括一第一封裝以及一第二封裝，該第一封裝包括：一第一元件；以及一第一重分佈層結構，耦接至該第一元件并且包括：一第一導電線路；該第二封裝接合至該第一封裝，其中，該第二封裝包括：一第二元件；以及一第二重分佈層結構，耦接至該第二元件以及包括：一第二導電線路，其中該第一導電線路直接接觸該第二導電線路；其中，該第一重分佈層結構夾在該第一元件和該第二重分佈層結構之間。
  2. 如申請專利範圍第1項所述的半導體封裝組件，其中該第一封裝為第一半導體封裝，該第一元件為第一半導體晶粒；該第二封裝為第二半導體封裝，該第二元件為第二半導體晶粒並且該第二半導體晶粒的主動面朝向該第一半導體晶粒的主動面。
  3. 如申請專利範圍第1項所述的半導體封裝組件，其中該第一封裝為第一半導體封裝，該第一元件為第一半導體晶粒；該第二元件為被動設備。
  4. 如申請專利範圍第1項所述的半導體封裝組件，其中該第一封裝包括：多於一個的該第一元件，及/或者，該第二封裝包括：多於一個的該第二元件。
  5. 如申請專利範圍第1項所述的半導體封裝組件，其中該第一導電線路和該第二導電線路均包括銅。
  6. 如申請專利範圍第1項所述的半導體封裝組件，其中該第一重分佈層結構進一步包括：一第一介電層，圍繞該第一導電線路；以及第二重分佈層結構進一步包括：一第二介電層，圍繞該第二導電線路並且該第二介電層直接接觸該第一介電層。
  7. 如申請專利範圍第1項所述的半導體封裝組件，其中該第一封裝進一步包括：一第一成型模料，圍繞該第一元件的側壁。
  8. 如申請專利範圍第7項所述的半導體封裝組件，其中該第一重分佈層結構覆蓋該第一成型模料。
  9. 如申請專利範圍第7項所述的半導體封裝組件，其中該第一封裝進一步包括：一通孔結構，穿過該第一成型模料並耦接至該第一重分佈層結構。
  10. 如申請專利範圍第9項所述的半導體封裝組件，進一步包括：一導電元件，耦接至該通孔結構，其中該第一元件設置在該第一重分佈層結構和該導電元件之間。
  11. 如申請專利範圍第7項所述的半導體封裝組件，其中，該第二封裝進一步包括：一第二成型模料，圍繞該第二元件的側壁。
  12. 如申請專利範圍第11項所述的半導體封裝組件，其中，該第二重分佈層結構覆蓋該第二成型模料。
  13. 如申請專利範圍第1項所述的半導體封裝組件，其中該第 一元件和該第二元件之一為主動設備，另一為被動設備。
  14. 如申請專利範圍第1項所述的半導體封裝組件，其中該第一封裝包括：一個或多於一個的該第一元件，該第二封裝包括：一個或多於一個的該第二元件，並且至少一個該第一元件與至少一個該第二元件具有不同的尺寸。
  15. 一種形成半導體封裝組件的方法，包括：形成一第一半導體封裝，其中該第一半導體封裝包括：一第一半導體晶粒；以及一第一重分佈層結構，耦接至該第一半導體晶粒并且包括：一第一導電線路；形成一第二半導體封裝，其中該第二半導體封裝包括：一第二半導體晶粒，其中該第二半導體晶粒的主動面朝向該第一半導體晶粒的主動面；以及一第二重分佈層結構，耦接至該第二半導體晶粒以及包括：一第二導電線路；以及將該第二半導體封裝接合至該第一半導體封裝，其中，該第一導電線路直接接觸該第二導電線路。
  16. 如申請專利範圍第15項所述的形成半導體封裝組件的方法，其中，該第二半導體封裝使用熔融接合方式接合至該第一半導體封裝。
  17. 如申請專利範圍第16項所述的形成半導體封裝組件的方法，其中，進一步包括：在將該第二半導體封裝接合至該第一半導體封裝期間，對該第一半導體封裝及該第二半導體封裝應用超聲能量。
  18. 如申請專利範圍第15項所述的形成半導體封裝組件的方法，其中，形成該第二半導體封裝的步驟包括：在一第二載體基底上形成一通孔結構；將該第二半導體晶粒接合至該第二載體基底上；在該第二載體基底上形成一第二成型模料，其中，該第二成型模料圍繞該通孔結構和該第二半導體晶粒的側壁，其中該第二成型模料露出該通孔結構的頂面以及該第二半導體晶粒的頂面；以及在該第二半導體晶粒和該第二成型模料上形成該第二重分佈層結構。
  19. 如申請專利範圍第18項所述的形成半導體封裝組件的方法，其中，進一步包括：在將該第二半導體封裝接合至該第一半導體封裝之後，移除該第二載體基底。
  20. 如申請專利範圍第19項所述的形成半導體封裝組件的方法，其中，進一步包括：在移除該第二載體基底之後，在該第二半導體封裝之上形成一導電元件。
  21. 如申請專利範圍第15項所述的形成半導體封裝組件的方法，其中，形成該第一半導體封裝的步驟包括：將該第一半導體晶粒接合至一第一載體基底之上；在該第一載體基底上形成一第一成型模料，其中，該第一成型模料圍繞該第一半導體晶粒的側壁並且露出該第一半導體晶粒的頂面；以及在該第一半導體晶粒和該第一成型模料上形成該第一重分佈層結構。
  22. 如申請專利範圍第21項所述的形成半導體封裝組件的方法，其中，進一步包括：在將該第二半導體封裝接合至該第一半導體封裝之後，移除該第一載體基底；以及對該第一半導體封裝和該第二半導體封裝執行切割製程。
  23. 如申請專利範圍第21項所述的形成半導體封裝組件的方法，其中，該第一半導體封裝的形成包括：將超過一顆的該半導體晶粒接合至該第一載體基底；其中該第一成型模料進一步圍繞該第一半導體晶粒的側壁，並且露出該第一半導體晶粒的頂面。
  24. 一種形成半導體封裝組件的方法，包括：形成一第一半導體封裝，其中該第一半導體封裝包括：一第一半導體晶粒；以及一第一重分佈層結構，耦接至該第一半導體晶粒并且包括：一第一導電線路；形成一第二封裝，其中該第二封裝包括：一被動設備；以及一第二重分佈層結構，耦接至該被動設備以及包括：一第二導電線路；以及將該第二封裝接合至該第一半導體封裝，其中，該第一導電線路直接接觸該第二導電線路。
TW105114086A 2015-05-21 2016-05-06 半導體封裝組件及其形成方法 TWI578460B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562164725P 2015-05-21 2015-05-21
US201562198865P 2015-07-30 2015-07-30
US15/071,573 US10032756B2 (en) 2015-05-21 2016-03-16 Semiconductor package assembly with facing active surfaces of first and second semiconductor die and method for forming the same

Publications (2)

Publication Number Publication Date
TW201642406A TW201642406A (zh) 2016-12-01
TWI578460B true TWI578460B (zh) 2017-04-11

Family

ID=55809003

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105114086A TWI578460B (zh) 2015-05-21 2016-05-06 半導體封裝組件及其形成方法

Country Status (4)

Country Link
US (1) US10032756B2 (zh)
EP (1) EP3096350B1 (zh)
CN (1) CN106169459A (zh)
TW (1) TWI578460B (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101731700B1 (ko) * 2015-03-18 2017-04-28 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9881902B2 (en) 2015-08-05 2018-01-30 Mediatek Inc. Semiconductor package, semiconductor device using the same and manufacturing method thereof
TWI628757B (zh) * 2015-12-23 2018-07-01 力成科技股份有限公司 終極薄扇出型晶片封裝構造及其製造方法
US10276403B2 (en) * 2016-06-15 2019-04-30 Avago Technologies International Sales Pe. Limited High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer
US10032702B2 (en) * 2016-12-09 2018-07-24 Dyi-chung Hu Package structure and manufacturing method thereof
TWI643305B (zh) * 2017-01-16 2018-12-01 力成科技股份有限公司 封裝結構及其製造方法
US10217720B2 (en) * 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
KR101922884B1 (ko) * 2017-10-26 2018-11-28 삼성전기 주식회사 팬-아웃 반도체 패키지
CN107818958B (zh) * 2017-11-20 2023-10-13 长鑫存储技术有限公司 底部封装结构及制作方法
US20210375814A1 (en) * 2017-12-06 2021-12-02 Anhui Yunta Electronic Technologies Co., Ltd. Integrated circuit module structure and method for manufacturing same
CN107845614A (zh) * 2017-12-06 2018-03-27 安徽云塔电子科技有限公司 一种集成电路模组结构及其制作方法
US10665522B2 (en) * 2017-12-22 2020-05-26 Intel IP Corporation Package including an integrated routing layer and a molded routing layer
CN110071073B (zh) * 2018-01-22 2022-03-22 江苏长电科技股份有限公司 封装结构及其制备方法
KR102491103B1 (ko) * 2018-02-06 2023-01-20 삼성전자주식회사 반도체 패키지 및 그 제조방법
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US11276676B2 (en) * 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US20200118940A1 (en) * 2018-10-15 2020-04-16 Intel Corporation Die with bumper for solder joint reliability
US11239173B2 (en) 2019-03-28 2022-02-01 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out feature
WO2020232678A1 (zh) * 2019-05-22 2020-11-26 华为技术有限公司 一种3dic芯片的制作方法及3dic芯片
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
KR102661671B1 (ko) 2019-07-25 2024-04-29 삼성전자주식회사 적층된 반도체 칩들을 포함하는 반도체 패키지
US11244879B2 (en) * 2019-09-26 2022-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
US11239203B2 (en) * 2019-11-01 2022-02-01 Xilinx, Inc. Multi-chip stacked devices
TWI720847B (zh) 2020-03-17 2021-03-01 欣興電子股份有限公司 晶片封裝結構及其製作方法
KR20210142465A (ko) 2020-05-18 2021-11-25 삼성전자주식회사 반도체 패키지
US20220165648A1 (en) * 2020-11-11 2022-05-26 Nepes Co., Ltd. Semiconductor package and method for manufacturing the same
TWI807827B (zh) * 2022-05-13 2023-07-01 矽品精密工業股份有限公司 電子封裝件及其製法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201432871A (zh) * 2013-02-04 2014-08-16 Taiwan Semiconductor Mfg 半導體裝置及其製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7842948B2 (en) * 2004-02-27 2010-11-30 Nvidia Corporation Flip chip semiconductor die internal signal access system and method
CN101480116B (zh) 2006-04-27 2013-02-13 日本电气株式会社 电路基板、电子器件配置及用于电路基板的制造工艺
JP5183949B2 (ja) 2007-03-30 2013-04-17 日本電気株式会社 半導体装置の製造方法
JP5406572B2 (ja) 2009-03-19 2014-02-05 新光電気工業株式会社 電子部品内蔵配線基板及びその製造方法
JP2010238898A (ja) 2009-03-31 2010-10-21 Toshiba Corp 半導体装置
US8039304B2 (en) 2009-08-12 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures
TWI402941B (zh) * 2009-12-03 2013-07-21 Advanced Semiconductor Eng 半導體結構及其製造方法
US8169065B2 (en) 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US8455936B2 (en) 2010-02-25 2013-06-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Configurable memory sheet and package assembly
US8674513B2 (en) * 2010-05-13 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for substrate
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
FR2980036A1 (fr) 2011-09-12 2013-03-15 St Microelectronics Crolles 2 Procede de realisation d'une structure integree tridimensionnelle et structure correspondante
US9087832B2 (en) 2013-03-08 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage reduction and adhesion improvement of semiconductor die package
KR102053349B1 (ko) * 2013-05-16 2019-12-06 삼성전자주식회사 반도체 패키지
CN104505382A (zh) 2014-12-30 2015-04-08 华天科技（西安）有限公司 一种圆片级扇出PoP封装结构及其制造方法
US9613931B2 (en) * 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201432871A (zh) * 2013-02-04 2014-08-16 Taiwan Semiconductor Mfg 半導體裝置及其製造方法

Also Published As

Publication number Publication date
US20160343695A1 (en) 2016-11-24
EP3096350A1 (en) 2016-11-23
EP3096350B1 (en) 2021-08-11
CN106169459A (zh) 2016-11-30
US10032756B2 (en) 2018-07-24
TW201642406A (zh) 2016-12-01

Similar Documents

Publication Publication Date Title
TWI578460B (zh) 半導體封裝組件及其形成方法
TWI618159B (zh) 半導體封裝組件及其製造方法
US11145622B2 (en) Discrete polymer in fan-out packages
US11069656B2 (en) Three-layer package-on-package structure and method forming same
US20210305086A1 (en) Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method
US10163853B2 (en) Formation method of chip package
US10373940B2 (en) Stacked semiconductor package
US11387205B2 (en) Semiconductor die connection system and method
TWI616956B (zh) 整合式扇出封裝及製造方法
TWI614850B (zh) 半導體封裝結構及其形成方法
TWI616980B (zh) 堆疊封裝構件及其製作方法
TWI415202B (zh) 封裝結構之製造方法
US8993380B2 (en) Structure and method for 3D IC package
CN106558573A (zh) 半导体封装结构及形成该半导体封装结构的方法
TW201919134A (zh) 晶片封裝及其形成方法
US20220310518A1 (en) Embedded bridge architecture with thinned surface
TWI559468B (zh) 電子封裝結構及其承載件