TWI618159B - 半導體封裝組件及其製造方法 - Google Patents

半導體封裝組件及其製造方法 Download PDF

Info

Publication number
TWI618159B
TWI618159B TW105114087A TW105114087A TWI618159B TW I618159 B TWI618159 B TW I618159B TW 105114087 A TW105114087 A TW 105114087A TW 105114087 A TW105114087 A TW 105114087A TW I618159 B TWI618159 B TW I618159B
Authority
TW
Taiwan
Prior art keywords
semiconductor package
semiconductor
layer structure
item
redistribution layer
Prior art date
Application number
TW105114087A
Other languages
English (en)
Other versions
TW201642368A (zh
Inventor
林子閎
蕭景文
彭逸軒
Original Assignee
聯發科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯發科技股份有限公司 filed Critical 聯發科技股份有限公司
Publication of TW201642368A publication Critical patent/TW201642368A/zh
Application granted granted Critical
Publication of TWI618159B publication Critical patent/TWI618159B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/63—Connectors not provided for in any of the groups H01L24/10 - H01L24/50 and subgroups; Manufacturing methods related thereto
    • H01L24/65—Structure, shape, material or disposition of the connectors prior to the connecting process
    • H01L24/67—Structure, shape, material or disposition of the connectors prior to the connecting process of a plurality of connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02319—Manufacturing methods of the redistribution layers by using a preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/22—Structure, shape, material or disposition of high density interconnect preforms of a plurality of HDI interconnects
    • H01L2224/221—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/63—Connectors not provided for in any of the groups H01L2224/10 - H01L2224/50 and subgroups; Manufacturing methods related thereto
    • H01L2224/65—Structure, shape, material or disposition of the connectors prior to the connecting process
    • H01L2224/67—Structure, shape, material or disposition of the connectors prior to the connecting process of a plurality of connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本發明提供半導體封裝組件，半導體封裝組件包含第一半導體封裝，第一半導體封裝包含第一半導體晶片，第一重佈層結構與第一半導體晶片耦接。半導體封裝組件也包含第二半導體封裝與第一半導體封裝接合，第二半導體封裝包含第二半導體晶片，第二半導體晶片之主動面朝向第一半導體晶片之主動面。第二重佈層結構與第二半導體晶片耦接，第一重佈層結構位於第一半導體晶片與第二重佈層結構之間。

Description

半導體封裝組件及其製造方法
本發明係有關於半導體封裝組件(semiconductor package assembly)，特別有關於三維(three-dimension,3D)半導體封裝組件及其製造方法。
為達到電子產品的小型化與多功能性的要求，半導體產業經歷了連續且快速地成長。已將積體密度(integration density)提高，使得更多晶片(die)或晶粒(chip)可整合於半導體封裝內，如二維(2D)半導體封裝。然而，二維半導體封裝有物理限制，例如當多於兩個具有各種功能的晶片放入二維半導體裝置中，會變得難以發展必要的更複雜的設計及佈局。
雖然已發展出且廣泛使用三維(3D)積體電路及堆疊晶片，然而整合於傳統的三維半導體封裝內的晶片被限制為相同尺寸。再者，三維半導體封裝技術也遭遇各種可能導致製造良率下降的問題。
因此，需要發展可以減緩或消除上述問題的半導體封裝組件及其製造方法。
本發明的一些實施例之半導體封裝組件包含第一半導體封裝。第一半導體封裝包含第一半導體晶片，第一重佈 層結構與第一半導體晶片耦接。半導體封裝組件也包含第二半導體封裝與第一半導體封裝接合。第二半導體封裝包含第二半導體晶片，第二半導體晶片之主動面朝向第一半導體晶片之主動面，第二重佈層結構與第二半導體晶片耦接，第一重佈層結構位於第一半導體晶片與第二重佈層結構之間。
本發明的另一些實施例之半導體封裝組件包含第一封裝。第一封裝包含第一元件，第一重佈層結構與第一元件耦接。半導體封裝組件也包含第二封裝與第一封裝接合，第二封裝包含第二元件，第二重佈層結構與第二元件耦接，第一重佈層結構位於第一元件與第二重佈層結構之間。
本發明的一些實施例之半導體封裝組件的製造方法包含形成第一半導體封裝。第一半導體封裝包含第一半導體晶片，第一重佈層結構與第一半導體晶片耦接。半導體封裝組件的製造方法也包含形成第二半導體封裝，第二半導體封裝包含第二半導體晶片，第二半導體晶片之主動面朝向第一半導體晶片之主動面，第二重佈層結構與第二半導體晶片耦接。半導體封裝組件的製造方法更包含將第二半導體封裝接合至第一半導體封裝，第一重佈層結構位於第一半導體晶片與第二重佈層結構之間。
上述半導體封裝組件及其製造方法使得利用半導體封裝組件製作出的電子產品之尺寸可縮減。
100A‧‧‧第一承載基底
100B‧‧‧第二承載基底
110A‧‧‧第一元件
110B‧‧‧第二元件
120A‧‧‧第一模塑料
120B‧‧‧第二模塑料
130A‧‧‧第一重佈層結構
130B‧‧‧第二重佈層結構
140A、140B、220‧‧‧導電線路
150A、150B、230‧‧‧金屬層間介電層
160‧‧‧導孔
170、210‧‧‧導電結構
180‧‧‧黏著層
190‧‧‧導電元件
200‧‧‧重佈層結構
300、400、500‧‧‧半導體封裝組件
A‧‧‧第一封裝
B‧‧‧第二封裝
L‧‧‧切割道
第1A至1C圖係根據本發明一些實施例之半導體封裝組 件製造方法之各階段的剖面示意圖。
第2A至2C圖係根據本發明一些實施例之半導體封裝組件製造方法之各階段的剖面示意圖。
第3A至3E圖係根據本發明一些實施例之半導體封裝組件製造方法之各階段的剖面示意圖。
第4圖係根據本發明一些實施例之半導體封裝組件的剖面示意圖。
第5圖係根據本發明一些實施例之半導體封裝組件的剖面示意圖。
以下的揭露內容提供許多不同的實施例或範例以及圖式，然而，這些僅是用以說明本發明之原理，且並非用以限制本發明之範圍。本發明之範圍係以申請專利範圍決定。附圖的描述僅用於理解本發明，並非用於限制本發明。為了說明的目的，在附圖中的一些元件的尺寸可能會放大且並未依照實際比例來繪製。附圖中的尺寸和相對尺寸可能不對應於本發明實際應用中的真實尺寸。
本發明的實施例提供三維(3D)系統級封裝(system-in-package,SIP)半導體封裝組件。半導體封裝組件係整合多於兩個元件或晶片，使得利用半導體封裝組件製作出的電子產品之尺寸可縮減，這些元件或晶片係分別被製造且接續被整合於半導體封裝組件內，因此元件或晶片的尺寸及/或功能並不受限為相同的，半導體封裝組件的設計彈性大幅地提升。再者，預先測試這些元件或晶片，以確保半導體封裝組件 僅包含良好的元件或晶片，由於複數個缺陷的元件或晶片而造成良率損失的問題顯著地減少或消除，因此，降低了半導體封裝組件的製造成本。
第1A至1C圖係根據本發明一些實施例之半導體封裝組件製造方法之各階段的剖面示意圖。於第1A至1C圖描述的各階段之前、期間及/或之後，可提供一些額外的操作步驟。描述的一些階段可依據不同實施例被代替或省略，額外的特徵部件可加入半導體封裝中。以下描述的一些特徵部件可依據不同實施例被代替或省略。
如第1A圖所示，提供第一承載基底(carrier substrate)100A。在一些實施例中，第一承載基底100A為晶圓(wafer)或板材(panel)，第一承載基底100A可包含玻璃或其他適合的支撐材料。
如第1A圖所示，複數個第一元件110A接合(bonded)至第一承載基底100A之上。根據本發明一些實施例，第一元件110A為已知良好(known-good)的元件，換句話說，沒有缺陷的元件接合至第一承載基底100A之上。在一些實施例中，第一元件110A和第一承載基底100A透過黏著層(adhesive layer)(例如膠(glue)或其他適合的黏著材料)貼附在一起。
在一些實施例中，第一元件110A為主動元件且可被稱為第一半導體晶片(或晶粒)110A，第一半導體晶片110A可包含電晶體或其他適合的主動元件，例如第一半導體晶片110A可為邏輯晶片(logic die)，其包含中央處理單元(central processing unit,CPU)、圖像處理單元(graphics processing unit,GPU)、動態隨機存取記憶體(dynamic random access memory,DRAM)控制器或者其任意組合。在一些其他實施例中，第一元件110A為被動元件，例如整合被動元件(integrated passive device,IPD)，第一元件110A可包含複數個電容、電阻、電感、變容二極體或其他適合的被動元件。
如第1B圖所示，第一模塑料(molding compound)120A形成於第一承載基底100A之上，第一模塑料120A圍繞第一元件110A之複數個側壁(sidewall)，而未覆蓋第一元件110A之頂表面和底表面。
在一些實施例中，第一模塑料120A由非導電性材料(例如環氧化物(epoxy)、樹脂(resin)、可塑形聚合物(moldable polymer)或其他適合的模塑材料)所形成。在一些實施例中，可在大體上為液態時塗佈第一模塑料120A，並經由化學反應固化第一模塑料120A。在一些實施例中，第一模塑料120A可為紫外光(ultraviolet,UV)或熱固化聚合物的膠體或具延展性的固體，且可經由紫外光或熱固化製程來固化。第一模塑料120A亦可使用模具來固化。
在一些實施例中，沉積的(deposited)第一模塑料120A覆蓋第一元件110A之頂表面，接著實施研磨(grinding)製程以薄化(thin)沉積的第一模塑料120A，結果薄化的第一模塑料120A露出第一元件110A之頂表面。在一些實施例中，第一模塑料120A之頂表面和底表面係分別與第一元件110A之頂表面和底表面共平面。
如第1C圖所示，第一重佈層(redistribution layer,RDL)結構130A(亦被稱為扇出(fan-out)結構)形成於第一模塑料120A之上且與第一元件110A耦接，結果形成第一(半導體)封裝A。在一些實施例中，第一(半導體)封裝A為晶圓級(wafer-level)扇出封裝。
第一重佈層結構130A覆蓋第一模塑料120A且可直接接觸第一模塑料120A。在一些實施例中，第一重佈層結構130A可包含一或多個導電線路(conductive trace)140A，設置於金屬層間介電(inter-metal dielectric,IMD)層150A中且被金屬層間介電層150A圍繞。第一元件110A係電性連接至第一重佈層結構130A的導電線路140A。金屬層間介電層150A可包含複數個子介電(sub-dielectric)層連續堆疊於第一模塑料120A和第一元件110A上，例如導電線路140A之第一層級(layer-level)位於子介電層之第一層級之上且被子介電層之第二層級覆蓋，導電線路140A之第二層級位於子介電層之第二層級之上且被子介電層之第三層級覆蓋。
在一些實施例中，金屬層間介電層150A可由有機材料(包含聚合基材料)、無機材料(包含氮化矽(SiNx)、氧化矽(SiOx)、石墨烯(graphene))或類似的材料形成。在一些實施例中，金屬層間介電層150A係高介電常數(high-k，k係介電層的介電常數)介電層。在一些實施例中，金屬層間介電層150A可由光敏感材料形成，其包含乾膜光阻(dry film photoresist)或膠膜(taping film)。
導電線路140A的導電墊(pad)部分從第一重佈層結 構130A之頂表面露出，例如導電線路140A的導電墊部分由金屬層間介電層150A之開口露出，且連接至後續形成的導電元件。應理解的是，繪示於圖中的導電線路140A和金屬層間介電層150A的數量和配置僅為範例且並不侷限本發明。
第2A至2C圖係根據本發明一些實施例之半導體封裝組件製造方法之各階段的剖面示意圖。於第2A至2C圖描述的各階段之前、期間及/或之後，可提供一些額外的操作步驟。描述的一些階段可依據不同實施例被代替或省略，額外的特徵部件可加入半導體封裝中。以下描述的一些特徵部件可依據不同實施例被代替或省略。
如第2A圖所示，提供第二承載基底100B。在一些實施例中，第二承載基底100B為晶圓或板材，第二承載基底100B可包含玻璃或其他適合的支撐材料。
如第2A圖所示，複數個導孔/導孔電極(via)160形成於第二承載基底100B之上。導孔160可為中介穿孔/中介穿孔電極(through interposer via,TIV)。在一些實施例中，導孔160為銅柱(pillar)或其他適合的導電結構。在一些實施例中，導孔160係透過電鍍(electroplating)製程或其他適合的製程形成。
如第2A圖所示，複數個第二元件110B接合至第二承載基底100B之上。根據本發明一些實施例，第二元件110B為已知良好的元件，換句話說，沒有缺陷的元件接合至第二承載基底100B之上。在一些實施例中，第二元件110B和第二承載基底100B透過黏著層(例如膠或其他適合的黏著材料)貼附在一起。在一些實施例中，每個第二元件110B係位於導孔160的 其中兩者之間，在一些實施例中，一或多個導孔160係位於第二元件110B的其中兩者之間。
在一些實施例中，第二元件110B為主動元件且可被稱為第二半導體晶片(或晶粒)110B，第二半導體晶片110B可包含電晶體或其他適合的主動元件，例如第二半導體晶片110B可為邏輯晶片包含中央處理單元、圖像處理單元、動態隨機存取記憶體控制器或者其任意組合。在一些其他實施例中，第二元件110B為被動元件，例如整合被動元件，第二元件110B可包含複數個電容、電阻、電感、變容二極體或其他適合的被動元件。
如第2B圖所示，第二模塑料120B形成於第二承載基底100B之上，第二模塑料120B圍繞導孔160和第二元件110B之複數個側壁，而未覆蓋第二元件110B和導孔160之頂表面和底表面。也就是說，導孔160穿透或貫穿第二模塑料120B。
在一些實施例中，第二模塑料120B由非導電性材料(例如環氧化物、樹脂、可塑形聚合物或其他適合的模塑材料)所形成。在一些實施例中，可在大體上為液態時塗佈第二模塑料120B，並經由化學反應固化第二模塑料120B。在一些實施例中，第二模塑料120B可為紫外光或熱固化聚合物的膠體或具延展性的固體，且可經由紫外光或熱固化製程來固化。第二模塑料120B亦可使用模具來固化。
在一些實施例中，沉積的第二模塑料120B覆蓋第二元件110B與導孔160之頂表面，接著實施研磨製程以薄化沉積的第二模塑料120B，結果薄化的第二模塑料120B露出第二元 件110B和導孔160之頂表面。在一些實施例中，第二模塑料120B之頂表面和底表面係分別與第二元件110B之頂表面和底表面共平面。在一些實施例中，第二模塑料120B之頂表面和底表面係分別與導孔160之頂表面和底表面共平面。
根據本發明一些實施例，在將第二元件110B接合至第二承載基底100B上之前，預先地薄化第二元件110B，結果使第二元件110B和導孔160大體上具有相同的厚度，進而有利於露出第二元件110B和導孔160。舉例來說，將半導體晶圓薄化且接續地切割成半導體晶片(或晶粒)，以形成第二元件110B。第二元件110B可藉由機械研磨(mechanical grinding)製程、化學機械研磨(chemical mechanical polishing)製程、銑削(milling)製程或其他適合的製程薄化。
如第2C圖所示，第二重佈層結構130B形成於第二模塑料120B之上且與第二元件110B和導孔160耦接，第二重佈層結構130B覆蓋第二模塑料120B且可直接接觸第二模塑料120B。在一些實施例中，第二重佈層結構130B可包含一或多個導電線路140B設置於金屬層間介電層150B中且被金屬層間介電層150B圍繞。第二元件110B係電性連接至第二重佈層結構130B的導電線路140B。導電線路140B之導電墊部分從第二重佈層結構130B之頂表面露出。第二重佈層結構130B之結構可相似或相同於第一重佈層結構130A之結構，如前述的詳細內容。應理解的是，繪示於圖中的導電線路140B和金屬層間介電層150B的數量和配置僅為範例且並不侷限本發明。
如第2C圖所示，複數個導電結構170形成於第二 重佈層結構130B之上，導電結構170係電性連接至導電線路140B的導電墊部分，結果形成第二(半導體)封裝B。在一些實施例中第二(半導體)封裝B為晶圓級扇出封裝。
在一些實施例中，導電結構170可為導電柱、導電凸塊(bump)(例如微凸塊)、導電膏/膠(paste/glue)或其他適合的導電結構。導電結構170可包含銅、焊料(solder)或其他適合的導電材料，例如導電結構170可為以焊料層覆蓋的銅柱。
第3A至3E圖係根據本發明一些實施例之半導體封裝組件製造方法之各階段的剖面示意圖。於第3A至3E圖描述的各階段之前、期間及/或之後，可提供一些額外的操作步驟。描述的一些階段可依據不同實施例被代替或省略，額外的特徵部件可加入半導體封裝中。以下描述的一些特徵部件可依據不同實施例被代替或省略。
如第3A圖所示，第二封裝B接合至第一封裝A，使第一重佈層結構130A位於第一元件110A與第二重佈層結構130B之間。導電結構170位於第一重佈層結構130A與第二重佈層結構130B之間，且與第一重佈層結構130A和第二重佈層結構130B耦接。第一重佈層結構130A之導電線路140A透過導電結構170電性連接至第二重佈層結構130B之導電線路140B，例如導電結構170係直接接觸導電線路140A與導電線路140B的導電墊部分。在一些實施例中，第一元件110A之主動面朝向第二元件110B之主動面。
根據本發明的一些實施例，第一封裝A與第二封裝B透過黏著層180接合在一起，黏著層180填充第一重佈層結構 130A與第二重佈層結構130B之間的空間。在一些實施例中，黏著層180圍繞導電結構170。在一些實施例中，黏著層180由環氧樹脂、丁基環丁烷(butyl cyclobutane,BCB)、環氧氯丙烷(epoxy chloropropane,ECP)或其他適合的黏著材料形成。
如第3B圖所示，將第二承載基底100B從第二封裝B移除，結果露出第二元件110B和導孔160，而第二元件110B與導孔160之側壁仍被第二模塑料120B圍繞。在一些實施例中，消除用來接合第二元件110B和第二承載基底100B的黏著層之黏性，以剝離(debond)第二承載基底100B。
如第3C圖所示，導電元件190形成於遠離第一封裝A的第二封裝B之上，換句話說，導電元件190和第一封裝A係位於第二封裝B之兩個相反側，第二元件110B係位於第二重佈層結構130B與導電元件190之間。
在一些實施例中，導電元件190透過導孔160及第二重佈層結構130B電性連接或耦接至第二元件110B。在一些實施例中，導電元件190透過導孔160、第二重佈層結構130B、導電結構170及第一重佈層結構130A更進一步電性連接至第一元件110A。
在一些實施例中，導電元件190由重佈層結構200和形成於重佈層結構200之上的導電結構210所構成。在一些實施例中，重佈層結構200包含一或多個導電線路220設置於金屬層間介電層230中且被金屬層間介電層230圍繞，導電線路220的導電墊部分從重佈層結構200之頂表面露出。重佈層結構200之結構可相似或相同於第一重佈層結構130A，如前述的詳細內 容。
導電結構210係電性連接露出的導電線路220的導電墊部分，導孔160透過導電線路220電性連接或耦接至導電結構210。在一些實施例中，導電結構210為接合球(bonding ball)(例如焊球(solder ball))或其他適合的導電材料。應理解的是，繪示於圖中的導電結構210和導電線路220的數量和配置僅為範例且並不侷限本發明。
在一些其他實施例中，導電元件190由導電結構210形成。導孔160直接電性連接至導電結構210，導孔160可透過一或多層導電層電性連接至導電結構210。
如第3D圖所示，將第一承載基底100A從第一封裝A移除，結果露出第一元件110A，而第一元件110A之側壁仍被第一模塑料120A圍繞。在一些實施例中，消除用來接合第一元件110A和第一承載基底100A的黏著層之黏性，以剝離第一承載基底100A。
之後，在接合的第一封裝A與第二封裝B上實施單體化(singulation)製程，沿切割道(scribe line)L切開或分割接合的第一封裝A與第二封裝B，以將接合的第一封裝A與第二封裝B分離成複數個半導體封裝組件300。半導體封裝組件300係系統級封裝半導體封裝組件，且晶圓級扇出封裝整合於半導體封裝組件300中。
如第3E圖所示，每個半導體封裝組件300包含一個第一元件110A和兩個第二元件110B，半導體封裝組件300可包含多於兩個的第二元件110B。在一些實施例中，第一元 件110A之尺寸不同於第二元件110B之尺寸，例如第一元件110A之尺寸大於第二元件110B之尺寸。在一些實施例中，複數個第二元件110B為相同尺寸。在一些其他實施例中，複數個第二元件110B為不同尺寸。
在一些實施例中，第一元件110A與第二元件110B具有相同功能，因此半導體封裝組件300係同質整合(homogeneous integration)。在一些其他實施例中，第一元件110A之功能不同於一或多個第二元件110B之功能，因此半導體封裝組件300係為異質整合(heterogeneous integration)。
在一些實施例中，第一元件110A與第二元件110B的其中一者為系統單晶片(system-on-chip,SOC)，且第一元件110A與第二元件110B的其中另一者為動態隨機存取記憶體。 在一些實施例中，第一元件110A與第二元件110B的其中一者為應用處理器(application processor,AP)，且第一元件110A與第二元件110B的其中另一者為數位處理器(digital processor,DP)。在一些實施例中，第一元件110A與第二元件110B的其中一者為基頻(baseband)元件，且第一元件110A與第二元件110B的其中另一者為射頻(radio frequency,RF)元件。
舉例來說，在一些實施例中，第一元件110A係主動元件，而複數個第二元件110B係有相同或不同功能的被動元件。在一些實施例中，第一元件110A和其中一個第二元件110B係具有相同或不同功能的主動元件，而其他的第二元件110B係被動元件。在一些其他實施例中，第一元件110A和複數個第二元件110係具有各種不同功能的主動元件。
或者，在一些實施例中，第一元件110A係被動元件，而複數個第二元件110B係具有相同或不同功能的主動元件。在一些實施例中，第一元件110A和其中一個第二元件110B係具有相同或不同功能的被動元件，而其他的第二元件110B係主動元件。
可於本發明的實施例作許多變更和修改。第4和5圖係根據本發明一些實施例之半導體封裝組件的剖面示意圖。為簡化，第4和5圖中相同於第3E圖中的部件係使用相同的標號並省略其說明。
請參照第4圖，繪示出半導體封裝組件400，半導體封裝組件400與第3E圖所示之半導體封裝組件300相似，半導體封裝組件300與半導體封裝組件400之間主要的不同處在於半導體封裝組件300包含一個第一元件110A，而半導體封裝組件400包含兩個第一元件110A。半導體封裝組件400可包含多於兩個第一元件110A。
在一些實施例中，複數個第一元件110A具有相同的尺寸。在一些其他實施例中，複數個第一元件110A具有不同的尺寸。在一些實施例中，第一元件110A之尺寸不同於第二元件110B之尺寸，例如第一元件110A之尺寸大於第二元件110B之尺寸。在一些實施例中，複數個第一元件110A具有相同的功能，在一些其他實施例中，複數個第一元件110A具有不同的功能。
請參照第5圖，繪示出半導體封裝組件500，半導體封裝組件500與第3E圖所示之半導體封裝組件300相似，半 導體封裝組件300與半導體封裝組件500之間主要的不同處在於半導體封裝組件300之導孔160係形成於第二封裝B內，而半導體封裝組件500之導孔160係形成於第一封裝A內，結果半導體封裝組件300之導電元件190係形成於第二封裝B之上，而半導體封裝組件500之導電元件190係形成於第一封裝A之上。
於第5圖中，導孔160穿透第一模塑料120A且電性連接或耦接至第一重佈層結構130A，導電元件190和第二封裝B係位於第一封裝A的兩個相反側，第一元件110A係位於第一重佈層結構130A與導電元件190之間。
本發明根據一些實施例的半導體封裝組件及其製造方法提供各種優點。根據前述的一些實施例，多於兩個元件或晶片可整合於單一半導體封裝組件內，這些元件或晶片係在不同的製程中製造且為已知良好的元件或晶片，因此，這些元件或晶片的尺寸及/或功能並未被侷限，進而有利於改善設計的彈性，且半導體封裝組件之製造良率更進一步顯著地提升。
雖然本發明的實施例及其優點已揭露如上，但應理解的是，本發明並未侷限於揭露之實施例。任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可做些許更動與潤飾，因此本發明的保護範圍當以權利要求所界定為准。凡依本發明權利要求所做的均等變化與修飾，皆應屬本發明的涵蓋範圍。
110A‧‧‧第一元件
110B‧‧‧第二元件
120A‧‧‧第一模塑料
120B‧‧‧第二模塑料
130A‧‧‧第一重佈層結構
130B‧‧‧第二重佈層結構
140A、140B、220‧‧‧導電線路
150A、150B、230‧‧‧金屬層間介電層
160‧‧‧導孔
170、210‧‧‧導電結構
180‧‧‧黏著層
190‧‧‧導電元件
200‧‧‧重佈層結構
300‧‧‧半導體封裝組件
A‧‧‧第一封裝
B‧‧‧第二封裝

Claims (30)

  1. 一種半導體封裝組件，包括：一第一半導體封裝，包括：一第一半導體晶片；以及一第一重佈層結構，與該第一半導體晶片耦接；以及一第二半導體封裝，與該第一半導體封裝接合，其中該第二半導體封裝包括：一第二半導體晶片，其中該第二半導體晶片之一主動面朝向該第一半導體晶片之一主動面；以及一第二重佈層結構，與該第二半導體晶片耦接。
  2. 如申請專利範圍第1項所述之半導體封裝組件，其中該第一半導體封裝包括一個以上的該第一半導體晶片或該第二半導體封裝包括一個以上的該第二半導體晶片。
  3. 如申請專利範圍第1項所述之半導體封裝組件，更包括一導電結構，其中該導電結構與該第一重佈層結構和該第二重佈層結構耦接。
  4. 如申請專利範圍第3項所述之半導體封裝組件，更包括一黏著層，其中該黏著層位於該第一重佈層結構與該第二重佈層結構之間，且圍繞該導電結構。
  5. 如申請專利範圍第1項所述之半導體封裝組件，其中該第一半導體晶片和該第二半導體晶片具有不同尺寸。
  6. 如申請專利範圍第1項所述之半導體封裝組件，其中該第一半導體封裝更包括一第一模塑料，其中該第一模塑料圍繞該第一半導體晶片之側壁。
  7. 如申請專利範圍第6項所述之半導體封裝組件，其中該第一重佈層結構覆蓋該第一模塑料。
  8. 如申請專利範圍第6項所述之半導體封裝組件，其中該第一半導體封裝更包括一導孔，其中該導孔穿透該第一模塑料且與該第一重佈層結構耦接。
  9. 如申請專利範圍第8項所述之半導體封裝組件，更包括一導電元件與該導孔耦接，其中該第一半導體晶片位於該第一重佈層結構與該導電元件之間。
  10. 如申請專利範圍第1項所述之半導體封裝組件，其中該第二半導體封裝更包括一第二模塑料，且該第二模塑料圍繞該第二半導體晶片之側壁。
  11. 如申請專利範圍第10項所述之半導體封裝組件，其中該第二重佈層結構覆蓋該第二模塑料。
  12. 如申請專利範圍第10項所述之半導體封裝組件，其中該第二半導體封裝更包括一導孔，其中該導孔穿透該第二模塑料且與該第二重佈層結構耦接。
  13. 如申請專利範圍第12項所述之半導體封裝組件，更包括一導電元件與該導孔耦接，其中該第二半導體晶片位於該第二重佈層結構與該導電元件之間。
  14. 一種半導體封裝組件，包括：一第一封裝，包括：一第一元件；以及一第一重佈層結構，與該第一元件耦接；以及一第二封裝，與該第一封裝接合，其中該第二封裝包括： 一第二元件；以及一第二重佈層結構，與該第二元件耦接，其中該第一重佈層結構位於該第一元件與該第二重佈層結構之間。
  15. 如申請專利範圍第14項所述之半導體封裝組件，其中該第一元件和該第二元件具有不同尺寸。
  16. 如申請專利範圍第14項所述之半導體封裝組件，其中該第一元件和該第二元件中的一個為一主動元件，而該第一元件和該第二元件中的另外一個為一被動元件。
  17. 如申請專利範圍第14項所述之半導體封裝組件，其中該第一封裝包括一個以上的該第一元件或該第二封裝包括一個以上的該第二元件。
  18. 如申請專利範圍第14項所述之半導體封裝組件，其中該第一封裝包括一個以上的該第一元件且該第二封裝包括一個以上的該第二元件，且其中該第一元件中至少一個和該第二元件中至少一個具有不同尺寸。
  19. 如申請專利範圍第14項所述之半導體封裝組件，更包括一第一模塑料和一第二模塑料，其中該第一模塑料圍繞該第一元件之側壁且該第二模塑料圍繞該第二元件之側壁。
  20. 如申請專利範圍第19項所述之半導體封裝組件，更包括一導孔，其中該導孔穿透該第一模塑料或該第二模塑料。
  21. 如申請專利範圍第20項所述之半導體封裝組件，更包括一導電元件與該導孔耦接。
  22. 一種半導體封裝組件的製造方法，包括：形成一第一半導體封裝，其中該第一半導體封裝包括： 一第一半導體晶片；以及一第一重佈層結構，與該第一半導體晶片耦接；形成一第二半導體封裝，其中該第二半導體封裝包括：一第二半導體晶片，其中該第二半導體晶片之一主動面朝向該第一半導體晶片之一主動面；以及一第二重佈層結構，與該第二半導體晶片耦接；以及將該第二半導體封裝接合至該第一半導體封裝，其中該第一重佈層結構位於該第一半導體晶片與該第二重佈層結構之間。
  23. 如申請專利範圍第22項所述之半導體封裝組件的製造方法，其中該第二半導體封裝透過一黏著層接合至該第一半導體封裝。
  24. 如申請專利範圍第22項所述之半導體封裝組件的製造方法，更包括形成一導電結構，以電性連接該第一半導體晶片和該第二半導體晶片。
  25. 如申請專利範圍第22項所述之半導體封裝組件的製造方法，其中該第二半導體封裝的形成包括：形成複數個導孔於一第二承載基底之上；接合該第二半導體晶片於該第二承載基底之上；形成一第二模塑料於該第二承載基底之上，其中該第二模塑料圍繞該等導孔和該第二半導體晶片之側壁，且其中該第二模塑料露出該等導孔和該第二半導體晶片之頂表面；以及形成該第二重佈層結構於該第二半導體晶片和該第二模塑 料之上。
  26. 如申請專利範圍第25項所述之半導體封裝組件的製造方法，更包括在將該第二半導體封裝接合至該第一半導體封裝之後，移除該第二承載基底。
  27. 如申請專利範圍第26項所述之半導體封裝組件的製造方法，更包括在移除該第二承載基底之後，形成一導電元件於該第二半導體封裝之上。
  28. 如申請專利範圍第22項所述之半導體封裝組件的製造方法，其中該第一半導體封裝的形成包括：接合該第一半導體晶片於一第一承載基底之上；形成一第一模塑料於該第一承載基底之上，其中該第一模塑料圍繞該第一半導體晶片之側壁，且露出該第一半導體晶片之頂表面；以及形成該第一重佈層結構於該第一半導體晶片和該第一模塑料之上。
  29. 如申請專利範圍第28項所述之半導體封裝組件的製造方法，更包括：在將該第二半導體封裝接合至該第一半導體封裝之後，移除該第一承載基底；以及對該第一半導體封裝和該第二半導體封裝實施一單體化製程。
  30. 如申請專利範圍第28項所述之半導體封裝組件的製造方法，其中該第一半導體封裝的形成包括接合一個以上的該第一半導體晶片於該第一承載基底之上，其中該第一模塑 料更圍繞該等第一半導體晶片之側壁，且露出該等第一半導體晶片之頂表面。
TW105114087A 2015-05-21 2016-05-06 半導體封裝組件及其製造方法 TWI618159B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562164725P 2015-05-21 2015-05-21
US62/164,725 2015-05-21
US15/071,559 2016-03-16
US15/071,559 US20160343685A1 (en) 2015-05-21 2016-03-16 Semiconductor package assembly and method for forming the same

Publications (2)

Publication Number Publication Date
TW201642368A TW201642368A (zh) 2016-12-01
TWI618159B true TWI618159B (zh) 2018-03-11

Family

ID=55750329

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105114087A TWI618159B (zh) 2015-05-21 2016-05-06 半導體封裝組件及其製造方法

Country Status (4)

Country Link
US (1) US20160343685A1 (zh)
EP (1) EP3096349A1 (zh)
CN (1) CN106169452A (zh)
TW (1) TWI618159B (zh)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US10276403B2 (en) * 2016-06-15 2019-04-30 Avago Technologies International Sales Pe. Limited High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer
US9859245B1 (en) 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same
US20180166417A1 (en) * 2016-12-13 2018-06-14 Nanya Technology Corporation Wafer level chip-on-chip semiconductor structure
TWI643305B (zh) * 2017-01-16 2018-12-01 力成科技股份有限公司 封裝結構及其製造方法
US10381301B2 (en) * 2017-02-08 2019-08-13 Micro Technology, Inc. Semiconductor package and method for fabricating the same
KR102351676B1 (ko) * 2017-06-07 2022-01-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US10217720B2 (en) * 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
WO2019066952A1 (en) * 2017-09-29 2019-04-04 Intel Corporation CONDUCTIVE PASSIVE SEMICONDUCTOR ELEMENTS
US11646288B2 (en) * 2017-09-29 2023-05-09 Intel Corporation Integrating and accessing passive components in wafer-level packages
US10763239B2 (en) 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
KR101942745B1 (ko) * 2017-11-07 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지
TWI643307B (zh) * 2018-01-30 2018-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US10700051B2 (en) 2018-06-04 2020-06-30 Intel Corporation Multi-chip packaging
KR102542617B1 (ko) * 2018-06-08 2023-06-14 삼성전자주식회사 반도체 패키지, 패키지 온 패키지 장치 및 이의 제조 방법
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
TWI659515B (zh) * 2018-07-26 2019-05-11 欣興電子股份有限公司 封裝結構及其製造方法
KR102534734B1 (ko) 2018-09-03 2023-05-19 삼성전자 주식회사 반도체 패키지
US10804188B2 (en) * 2018-09-07 2020-10-13 Intel Corporation Electronic device including a lateral trace
WO2020101572A1 (en) * 2018-11-12 2020-05-22 Agency For Science, Technology And Research Multi-chip system and method of forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11824040B2 (en) * 2019-09-27 2023-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package component, electronic device and manufacturing method thereof
DE102020116106B4 (de) 2019-11-22 2023-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtungen und herstellungsverfahren
CN111430313A (zh) * 2020-05-11 2020-07-17 上海天马微电子有限公司 半导体封装及其制作方法
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
KR20220017022A (ko) 2020-08-03 2022-02-11 삼성전자주식회사 반도체 패키지
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
JP2024515033A (ja) * 2021-03-31 2024-04-04 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 担体の直接ボンディング及び剥離
TWI807827B (zh) * 2022-05-13 2023-07-01 矽品精密工業股份有限公司 電子封裝件及其製法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080237883A1 (en) * 2007-03-30 2008-10-02 Nec Corporation Semiconductor device and method of manufacturing the same
US20100044845A1 (en) * 2006-04-27 2010-02-25 Nec Corporation Circuit substrate, an electronic device arrangement and a manufacturing process for the circuit substrate
JP2010219477A (ja) * 2009-03-19 2010-09-30 Shinko Electric Ind Co Ltd 電子部品内蔵配線基板の製造方法
JP2010238898A (ja) * 2009-03-31 2010-10-21 Toshiba Corp 半導体装置
US20110037169A1 (en) * 2009-08-12 2011-02-17 Stats Chippac, Ltd. Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structures
US20110147911A1 (en) * 2009-12-22 2011-06-23 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US8455936B2 (en) * 2010-02-25 2013-06-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Configurable memory sheet and package assembly

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7842948B2 (en) * 2004-02-27 2010-11-30 Nvidia Corporation Flip chip semiconductor die internal signal access system and method
JP5412831B2 (ja) * 2006-07-24 2014-02-12 三菱瓦斯化学株式会社 分散媒置換方法
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
TW201110285A (en) * 2009-09-08 2011-03-16 Unimicron Technology Corp Package structure having embedded semiconductor element and method of forming the same
TWI402941B (zh) * 2009-12-03 2013-07-21 Advanced Semiconductor Eng 半導體結構及其製造方法
US8674513B2 (en) * 2010-05-13 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for substrate
US8884431B2 (en) * 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
CN102445933B (zh) * 2011-10-14 2013-06-12 兰泽华 基于物联网的农田大棚监测报警管理***
KR102053349B1 (ko) * 2013-05-16 2019-12-06 삼성전자주식회사 반도체 패키지
CN104505382A (zh) * 2014-12-30 2015-04-08 华天科技（西安）有限公司 一种圆片级扇出PoP封装结构及其制造方法
US9613931B2 (en) * 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100044845A1 (en) * 2006-04-27 2010-02-25 Nec Corporation Circuit substrate, an electronic device arrangement and a manufacturing process for the circuit substrate
US20080237883A1 (en) * 2007-03-30 2008-10-02 Nec Corporation Semiconductor device and method of manufacturing the same
JP2010219477A (ja) * 2009-03-19 2010-09-30 Shinko Electric Ind Co Ltd 電子部品内蔵配線基板の製造方法
JP2010238898A (ja) * 2009-03-31 2010-10-21 Toshiba Corp 半導体装置
US20110037169A1 (en) * 2009-08-12 2011-02-17 Stats Chippac, Ltd. Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structures
US20110147911A1 (en) * 2009-12-22 2011-06-23 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US8455936B2 (en) * 2010-02-25 2013-06-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Configurable memory sheet and package assembly

Also Published As

Publication number Publication date
CN106169452A (zh) 2016-11-30
EP3096349A1 (en) 2016-11-23
US20160343685A1 (en) 2016-11-24
TW201642368A (zh) 2016-12-01

Similar Documents

Publication Publication Date Title
TWI618159B (zh) 半導體封裝組件及其製造方法
EP3096350B1 (en) Semiconductor package assembly and method for forming the same
US11069656B2 (en) Three-layer package-on-package structure and method forming same
US11631611B2 (en) Wafer level chip scale packaging intermediate structure apparatus and method
TWI701790B (zh) 晶片封裝結構與其形成方法
US10636773B2 (en) Semiconductor package structure and method for forming the same
TWI616980B (zh) 堆疊封裝構件及其製作方法
US8803306B1 (en) Fan-out package structure and methods for forming the same
US20170098628A1 (en) Semiconductor package structure and method for forming the same
TWI500091B (zh) 封裝一半導體裝置之方法及封裝裝置
US10515887B2 (en) Fan-out package structure having stacked carrier substrates and method for forming the same
TW201714275A (zh) 半導體封裝結構及其形成方法
TWI626717B (zh) 半導體封裝結構
US9875949B2 (en) Electronic package having circuit structure with plurality of metal layers, and fabrication method thereof
US20230245923A1 (en) Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method
US10249562B2 (en) Package structure and fabrication method thereof
US11201142B2 (en) Semiconductor package, package on package structure and method of froming package on package structure
TWI694562B (zh) 堆疊封裝結構及其製造方法
TWI559468B (zh) 電子封裝結構及其承載件
US20150380369A1 (en) Wafer packaging structure and packaging method
TW202207366A (zh) 半導體封裝裝置及其製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees