CN106558573A - 半导体封装结构及形成该半导体封装结构的方法 - Google Patents

半导体封装结构及形成该半导体封装结构的方法 Download PDF

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CN106558573A
CN106558573A CN201610635402.8A CN201610635402A CN106558573A CN 106558573 A CN106558573 A CN 106558573A CN 201610635402 A CN201610635402 A CN 201610635402A CN 106558573 A CN106558573 A CN 106558573A
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semiconductor wafer
semiconductor
rotating fields
conductive
semiconductor package
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郭哲宏
周哲雅
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明提供了一种半导体封装结构。该半导体封装结构包括第一半导体晶片，具有第一活性表面和第一非活性表面；第二半导体晶片，具有第二活性表面和第二非活性表面，其中，所述第二半导体晶片堆叠在所述第一半导体晶片上，以及，所述第一非活性表面面向所述第二非活性表面；第一重布线层结构，其中，所述第一活性表面面向所述第一重布线层结构；以及第二重布线层结构，其中，所述第二活性表面面向所述第二重布线层结构。相应地，本发明还提供了一种用于形成半导体封装结构的方法。采用本发明，半导体装结构包括以背靠背方式堆叠的两个半导体晶片，可以减少封装尺寸。

Description

半导体封装结构及形成该半导体封装结构的方法
技术领域
本发明涉及一种半导体封装结构，以及更特别地，涉及一种多晶片(multi-die)的半导体封装结构及形成该半导体封装结构的方法。
背景技术
随着如与3C(计算机(Computer)、通信(Communication)以及消费电子(Consumerelectronic)有关的这些电子产业的持续发展，消费者对多功能、更便捷以及更小的设备需求迅速增加。该需求驱动了集成电路(integrated circuit，IC)密度增大的必要。输入/输出(input-output，I/O)引脚数量的增加以及对集成电路密度的增大需求已带来多晶片封装的发展。随着对高性能和高集成度的需求，双晶片扇出式(fan-out)晶圆级芯片级封装(wafer level chip scale package，WLCSP)、硅通孔(through silicon via，TSV)技术以及三维封装体叠层(three-dimensional package on package，3D PoP)结构已被接受为一些替代选择。
然而，双晶片扇出式晶圆级芯片级封装(WLCSP)包括两个并排(side by side)设置的晶片。因此，封装尺寸太大，且翘曲变形(warpage)是需要关心的问题。硅通孔(TSV)技术包括形成贯穿(penetrating)多个晶片的硅通孔(TSV)。因此，制造成本高，以及浪费晶片的面积。三维封装体叠层(3D PoP)结构在底部封装上堆叠顶部封装。因此，这甚至难以进一步减少三维封装体叠层(3D PoP)结构的厚度。
因此，需求一种新颖的半导体封装结构以及形成该半导体封装结构的方法。
发明内容
有鉴于此，本发明的目的之一在于提供一种半导体封装结构以及形成该半导体封装结构的方法，以解决上述问题。
第一方面，本发明的示例性实施例提供了一种半导体封装结构，该半导体封装结构包括第一半导体晶片，第一半导体晶片包括第一活性表面和第一非活性表面。该半导体封装结构还包括第二半导体晶片，第二半导体晶片包括第二活性表面和第二非活性表面。其中，第二半导体晶片堆叠在第一半导体晶片上，以及，第一非活性表面面向第二非活性表面。该半导体封装结构还包括第一重布线层结构，第一活性表面面向第一重布线层结构。此外，该半导体封装结构还包括第二重布线层结构，第二活性表面面向第二重布线层结构。
第二方面，本发明的另一示例性实施例提供了一种半导体封装结构，该半导体封装结构包括第一半导体晶片，第一半导体晶片包括第一导电垫，其中，所述第一半导体晶片具有第一表面和与所述第一表面相对的第二表面，所述第一导电垫位于所述的第一表面上；第二半导体晶片，包括第二导电垫，其中，所述第二半导体晶片垂直地堆叠在所述第一半导体晶片上，所述第二半导体晶片具有第三表面和与所述第三表面相对的第四表面，所述第一导电垫位于所述的第三表面上，所述第二表面面向所述第四表面；以及模塑料，围绕所述第一半导体晶片和所述第二半导体晶片。
第三方面，本发明的示例性实施例提供了一种用于形成半导体封装结构的方法，包括：提供第一半导体晶片，所述第一半导体晶片包括第一非活性表面。该方法还包括：将第二半导体晶片堆叠在所述第一半导体晶片上；其中，所述第一半导体晶片的第一非活性表面面向所述第二半导体晶片的第二非活性表面。该方法还包括：形成围绕所述第一半导体晶片和所述第二半导体晶片的模塑料。
在上述技术方案中，本发明提供了一种新颖的半导体封装结构及形成该半导体封装结构的方法，该半导体封装结构包括以背靠背方式堆叠的两个半导体晶片，可以减小封装尺寸。
本领域技术人员在阅读附图所示优选实施例的下述详细描述之后，可以毫无疑义地理解本发明的这些目的及其它目的。
附图说明
图1A至图1E是根据本发明一些实施例的一种用于形成半导体封装结构的各个阶段的剖视图；
图2是根据本发明一些实施例的一种半导体封装结构的剖视图；
图3是根据本发明一些实施例的一种半导体封装结构的剖视图；
图4是根据本发明一些实施例的一种半导体封装结构的剖视图；
图5是根据本发明一些实施例的一种半导体封装结构的剖视图。
具体实施方式
以下描述为实施本发明的较佳实施例，其用说明本发明的一般原则，而并非用来限制本发明的范畴。本发明的范围应当参考所附的权利要求书来确定。
本发明将根据特定的实施例以及参考某些附图来描述，但是，本发明并不限于此，以及，仅受权利要求书的限制。所描述的附图仅是一种示意而并非限制。在附图中，为了说明目的，一些组件的尺寸可能被夸大而不是按比例绘制。附图中的尺寸和相对尺寸可以或可以不对应于本发明实践中的实际尺寸。
图1A至图1E是根据本发明一些实施例的一种用于形成半导体封装结构的各个阶段的剖视图。在图1A至图1E所描述的各阶段之前、期间和/或之后均可以提供附加的操作。对于不同的实施例，所描述的一些阶段可以被替换或消除。附加的特征可以被添加至该半导体封装结构。对于不同的实施例，以下描述的一些特征可以被替换或消除。为了简化附图，图1A至图1E中仅示出半导体封装结构的一部分。
如图1A所示，提供载体基板(carrier substrate)100。载体基板100是临时性(temporary)基板，以及，将在后续的步骤中被移除。在一些实施例中，载体基板100为晶圆(wafer)或面板(panel)。在一些实施例中，载体基板100包括玻璃、硅，或其它合适的载体材料。
如图1A所示，一个或多个导电孔(conductive via)110被形成在载体基板100上。导电孔110为封装通孔(through package vias，TPV)。在一些实施例中，导电孔110包括铜或其它合适的导电材料。
如图1A所示，半导体晶片200被提供在载体基板100上。在一些实施例中，半导体晶片200是翻转的，以及通过粘接层(adhesive layer)(未示出，该粘接层将在后续的步骤中被移除)附着于(attached to)载体基板100。在另一些实施例中，多个半导体晶片200被提供在载体基板100上。为方便描述，图1A至图1E所示的实施例以一个半导体晶片200被直接提供在载体基板100上为例。但应当说明的是，本发明并不限于此示例情形。
在一些实施例中，半导体晶片200可以为***级芯片(system-on-chip，SOC)、存储器晶片(memory die)、逻辑晶片(logic die)、模拟处理器(analog processor，AP)、数字处理器(digital processor，DP)、基带(baseband，BB)元件、射频(radio-frequency，RF)元件，或者其它合适的有源(active)电子元件。存储器晶片可以是动态随机存取存储器(dynamic random access memory，DRAM)晶片。逻辑晶片可以是中央处理单元(centralprocessing unit，CPU)、图像处理单元(graphics processing unit，GPU)或动态随机存取存储器(DRAM)控制器。半导体晶片200具有活性表面(active surface)200a、非活性表面(non-active surface)200b和侧壁(sidewall)200c。侧壁200c基本上垂直于活性表面200a和非活性表面200b。
如图1A所示，半导体晶片200包括一个或多个导电垫(conductive pad)210，导电垫210位于活性表面200a上。导电垫210面向载体基板100。导电垫210可以位于半导体晶片200的互连结构中的最顶层中。在一些实施例中，导电垫210可被包括为该互连结构的导电迹线(conductive trace)。为简化附图，此处仅描述导电垫210。在一些实施例中，导电垫210可以通过电镀工艺(electroplating process)、接合工艺(bonding process)或另一适用的工艺形成。
钝化层(passivation layer)220被设置在活性表面200a上，以及，部分覆盖导电垫210。钝化层220包括一个或多个开孔(opening)。每个开孔露出相应的导电垫210的一部分。如图1A所示，每个导电垫210的周围部分可以被钝化层覆盖，而导电垫210的中央部分从钝化层露出。
一个或多个导电结构(conductive structure)230被形成在钝化层220上，以及，填充钝化层220的开孔。因此，每一个导电结构230电连接于相应的导电垫210。在一些实施例中，导电结构230可以是导电层的多个部分。在一些实施例中，导电结构230可以是导电凸块(conductive bump)(如微凸块，micro bump)，导电球(ball)或导电柱(pillar)。在另一些实施例中，导电结构230未被形成。
底部填充层(underfill layer)240被形成在钝化层220上，以及，围绕导电结构230的上部。在另一些实施例中，底部填充层240未被形成。
在一些实施例中，半导体晶片200的构造(formation)包括依次形成的导电垫210、钝化层220、导电结构230以及位于半导体晶圆或面板上的底部填充层240。此后，半导体晶圆或面板被切割为多个半导体晶片。半导体晶片200是已知合格的(即半导体晶片200为已知合格芯片(known-good die，KGD))，且被提供在载体基板100上。
在一些实施例中，形成导电孔110之后，将半导体晶片200设置在载体基板100上。在另一些实施例中，形成导电孔110之前，将半导体晶片200设置在载体基板100上。在一些实施例中，导电孔110比半导体晶片200厚。
如图1B所示，根据本发明的一些实施例，半导体晶片400被垂直堆叠在半导体晶片200上。因此，导电孔110、半导体晶片200和400并排设置。在一些实施例中，导电孔110比半导体晶片400厚。
在一些实施例中，半导体晶片400通过粘接层300附着于半导体晶片200。粘接层300夹在半导体晶片200和半导体晶片400之间。在另一些实施例中，多个半导体晶片400被堆叠在半导体晶片200上。为方便描述，本实施例中以一个半导体晶片400堆叠在一个半导体晶片200上为例。但应当说明的是，本发明并不限于此，具体实现中，可以是多个半导体晶片400堆叠在一个半导体晶片200上，也可以是多个半导体晶片400被堆叠在多个半导体晶片200上，还可以是一个半导体晶片400堆叠在多个半导体晶片200上，具体地，本发明不做限制。
在一些实施例中，半导体晶片400可以为***级芯片(SOC)、存储器晶片、逻辑晶片、模拟处理器(AP)、数字处理器(DP)、基带(BB)元件、射频(RF)元件，或者其它合适的有源电子元件。半导体晶片400包括活性表面400a、非活性表面400b和侧壁400c。侧壁400c基本上垂直于活性表面400a和非活性表面400b。
根据本发明的一些实施例，非活性表面400b面向非活性表面200b。在一些实施例中，粘接层300直接接触非活性表面400b和200b，以及，被夹在非活性表面400b和200b之间。
如图1B所示，半导体晶片400包括一个或多个导电垫410，导电垫410位于活性表面400a上。导电垫410的面向远离半导体晶片200和载体基板100。因此，导电垫210和410彼此远离面向。在一些实施例中，导电垫410可以通过电镀工艺、接合工艺或其它适用的工艺形成。在一些实施例中，半导体晶片400的结构与构造类似于或相同于半导体晶片200的结构与构造。因此，为简洁起见，此处不再赘述关于钝化层420、导电结构430以及底部填充层440的类似描述。
半导体晶片200和400可以具有不同的功能。举例来说，在一些实施例中，半导体晶片200和400之一为***级芯片(SOC)，而半导体晶片200和400之另一为存储器晶片。在另一些实施例中，半导体晶片200和400之一为模拟处理器(AP)，而半导体晶片200和400之另一为数字处理器(DP)。在一些实施例中，半导体晶片200和400之一为基带(BB)元件，而半导体晶片200和400之另一为射频(RF)元件。在另一些实施例中，半导体晶片200和400可以具有相同的功能。
在一些实施例中，如图1B所示，半导体晶片200和400具有相同的尺寸。在另一些实施例中，半导体晶片200和400可以具有不同的尺寸。半导体晶片200和400可以彼此对齐(align)或不对齐(misalign)。在一些实施例中，半导体晶片400完全地垂直地堆叠在半导体晶片200上。因此，侧壁400c与侧壁200c基本共面(coplanar)。在另一些实施例中，半导体晶片400部分地垂直堆叠在半导体晶片200上(例如，对于半导体晶片400窄于半导体晶片200的情形)。因此，侧壁400c与侧壁200c不共面。
如图1B所示，模塑料(molding compound)500被形成在载体基板100上。模塑料500围绕导电孔110、半导体晶片200和400，以及粘接层300。模塑料500邻接(adjoin)侧壁200c和400c。
在一些实施例中，模塑料500的一部分被夹在其中一个导电孔110与半导体晶片200之间。在一些实施例中，模塑料500的一部分被夹在其中一个导电孔110与半导体晶片400之间。
在一些实施例中，半导体晶片400窄于半导体晶片200，或者，半导体晶片200和400不完全堆叠于彼此之上。因此，模塑料500的一部分延伸在半导体晶片200上。模塑料500的一部分可以直接接触到非活性表面200b。在一些实施例中，半导体晶片400宽于半导体晶片200，或者，半导体晶片200和400彼此不完全重叠。因此，模塑料500的一部分延伸在半导体晶片400之下。模塑料500的一部分可以直接接触到粘接层300。
在一些实施例中，模塑料500包括非导电材料，如环氧树脂(epoxy)、树脂(resin)、可模塑的聚合物(moldable polymer)，或其它合适的模塑材料。在一些实施例中，模塑料500作为实质性的液体，然后通过化学反应固化。在另一些实施例中，模塑料500是作为凝胶(gel)或可塑固体(malleable solid)的紫外线(ultraviolet，UV)或热固化的聚合物，然后通过紫外线(UV)或热固化工艺进行固化。可以利用模具(mold)来固化模塑料500。
在一些实施例中，沉积后的模塑料500覆盖导电孔110和导电结构430的顶部表面。此后，进行减薄工艺(thinning process)(如蚀刻工艺，碾磨工艺，磨削工艺或抛光工艺)，以使该沉积后的模塑料500变薄。因此，减薄后的模塑料500露出导电孔110和导电结构430的顶部表面。在一些实施例中，模塑料500的顶部表面与导电孔110、导电结构430的顶部表面基本上共面。
如图1C所示，重布线层(redistribution layer，RDL)结构600(也被称之为扇出式结构)被形成在模塑料500、导电孔100和半导体晶片400上。在一些实施例中，重布线层(RDL)结构600可以包括设置在金属间介电(inter-metal dielectric，IMD)层中的一个或多个导电迹线。该金属间介电(IMD)层可以包括多个子介电层(sub-dielectric layer)，该多个子介电层依次堆叠在模塑料500上。
举例来说，多个导电迹线620设置在第一子介电层610上，且被第二子介电层630覆盖。多个导电迹线620中的至少一个(如与半导体晶片400相邻的其中两个导电迹线)电耦接于导电孔110以及半导体晶片400。导电垫410通过导电结构430电连接于重布线层(RDL)结构600的导电迹线620。在另一些实施例中，导电结构430未被形成，以及，导电垫410直接电连接于导电迹线620。应当注意的是，附图中所示的重布线层(RDL)结构600的导电迹线与子介电层的数量和安排仅为一种示例，而并不是本发明的限制。
在一些实施例中，金属间介电(IMD)层可由有机材料(organic material)(如包括聚合物基体材料)或非有机材料(non-organic material)(如包括氮化硅(SiNx)、氧化硅(SiOx)、石墨烯等等)组成。举例来说，第一子介电层610和第二子介电层630由聚合物基体材料制成。在一些实施例中，金属间介电(IMD)层为高k介电层(k为介电层的介电常数)。在另一些实施例中，金属间介电(IMD)层可以由感光材料(包括干膜抗蚀剂(dry filmphotoresist)或者包带薄膜(taping film))制成。
如图1C所示，支撑基板(supporting substrate)700被提供在重布线层(RDL)结构600上。支撑基板700是临时性基板，以及，将在后续的步骤中被移除。在一些实施例中，支撑基板700包括玻璃、硅，或者其它合适的支撑材料。
本发明并不限于所描述的实施例。在另一些实施例中，重布线层(RDL)结构600被预先形成在支撑基板700上。此后，具有重布线层(RDL)结构600的支撑基板700被接合到模塑材料500、导电孔110和半导体晶片400上。在另一些实施例中，重布线层(RDL)结构600也可以不预先形成在支撑基板700上而直接被接合到模塑材料500、导电孔110和半导体晶片400上。
如图1D所示，载体基板100被移除。在一些实施例中，如前所述，粘接层(未示出)可以被夹在半导体晶片200和载体基板100之间。在移除载体基板100之后，该粘接层也被移除。举例来说，进行减薄工艺(如磨削工艺)，以移除粘接层。在移除粘接层的期间，可以部分地移除导电孔110和模塑料500。
此后，利用支撑基板700作为载体，重布线层(RDL)结构800被形成。重布线层(RDL)结构600和800位于模塑料500的相对的两侧上。换言之，半导体晶片200位于重布线层(RDL)结构800与半导体晶片400之间，而半导体晶片400位于重布线层(RDL)结构600与半导体晶片200之间。重布线层(RDL)结构600和800还位于贯穿模塑料500的导电孔110的相对的两侧上。活性表面200a面向重布线层(RDL)结构800，而活性表面400a面向重布线层(RDL)结构600。
在一些实施例中，重布线层(RDL)结构800可以包括一个或多个导电迹线，该一个或多个导电迹线设置在金属间介电(IMD)层中。金属间介电(IMD)层可以包括多个子介电层，该多个子介电层依次堆叠在模塑料500上。
举例来说，多个第一导电迹线820位于第一子介电层810上，以及被第二子介电层830覆盖。多个第一导电迹线820中的至少一个电耦接于导电孔110和半导体晶片200。导电垫210通过导电结构230电连接于重布线层(RDL)结构800的第一导电迹线820。在另一些实施例中，导电结构230未被形成，以及，导电垫210直接电连接于第一导电迹线820。多个第二导电迹线840位于第二子介电层830上，且被第三子介电层850覆盖。应当注意的是，附图中所示的重布线层(RDL)结构800的导电迹线与子介电层的数量和安排仅为一种示例，而并不是本发明的限制。
导电迹线的导电垫部分从重布线层(RDL)结构800的顶部暴露出来。举例来说，第二导电迹线840的导电垫部分从第三子介电层850的开孔暴露出来，以及连接至后续形成的导电元件。
本发明并不限于所描述的实施例。在另一些实施例中，重布线层(RDL)结构800被预先形成在载体基板100上。其后，导电孔110、半导体晶片200和400、模塑料500以及重布线层(RDL)结构600被形成在位于载体基板100上的重布线层(RDL)结构800上。在该情形中，半导体晶片200被接合至重布线层(RDL)结构800，以及通过导电结构230电连接于重布线层(RDL)结构800。在支撑基板700被提供在重布线层(RDL)结构600上之后，移除载体基板100，以及，重布线层(RDL)结构800露出。
如图1D所示，利用支撑基板700作为载体，一个或多个导电元件900被形成在重布线层(RDL)结构800上。导电元件900电连接于第二导电迹线840的导电垫部分。在一些实施例中，导电元件900是导电柱、导电凸块(如微凸块)、导电胶结构(conductive pastestructure)，或者其它合适的导电元件。导电元件900可以包括铜、焊料，或者其它合适的导电材料。
在一些实施例中，其中一个导电元件900与第二导电迹线的其中一个焊片部分之间具有凸块下金属(under-bump metallurgy，UBM)层910。凸块下金属(UBM)层910可以包括一层或多层，如阻挡层(barrier layer)以及种晶层(seed layer)。此处作为一种示例描述了具有单个层的凸块下金属(UBM)层910。
如图1E所示，支撑基板700被移除。因此，重布线层(RDL)结构600露出。在一些实施例中，移除支撑基板700之后执行切单工艺(singulation process)。举例来说，重布线层(RDL)结构600和800，以及模塑料500可以被切割。因此，多个半导体封装1000A被形成。在一些实施例中，半导体封装1000A可以被直接接合至印刷电路板(printed circuit board，PCB)。在图1E所示的情形中，没有半导体器件(如半导体晶片或半导体封装)被堆叠在半导体封装1000A上。
如图1E所示，每一个半导体封装1000A包括垂直堆叠的半导体晶片200和400。特别地，半导体晶片200的非活性表面200b面向半导体晶片400的非活性表面400b。半导体晶片200和400通过上面的(overlying)重布线层(RDL)结构600、下面的(underlying)重布线层(RDL)结构800以及其附近的导电孔110彼此电连接。因此，多个半导体晶片可以被集成在一个半导体封装中，而无需增大半导体封装的水平尺寸(面积)。此外，从半导体晶片至印刷电路板(PCB)的导电路径的长度短，以及具有大数量的导电路径。因此，本发明提供了一种具有小尺寸和良好的电气性能的多晶片半导体封装。
可以对本发明实施例做出许多变型和/或修改。例如，在一些变型实施例中，导电孔和模塑料是可选的。例如，半导体封装结构可以包括第一半导体晶片(如200)、第二半导体晶片(如400)、第一重布线层结构(如800)和第二重布线层结构(如600)。第二半导体晶片堆叠在第一半导体晶片上，第一半导体晶片的第一非活性表面面向第二半导体晶片的第二非活性表面，以及，第一半导体晶片的第一活性表面面向第一重布线层结构，第二半导体晶片的第二活性表面面向第二重布线层结构。再例如，第一半导体晶片可以包括第一导电垫，第一导电垫电连接于第一重布线层结构；以及，第二半导体晶片可以包括第二导电垫，第二导电垫可以电连接于第二重布线层结构。此外，该半导体封装结构还可以包括导电孔，从而，第一半导体晶片可以通过第一导电垫、第一重布线层结构、导电孔、第二重布线层结构、第二导电垫电连接于第二半导体晶片。
图2是根据本发明一些实施例的一种半导体封装结构的剖视图。在图2中，与图1A至图1E相同的组件采用与图1A至图1E相同的参考标号来标注，因此，为简洁起见，此处不再描述这些相同的组件。
图2所示的半导体封装1000B的结构与图1E所示的半导体封装1000A的结构类似。两者之间的差异是，半导体封装1000B的重布线层(RDL)结构600上具有阻焊层(soldermask layer)650。一个或多个开孔660形成在阻焊层650中，以及延伸到重布线层(RDL)结构600，以露出重布线层(RDL)结构600中的导电迹线的导电垫部分。举例来说，开孔660延伸到第二子介电层630中。因此，导电迹线620的导电垫部分从开孔660露出。在一些实施例中，第二子介电层630可以直接作为阻焊层650使用，具体地，本发明实施例不做限制。
构造具有多个开孔660的阻焊层650的目的是为了进一步地电连接。举例来说，一芯片/晶片可以被接合到阻焊层650上，以及，通过开孔660电连接至重布线层(RDL)结构600。或者，一封装可以被堆叠在半导体封装1000B上，以及通过开孔660电连接于重布线层(RDL)结构600。举例来说，该封装可以是存储器封装(如DRAM封装)或另一合适的封装。因此，可以形成包括多个半导体封装的半导体封装组件(assembly)。该半导体封装组件的示例将在以后进行更加详细的描述。
本发明并不限于前述实施例。两个以上的半导体晶片可被集成在一个半导体封装中。图3和图4是根据本发明一些实施例的半导体封装结构的剖视图。在图3和图4中，与图1A至图1E以及图2相同的组件采用与图1A至图1E以及图2相同的参考标号来标注，因此，为简洁起见，此处不再描述这些相同的组件。
图3所示的半导体封装1000C的结构与图2所示的半导体封装1000B的结构类似。两者之间的差异是，半导体封装1000C中具有多个半导体晶片200和多个半导体晶片400。
在一些实施例中，如图3所示，多个半导体晶片400(如左部所示的两个半导体晶片400)垂直堆叠在一个半导体晶片200上。在一些实施例中，一个半导体晶片400(如右部所示的一个半导体晶片400)垂直堆叠在多个半导体晶片200上。在一些实施例中，多个半导体晶片400中的其中一个与多个半导体晶片200中的其中一个彼此未完全地垂直重叠。在一些实施例中，多个半导体晶片200具有不同的尺寸。在另一些实施例中，多个半导体晶片200具有相同的尺寸。在一些实施例中，多个半导体晶片400具有不同的尺寸。在另一些实施例中，多个半导体晶片400具有相同的尺寸。在一些实施例中，如图3所示，模塑料500的一些部分延伸在半导体晶片200与半导体晶片200之间，以及，半导体晶片400与半导体晶片400之间。
图4所示的半导体封装1000D的结构与半导体封装1000B和1000C的结构类似。它们之间的差异是，半导体封装1000D中具有垂直堆叠在多个半导体晶片200上的多个半导体晶片400。多个半导体晶片200可以具有不同的尺寸或相同的尺寸。多个半导体晶片400可以具有不同的尺寸或相同的尺寸。如图4所示，在一些实施例中，模塑料500的一些部分延伸在半导体晶片200与半导体晶片200之间，以及半导体晶片400与半导体晶片400之间。
尽管半导体封装1000B、1000C或1000D在重布线层(RDL)结构600上包括具有开孔660的阻焊层650，但本发明并不限于此。在一些实施例中，部分地露出重布线层(RDL)结构600的开孔660未被形成。在一些实施例中，未在重布线层(RDL)结构600上形成阻焊层650。在这些情形中，没有半导体器件(如半导体晶片或半导体封装)堆叠在半导体封装1000B、1000C或1000D上。
根据本发明的一些实施例，半导体封装结构和用于形成该半导体封装结构的方法提供了多种优势。垂直堆叠的多个半导体晶片被集成在半导体封装1000A、1000B、1000C或1000D中。与具有两个并排设置的晶片的双晶片扇出式封装相比，半导体封装1000A、1000B、1000C或1000D的水平尺寸(面积)非常小。还可以避免翘曲变形的问题。与具有垂直堆叠封装的三维封装体叠层(3D PoP)结构相比，半导体封装1000A、1000B、1000C或1000D的垂直尺寸(厚度)非常小。因此，具有多个半导体晶片的半导体封装的尺寸被大大地减少。此外，与硅通孔(TSV)技术相比，半导体封装1000A、1000B、1000C或1000D的构造简单，以及，必要的制造成本和时间要少得多。
如以上所描述的，各种各样的半导体封装还可以被堆叠在半导体封装1000B、1000C或1000D上。举例来说，如图5所示，半导体封装2000垂直堆叠在半导体封装1000B上。图5是根据本发明一些实施例的一种半导体封装结构的剖视图。在图5中，与图1A至图1E以及图2相同的组件采用相同的参考标号，因此，为简洁起见，此处不再描述这些相同的组件。应当注意的是，图5所示的半导体封装2000的结构仅是一种示例，以及，本发明并不限于此。
半导体封装2000与半导体封装1000B被安装在一起，以及，通过导电元件2100彼此电连接。导电元件2100位于开孔660中，以及从阻焊层650突出。在一些实施例中，导电元件2100是导电凸块(如微凸块)、导电柱、导电胶结构或其它合适的导电元件。导电元件2100可以包括铜、焊料或者其它合适的导电材料。在另一些实施例中，导电元件2100被底部填充材料围绕。
在一些实施例中，半导体封装2000包括基座(base)2200、至少一个半导体晶片(如两个垂直堆叠的半导体晶片2300和2400)、接合引线(bonding wire)2500以及模塑料2600。在一些实施例中，基座2200为基板(substrate)，以及，可以由聚丙烯(propathene，PP)或其它合适的材料组成。基座2200通过导电元件2100电连接至重布线层(RDL)结构600。
半导体晶片2300通过粘接层(如胶水(glue)或其它合适的粘附材料)附着于基座2200上。半导体晶片2300通过其导电垫2310以及接合引线2500电连接于基座2200。在一些实施例中，半导体晶片2300为存储器晶片或另一合适的半导体晶片。半导体晶片2400通过粘接层(如胶水或另一合适的粘附材料)附着于半导体晶片2300上。半导体晶片2400通过其导电垫2410以及接合引线2500电连接于基座2200。在一些实施例中，半导体晶片2400是存储器晶片或另一合适的半导体晶片。在一些实施例中，半导体晶片2300和2400是DRAM晶片。在一些实施例中，导电垫2300和/或2400可以通过电镀工艺、接合工艺或其它适用的工艺形成。
模塑料2600覆盖基座2200以及围绕半导体晶片2300和2400。接合引线2500被嵌入在模塑料2600中。在一些实施例中，模塑料2600由非导电材料(如环氧树脂、树脂、可模塑的聚合物，或者其它合适的模塑材料)组成。
如图5中所示，小尺寸的半导体封装1000B和半导体封装2000被垂直地堆叠以及被集成在半导体封装结构/组件中。因此，本发明提供了一种具有两个以上半导体晶片的封装体叠层(PoP)结构，以及，其尺寸被大大减少。
在不脱离本发明的精神以及范围内，本发明可以其它特定格式呈现。所描述的实施例在所有方面仅用于说明的目的而并非用于限制本发明。本发明的保护范围当视所附的权利要求所界定者为准。本领域技术人员皆在不脱离本发明之精神以及范围内做些许更动与润饰。

Claims (23)

1.一种半导体封装结构，其特征在于，包括：
第一半导体晶片，具有第一活性表面和第一非活性表面；
第二半导体晶片，具有第二活性表面和第二非活性表面，其中，所述第二半导体晶片堆叠在所述第一半导体晶片上，以及，所述第一非活性表面面向所述第二非活性表面；
第一重布线层结构，其中，所述第一活性表面面向所述第一重布线层结构；以及
第二重布线层结构，其中，所述第二活性表面面向所述第二重布线层结构。
2.如权利要求1所述的半导体封装结构，其特征在于，所述半导体封装结构还包括：
粘接层，直接接触所述第一非活性表面和所述第二非活性表面。
3.如权利要求1所述的半导体封装结构，其特征在于，所述半导体封装结构还包括：
导电孔，设置在所述第一半导体晶片和所述第二半导体晶片的周围。
4.如权利要求3所述的半导体封装结构，其特征在于，所述半导体封装结构还包括：
模塑料，围绕所述导电孔、所述第一半导体晶片和所述第二半导体晶片。
5.如权利要求4所述的半导体封装结构，其特征在于，所述第一重布线层结构和所述第二重布线层结构位于所述模塑料的相对的两侧上。
6.如权利要求1所述的半导体封装结构，其特征在于，所述第一半导体晶片的侧壁与所述第二半导体晶片的侧壁基本上共面。
7.如权利要求1所述的半导体封装结构，其特征在于，所述半导体封装结构包括多个第二半导体晶片，所述多个第二半导体晶片堆叠在所述第一半导体晶片上。
8.如权利要求1所述的半导体封装结构，其特征在于，所述半导体晶片封装结构包括多个第一半导体晶片和多个第二半导体晶片，其中，所述多个第二半导体晶片堆叠在所述多个第一半导体晶片上。
9.如权利要求8所述的半导体封装结构，其特征在于，所述半导体晶片封装结构还包括：
模塑料，位于所述多个第二半导体晶片的两者之间和/或所述多个第一半导体晶片的两者之间。
10.一种半导体封装结构，其特征在于，包括：
第一半导体晶片，包括第一导电垫，其中，所述第一半导体晶片具有第一表面和与所述第一表面相对的第二表面，所述第一导电垫位于所述第一表面上；
第二半导体晶片，包括第二导电垫，其中，所述第二半导体晶片垂直地堆叠在所述第一半导体晶片上，所述第二半导体晶片具有第三表面和与所述第三表面相对的第四表面，所述第一导电垫位于所述第三表面上，所述第二表面面向所述第四表面；以及
模塑料，围绕所述第一半导体晶片和所述第二半导体晶片。
11.如权利要求10所述的半导体封装结构，其特征在于，所述半导体封装结构还包括：
贯穿所述模塑料的导电孔，其中，所述第一导电垫通过所述导电孔电连接于所述第二导电垫。
12.如权利要求11所述的半导体封装结构，其特征在于，所述模塑料的一部分被夹在所述导电孔和所述第一半导体晶片之间，以及所述导电孔与所述第二半导体晶片之间。
13.如权利要求11所述的半导体封装结构，其特征在于，所述导电孔厚于所述第一半导体晶片和所述第二半导体晶片之一者或两者。
14.如权利要求10所述的半导体封装结构，其特征在于，所述半导体封装结构还包括：
粘接层，位于所述第一半导体晶片和所述第二半导体晶片之间，以及被所述模塑料围绕。
15.如权利要求10所述的半导体封装结构，其特征在于，所述半导体封装结构还包括：
第一重布线层结构和第二重布线层结构，位于所述模塑料的相对的两侧上；其中，所述第一导电垫面向所述第一重布线层结构，以及，所述第二导电垫面向所述第二重布线层结构。
16.如权利要求15所述的半导体封装结构，其特征在于，所述半导体封装结构还包括：
导电元件，连接于所述第一重布线层结构。
17.如权利要求15或16所述的半导体封装结构，其特征在于，所述半导体封装结构还包括：
阻焊层，位于所述第二重布线层结构上，其中，所述阻焊层包括开孔，所述开孔使所述第二重布线层结构的一部分露出。
18.一种形成半导体封装结构的方法，其特征在于，包括：
提供第一半导体晶片；
将第二半导体晶片堆叠在所述第一半导体晶片上；其中，所述第一半导体晶片的第一非活性表面面向所述第二半导体晶片的第二非活性表面；以及
形成围绕所述第一半导体晶片和所述第二半导体晶片的模塑料。
19.如权利要求18所述的方法，其特征在于，所述方法还包括：
形成第一重布线层结构，其中，所述第二非活性表面面向所述第一重布线层结构；以及
形成第二重布线层结构，其中，所述第一非活性表面面向所述第二重布线层结构；
所述第一重布线层结构和所述第二重布线层结构位于所述模塑料的相对的两侧上。
20.如权利要求19所述的方法，其特征在于，所述方法还包括：
形成导电孔，其中，所述导电孔设置在所述第一半导体晶片和所述第二半导体晶片的周围。
21.如权利要求20所述的方法，其特征在于，所述第一半导体晶片被提供在载体基板上，以及，所述导电孔被形成在所述载体基板上；以及，所述方法还包括：
在形成所述第二重布线层结构之后移除所述载体基板。
22.如权利要求21所述的方法，其特征在于，所述方法还包括：
在移除所述载体基板之前，提供支撑基板到所述第二重布线层结构上；以及
在形成所述第一重布线层结构之后，移除所述支撑基板。
23.如权利要求18所述的方法，其特征在于，所述第二非活性表面通过粘接层附着于所述第一非活性表面。
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107579009A (zh) * 2017-09-02 2018-01-12 中国电子科技集团公司第五十八研究所 一种多芯片叠层封装结构及其制作方法
CN107731761A (zh) * 2017-09-30 2018-02-23 睿力集成电路有限公司 底部半导体封装件及其制造方法
CN109638009A (zh) * 2018-12-17 2019-04-16 华进半导体封装先导技术研发中心有限公司 一种多芯片层叠扇出型封装结构及其制造方法
CN110634838A (zh) * 2019-08-29 2019-12-31 上海先方半导体有限公司 一种超薄扇出型封装结构及其制作方法
US10535633B2 (en) 2015-07-02 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
TWI693645B (zh) * 2018-04-30 2020-05-11 台灣積體電路製造股份有限公司 晶片封裝體
CN111370395A (zh) * 2020-03-24 2020-07-03 青岛歌尔智能传感器有限公司 心率模组的封装结构、封装方法及可穿戴设备
CN112908868A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 存储器三维封装方法及结构
CN113497021A (zh) * 2020-04-07 2021-10-12 联发科技股份有限公司 半导体封装结构
CN115547852A (zh) * 2022-12-01 2022-12-30 合肥矽迈微电子科技有限公司 一种高功率芯片的半成品结构、器件及其封装工艺
WO2023010555A1 (zh) * 2021-08-06 2023-02-09 华为技术有限公司 芯片封装结构及电子设备

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9960150B2 (en) 2016-06-13 2018-05-01 Micron Technology, Inc. Semiconductor device assembly with through-mold cooling channel formed in encapsulant
US9859253B1 (en) * 2016-06-29 2018-01-02 Intel Corporation Integrated circuit package stack
US10290590B2 (en) * 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Company Ltd. Stacked semiconductor device and method of manufacturing the same
DE112016007539T5 (de) * 2016-12-23 2019-09-12 Intel Corporation VERTIKALES, GESTAPELTES CHIP-GRÖßENORDNUNG BONDDRAHTGEHÄUSE MIT ANWENDUNGSSPEZIFISCHEM INTEGRIERTEM SCHALTUNGS-DIE AUF DEM STAPEL UND VERFAHREN ZUM HERSTELLEN DESSELBEN
US10438931B2 (en) * 2017-01-16 2019-10-08 Powertech Technology Inc. Package structure and manufacturing method thereof
US10403602B2 (en) 2017-06-29 2019-09-03 Intel IP Corporation Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory
US10872885B2 (en) 2017-06-30 2020-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming same
DE102018108409B4 (de) 2017-06-30 2023-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte schaltkreis-packages und verfahren zu deren herstellung
US10290611B2 (en) 2017-07-27 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same
US10475747B2 (en) * 2017-08-14 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
TWI736780B (zh) 2017-10-31 2021-08-21 台灣積體電路製造股份有限公司 晶片封裝及其形成方法
US11322449B2 (en) 2017-10-31 2022-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package with fan-out structures
DE102018122228B4 (de) 2017-11-15 2023-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integriertes Multichip-Fan-Out-Package sowie Verfahren zu dessen Herstellung
US10515922B2 (en) 2017-11-15 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip integrated fan-out package
US11232957B2 (en) * 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and package structure
CN110729271A (zh) * 2019-03-04 2020-01-24 Pep创新私人有限公司 芯片封装方法及封装结构
US11610855B2 (en) * 2017-11-29 2023-03-21 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US20190247618A1 (en) * 2018-02-09 2019-08-15 Qualcomm Incorporated Wireless guidewire
US11075151B2 (en) * 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package with controllable standoff
US10510668B1 (en) * 2018-07-16 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating semiconductor device
EP3621104A1 (en) * 2018-09-05 2020-03-11 Infineon Technologies Austria AG Semiconductor package and method of manufacturing a semiconductor package
US20200312732A1 (en) 2018-09-14 2020-10-01 Mediatek Inc. Chip scale package structure and method of forming the same
US11450606B2 (en) 2018-09-14 2022-09-20 Mediatek Inc. Chip scale package structure and method of forming the same
TWI679735B (zh) * 2018-10-05 2019-12-11 力成科技股份有限公司 雙面扇出型層疊封裝結構及其封裝方法
US20200203470A1 (en) * 2018-12-20 2020-06-25 Intel Corporation Magnetic mold material inductors for electronic packages
US10770433B1 (en) * 2019-02-27 2020-09-08 Apple Inc. High bandwidth die to die interconnect with package area reduction
TWI688059B (zh) * 2019-03-14 2020-03-11 力成科技股份有限公司 半導體封裝結構及其製造方法
US11657862B2 (en) * 2019-03-22 2023-05-23 Intel Corporation Electrically coupled trace routing configuration in multiple layers
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US10867966B2 (en) * 2019-04-29 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure, package-on-package structure and method of fabricating the same
KR102671078B1 (ko) * 2019-05-02 2024-05-30 에스케이하이닉스 주식회사 팬 아웃 서브 패키지를 포함한 스택 패키지
US11133423B2 (en) * 2019-07-03 2021-09-28 Advanced Semiconductor Engineering, Inc. Optical device and method of manufacturing the same
DE102020106799A1 (de) * 2019-09-20 2021-03-25 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterbauelemente und verfahren zur herstellung
US11856800B2 (en) * 2019-09-20 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices with system on chip devices
US11251100B2 (en) * 2019-09-25 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and method of fabricating the semiconductor structure
CN112687615A (zh) 2019-10-17 2021-04-20 美光科技公司 微电子装置组合件、封装体和相关方法
US11393794B2 (en) * 2019-10-17 2022-07-19 Micron Technology, Inc. Microelectronic device assemblies and packages including surface mount components
US20220375902A1 (en) * 2019-10-17 2022-11-24 Micron Technology, Inc. Microelectronic device assemblies and packages and related methods and systems
CN112687613A (zh) * 2019-10-17 2021-04-20 美光科技公司 包含表面安装部件的微电子装置组合件和封装体
CN112687614A (zh) 2019-10-17 2021-04-20 美光科技公司 包含多个装置堆叠的微电子装置组合件和封装体以及相关方法
TWI751506B (zh) * 2020-03-06 2022-01-01 欣興電子股份有限公司 線路板及其製造方法
DE102021107982B4 (de) * 2020-04-07 2024-02-22 Mediatek Inc. Halbleiter-packagestruktur
US11710702B2 (en) * 2020-06-08 2023-07-25 Micron Technology, Inc. Substrate-free semiconductor device assemblies with multiple semiconductor devices and methods for making the same
KR20210152772A (ko) * 2020-06-09 2021-12-16 삼성전자주식회사 반도체 패키지
US11456291B2 (en) * 2020-06-24 2022-09-27 Qualcomm Incorporated Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods
KR20220047066A (ko) * 2020-10-08 2022-04-15 삼성전자주식회사 반도체 패키지 장치
US11923285B2 (en) * 2021-01-05 2024-03-05 Advanced Semiconductor Engineering, Inc. Electronic device package and method of manufacturing the same
US20230110957A1 (en) * 2021-10-13 2023-04-13 Mediatek Inc. Electronic device with stacked printed circuit boards
US20230213715A1 (en) * 2022-01-03 2023-07-06 Apple Inc. Technologies for Increased Volumetric and Functional Efficiencies of Optical Packages
US20240186301A1 (en) * 2022-12-06 2024-06-06 Nxp Usa, Inc. Double-sided multichip packages

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090239336A1 (en) * 2008-03-21 2009-09-24 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same
US20120056312A1 (en) * 2010-09-02 2012-03-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming TSV Semiconductor Wafer with Embedded Semiconductor Die
CN103296014A (zh) * 2012-02-28 2013-09-11 刘胜 扇出晶圆级半导体芯片三维堆叠封装结构及工艺
CN103730434A (zh) * 2012-10-11 2014-04-16 台湾积体电路制造股份有限公司 Pop结构及其形成方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7166495B2 (en) * 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
JP3481444B2 (ja) * 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
US6093969A (en) * 1999-05-15 2000-07-25 Lin; Paul T. Face-to-face (FTF) stacked assembly of substrate-on-bare-chip (SOBC) modules
JP3581086B2 (ja) * 2000-09-07 2004-10-27 松下電器産業株式会社 半導体装置
TW511415B (en) * 2001-01-19 2002-11-21 Matsushita Electric Ind Co Ltd Component built-in module and its manufacturing method
SG121705A1 (en) * 2002-02-21 2006-05-26 United Test & Assembly Ct Ltd Semiconductor package
CN101480116B (zh) 2006-04-27 2013-02-13 日本电气株式会社 电路基板、电子器件配置及用于电路基板的制造工艺
US20080079150A1 (en) * 2006-09-28 2008-04-03 Juergen Simon Die arrangement and method for producing a die arrangement
US20090127686A1 (en) * 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
US20100193930A1 (en) * 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same
US7923304B2 (en) * 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090239336A1 (en) * 2008-03-21 2009-09-24 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same
US20120056312A1 (en) * 2010-09-02 2012-03-08 Stats Chippac, Ltd. Semiconductor Device and Method of Forming TSV Semiconductor Wafer with Embedded Semiconductor Die
CN103296014A (zh) * 2012-02-28 2013-09-11 刘胜 扇出晶圆级半导体芯片三维堆叠封装结构及工艺
CN103730434A (zh) * 2012-10-11 2014-04-16 台湾积体电路制造股份有限公司 Pop结构及其形成方法

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069657B2 (en) 2015-07-02 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
US10535633B2 (en) 2015-07-02 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
CN107579009A (zh) * 2017-09-02 2018-01-12 中国电子科技集团公司第五十八研究所 一种多芯片叠层封装结构及其制作方法
CN107731761A (zh) * 2017-09-30 2018-02-23 睿力集成电路有限公司 底部半导体封装件及其制造方法
TWI693645B (zh) * 2018-04-30 2020-05-11 台灣積體電路製造股份有限公司 晶片封裝體
CN109638009A (zh) * 2018-12-17 2019-04-16 华进半导体封装先导技术研发中心有限公司 一种多芯片层叠扇出型封装结构及其制造方法
CN110634838A (zh) * 2019-08-29 2019-12-31 上海先方半导体有限公司 一种超薄扇出型封装结构及其制作方法
CN111370395A (zh) * 2020-03-24 2020-07-03 青岛歌尔智能传感器有限公司 心率模组的封装结构、封装方法及可穿戴设备
CN111370395B (zh) * 2020-03-24 2022-12-23 青岛歌尔智能传感器有限公司 心率模组的封装结构、封装方法及可穿戴设备
CN113497021A (zh) * 2020-04-07 2021-10-12 联发科技股份有限公司 半导体封装结构
CN112908868A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 存储器三维封装方法及结构
WO2023010555A1 (zh) * 2021-08-06 2023-02-09 华为技术有限公司 芯片封装结构及电子设备
CN115547852A (zh) * 2022-12-01 2022-12-30 合肥矽迈微电子科技有限公司 一种高功率芯片的半成品结构、器件及其封装工艺
CN115547852B (zh) * 2022-12-01 2023-03-07 合肥矽迈微电子科技有限公司 一种高功率芯片的半成品结构、器件及其封装工艺

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