TWI431759B - 可堆疊式功率mosfet、功率mosfet堆疊及其製備方法 - Google Patents

可堆疊式功率mosfet、功率mosfet堆疊及其製備方法 Download PDF

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TWI431759B
TWI431759B TW100113852A TW100113852A TWI431759B TW I431759 B TWI431759 B TW I431759B TW 100113852 A TW100113852 A TW 100113852A TW 100113852 A TW100113852 A TW 100113852A TW I431759 B TWI431759 B TW I431759B
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substrate
conductive
drain
source
gate
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TW100113852A
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TW201140800A (en
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Tao Feng
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Alpha & Omega Semiconductor
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Description

可堆疊式功率MOSFET、功率MOSFET堆疊及其製備方法
本發明主要關於一種半導體元件結構領域。更確切地說，本發明是關於一種製備功率半導體元件(例如功率金屬氧化物半導體場效電晶體(MOSFET)和絕緣閘雙極電晶體(IGBT))的可堆疊式晶片的元件結構和製備方法。
正如市場所需求的那樣，現今電子產品的主流趨勢就是，帶有極其豐富功能的產品的微型化。電力電子領域也具有同樣的趨勢。因此，在功率半導體元件領域中，仍然需要在滿足降低元件的內部電阻以及高效的熱耗散等功能要求的同時，做到產品微型化。
由於功率半導體元件的多個薄晶片具有在保持很小的封裝引線的同時，减小體型元件電阻的優勢，因此半導體行業急需製備和堆疊功率半導體元件的多個薄晶片。以下簡要概述了一些製備和堆疊多晶片的原有技術。
第1圖摘自SunWon KANG等人發明的題為《晶片堆疊封裝》美國專利公開號為20090108469的專利中的第2圖，該專利在下文中稱為US20090108469。如圖所示，US20090108469的晶片堆疊封裝500包括一個佈線的基板10、多個晶片100以及多個黏合層108，其中 晶片100藉由黏合層108相互堆疊並黏合在一起，利用一個晶圓級或晶片級製程，作為佈線基板10上的中間媒介。利用直通通孔電極102，晶片100相互電耦合，直通通孔電極102穿過晶片100形成，並且直通通孔電極102電耦合到佈線基板10上。晶片100形成在一個矽晶圓上，直通通孔電極102穿過矽晶圓形成。每個外部輸入/輸出(I/O)端110的形狀都與焊錫球類似，它們都形成在佈線基板10的底面上。每個黏合層108都是一個黏合帶。
第2圖摘自Yuui Shimizu發明的題為《能夠區分多個堆疊在同一封裝中的儲存器晶片的半導體儲存器》美國專利申請公開號為20090135638的專利中的第1圖，該專利在下文中稱為US20090135638。更確切地說，第2圖表示依據US20090135638的第一實施例，一種多晶片封裝結構儲存元件(半導體儲存元件)100結構的透視圖。將一個電阻值變化的儲存器元件用作儲存器單元，把四個電阻值變化的儲存器晶片(以下稱為儲存器晶片)111A至111D，堆疊在同一封裝中。本實施例的儲存元件100含有四個儲存器晶片111A至111D，它們連續堆疊在一個封裝基板101中。這四個儲存器晶片111A至111D都具有相同的結構(規格)，藉由堆疊，使它們作為一個整體，垂直地相互重叠起來。儲存器晶片111A至111D中的每一個晶片都帶有多個(在本實施例中為九個)墊121至129，以及一個晶片地址標識電路150。墊121至129中的墊121和122用作第一和第二儲存器的位置探測墊P1(Vtest)和P2(Vss)，以便分別識別晶片的地址。其他墊123至129分別用作輸入/輸出(I/O)、控制、電源(Vdd)和基態(Vss)墊。利用一個直通通孔(垂直通孔技術)103，將每個儲存器晶片 111A至111D的墊121至129相互連接起來。例如，示例中所示的墊121。直通通孔103連接在儲存器晶片111A的墊121和儲存器晶片111B的墊121之間，儲存器晶片111B的墊121和儲存器晶片111C的墊121之間，以及儲存器晶片111C的墊121和儲存器晶片111D的墊121之間。藉由最低的直通通孔103，儲存器晶片111A的墊121連接到封裝基板101上。下文更將詳述，每個儲存器晶片111A至111D的墊121至129都具有一個直通矽通孔結構(TSV)。根據這種直通矽通孔結構(TSV)，墊121至129在每個晶片的正面和背面上都有一個電極。第一和第二儲存器位置探測墊121(P1)和122(P2)短接起來。依據本實施例，藉由一個位於封裝基板101的表面上最低的直通通孔103之間的封裝框導線分佈圖131，將第一和第二儲存器位置探測墊121(P1)和122(P2)連接起來。更確切地說，利用八個直通通孔103以及一個導線分佈圖131，將儲存器晶片111A至111D的第一和第二儲存器位置探測墊121(P1)和122(P2)傳導起來。因此，從外部測試器(圖中沒有表示出)開始，在最高的儲存器晶片111D的第一和第二儲存器位置探測墊121(P1)上，加載測試電壓Vtest。儲存器晶片111D的第二儲存器位置探測墊122(P2)連接到基態(Vss)。藉由這種方式，電流從儲存器晶片111D的第一儲存器位置探測墊121(P1)，流至第二儲存器位置探測墊122(P2)。儘管本文沒有說明，但是在除了最高的儲存器晶片111D的墊121至129以外的周圍區域，封裝基板101上的儲存器晶片111A至111D都是利用樹脂等密封器進行密封的。
除了上述內容，以下原有技術也是關於直接晶片堆疊的： 美國專利：US5818107、US6002177、US7217995、US7446420、US7494909、US7507637、US7595559、US7598617。
美國專利申請公開：US20080157357、US20090032928、US20090209063、US20090261457、US20090001543、US20090065950、US20090160051、US20090020855。
雖然上述原有技術是關於僅僅具有頂部電極的橫向元件，但是並沒有表示出在頂部和底部都有電極的垂直半導體晶片(尤其是功率半導體元件)是如何堆疊的。鑒於上述原有技術，本發明提出了一種可堆疊式功率MOSFET結構，用於直接堆疊功率MOSFET元件(這些元件在頂部和底部都具有電極)，以便在有限的封裝引脚和尺寸中，獲得較高的使用性能。
第3A圖和第3B圖分別摘自Khalil Hosseini等人發明的題為《利用帶有表面可安裝的外部接頭的引線技術進行功率半導體零部件堆疊及其製備方法》美國專利申請公開號為20080150105的專利中的第3圖和第4圖，該專利在下文中稱為US20080150105。更確切地說，第3A圖表示一個並聯的MOSFET功率半導體零部件堆疊30的兩個MOSFET功率半導體零部件2和3的示意、帶開口的、透視圖，該並聯的MOSFET功率半導體零部件堆疊30如第3B圖所示。此時，在並聯的MOSFET功率半導體零部件堆疊的中間平面14中，兩個源極電極S一個接一個地安裝在一起，兩個閘極外部接頭G也同樣地相互校準在一起。對於並聯電路而言，中間平面14中的這兩個源極和兩個閘極外部接頭相互校準，並且藉由一個焊錫層，相互電連接。從而形成如第3B圖所示的MOSFET功率半導體零部件堆疊30。
第3B圖表示一種並聯的MOSFET功率半導體零部件堆疊30的示意透視圖，該並聯的MOSFET功率半導體零部件堆疊30在其頂部具有一個汲極外部接頭D、一個源極外部接頭S以及一個閘極外部接頭G。在這種情况下，閘極外部接頭G和源極外部接頭S，藉由中間平面14，向下循環到MOSFET功率半導體零部件堆疊30的下面5，同時在MOSFET功率半導體零部件堆疊30的頂部13上的汲極外部接頭D，利用導電帶32，以便將汲極外部接頭D從MOSFET功率半導體零部件堆疊30的頂部13，引導至MOSFET功率半導體零部件堆疊30的下面5的能級上。如果除了如第3圖所示的中間平面14上的源極外部接頭S和閘極外部接頭G之外，更提供相應的汲極外部接頭的話，那麽在串聯電路中，就可以省去導電帶32。
但是US20080150105僅說明了在封裝式零部件能級上堆疊MOSFET的方法。而且，並沒有說明如何輕鬆堆疊兩個以上的MOSFET零部件。
第4圖表示帶有多個交叉指型源極本體區23a~23i以及帶溝槽的閘極區24a~24j的傳統MOSFET 10，帶溝槽的閘極區24a~24j位於帶有底部汲極金屬層22的半導體基板21頂部。在本例中，半導體基板21可以由一個位於重摻雜的基板層21a上方的外延層21b。多個源極本體區23a~23i相互接觸，並聯到帶圖案的源極本體金屬層25c上。與之類似，儘管為了避免產生不必要的混淆，本文沒有詳述連接的具體細節，但是帶溝槽的閘極區24a~24j是相互接觸的，並聯到頂部鈍化物29下方的帶圖案的閘極金屬層26h上。要注意的是，頂部源極金屬25c和底部汲極金屬22位於半導體元件的對邊，這使得堆疊這種元件非常困難，尤其是在使用了直通通 孔時。
本發明提出了一種可堆疊式垂直功率MOSFET元件。這種可堆疊式垂直功率MOSFET具有超薄的厚度，並且包括：一形成在它上面的帶有底部汲極金屬層之半導體基板。作為示例，半導體基板本身可以含有一上部輕摻雜之漂流層及一下部重摻雜之接觸層，以便接觸汲極金屬層。
多個形成在半導體基板上方的交叉指型之帶有溝槽之閘極區和源極本體區。
一帶圖案之閘極金屬層和一帶圖案之源極本體金屬層，它們分別接觸帶溝槽之閘極區和源極本體區。
下列項目中的至少一個：
a.一導電直通基板汲極通孔(TSDV)，穿過半導體基板，並與汲極金屬層接觸。該導電直通基板汲極通孔具有一頂部汲極接觸墊和一底部汲極接觸墊，分別在頂面和底面電接觸到導電直通基板汲極通孔上。相應地，每個位於導電直通基板汲極通孔附近之源極本體區，都帶有一距離導電直通基板汲極通孔足夠遠之源極本體切斷剖面，以承載它們之間的汲極源極電壓。
b.一導電直通基板閘極通孔(TSGV)，穿過半導體基板，並與閘極金屬層接觸。該導電直通基板閘極通孔具有一頂部閘極接觸墊和一底部閘極接觸墊，分別在頂面和底面電接觸到導電直通基板閘極通孔上。
c.一導電直通基板源極通孔(TSSV)，穿過半導體基板，並與源極本體金屬層接觸。導電直通基板源極通孔具有一頂部源極接觸墊和一底部源極接觸墊，分別在頂面和底面電接觸到導電直通基板源極通孔上。
一旦多個可堆疊式垂直功率MOSFET元件一個壓一個地向上堆疊並黏合起來，所形成的可堆疊式垂直功率MOSFET堆疊就會起堆疊式MOSFET元件的並聯導電連接的作用，從而降低了導通電阻Rds、增大了載流能力、减少了封裝引脚並縮小了封裝高度。此外，可堆疊式垂直功率MOSFET堆疊也可以與各種封裝零部件一同封裝，以便將堆疊與其外部的作業環境互聯起來。
在一個較詳細的實施例中，導電直通基板汲極通孔、導電直通基板閘極通孔和導電直通基板源極通孔在它們各自的可堆疊式垂直功率MOSFET單元的主元件平面內，都設置在恰當的位置，因此，一旦將它們堆疊起來：可堆疊式垂直功率MOSFET單元之頂部汲極接觸墊和底部汲極接觸墊就會分別與它們相鄰的可堆疊式垂直功率MOSFET單元的底部汲極接觸墊和頂部汲極接觸墊對齊。
可堆疊式垂直功率MOSFET單元之頂部閘極接觸墊和底部閘極接觸墊就會分別與它們相鄰的可堆疊式垂直功率MOSFET單元的底部閘極接觸墊和頂部閘極接觸墊對齊。
可堆疊式垂直功率MOSFET單元之頂部源極接觸墊和底部源極接觸墊就會分別與它們相鄰的可堆疊式垂直功率MOSFET單元的底部源極接觸墊和頂部源極接觸墊對齊。
在一個較典型的實施例中，可堆疊式垂直功率MOSFET元件厚度約為5微米至100微米。
在一個較典型的實施例中，每一導電直通基板汲極通孔、導電直通基板閘極通孔和導電直通基板源極通孔都用銅或一種金屬填充，並且都有一通孔絕緣層包圍著，從而使它與半導體基板絕緣。 該通孔絕緣層可以由一種半導體氧化物、氮化物或一種聚合物材料製成。更可選擇，每一導電直通基板汲極通孔、導電直通基板閘極通孔和導電直通基板源極通孔都以銅或一種金屬製成的空心殼體的形式製備。
本發明更提出了一種封裝的多單元可堆疊式垂直功率MOSFET堆疊的製備方法，該封裝的多單元可堆疊式垂直功率MOSFET堆疊具有多個可堆疊式垂直功率MOSFET單元一個壓一個地向上黏合，並且相互並聯。該方法包括：製備多個可堆疊式垂直功率MOSFET單元。
可堆疊式垂直功率MOSFET單元一個壓一個地向上堆疊並黏合，以構成帶有由導電直通基板汲極通孔、導電直通基板閘極通孔和導電直通基板源極通孔實現的並聯連接的多單元可堆疊式垂直功率MOSFET堆疊。
將該堆疊與其外部作業環境互聯。
在一個較典型的實施例中，其中每一可堆疊式垂直功率MOSFET單元都具有超薄的厚度，以便减小多單元可堆疊式垂直功率MOSFET堆疊的相應的厚度以及導通電阻Rds，製備每一可堆疊式垂直功率MOSFET單元包括： 一原始厚度之基板晶圓上，製備可堆疊式垂直功率MOSFET單元的頂部，在基板晶圓上方連接一臨時之晶圓承載元件。
將基板晶圓之底部减薄至所需的超薄厚度，平行製備以下項目：
a.導電直通基板汲極通孔加上其底部汲極接觸墊、導電直通基板閘極通孔加上其底部閘極接觸墊、導電直通基板源極通孔加上其底部源極接觸墊。
除去臨時之晶圓承載元件。
在上述內容中，製備可堆疊式垂直功率MOSFET之頂部部分包括，在需要導電直通基板汲極通孔的位置處將源極本體金屬層分段，並在上面製備頂部汲極接觸墊。而且，製備導電直通基板汲極通孔加上其底部汲極接觸墊包括：製備底部汲極金屬層，並在需要導電直通基板汲極通孔的位置處打開它。
一起製備導電直通基板汲極通孔及其底部汲極接觸墊，使導電直通基板汲極通孔與半導體基板以及汲極金屬層絕緣，同時，與頂部汲極接觸墊以及底部汲極接觸墊接觸。
在一個較詳細的實施例中，並行製備導電直通基板汲極通孔加上其底部汲極接觸墊、導電直通基板閘極通孔加上其底部閘極接觸墊、導電直通基板源極通孔加上其底部源極接觸墊包括：製備底部汲極金屬層，並在需要導電直通基板漏極通孔、導電直通基板閘極通孔和導電直通基板源極通孔的不同位置處打開它。
同時製備以下項目：
a.一起製備導電直通基板汲極通孔及其底部汲極接觸墊，使導電直通基板汲極通孔與半導體基板以及汲極金屬層絕緣，同時，與頂部汲極接觸墊以及底部汲極接觸墊接觸。
b.一起製備導電直通基板閘極通孔及其底部閘極接觸墊，使導電直通基板閘極通孔與半導體基板以及汲極金屬層絕緣，同時，與頂部閘極接觸墊以及底部閘極接觸墊接觸。
c.一起製備導電直通基板源極通孔及其底部源極接觸墊，使導電直通基板源極通孔與半導體基板以及汲極金屬層絕緣，同時，與頂部源極接觸墊以及底部源極接觸墊接觸。
在一個較詳細的實施例中，一起製備導電直通基板汲極通孔加上其底部汲極接觸墊包括：在汲極金屬層上沉積汲極金屬鈍化物，並形成圖案，同時包圍著需要導電直通基板汲極通孔的位置。
帶開口之汲極金屬層和帶圖案之汲極金屬鈍化物作為遮罩，穿過半導體基板定向刻蝕，以製成一直通基板隧道，觸及分段之源極本體金屬層，但受到分段之源極本體金屬層的限制。
在直通基板隧道內部，製備導電直通基板漏極通孔，以及在汲極金屬層和汲極金屬鈍化物上製備底部汲極接觸墊。這更需要：
a.在半導體基板之底部上方和直通基板隧道之裸露表面，沉積一通孔絕緣層。
b.定向刻蝕掉通孔絕緣層之所有的水平導向層，以便裸露出分段 之源極本體金屬層和汲極金屬層。
c.用導電通孔材料，過填充直通基板隧道和帶圖案之汲極金屬鈍化物。
d.將導電通孔材料之底部形成圖案，以製成底部汲極接觸墊。
在上述內容中，製備可堆疊式垂直功率MOSFET頂部部分包括，在閘極金屬層上方製備頂部閘極接觸墊。而且，製備導電直通基板閘極通孔加上其底部閘極接觸墊包括：製備底部汲極金屬層，並在需要導電直通基板閘極通孔的位置處打開它。
一起製備導電直通基板閘極通孔及其底部閘極接觸墊，使導電直通基板閘極通孔與半導體基板以及汲極金屬層絕緣，同時，與頂部閘極接觸墊以及底部閘極接觸墊接觸。
在一個較詳細的實施例中，一起製備導電直通基板閘極通孔加上其底部閘極接觸墊包括：在汲極金屬層上沉積汲極金屬鈍化物，並形成圖案，同時包圍著需要導電直通基板閘極通孔的位置。
以帶開口之汲極金屬層和帶圖案之汲極金屬鈍化物作為遮罩，穿過半導體基板定向刻蝕，以製成一直通基板隧道，觸及閘極金屬層，但受到閘極金屬層的限制。
在直通基板隧道內部製備導電直通基板閘極通孔，以及在汲極金屬層和汲極金屬鈍化物上製備底部閘極接觸墊。這更需要：
a.在半導體基板之底部上方和直通基板隧道之裸露表面，沉積一通孔絕緣層。
b.直接刻蝕掉通孔絕緣層之所有的水平導向層，以便裸露出閘極金屬層。
c.用導電通孔材料，過填充直通基板隧道和帶圖案之汲極金屬鈍化物。
d.將導電通孔材料之底部形成圖案，以製成底部閘極接觸墊。
在上述內容中，製備可堆疊式垂直功率MOSFET頂部部分包括，在需要導電直通基板源極通孔的位置處之源極本體金屬層上方，製備頂部源極接觸墊。而且，製備導電直通基板源極通孔加上其底部源極接觸墊包括：製備底部汲極金屬層，並在需要導電直通基板源極通孔的位置處打開它。
一起製備導電直通基板源極通孔及其底部源極接觸墊，使導電直通基板源極通孔與半導體基板以及汲極金屬層絕緣，同時，與頂部源極接觸墊以及底部源極接觸墊接觸。
在一個較詳細的實施例中，一起製備導電直通基板源極通孔加上其底部源極接觸墊包括：在汲極金屬層上沉積汲極金屬鈍化物，並形成圖案，同時包圍著需要導電直通基板源極通孔的位置。
以帶開口之汲極金屬層和帶圖案之汲極金屬鈍化物作為遮罩，穿過半導體基板定向刻蝕，以製成一直通基板隧道，觸及源極本體 金屬層，但受到源極本體金屬層的限制。
在直通基板隧道內部，以及在汲極金屬層和汲極金屬鈍化物上之底部源極接觸墊中，製備導電直通基板源極通孔。這更需要：
a.在半導體基板之底部上方和直通基板隧道之裸露表面，沉積一通孔絕緣層。
b.直接刻蝕掉通孔絕緣層之所有的水平導向層，以便裸露出源極本體金屬層。
c.用導電通孔材料，過填充直通基板隧道和帶圖案之汲極金屬鈍化物。
d.將導電通孔材料之底部形成圖案，以製成底部源極接觸墊。
對於底部可堆疊式可堆疊式垂直功率MOSFET單元的特殊情况，减薄基板晶圓之底部並製備導電直通基板汲極通孔加上其底部汲極接觸墊包括：在需要導電直通基板汲極通孔的位置處，打開源極本體金屬層。
一起製備部分直通基板汲極通孔(PTSDV)及其頂部汲極接觸墊，使得：
a.部分導電直通基板汲極通孔與半導體基板絕緣。
b.部分導電直通基板汲極通孔之一部分進入基板晶圓中，但部分導電直通基板汲極通孔之底部將縮短至稍後基板晶圓之减薄處。
將基板晶圓之底部减薄至所需的超薄厚度，同時裸露出縮短的部分導電直通基板汲極通孔底部，從而製成導電直通基板汲極通孔 。
在基板晶圓上方製備底部汲極金屬層。
對於本領域的技術人員，閱讀本說明的以下內容後，本發明的這些方面及其多個實施例將顯而易見。
2、3‧‧‧MOSFET功率半導體零部件
5‧‧‧下面
10‧‧‧基板
13‧‧‧頂部
14‧‧‧中間平面
20、301‧‧‧MOSFET
21‧‧‧半導體基板
21a‧‧‧基板層
21b‧‧‧外延層
22‧‧‧底部汲極金屬
22a、22b、22c、22d‧‧‧汲極金屬元件
23a、23b、23c、23d、23e、23f、23g、23h、23i‧‧‧源極本體區
24、28、48‧‧‧導電直通基板汲極通孔
24a、24b、24c、24d、24e、24f、24g、24h、24i、24j‧‧‧閘極區
25a、25c‧‧‧源極本體金屬層
26、46‧‧‧導電直通基板源極通孔
26a、26b‧‧‧頂部源極接觸墊
26h‧‧‧閘極金屬層
27、47‧‧‧導電直通基板閘極通孔
27a、27b‧‧‧頂部閘極接觸墊
28a‧‧‧頂部汲極接觸墊
28b‧‧‧底部汲極接觸墊
29‧‧‧頂部鈍化物
29a、29b、29c、29d‧‧‧頂部鈍化元件
30‧‧‧MOSFET功率半導體零部件堆疊
30a、30b、30c、30d‧‧‧汲極金屬鈍化物元件
31、32、33‧‧‧通孔絕緣層
34‧‧‧鈍化層
35‧‧‧源極本體金屬
36‧‧‧源極本體切斷結構
38、40‧‧‧空殼導電內核
100‧‧‧晶片
101‧‧‧封裝基板
102‧‧‧直通通孔電極
103‧‧‧直通通孔
108‧‧‧黏合層
110‧‧‧輸入/輸出(I/O)端
111A、111B、111C、111D‧‧‧儲存器晶片
121(P1)、122(P2)、123、124、125、126、127、128、129‧‧‧墊
130‧‧‧通孔絕緣層
131‧‧‧封裝框導線分佈圖
132‧‧‧導電通孔材料
134‧‧‧溝槽
138‧‧‧部分導電直通基板汲極通孔
150‧‧‧晶片地址標識電路
300、400、600‧‧‧可堆疊式垂直功率MOSFET堆疊
302、302a、402、602‧‧‧可堆疊式垂直功率MOSFET 2
352、354‧‧‧等效電路圖
401、601‧‧‧可堆疊式垂直功率MOSFET 1
403、603‧‧‧可堆疊式垂直功率MOSFET 3
500‧‧‧多單元功率MOSFET堆疊
502‧‧‧引線框
504‧‧‧晶片接合材料
506‧‧‧接合板
604‧‧‧可堆疊式垂直功率MOSFET 4
FET 1、FET 2、FET 3、FET 4‧‧‧可堆疊式垂直功率MOSFET單元
S‧‧‧源極外部接頭
G‧‧‧閘極外部接頭
T‧‧‧厚度
為了更加完整地說明本發明的各種實施例，可參照圖式。但是，這些圖式僅用作解釋說明，並不作為本發明範圍的侷限。
第1圖 摘自原有技術US20090108469；第2圖 摘自原有技術US20090135638；第3A圖和第3B圖 摘自原有技術US20080150105；第4圖 表示一種傳統的多溝槽功率MOSFET；第5圖 表示本發明所述之帶有導電直通基板源極通孔、導電直通基板閘極通孔以及導電直通基板汲極通孔之第一實施例可堆疊式垂直功率MOSFET；6A圖 表示本發明所述之帶有導電直通基板源極通孔以及導電直通基板閘極通孔之第二實施例可堆疊式垂直功率MOSFET；第6B圖 表示本發明所述之帶有導電直通基板汲極通孔之第三實施例可堆疊式垂直功率MOSFET；第6C圖 表示除了直通基板通孔的內部結構的變化之外，其他都與第6A圖之第二實施例類似的本發明所述之第四實施例可堆疊式垂直功率MOSFET；第6D圖 表示本發明之第五實施例，即兩可堆疊式垂直功率MOSFET單元之堆疊；第7A圖 表示對應第6D圖所示之兩重可堆疊式垂直功率MOSFET堆 疊之等效電路圖；第7B圖 表示對應由本發明所述之四個可堆疊式垂直功率MOSFET單元製成的四重可堆疊式垂直功率MOSFET堆疊之等效電路圖；第8圖 表示本發明之第六實施例，即三個可堆疊式垂直功率MOSFET單元之堆疊；第9A圖至第9F圖表示本發明所述之廣義三重可堆疊式垂直功率MOSFET堆疊的獨立可堆疊式垂直功率MOSFET單元之頂部和底部示意圖，該結構帶有大量分別並聯的直通基板源極通孔和直通基板汲極通孔；第10A圖 表示本發明所述之四重可堆疊式垂直功率MOSFET堆疊之部分源極接觸墊、閘極接觸墊、汲極接觸墊、直通基板源極通孔、直通基板閘極通孔以及直通汲極通孔之立體透視圖；第10B圖 表示本發明所述之四重可堆疊式垂直功率MOSFET堆疊的部分源極接觸墊、閘極接觸墊、直通基板源極通孔以及直通基板閘極通孔之立體透視圖；第10C圖 表示本發明所述之四重可堆疊式垂直功率MOSFET堆疊的部分汲極接觸墊以及直通汲極通孔之立體透視圖；第10D圖 表示同引線框和連接板一起封裝之四重可堆疊式垂直功率MOSFET堆疊之剖面圖；第11A圖至第11M圖 表示製備第8圖所示之三重可堆疊式垂直功率MOSFET堆疊的中間的可堆疊式垂直功率MOSFET單元之詳細製程流程；以及第12A圖至第12G圖表示製備第8圖所示之三重可堆疊式垂直功率MOSFET堆疊的底部的可堆疊式垂直功率MOSFET單元之詳細製程流程。
本文所含的上述及以下說明和圖式僅用於說明本發明的一個或多個現有的較佳實施例，以及一些典型的可選件和/或可選實施例。說明及圖式用於解釋說明，就其本身而言，並不侷限本發明。因此，本領域的技術人員將輕鬆掌握各種改動、變化和修正。這些改動、變化和修正也應認為屬於本發明的範圍。
參閱第5圖表示本發明所述之可堆疊式功率溝槽MOSFET 20之第一實施例。除了與傳統的功率溝槽MOSFET 10(與第4圖和第5圖相比較)的那些零部件相同之外，本發明所述之可堆疊式垂直功率MOSFET 20的顯著特點是，具有導電直通基板源極通孔(TSSV)26、導電直通基板閘極通孔(TSGV)27以及導電直通基板汲極通孔(TSDV)28。傳統的功率溝槽MOSFET 10的典型厚度約為200微米，與之相反，本發明所述之可堆疊式垂直功率MOSFET 20具有超薄的厚度TSVP，例如，其範圍約為5微米至100微米。更確切地說，與傳統的功率溝槽MOSFET 10相同的零部件包括以下內容：
a.半導體基板21，底部汲極金屬層22形成在上面。作為一個更加詳細的示例，半導體基板21可以由一上部輕摻雜的漂流層21b和一下部重摻雜之接觸層21a製成，以便接觸底部汲極金屬層22並支撑半導體元件。
b.多個相互間隔知溝槽閘極區24a~24g和閘極滑道24j，以及形成在半導體基板21上方的源極本體區23a~23g。
c.一帶圖案的閘極金屬層26h，接觸溝槽閘極區24a~24g和閘極滑道24j，以及帶圖案的源極本體金屬層25a、25c，接觸源極本體 區23a~23g。源極本體金屬層25a和25c在立體空間上相互連接。
然而，與本發明所述之可堆疊式垂直功率MOSFET 20不同的零部件包括以下內容：
a.穿過半導體基板21並與底部汲極金屬層22相接觸的導電直通基板汲極通孔(TSDV)28。該導電直通基板汲極通孔28具有一頂部汲極接觸墊28a以及一底部汲極接觸墊28b，分別用於將頂面和底面電接觸到導電直通基板汲極通孔28上。要注意的是，頂面電接觸到導電直通基板汲極通孔28上，是藉由一分段的源極本體金屬35，分段的源極本體金屬35與帶圖案的源極本體金屬層25a和25c分開。為了清楚說明導電直通基板汲極通孔28，位於導電直通基板汲極通孔28附近的源極本體區23b和23c都帶有源極本體切斷結構36，這些結構距離導電直通基板汲極通孔28足夠遠，以便當本發明所述之可堆疊式垂直功率MOSFET 20工作時，承載它們之間的汲源電壓。
b.穿過半導體基板21並與帶圖案的閘極金屬層26h相接觸之導電直通基板閘極通孔(TSGV)27。該導電直通基板閘極通孔27具有一頂部閘極接觸墊27a以及一底部閘極接觸墊27b，分別用於將頂面和底面電接觸到導電直通基板閘極通孔27上。
c.穿過半導體基板21並與帶圖案的源極本體金屬層25c相接觸的導電直通基板源極通孔(TSSV)26。該導電直通基板源極通孔26具有一頂部源極接觸墊26a以及一底部源極接觸墊26b，分別用於將頂面和底面電接觸到導電直通基板源極通孔26上。
d.每一頂部汲極接觸墊28a、頂部閘極接觸墊27a、頂部源極接觸 墊26a的周圍，都藉由頂部鈍化物29，與下面的元件結構分開。而且，除了在底部汲極接觸墊28b和底部汲極金屬層22之間直接接觸之外，每一底部閘極接觸墊27b、底部源極接觸墊26b都藉由汲極金屬鈍化物30，與底部汲極金屬層22分開。
作為一個較典型的實施例，每一導電直通基板汲極通孔28、導電直通基板閘極通孔27和導電直通基板源極通孔26都用鎢或銅、或一般金屬填充。導電直通基板汲極通孔28具有一汲極通孔絕緣層33包圍著它，使它與半導體基板21絕緣。與之類似，導電直通基板閘極通孔27具有一閘極通孔絕緣層32包圍著它，使它與半導體基板21絕緣，導電直通基板源極通孔26具有一源極通孔絕緣層31包圍著它，使它與半導體基板21絕緣。通孔絕緣層33、32、31可以由半導體氧化物、氮化物或聚合材料製成。
參閱第6A圖表示本發明所述之帶有導電直通基板源極通孔26和導電直通基板閘極通孔27之第二實施例可堆疊式垂直功率MOSFET 2 302。該導電直通基板源極通孔26具有一頂部源極接觸墊26a以及一底部源極接觸墊26b，分別用於將頂面和底面電接觸到導電直通基板源極通孔26上。該導電直通基板閘極通孔27具有一頂部閘極接觸墊27a以及一底部閘極接觸墊27b，分別用於將頂面和底面電接觸到導電直通基板閘極通孔27上。為了將底面僅僅電接觸到底部汲極金屬層22上，該可堆疊式垂直功率MOSFET 2 302具有一不帶有導電直通基板汲極通孔的底部汲極接觸墊28b。在堆疊式元件中，可堆疊式垂直功率MOSFET 2 302可以位於堆疊的頂部。
參閱第6B圖表示本發明所述之僅僅帶有與底部汲極金屬層22直接 接觸的導電直通基板汲極通孔28，不帶有底部汲極接觸墊之第三實施例可堆疊式垂直功率MOSFET 1 301。該導電直通基板汲極通孔28具有一頂部汲極接觸墊28a，用於將頂面電接觸到導電直通基板汲極通孔28上。為了將頂面電接觸到帶圖案的源極本體金屬層25c上，該可堆疊式垂直功率MOSFET 1 301具有一不帶有導電直通基板源極通孔的頂部源極接觸墊26a。為了將頂面僅僅電接觸到帶圖案的閘極金屬層26h上，該可堆疊式垂直功率MOSFET 1 301具有一不帶有導電直通基板閘極通孔的頂部閘極接觸墊27a。在堆疊式元件中，可堆疊式垂直功率MOSFET 1 301可以位於堆疊之底部。
參閱第6C圖表示本發明所述之可堆疊式垂直功率MOSFET 2 302a之第四實施例，其中直通基板通孔的內部結構發生了變化，不再是實心導電內核，取而代之的是導電直通基板閘極通孔27具有一空殼導電內核40加上閘極通孔絕緣層32，導電直通基板源極通孔26具有一空殼導電內核38加上源極通孔絕緣層31，除此之外都與第6A圖所示之可堆疊式垂直功率MOSFET 2 302之第二實施例相類似。空殼導電內核40與空殼導電內核38可以由鎢、銅或其他金屬製成。因此，空殼導電內核40是一導電層，穿過閘極通孔絕緣層32，遍佈在導電直通基板閘極通孔27的側壁上。雖然空殼導電內核所具有的電阻高於同種材料製成的實心導電內核的電阻，但是只要空殼導電內核電阻仍遠低於可堆疊式垂直功率MOSFET 2 302a的元件內部電阻，就仍然可以維持較低的直通基板電阻。在這種情况下，空殼導電內核的優勢在於，减少材料消耗，降低內在的材料應力，在某些情况下，比其他實心導電內核更加易於製 備。
參閱第6D圖表示兩重可堆疊式垂直功率MOSFET堆疊300之第五實施例，這兩堆疊是第6B圖所示之兩可堆疊式垂直功率MOSFET單元可堆疊式垂直功率MOSFET 1 301以及第6A圖所示之可堆疊式垂直功率MOSFET 2 302。此時，導電直通基板汲極通孔28、導電直通基板閘極通孔27以及導電直通基板源極通孔26在它們各自可堆疊式垂直功率MOSFET單元的主元件平面(XY平面)內適當地設置，從而在它們的堆疊上：
a.可堆疊式垂直功率MOSFET 1 301的頂部汲極接觸墊28a與可堆疊式垂直功率MOSFET 2 302的底部汲極接觸墊28b排成直線。
b.可堆疊式垂直功率MOSFET 1 301的頂部源極接觸墊26a與可堆疊式垂直功率MOSFET 2 302的底部源極接觸墊26b排成直線。
c.可堆疊式垂直功率MOSFET 1 301的頂部閘極接觸墊27a與可堆疊式垂直功率MOSFET 2 302的底部閘極接觸墊27b排成直線。
第7A圖表示兩並聯MOSFET等效電路圖352，對應第6D圖所示之兩重可堆疊式垂直功率MOSFET堆疊300。要注意的是，儘管這兩可堆疊式垂直功率MOSFET單元FET 1和FET 2(第6D圖中的可堆疊式垂直功率MOSFET 1 301和可堆疊式垂直功率MOSFET 2 302)是並聯的，但是所有物理互聯的元件都表現出在FET 1和FET 2之間的寄生互聯電阻的有限量。例如，寄生汲極互聯電阻Rdv來自於可堆疊式垂直功率MOSFET 1 301的導電直通基板汲極通孔28。又例如，寄生閘極互聯電阻Rgv來自於可堆疊式垂直功率MOSFET 2 302的導電直通基板閘極通孔27。再例如，寄生源極互聯電阻Rsv 來自於可堆疊式垂直功率MOSFET 2 302的導電直通基板源極通孔26。第7B圖表示四個並聯MOSFET等效電路圖354，對應由本發明所述之四個可堆疊式垂直功率MOSFET單元(FET 1、FET 2、FET 3、FET 4)製成的四重可堆疊式垂直功率MOSFET堆疊。由於獨立的可堆疊式垂直功率MOSFET的各個直通基板通孔的寄生互聯電阻都對總電阻有貢獻，因此相應的互聯電阻就會隨堆疊可堆疊式垂直功率MOSFET單元數量的增加而增大。
因此，本發明提出的另一個重要思想是，製備多重並聯的直通基板通孔，以降低互聯電阻，這在下文將作詳細介紹。另外，也可以藉由用金屬等高導電率材料製備直通通孔，來降低通孔電阻(例如Rsv)。在這些電路中，當路由信號從閘極墊到閘極溝槽電極傳輸時，所有的MOSFET中都有內部閘極電阻Rg。
參閱第8圖表示三重可堆疊式垂直功率MOSFET堆疊400之第六實施例，即三個可堆疊式垂直功率MOSFET單元可堆疊式垂直功率MOSFET 1 401、可堆疊式垂直功率MOSFET 2 402以及可堆疊式垂直功率MOSFET 3 403的堆疊。可堆疊式垂直功率MOSFET 1 401對應第6B圖所示之可堆疊式垂直功率MOSFET 301，可堆疊式垂直功率MOSFET 3 402對應第5圖所示之可堆疊式垂直功率MOSFET 20，可堆疊式垂直功率MOSFET 3 403對應第6A圖所示之可堆疊式垂直功率MOSFET 302。此時，導電直通基板汲極通孔28、導電直通基板閘極通孔27以及導電直通基板源極通孔26在它們各自可堆疊式垂直功率MOSFET單元的主元件平面(XY平面)內適當地設置，從而在它們的堆疊上：
a.可堆疊式垂直功率MOSFET 1 401的頂部汲極接觸墊28a與可堆 疊式垂直功率MOSFET 2 402的底部汲極接觸墊28b排成直線；可堆疊式垂直功率MOSFET 2 402的頂部汲極接觸墊28a與可堆疊式垂直功率MOSFET 3 403的底部汲極接觸墊28b排成直線。
b.可堆疊式垂直功率MOSFET 1 401的頂部源極接觸墊26a與可堆疊式垂直功率MOSFET 2 402的底部源極接觸墊26b排成直線；可堆疊式垂直功率MOSFET 2 402的頂部源極接觸墊26a與可堆疊式垂直功率MOSFET 3 403的底部源極接觸墊26b排成直線。
c.可堆疊式垂直功率MOSFET 1 401的頂部閘極接觸墊27a與可堆疊式垂直功率MOSFET 2 402的底部閘極接觸墊27b排成直線；可堆疊式垂直功率MOSFET 2 402的頂部閘極接觸墊27a與可堆疊式垂直功率MOSFET 3 403的底部閘極接觸墊27b排成直線。
然而，可堆疊式垂直功率MOSFET 3 403的導電直通基板源極通孔(導電直通基板源極通孔)46的頂部源極接觸墊26a，用於外部源極接觸到三重可堆疊式垂直功率MOSFET堆疊400上。同樣地，可堆疊式垂直功率MOSFET 3 403的導電直通基板閘極通孔(導電直通基板閘極通孔)47的頂部源極接觸墊27a，用於外部源極接觸到三重可堆疊式垂直功率MOSFET堆疊400上。
至此，本領域的技術人員應明確，只要各種頂部和底部接觸墊(26a、26b、27a、27b、28a、28b)用於可堆疊式垂直功率MOSFET堆疊的作用相同，例如突起和多個球形接頭，那麽就可以其他形式實現它們。這些接觸墊可以由銅、金屬和/或用於銅銅直接接合或焊錫焊錫接合的焊錫材料製成。然而，對於底部可堆疊式垂直功率MOSFET 1 401而言，在導電直通基板汲極通孔(導電直通 基板汲極通孔)48底部的底部汲極金屬層22，已經用作外部接頭。
如上所述，本發明的一個重要方面在於，製備多個並聯的直通基板通孔，以降低總互聯電阻，如第9A圖至第9F圖所示，類似於第8圖所示之堆疊400的一種一般的三重可堆疊式垂直功率MOSFET堆疊。第9A圖和第9B圖分別表示其頂部可堆疊式垂直功率MOSFET單元之頂面和底面示意圖。第9C圖和第9D圖分別表示其中部可堆疊式垂直功率MOSFET單元之頂面和底面示意圖。第9E圖和第9F圖分別表示其底部可堆疊式垂直功率MOSFET單元之頂面和底面示意圖。因此，第9A圖表示頂部閘極接觸墊27a和頂部源極接觸墊26a。第9B圖、第9C圖、第9D圖和第9E圖表示在平行於XY平面之頂部和底部視圖中，一導電直通基板閘極通孔27，23個導電直通基板汲極通孔28以及24個導電直通基板源極通孔26相互間隔的陣列，第9F圖表示底部可堆疊式垂直功率MOSFET單元之底部汲極金屬層22。這23個導電直通基板汲極通孔28藉由每一可堆疊式垂直功率MOSFET單元的底部汲極金屬層22並聯，同時，這24個導電直通基板源極通孔26藉由每一可堆疊式垂直功率MOSFET單元的頂部源極接觸墊26a以及頂部源極金屬(圖中沒有表示出)並聯。雖然，這種並聯體系也可適用於直通基板閘極通孔，但是在本例中卻並沒有採用，這是由於MOSFET元件的閘極電流明顯遠低於汲極和源極電極的電流，因此一單獨的閘極通孔就已足夠了。源極和汲極通孔相互間隔，使得直通基板連接無需將源極短接至汲極，就可以降低橫嚮導通電阻。實際上，將多個本發明所述之具有一個挨一個地相互間隔的直通通孔的超薄可堆疊式垂直功率MOSFET元件 堆疊並接合起來，所形成的可堆疊式垂直功率MOSFET堆疊作為堆疊式可堆疊式垂直功率MOSFET元件的並聯連接，可相應地减少導通電阻Rds，降低電流承載能力，减少封裝引脚，並且封裝高度與以前相同。源極和汲極直通通孔在整個晶片上相互間隔，使得直通基板連接無需將源極短接至汲極，就能降低橫嚮導通電阻。
參閱第10A圖至第10C圖表示對於由可堆疊式垂直功率MOSFET 1 601、可堆疊式垂直功率MOSFET 2 602、可堆疊式垂直功率MOSFET 3 603以及可堆疊式垂直功率MOSFET 4 604(每一都帶有各自的頂部源極接觸墊26a和底部汲極接觸墊28b)製成的一種一般的四重可堆疊式垂直功率MOSFET堆疊600，利用多個並聯的直通基板通孔另一示例之立體透視圖，以便降低總互聯電阻以及傳導電阻。閘極連接是藉由四個頂部閘極接觸墊27a製成的，頂部閘極接觸墊27a連接有一單獨的導電直通基板閘極通孔(TSGV)47。為了表示清晰，第10A圖僅僅表示四重可堆疊式垂直功率MOSFET堆疊600的部分源極接觸墊、閘極接觸墊、汲極接觸墊、直通基板源極通孔、直通基板閘極通孔以及直通基板汲極通孔。因此，並聯的導電直通基板汲極通孔是48，並聯的導電直通基板源極通孔是46。同樣地，為了表示清晰，第10B圖僅僅表示四重可堆疊式垂直功率MOSFET堆疊600的部分源極接觸墊、閘極接觸墊、直通基板源極通孔、直通基板閘極通孔。同樣地，為了表示清晰，第10C圖僅僅表示四重可堆疊式垂直功率MOSFET堆疊600的部分汲極接觸墊和直通基板通孔。要注意的是，導電直通基板源極通孔46可以無需接觸，就能穿過汲極接觸墊28b，同樣地，導電直通基板汲極通孔48也可以無需接觸，就能穿過源極接觸墊 26a。因此，可以形成相互間隔的源極和汲極通孔，以便分別並聯堆疊式MOSFET的源極和汲極，並且無需將源極短接至汲極，就能降低傳導電阻。
參閱第10D圖表示封裝的多單元功率MOSFET堆疊500之剖面圖，其中封裝第10A圖所示之四重可堆疊式垂直功率MOSFET堆疊600，用作帶有引線框502和接合板506(如美國申請11/906,136所述)的外部運行環境。然而，四重可堆疊式垂直功率MOSFET堆疊600可以藉由引線框502上方的晶片接合材料504(例如焊錫或導電環氧樹脂)接合起來，引線框502可以用印刷電路板(PCB)或普通的多層電路層壓板等其他類型的電路基板代替。同樣地，接合板506可以用接合線等其他封裝元件代替。另外地，儘管在此沒有詳述，封裝的多單元功率MOSFET堆疊500也可以用成型混料密封。如上所述，傳統的MOSFET 10的典型厚度約為200微米，與之相反，本發明所述之每一可堆疊式垂直功率MOSFET單元(可堆疊式垂直功率MOSFET 1 601、可堆疊式垂直功率MOSFET 2 602、可堆疊式垂直功率MOSFET 3 603、可堆疊式垂直功率MOSFET 4 604)的超薄厚度TSVP約為5微米至100微米。因此，封裝的多單元功率MOSFET堆疊500的優點在於，與之前相同封裝高度下的小封裝引脚，極其低的Rdson。另一優勢在於，多個並聯的導電直通基板汲極通孔48和導電直通基板源極通孔46用於將橫向電流(平行於XY平面)侷限在每一MOSFET的源極金屬和汲極金屬內。這將降低相關的傳導電阻。
參閱第11A圖至第11M圖表示製備第8圖所示之三重可堆疊式垂直功率MOSFET堆疊400的中間可堆疊式垂直功率MOSFET單元可堆疊 式垂直功率MOSFET 2 402(也可參見第5圖所示之可堆疊式垂直功率MOSFET單元20)之詳細製程流程。由該製程可知，從第11A圖至第11E圖表示在一原始厚度的基板晶圓上，製備可堆疊式垂直功率MOSFET 2 402的頂部，無需以下內容：導電直通基板汲極通孔加上其底部汲極接觸墊、導電直通基板閘極通孔加上其底部閘極接觸墊、導電直通基板源極通孔加上其底部源極接觸墊。
然後，第11F圖至第11M圖表示將基板晶圓的底部减薄至所需的超薄厚度，並製備以下內容：導電直通基板汲極通孔加上其底部汲極接觸墊、導電直通基板閘極通孔加上其底部閘極接觸墊、導電直通基板源極通孔加上其底部源極接觸墊。
在第11A圖中，被鈍化層34覆蓋的多個相互間隔的源極本體區23a~23g以及帶溝槽的閘極區24a~24h，都製備在半導體基板21上方，半導體基板21的原始厚度為TORG。作為一個典型示例，半導體基板21具有一下部重摻雜的接觸層21a以及一上部輕摻雜的漂流層21b。例如，鈍化層34的材料為含有硼酸的矽玻璃(BPSG)。要注意的是，源極本體區23b、23c都帶有源極本體切斷結構36，以便清除稍後在它們之間形成的導電直通基板汲極通孔。源極本體區23f、23g不帶有閘極溝槽或在中間的源極區，以便為稍後形成的導電直通基板源極通孔留有空隙。
在第11B圖中，將鈍化層34形成閘極鈍化物分段的圖案，對應源極本體區23a~23g以及帶溝槽的閘極區24a~24h，然後進行源極本 體接觸刻蝕以及本體接觸植入。
在第11C圖中，沉積頂部金屬，然後形成圖案，以製備帶圖案的閘極金屬層26h、帶圖案的源極本體金屬層25a以及帶圖案的源極本體金屬層25c，並帶有之間的分段頂部汲極金屬35，位於稍後的導電直通基板汲極通孔的位置處。對於本領域的技術人員而言，源極本體金屬層25a和25c在立體空間上相互連接。
在第11D圖中，沉積頂部鈍化層，並形成圖案，以製備帶圖案的頂部鈍化元件29a、29b、29c、29d，鄰近帶圖案的源極本體金屬層25c、分段的源極本體金屬35以及帶圖案的閘極金屬層26h。頂部鈍化元件29a-29d可以用氧化物、氮化物或兩者的組合製成。
在第11E圖中，頂部汲極接觸墊28a、頂部源極接觸墊26a以及頂部閘極接觸墊27a都同時形成在上方，使頂部汲極接觸墊28a接觸分段的頂部汲極金屬35，頂部源極接觸墊26a接觸帶圖案的源極本體金屬層25c，並且頂部閘極接觸墊27a接觸帶圖案的閘極金屬層26h。這可以藉由以下方式完成，例如濺射種子層，在種子層上方電鍍銅，然後對鍍銅形成圖案。更可選擇，使用無電、無遮罩的鎳金電鍍製程。此後，可以利用可選的化學機械拋光(CMP)和/或退火製程，使頂面平坦光滑，以消除內部材料應力。
在第11F圖中，更可選擇在製備中的元件上方連接一臨時的支撑元件(圖中沒有表示出)，並將半導體基板21從原始厚度TORG减薄至所需的超薄厚度TSVP，例如5微米至100微米。在製備中的半導體元件上連接一臨時的支撑元件，有利於向下减薄其背面，這在本領域中是眾所皆知的。作為示例，也可以在製備中的元件頂 部，連接一玻璃板或矽晶圓。
在第11G圖中，在製備中的元件上沉積一底部汲極金屬層22，然後形成在之間帶有開口的汲極金屬元件22a~22d的圖案，以容納稍後形成的各種導電直通基板汲極通孔、導電直通基板源極通孔和導電直通基板閘極通孔。作為一個典型示例，沉積底部汲極金屬層22，可以藉由背部刻蝕，以及用界面鈦或鋁進行背面金屬沉積。
在第11H圖中，在製備中的元件上沉積一底部汲極金屬鈍化物30(例如一種氧化物)，然後形成汲極金屬鈍化物元件30a~30d的圖案。
在第11I圖中，藉由直接刻蝕穿過半導體基板21，製成直通基板隧道128、126、127，帶圖案的汲極金屬元件22和汲極金屬鈍化元件30作為硬遮罩。要注意，直通基板隧道128觸及分段頂部汲極金屬35和鈍化層34，但是受分段頂部汲極金屬35和鈍化層34的限制。與之類似，直通基板隧道126觸及帶圖案的源極本體金屬層25c和鈍化層34，但是受帶圖案的源極本體金屬層25c和鈍化層34的限制。與之類似，直通基板隧道127觸及帶圖案的閘極金屬層26h和鈍化層34，但是受帶圖案的閘極金屬層26h和鈍化層34的限制。
在第11J圖中，在製備中的元件上方，沉積底部通孔絕緣層130(例如氧化物或聚合材料)，也就是說，在半導體基板21的底部和汲極金屬22以及鈍化物30的上方，以及直通基板隧道128、126、127裸露的表面上方。
在第11K圖中，直接刻蝕掉(例如藉由直接等離子刻蝕製程)通孔絕緣層130所有的水平定向層部分，使分段的頂部汲極金屬35、帶圖案的源極本體金屬層25c、帶圖案的閘極金屬層26h以及汲極金屬元件22裸露出來，保留分別位於直通基板隧道128、126、127的側壁上方的汲極通孔絕緣層33、源極通孔絕緣層31以及閘極通孔絕緣層32。
在第11L圖中，用導電通孔材料132過填充直通基板隧道128、126、127、汲極金屬鈍化物30以及汲極金屬22。作為一個示例製程，首先在製備中的元件所有裸露的底面上方，濺射一種子層。然後，在種子層上方，電鍍厚金屬，直到電鍍的厚金屬填滿並形成導電通孔材料132為止。作為一種示例材料，厚金屬為銅，種子層是由鈦和銅製成。更可選擇，用CMP平整化導電通孔材料132的底面，並對製備中的元件退火，以消除其內部應力。作為另一種選擇，可以用第一金屬化過程，填充通孔，然後用第二金屬化過程，在通孔上方，形成底部接觸墊。
在第11M圖中，形成導電通孔材料132的底部圖案，以製成所需的底部汲極接觸墊28b、底部源極接觸墊26b和底部閘極接觸墊27b，它們分別是導電直通基板汲極通孔28、導電直通基板源極通孔26和導電直通基板閘極通孔27的一部分。然後，從製備中的元件上除去臨時的支撑元件，以製成厚度為TSVP的最終的可堆疊式垂直功率MOSFET 2 402。要注意的是，我們的目的是：
a.導電直通基板汲極通孔28與半導體基板21和頂部源極接觸墊26a絕緣，同時，與汲極金屬層22、頂部汲極接觸墊28a以及底部汲極接觸墊28b相接觸。
b.導電直通基板源極通孔26與半導體基板21和底部汲極金屬層22絕緣，同時，與頂部源極接觸墊26a以及底部源極接觸墊26b相接觸。
c.導電直通基板閘極通孔27與半導體基板21和底部汲極金屬層22絕緣，同時，與頂部閘極接觸墊27a以及底部閘極接觸墊27b相接觸。
參閱第12A圖至第12G圖表示製備第8圖所示之三重可堆疊式垂直功率MOSFET堆疊400之底部可堆疊式垂直功率MOSFET單元可堆疊式垂直功率MOSFET 1 401之詳細化簡製程流程。該製程簡化為底部可堆疊式垂直功率MOSFET單元401，導電直通基板源極通孔26和導電直通基板閘極通孔27都不需要該製程。
參閱第12A圖中除了不帶有分段的頂部汲極金屬35(如第11C圖)，並且相互間隔的源極本體區和帶溝槽的閘極區數量有所增加之外，其他都與第11C圖類似。因此，對於本領域的技術人員而言，只要相應地調整遮罩設備，就可以用與第11C圖相同的製程製備第12A圖所示之製備中的元件。要注意的是，在帶圖案的源極本體金屬層25a和帶圖案的源極本體金屬層25c之間的源極本體金屬層中，要留有開口，以用於將來的導電直通基板汲極通孔。
參閱第12B圖至第12E圖表示部分直通基板汲極通孔(PTSDV)138及其頂部汲極接觸墊28a的製備。
在第12B圖中，沉積一頂部鈍化層，並形成圖案，以製備帶圖案的頂部鈍化元件29，鄰近帶圖案的源極本體金屬層25a、帶圖案的源極本體金屬層25c以及帶圖案的閘極金屬層26h。頂部鈍化元 件29a~29d可以用氧化物、氮化物或兩者的組合製成。
在第12C圖中，藉由直接部分刻蝕到半導體基板21中，製備基板中的溝槽134，頂部鈍化元件29、帶圖案的源極本體接觸25c以及帶圖案的閘極金屬層26h作為硬遮罩。
在第12D圖中，在製備中的元件(包括基板中的溝槽134裸露的表面)上方，沉積通孔絕緣材料130(例如氧化物或聚合材料)，然後各向異性地回刻，以除去它的水平部分，同時保留基板中的溝槽134側壁上的汲極通孔絕緣層33。
在第12E圖中，用導電通孔材料132，過填充基板中的溝槽134和頂部鈍化物29，以製備部分直通基板汲極通孔部分導電直通基板汲極通孔138，直通基板汲極通孔部分導電直通基板汲極通孔138藉由通孔絕緣層130，與半導體基板21絕緣。然後，形成導電通孔材料132的頂部圖案，以製備所需的頂部汲極接觸墊28a、頂部源極接觸墊26a以及頂部閘極接觸墊27a，頂部汲極接觸墊28a作為部分導電直通基板汲極通孔138的一部分。要注意的是，從第12A圖至第12E圖所示之全部製程都是在原始厚度為TORG的半導體基板21上進行的。
在第12F圖中，藉由背部减薄，將半導體基板21的厚度减至所需的超薄厚度TSVP。由於，設計的部分導電直通基板汲極通孔138要部分穿過半導體基板21，從而使部分導電直通基板汲極通孔的底部將觸及到稍後减薄的厚度為T的半導體基板21上方，同時，底部减薄將變短後的部分導電直通基板汲極通孔底部裸露出來，用於外部接觸。由於，底部晶片除了回刻和背部金屬化之外，不 再需要其他處理(即，不需要再形成導電直通通孔)，因此，在這種情况下，其實不需要臨時支撑元件。但是，如果的確需要，仍可選用臨時支撑元件。
在第12G圖中，在减薄的半導體基板21上方，形成一底部汲極金屬層22。最終的可堆疊式垂直功率MOSFET 1 401的厚度為TSVP，並且具有一直通基板汲極通孔28。參照上述製備如第8圖所示之三重可堆疊式垂直功率MOSFET堆疊400的中間可堆疊式垂直功率MOSFET 2 402和底部可堆疊式垂直功率MOSFET 1 401的詳細製程，本領域的技術人員應掌握，如何製備三重可堆疊式垂直功率MOSFET堆疊400的頂部可堆疊式垂直功率MOSFET 3 403。
儘管上述說明含有許多具體參數，但是這些參數僅僅用作對本發明現有的較佳實施例的解釋說明，而不應作為本發明範圍的侷限。例如，除了MOSFET之外，本發明也可用於一般的垂直功率半導體元件，在這些元件中，元件電流主要集中在其正面和背部基板之間，例如絕緣閘雙極晶體管(IGBT)。
藉由說明和圖式，給出了關於典型結構的各種典型實施例。對於本領域的技術人員應顯而易見，本發明可以用於各種其他特殊形式，上述各種實施例經過輕鬆修改，就可以適合於其他具體應用。本專利說明書旨在說明，本發明的範圍不應侷限於上述說明中的典型實施例，而應由以下的申請專利範圍來界定。任何和所有來自於申請專利範圍中內容或同等範圍中的修正，都將被認為屬於本發明的保護範圍之內。
20‧‧‧MOSFET
21‧‧‧半導體基板
21a‧‧‧基板層
21b‧‧‧外延層
22‧‧‧底部汲極金屬
23a、23c、23d、23e、23f、23g‧‧‧源極本體區
24a、24c、24d、24e、24g、24j‧‧‧閘極區
25a、25c‧‧‧源極本體金屬層
26‧‧‧導電直通基板源極通孔
26a、26b‧‧‧頂部源極接觸墊
26h‧‧‧閘極金屬層
27‧‧‧導電直通基板閘極通孔
27a、27b‧‧‧頂部閘極接觸墊
28‧‧‧導電直通基板汲極通孔
28a‧‧‧頂部汲極接觸墊
28b‧‧‧底部汲極接觸墊
29‧‧‧頂部鈍化物
30‧‧‧MOSFET功率半導體零部件堆疊
31、32、33‧‧‧通孔絕緣層
35‧‧‧源極本體金屬
36‧‧‧源極本體切斷結構

Claims (21)

  1. 一種可堆疊式垂直功率MOSFET(SVP-MOSFET)元件，其包括：一半導體基板，該半導體基板上帶有一底部汲極金屬層；多個形成在該半導體基板上方之交叉指型之閘極區和源極本體區；一帶圖案之閘極金屬層和一帶圖案之源極本體金屬層，它們分別接觸該閘極區和該源極本體區；以及一導電直通基板汲極通孔(TSDV)，穿過該半導體基板，並與一汲極金屬層接觸，但與該半導體基板絕緣，具有一頂部汲極接觸結構和一底部汲極接觸結構，分別在頂面和底面電接觸到該導電直通基板汲極通孔上；一導電直通基板閘極通孔(TSGV)，穿過該半導體基板，並與該閘極金屬層接觸，但與該半導體基板絕緣，具有一頂部閘極接觸結構和一底部閘極接觸結構，分別在頂面和底面電接觸到該導電直通基板閘極通孔上；以及一導電直通基板源極通孔(TSSV)，穿過該半導體基板，並與該源極本體金屬層接觸，但與該半導體基板絕緣，具有一頂部源極接觸結構和一底部源極接觸結構，分別在頂面和底面電接觸到該導電直通基板源極通孔上；當多個該可堆疊式垂直功率MOSFET元件一個壓一個地向上堆疊起來，所形成之一可堆疊式垂直功率MOSFET堆疊就會起並聯導電連接之作用，從而降低了導通電阻Rds、增大了載流能力並减少了 封裝引脚。
  2. 如申請專利範圍第1項所述之可堆疊式垂直功率MOSFET元件，其中該可堆疊式垂直功率MOSFET元件厚度為5微米至100微米。
  3. 如申請專利範圍第1項所述之可堆疊式垂直功率MOSFET元件，其中每一位於該導電直通基板汲極通孔附近之該源極本體區，都帶有一源極本體切斷剖面，距離該導電直通基板汲極通孔足夠遠，以承載它們之間之一汲極源極電壓。
  4. 如申請專利範圍第1項所述之可堆疊式垂直功率MOSFET元件，其中每一該導電直通基板汲極通孔、該導電直通基板閘極通孔和該導電直通基板源極通孔更包括一相應之通孔絕緣層包圍著它，從而使它與該半導體基板絕緣。
  5. 一種封裝多單元可堆疊式垂直功率MOSFET之堆疊，其包括：多個可堆疊式功率MOSFET單元一個壓一個地向上黏合，每一該可堆疊式功率MOSFET單元包括：一半導體基板，該半導體基板上帶有一底部汲極金屬層；多個形成在該半導體基板上方之交叉指型之閘極區和源極本體區；一帶圖案之閘極金屬層和一帶圖案之源極本體金屬層，它們分別接觸該閘極區和該源極本體區；以及一導電直通基板汲極通孔(TSDV)，穿過該半導體基板，並與一汲極金屬層接觸，但與該半導體基板絕緣，具有一頂部汲極接觸結構和一底部汲極接觸結構，分別在頂面和底面電接觸到該導電直通基板汲極通孔上；一導電直通基板閘極通孔(TSGV)，穿過該半導體基板，並與該閘極金屬層接觸，但與該半導體基板絕緣，具有一頂部閘極接觸 結構和一底部閘極接觸結構，分別在頂面和底面電接觸到該導電直通基板閘極通孔上；以及一導電直通基板源極通孔(TSSV)，穿過該半導體基板，並與一源極本體金屬層接觸，但與該半導體基板絕緣，具有一頂部源極接觸結構和一底部源極接觸結構，分別在頂面和底面電接觸到該導電直通基板源極通孔上；使得該堆疊起到可堆疊式功率MOSFET元件之並聯導電連接之作用，從而降低了導通電阻Rds、增大了載流能力並减少了封裝引脚。
  6. 如申請專利範圍第5項所述之封裝堆疊，其中在含有該導電直通基板源極通孔和/或該導電直通基板汲極通孔之一個該可堆疊式功率MOSFET單元中，該導電直通基板源極通孔和/或該導電直通基板汲極通孔分佈在整個MOSFET單元之有源區上。
  7. 如申請專利範圍第5項所述之封裝堆疊，其中在含有多個該導電直通基板源極通孔和該導電直通基板汲極通孔之一個該可堆疊式功率MOSFET單元中，該導電直通基板源極通孔和該導電直通基板汲極通孔相互間隔，相互電絕緣。
  8. 如申請專利範圍第5項所述之封裝堆疊，其中該導電直通基板汲極通孔、該導電直通基板閘極通孔和該導電直通基板源極通孔在它們各自之該可堆疊式功率MOSFET單元之主元件平面內，都設置於恰當之位置，因此，一旦將它們堆疊起來：功率MOSFET單元之該頂部汲極接觸結構和該底部汲極接觸結構就會分別與它們相鄰之功率MOSFET單元之該底部汲極接觸結構和該頂部汲極接觸結構對齊；功率MOSFET單元之該頂部閘極接觸結構和該底部閘極接觸結構就 會分別與它們相鄰之功率MOSFET單元之該底部閘極接觸結構和該頂部閘極接觸結構對齊；以及功率MOSFET單元之該頂部源極接觸結構和該底部源極接觸結構就會分別與它們相鄰之功率MOSFET單元之該底部源極接觸結構和該頂部源極接觸結構對齊。
  9. 如申請專利範圍第5項所述之封裝堆疊，其中每一位於該導電直通基板汲極通孔附近之該源極本體區，都帶有一源極本體切斷剖面，距離該導電直通基板汲極通孔足夠遠，以承載它們之間之汲極源極電壓。
  10. 如申請專利範圍第5項所述之封裝堆疊，其中每一該導電直通基板汲極通孔、該導電直通基板閘極通孔和該導電直通基板源極通孔更包括一相應之通孔絕緣層包圍著它，從而使它與該半導體基板絕緣。
  11. 如申請專利範圍第5項所述之封裝堆疊，其中最底部之功率MOSFET單元僅含有該導電直通基板汲極通孔，最頂部之功率MOSFET單元僅含有該導電直通基板閘極通孔和該導電直通基板源極通孔，並且其中如果有中間之功率MOSFET單元，則中間功率MOSFET單元含有該導電直通基板汲極通孔、該導電直通基板閘極通孔和該導電直通基板源極通孔。
  12. 一種封裝之多單元功率MOSFET堆疊之製備方法，該封裝之多單元功率MOSFET堆疊具有多個功率MOSFET單元一個壓一個地向上黏合，並且相互並聯，該方法包括：製備多個可堆疊式功率MOSFET單元，每一該可堆疊式功率MOSFET單元都具有：一半導體基板，該半導體基板上帶有一底部汲極金屬層； 多個形成在該半導體基板上方之交叉指型之閘極區和源極本體區；一帶圖案之閘極金屬層和一帶圖案之源極本體金屬層，它們分別接觸該閘極區和該源極本體區；並且一直通基板通孔含有：一導電直通基板汲極通孔(TSDV)，與一汲極金屬層接觸，具有一頂部汲極接觸結構和一底部汲極接觸結構，分別在頂面和底面電接觸到該導電直通基板汲極通孔上；一導電直通基板閘極通孔(TSGV)，與該閘極金屬層接觸，具有一頂部閘極接觸結構和一底部閘極接觸結構，分別在頂面和底面電接觸到該導電直通基板閘極通孔上；以及一導電直通基板源極通孔(TSSV)，與該源極本體金屬層接觸，具有一頂部源極接觸結構和一底部源極接觸結構，分別在頂面和底面電接觸到該導電直通基板源極通孔上；將功率MOSFET單元一個壓一個地向上堆疊並黏合，以構成帶有由該導電直通基板汲極通孔、該導電直通基板閘極通孔和該導電直通基板源極通孔實現的並聯連接之該多單元功率MOSFET堆疊；以及將該堆疊與其外部作業環境互聯。
  13. 如申請專利範圍第12項所述之方法，其中在含有該導電直通基板汲極通孔和/或該導電直通基板源極通孔之一個該功率MOSFET單元中，該方法更包括將該導電直通基板汲極通孔和/或該導電直通基板源極通孔分佈在整個MOSFET單元之有源區上。
  14. 如申請專利範圍第12項所述之方法，其中每一該功率MOSFET單元都有一超薄厚度，以便减少多單元功率MOSFET堆疊相應的厚度和導通電阻Rds，因此，製備每一該功率MOSFET單元更包括： 製備該功率MOSFET單元之頂部；將一基板晶圓之底部减薄至所需之超薄厚度，並製備該導電直通基板汲極通孔加上其底部汲極接觸結構、該導電直通基板閘極通孔加上其底部閘極接觸結構以及該導電直通基板源極通孔加上其底部源極接觸結構之至少其中之一。
  15. 如申請專利範圍第14項所述之方法，其中：製備該導電直通基板汲極通孔加上其底部汲極接觸結構、該導電直通基板閘極通孔加上其底部閘極接觸結構以及該導電直通基板源極通孔加上其底部源極接觸結構之至少其中之一；更包括將它們並行進行。
  16. 如申請專利範圍第15項所述之方法，其更包括：製備一個該底部汲極金屬層，在各個需要設置該導電直通基板汲極通孔、該導電直通基板閘極通孔和該導電直通基板源極通孔之位置處，將該底部汲極金屬層開孔；以及如果需要，就同時製備：在需要設置該導電直通基板汲極通孔之位置處，一起製備該導電直通基板汲極通孔及其底部汲極接觸結構，使該導電直通基板汲極通孔與該半導體基板絕緣，同時，與該頂部汲極接觸結構、該底部汲極接觸結構以及該底部汲極金屬層電接觸；在需要設置該導電直通基板閘極通孔之位置處，一起製備該導電直通基板閘極通孔及其底部閘極接觸結構，使該導電直通基板閘極通孔與該半導體基板以及該汲極金屬層絕緣，同時，與該頂部閘極接觸結構、該底部閘極接觸結構以及該閘極金屬層電接觸；以及在需要設置該導電直通基板源極通孔之位置處，一起製備該導電 直通基板源極通孔及其底部源極接觸結構，使該導電直通基板源極通孔與該半導體基板以及該汲極金屬層絕緣，同時，與該頂部源極接觸結構、該底部源極接觸結構以及該源極本體金屬層電接觸。
  17. 如申請專利範圍第12項所述之方法，其中為底部可堆疊式功率MOSFET單元，製備該導電直通基板汲極通孔加上其底部汲極接觸結構，更包括：在需要設置該導電直通基板汲極通孔之位置處，將該源極本體金屬層開孔；在需要設置該導電直通基板汲極通孔之位置處，一起製備一部分直通基板汲極通孔(PTSDV)及其頂部汲極接觸結構，使該部分直通基板汲極通孔：與該半導體基板絕緣；以及部分穿入一半導體晶圓中；將一基板晶圓之底部减薄至所需厚度，同時將該部分直通基板汲極通孔之底部裸露出來，以製成該導電直通基板汲極通孔；以及在該基板晶圓上形成一個該底部汲極金屬層。
  18. 如申請專利範圍第12項所述之方法，其中製備直通基板通孔更包括：在該半導體基板上方，製備一頂部金屬層；將該頂部金屬層分段設置成一源極本體金屬層、閘極金屬層以及在需要設置該導電直通基板汲極通孔之位置處，設置一頂部汲極金屬層；製備一底部汲極金屬層，並在需要設置該直通基板通孔之位置處，開孔；以及 在需要設置該直通基板通孔之位置處，製備帶有一底部接觸結構之該直通基板通孔，使該直通基板通孔與該半導體基板絕緣，同時與合適之一頂部分段金屬層和該底部接觸結構相接觸，其中，該導電直通基板源極通孔和該導電直通基板閘極通孔與底部汲極金屬絕緣。
  19. 如申請專利範圍第18項所述之方法，其中製備該直通基板通孔更包括：在該底部汲極金屬層上，沉積一汲極金屬鈍化物並形成圖案，同時包圍著需要設置該直通基板通孔處；以帶開口之該底部汲極金屬層和帶圖案之該汲極金屬鈍化物作為遮罩，對該半導體基板進行定向刻蝕，以形成一直通基板隧道，觸及分段之該頂部金屬層，但受分段之該頂部金屬層限制；以及在該直通基板隧道內，製備該直通基板通孔，並且在該底部汲極金屬層和該汲極金屬鈍化物上，製備該底部接觸結構。
  20. 如申請專利範圍第19項所述之方法，其中製備該直通基板通孔更包括：在該直通基板隧道裸露之表面上方，製備一通孔絕緣層；定向刻蝕掉該通孔絕緣層之所有之水平導向層，以便裸露出在該直通基板隧道末端之分段之該頂部金屬層；用一導電通孔材料，過填充該直通基板隧道和帶圖案之該汲極金屬鈍化物；以及形成該導電通孔材料底部之圖案，以形成該底部接觸結構。
  21. 如申請專利範圍第20項所述之方法，其中用該導電通孔材料過填充包括：在該半導體基板之背面，濺射一種子層； 在該種子層上方電鍍一厚金屬，直到該厚金屬過填充該直通基板隧道以及帶圖案之該汲極金屬鈍化物為止，以構成一底面金屬層。
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Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4833307B2 (ja) * 2009-02-24 2011-12-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体モジュール、端子板、端子板の製造方法および半導体モジュールの製造方法
JP5641701B2 (ja) * 2009-03-25 2014-12-17 株式会社東芝 三次元半導体集積回路
KR20110055973A (ko) * 2009-11-20 2011-05-26 주식회사 하이닉스반도체 반도체 칩 모듈 및 이를 포함하는 반도체 패키지
TWI419257B (zh) * 2009-12-29 2013-12-11 Advanced Semiconductor Eng 半導體製程、半導體元件及具有半導體元件之封裝結構
US8519473B2 (en) 2010-07-14 2013-08-27 Infineon Technologies Ag Vertical transistor component
US8466024B2 (en) * 2010-12-13 2013-06-18 International Business Machines Corporation Power domain controller with gated through silicon via having FET with horizontal channel
TWI423415B (zh) * 2011-02-01 2014-01-11 Niko Semiconductor Co Ltd 具有低阻值基材與低損耗功率之半導體結構
US8823090B2 (en) 2011-02-17 2014-09-02 International Business Machines Corporation Field-effect transistor and method of creating same
US8492903B2 (en) 2011-06-29 2013-07-23 International Business Machines Corporation Through silicon via direct FET signal gating
US9478646B2 (en) * 2011-07-27 2016-10-25 Alpha And Omega Semiconductor Incorporated Methods for fabricating anode shorted field stop insulated gate bipolar transistor
US9224669B2 (en) * 2011-08-09 2015-12-29 Alpha And Omega Semiconductor Incorporated Method and structure for wafer level packaging with large contact area
TWI456737B (zh) * 2012-03-05 2014-10-11 Richtek Technology Corp 垂直式半導體元件及其製造方法
CN103325747A (zh) * 2012-03-19 2013-09-25 立锜科技股份有限公司 垂直式半导体元件及其制造方法
US9466552B2 (en) * 2012-03-30 2016-10-11 Richtek Technology Corporation Vertical semiconductor device having a non-conductive substrate and a gallium nitride layer
TWI455272B (zh) * 2012-07-18 2014-10-01 矽品精密工業股份有限公司 半導體基板及其製法
KR20140037392A (ko) * 2012-09-17 2014-03-27 삼성전자주식회사 반도체 소자 및 그 제조방법
US9078380B2 (en) * 2012-10-19 2015-07-07 Nvidia Corporation MOSFET stack package
US9177914B2 (en) * 2012-11-15 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad structure over TSV to reduce shorting of upper metal layer
US8896128B2 (en) 2012-11-16 2014-11-25 Infineon Technologies Ag Integrated circuit, a semiconductor die arrangement and a method for manufacturing an integrated circuit
TWI483378B (zh) * 2013-01-04 2015-05-01 Tsai Yu Huang 三維晶片堆疊結構
US9673316B1 (en) * 2013-03-15 2017-06-06 Maxim Integrated Products, Inc. Vertical semiconductor device having frontside interconnections
US10090239B2 (en) 2013-06-26 2018-10-02 Intel Corporation Metal-insulator-metal on-die capacitor with partial vias
US9455214B2 (en) 2014-05-19 2016-09-27 Globalfoundries Inc. Wafer frontside-backside through silicon via
FR3028095B1 (fr) 2014-11-04 2018-01-26 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif electronique de puissance a cellule de commutation 3d verticale
US9525001B2 (en) * 2014-12-30 2016-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
JP6528592B2 (ja) * 2015-08-17 2019-06-12 富士通株式会社 半導体装置
CN107980171B (zh) * 2016-12-23 2022-06-24 苏州能讯高能半导体有限公司 半导体芯片、半导体晶圆及半导体晶圆的制造方法
IT201700113926A1 (it) 2017-10-10 2019-04-10 St Microelectronics Srl Dispositivo mosfet di potenza e relativo procedimento di fabbricazione
JP2022143187A (ja) * 2021-03-17 2022-10-03 株式会社東芝 半導体装置
CN115548009A (zh) * 2021-06-29 2022-12-30 联华电子股份有限公司 半导体结构及其制造方法
CN117810267B (zh) * 2024-03-01 2024-04-30 深圳市冠禹半导体有限公司 一种栅极嵌埋式mosfet器件及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4124981B2 (ja) * 2001-06-04 2008-07-23 株式会社ルネサステクノロジ 電力用半導体装置および電源回路
US7300857B2 (en) * 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
CN100505300C (zh) * 2005-03-30 2009-06-24 三洋电机株式会社 半导体装置及其制造方法
JP5048230B2 (ja) * 2005-03-30 2012-10-17 オンセミコンダクター・トレーディング・リミテッド 半導体装置およびその製造方法
JP2007067216A (ja) * 2005-08-31 2007-03-15 Sanyo Electric Co Ltd 半導体装置およびその製造方法、回路基板およびその製造方法
US8294208B2 (en) * 2008-03-04 2012-10-23 International Rectifier Corporation Semiconductor device having a gate contact on one surface electrically connected to a gate bus on an opposing surface

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