JP2022143187A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2022143187A JP2022143187A JP2021043577A JP2021043577A JP2022143187A JP 2022143187 A JP2022143187 A JP 2022143187A JP 2021043577 A JP2021043577 A JP 2021043577A JP 2021043577 A JP2021043577 A JP 2021043577A JP 2022143187 A JP2022143187 A JP 2022143187A
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- Prior art keywords
- electrode
- semiconductor
- semiconductor element
- control
- insulating member
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Abstract
【解決手段】半導体装置は、複数の半導体素子と、絶縁部材と、第1端子と、第2端子と、複数の制御端子と、を備える。前記複数の半導体素子は、半導体部と、前記半導体部の裏面上の第1電極と、表面上の第2電極と、前記表面上の制御電極と、をそれぞれ含み、前記第1電極から前記第2電極に向かう第1方向に並ぶ。前記複数の半導体素子は直列接続され、一方の端の第1素子と、他方の端の第2素子と、を含む。前記絶縁部材は、前記第1素子に向き合う第1表面と、前記第2素子に向き合う第2表面と、を有する。前記第1端子は、前記第1素子の前記第1電極、前記第2端子は、前記第2素子の前記第2電極、前記複数の制御端子はそれぞれ前記制御電極に電気的に接続される。前記第2端子および前記複数の制御端子は、前記第1表面および前記第2表面のいずれか一方に設けられる。
【選択図】図1
Description
図1は、第1実施形態に係る半導体装置1を示す模式断面図である。
図2(a)および(b)は、第1実施形態に係る半導体素子Trを示す模式図である。
図3(a)は、絶縁部材IMの第2表面S2を示す模式平面図である。
図3(b)は、図3(a)中に示すA-A線に沿った断面図である。
なお、図1は、図3(a)中に示すB-B線に沿った断面図である。
図3(c)は、絶縁部材IMの第1表面S1を示す模式平面図である。
図15(a)~(c)、図16(a)および(b)は、第2実施形態に係る半導体装置4を示す模式図である。図15(a)および(c)は、半導体装置4の構成を示す平面図である。図16(a)は、半導体装置4の裏面を示す平面図である。図15(b)は、図15(a)中に示すE-E線に沿った断面図である。図16(b)は、図16(a)中に示すF-F線に沿った断面図である。
Claims (7)
- 半導体部と、前記半導体部の裏面上に設けられた第1電極と、前記半導体部の前記裏面とは反対側の表面上に設けられた第2電極と、前記半導体部の前記表面上に設けられ、前記第1電極と前記第2電極との間に流れる電流を制御する制御電極と、をそれぞれ含み、前記第1電極から前記第2電極に向かう第1方向に並ぶ複数の半導体素子であって、前記第1方向において隣り合う半導体素子の間において、前記第2電極と別の第1電極とを電気的に接続することにより直列接続され、前記直列接続の一方の端に設けられる第1半導体素子と、他方の端に設けられる第2半導体素子と、を含む複数の半導体素子と、
前記第1方向に並んだ前記複数の半導体素子を封じ、前記第1半導体素子に向き合う第1表面と、前記第2半導体素子に向き合う第2表面と、を有し、前記第1表面および前記第2表面は、前記第1方向と交差する絶縁部材と、
前記第1半導体素子の前記第1電極に電気的に接続された第1端子と、
前記第2半導体素子の前記第2電極に電気的に接続され、前記絶縁部材の前記第1表面および前記第2表面のいずれか一方に設けられた第2端子と、
前記複数の半導体素子の前記制御電極にそれぞれ電気的に接続され、前記絶縁部材の前記第1表面および前記第2表面のうちの前記一方に相互に離間して設けられ、前記第2端子から離間した複数の制御端子と、
を備えた半導体装置。 - 前記第1端子は、前記絶縁部材の前記第1表面および前記第2表面のうちの前記一方に設けられ、前記第2端子および前記複数の制御端子から離間した請求項1記載の半導体装置。
- 前記複数の半導体素子の間にそれぞれ設けられ、前記第2電極と前記別の第1電極とを電気的に接続する配線をさらに備え、
前記絶縁部材は、前記複数の半導体素子のそれぞれを内蔵した第1部材と、前記配線を含む第2部材と、を交互に積層した構造を有する請求項1または2に記載の半導体装置。 - 前記絶縁部材の前記第1部材は、前記第2電極に連通した複数のコンタクトホールを有し、
前記配線は、前記複数のコンタクトホール内にそれぞれ延在する複数のコンタクト部と、前記第1部材上に設けられる金属層と、を含み、前記複数のコンタクト部は、前記金属層につながり、前記コンタクト部を介して、前記第2電極に電気的に接続される請求項3記載の半導体装置。 - 前記複数の半導体素子は、前記第1方向に積層され、
前記絶縁部材は、前記第1方向に積層された前記複数の半導体素子を覆う請求項1または2に記載の半導体装置。 - 前記複数の半導体素子のうちの1つは、前記半導体部の前記表面に沿った第2方向に並ぶ前記第2電極および前記制御電極を含み、
前記複数の半導体素子のうちの前記1つの上に設けられる別の1つは、前記半導体部の前記表面に沿った第3方向であって、前記第2方向に直交する前記第3方向に並ぶ前記第2電極および前記制御電極を含む請求項5記載の半導体装置。 - 前記複数の半導体素子それぞれは、前記第1電極と前記第2電極との間における略同一の容量を有する請求項1~6のいずれか1つに記載の半導体装置。
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