TWI419257B - 半導體製程、半導體元件及具有半導體元件之封裝結構 - Google Patents
半導體製程、半導體元件及具有半導體元件之封裝結構 Download PDFInfo
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Description
本發明係關於一種半導體製程、半導體元件及具有半導體元件之封裝結構,詳言之,係關於一種具有穿導孔結構之半導體元件之製程、半導體元件及具有半導體元件之封裝結構。
參考圖1及圖2,顯示習知半導體元件之剖面示意圖及其局部放大圖。該習知半導體元件1具有一矽基材11、至少一電性元件12、至少一穿導孔結構13、一保護層(Passivation Layer)14及一重佈層15。該矽基材11具有一第一表面111、一第二表面112及至少一溝槽113。該溝槽113係開口於該第一表面111。該電性元件12係位於該矽基材11內,且顯露於該矽基材11之第二表面112。該穿導孔結構13係位於該矽基材11之溝槽113內。該穿導孔結構13具有一第一端131及一第二端132,該第一端131係顯露於該矽基材11之第一表面111,且該第二端132連接該電性元件12。該保護層14係位於該矽基材11之第一表面111,該保護層14具有一表面141及至少一開口142,該開口142顯露該穿導孔結構13之第一端131。該重佈層15係位於該保護層14之表面141及開口142,該重佈層15具有至少一電性連接區域151,用以連接該穿導孔結構13之第一端131。
該習知半導體元件1之缺點如下。該保護層14之開口142係利用乾蝕刻(Dry Etching)方式形成,而乾蝕刻係利用電漿撞擊欲蝕刻之表面以進行蝕刻。然而,當該保護層14逐漸被移除而顯露該穿導孔結構13之第一端131時,該穿導孔結構13之第一端131所累積之電荷也逐漸增加,而開始排斥電漿,導致電漿減少撞擊該穿導孔結構13之第一端131,而無法完全移除位於其上之保護層14。最後,部分該保護層14殘留於該穿導孔結構13之第一端131,如圖1及圖2之區域A所示,而降低該穿導孔結構13與該重佈層15電性連接之良率。此外,該穿導孔結構13之第一端131係僅顯露於該矽基材11之第一表面111,而未顯露於該保護層14之表面141,故形成該重佈層15之製程較為複雜。
因此,有必要提供一種半導體製程、半導體元件及具有半導體元件之封裝結構,以解決上述問題。
本發明提供一種半導體製程。該半導體製程包括以下步驟:(a)提供一半導體元件,該半導體元件包括一矽基材及至少一導電孔結構,該導電孔結構係位於該矽基材內;(b)移除部分該矽基材,以形成一第一表面,使得該導電孔結構突出於該矽基材之第一表面,而形成一穿導孔結構;(c)形成一保護層於該矽基材之第一表面,以覆蓋該穿導孔結構,該保護層係為感光材料,且具有一上表面;(d)提供一光罩於該保護層之上方,以遮住部分該保護層;(e)提供一光源,以照射未被遮住之部分該保護層;及(f)移除部分該保護層,使得該穿導孔結構顯露於該保護層之第一表面。
藉此,利用感光材料經一光源照射產生化學反應之特性,可完全移除位於該穿導孔結構上之部分該保護層,以確保該穿導孔結構對外電性連接之良率。
本發明更提供一種半導體元件。該半導體元件包括一矽基材、一保護層及至少一穿導孔結構。該矽基材具有一第一表面及至少一溝槽,該溝槽係開口於該矽基材之第一表面。該保護層係位於該矽基材之第一表面,該保護層具有一第一表面及至少一穿孔,該穿孔貫穿該保護層。該穿導孔結構係位於該矽基材之溝槽及該保護層之穿孔內,且突出於該保護層之第一表面。
本發明再提供一種具有半導體元件之封裝結構。該封裝結構包括一基板、一半導體元件、一晶片及一保護材。該半導體元件係位於該基板上,且電性連接至該基板。該半導體元件包括一矽基材、一保護層及至少一穿導孔結構。該矽基材具有一第一表面及至少一溝槽,該溝槽係開口於該矽基材之第一表面。該保護層係位於該矽基材之第一表面,該保護層具有一第一表面及至少一穿孔,該穿孔貫穿該保護層。該穿導孔結構係位於該矽基材之溝槽及該保護層之穿孔內,且突出於該保護層之第一表面。該晶片係位於該半導體元件上,且電性連接至該半導體元件。該保護材係位於該基板上,包覆該半導體元件及該晶片。
藉此,該穿導孔結構突出於該保護層之第一表面,可直接對外電性連接,故省略一形成一重佈層之步驟,而簡化製程。
參考圖3至圖10,顯示本發明半導體製程之示意圖。參考圖3,提供一半導體元件2。該半導體元件2包括一基材21及至少一導電孔結構26。在本實施例中,該半導體元件2係為一晶圓,且更包括至少一電性元件22。該矽基材21具有一上表面211、一第二表面212及至少一溝槽213。該電性元件22係位於該矽基材21內,且顯露於該矽基材21之第二表面212。在本實施例中,該電性元件22係為互補式金屬-氧化層-半導體(Complementary Metal-Oxide-Semiconductor,CMOS)。
該導電孔結構26係位於該矽基材21之溝槽213內,且具有一第一端231及一第二端232。該第二端232連接該電性元件22,該導電孔結構26並未貫穿該矽基材21,亦即該導電孔結構26之第一端231並未顯露於或突出於該矽基材21之上表面211。在本實施例中,該導電孔結構26包括一外絕緣層233及一導體234,該外絕緣層233係位於該溝槽213之側壁,定義出一第二中心槽235,該導體234填滿該第二中心槽235。該導電孔結構26之導體234之材質係為銅。然而,在其他應用中,該導體234係可不填滿該第二中心槽235,而僅位於該第二中心槽235之側壁,定義出一第一中心槽236(圖11)。或者,該導電孔結構26更包括一內絕緣層237(圖12),填滿該第一中心槽236。
參考圖4,利用研磨方式,從該基材21之上表面211(圖3)移除部分該基材21,以形成一第三表面214,該導電孔結構26之第一端231顯露於該基材21之第三表面214。參考圖5,移除部分該矽基材21,以形成一第一表面215,該溝槽213係開口於該矽基材21之第一表面215,該導電孔結構26突出於該矽基材21之第一表面215,而形成一穿導孔結構23。在本實施例中,係以蝕刻方式從該基材21之第三表面214(圖4)移除部分該基材21,以形成該第一表面215,該導電孔結構26之第一端231突出於該基材21之第一表面215,而形成該穿導孔結構23。
參考圖6,形成一保護層24於該矽基材21之第一表面215,以覆蓋該穿導孔結構23之第一端231。該保護層24具有一上表面241及一第二表面243,且係為感光材料。在本實施例中,該保護層24係為負型光阻,例如苯環丁烯(Benzocyclobutance,BCB),且係利用旋轉塗佈(Spin Coating)或噴霧塗佈(Spray Coating)方式形成該保護層24。較佳地,該保護層24包括一第一部分244及一第二部分245。該保護層24之第一部分244覆蓋該穿導孔結構23,在後續製程中,將移除部分該保護層24之第一部分244,以顯露該穿導孔結構23。該保護層24之第二部分245覆蓋該基材21之第一表面215,在後續製程中,將保留該保護層24之第二部分245,且該第二部分245之頂部之水平高度係低於該穿導孔結構23之頂部(即第一端231)之水平高度,使得該第二部分245之頂部及該穿導孔結構23之頂部(即第一端231)之間具有一間距d。
參考圖7,提供一光罩25於該保護層24之上表面241之上,以遮住部分該保護層24。在本實施例中,該保護層24係為負型光阻,而具有經一光源(圖中未示)照射後,其分子鍵產生交聯反應(Cross-linking Reaction)而硬化之特性,因此,該光罩25遮住欲移除之該保護層24之第一部分244,且該光罩25具有至少一開口251以顯露欲保留之該保護層24之第二部分245。接著,提供該光源,以照射未被遮住之部分該保護層24,在本實施例中,係為該保護層24之第二部分245。
然而,在其他應用中,該保護層24係可為正型光阻,而具有經一光源照射後,其分子鍵斷裂之特性。因此,該光罩25遮住欲保留之該保護層24之第二部分245,且該光罩25之開口251顯露並以該光源照射欲移除之該保護層24之第一部分244,如圖8所示。由此可知,使用正型光阻時,該光罩25所遮住及顯露之部分與負型光阻相反。
參考圖9,移除部分該保護層24,亦即,移除該保護層24之第一部分244,以形成一第一表面246及至少一穿孔242,同時形成本發明半導體元件3。該穿孔242貫穿該保護層24之第一表面246及第二表面243,該穿導孔結構23係位於該保護層24之穿孔242內,且顯露於該保護層24之第一表面246。較佳地,該穿導孔結構23之第一端231與該保護層24之第一表面246之距離為1μm以上,亦即,該穿導孔結構23之第一端231突出於該保護層24之第一表面246約1μm以上。
藉此,利用感光材料之保護層24經一光源照射產生化學反應之特性,可完全移除位於該穿導孔結構23上之部分該保護層24,以確保該穿導孔結構23對外電性連接之良率。
再參考圖9及圖10,顯示本發明半導體元件之第一實施例之剖面示意圖及其局部放大圖。該半導體元件3包括一矽基材21及至少一穿導孔結構23。在本實施例中,該半導體元件3係為一晶圓,且更包括至少一電性元件22及一保護層24。該矽基材21具有一第一表面215、一第二表面212、至少一溝槽213。該溝槽213係開口於該第一表面215。該電性元件22係位於該矽基材21內,且顯露於該矽基材21之第二表面212。在本實施例中,該電性元件22係為互補式金屬-氧化層-半導體(Complementary Metal-Oxide-Semiconductor,CMOS)。
該保護層24係位於該矽基材21之第一表面215,該保護層24具有一第一表面246、一第二表面243及至少一穿孔242。該穿孔242貫穿該第一表面246及該第二表面243。在本實施例中,該保護層24之厚度不一致,位於該穿孔242周圍之保護層24之厚度比其餘區域之保護層24之厚度較薄。該保護層24係為感光材料,在本實施例中,係為負型光阻,例如苯環丁烯(Benzocyclobutance,BCB)。然而,在其他應用中,該保護層24係可為正型光阻。
該穿導孔結構23係位於該矽基材21之溝槽213及該保護層24之穿孔242內,且突出於該保護層24之第一表面246。該穿導孔結構23具有一第一端231及一第二端232,該第一端231係突出於該保護層24之第一表面246,且該第二端232連接該電性元件22。在本實施例中,該穿導孔結構23包括一外絕緣層233及一導體234,該外絕緣層233係位於該溝槽213之側壁,定義出一第二中心槽235,該導體234填滿該第二中心槽235。該穿導孔結構23之導體234之材質係為銅。
藉此,該穿導孔結構23突出於該保護層24之第一表面246,可直接對外電性連接,故省略一形成一重佈層15(圖1)之步驟,而簡化製程。
參考圖11,顯示本發明半導體元件之第二實施例之剖面示意圖。本實施例之半導體元件4與第一實施例之半導體元件3(圖9)大致相同,其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於,在本實施例中,該導體234係可不填滿該第二中心槽235,而僅位於該第二中心槽235之側壁,定義出一第一中心槽236。此外,該保護層24之厚度不一致,位於該穿孔242周圍之保護層24之厚度比其餘區域之保護層24之厚度較厚。
參考圖12,顯示本發明半導體元件之第三實施例之剖面示意圖。本實施例之半導體元件5與第二實施例之半導體元件4(圖11)大致相同,其中相同之元件賦予相同之編號。本實施例與第二實施例之不同處在於,在本實施例中,該穿導孔結構23更包括一內絕緣層237,填滿該第一中心槽236。此外,該保護層24之厚度一致,位於該穿孔242周圍之保護層24之厚度與其餘區域之保護層24之厚度一樣。
參考圖13,顯示本發明具有半導體元件之封裝結構之剖面示意圖。該封裝結構6包括一基板7、一半導體元件、一晶片8及一保護材9。該半導體元件係位於該基板7上,且電性連接至該基板7。在本實施例中,該半導體元件係為本發明半導體元件3之第一實施例。然而,在其他應用中,該半導體元件係可置換成本發明半導體元件4之第二實施例或本發明半導體元件5之第三實施例。該晶片8係位於該半導體元件上,且電性連接至該半導體元件。該保護材9係位於該基板7上,包覆該半導體元件及該晶片8。
惟上述實施例僅為說明本發明之原理及其功效,而非用以限制本發明。因此,習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
1...習知半導體元件
2...半導體元件
3...本發明半導體元件之第一實施例
4...本發明半導體元件之第二實施例
5...本發明半導體元件之第三實施例
6...封裝結構
7...基板
8...晶片
9...保護材
11...矽基材
12...電性元件
13...穿導孔結構
14...保護層
15...重佈層
21...矽基材
22...電性元件
23...穿導孔結構
24...保護層
25...光罩
26...導電孔結構
111...第一表面
112...第二表面
113...溝槽
131...第一端
132...第二端
141...表面
142...開口
151...電性連接區域
211...上表面
212...第二表面
213...溝槽
214...第三表面
215...第一表面
231...第一端
232...第二端
233...外絕緣層
234...導體
235...第二中心槽
236...第一中心槽
237...內絕緣層
241...上表面
242...穿孔
243...第二表面
244...第一部分
245...第二部分
246...第一表面
251...開口
圖1顯示習知半導體元件之剖面示意圖;
圖2顯示圖1之局部放大圖;
圖3至圖10顯示本發明半導體製程之示意圖;
圖11顯示本發明半導體元件之第二實施例之剖面示意圖;
圖12顯示本發明半導體元件之第三實施例之剖面示意圖;及
圖13顯示本發明具有半導體元件之封裝結構之剖面示意圖。
3...本發明半導體元件之第一實施例
21...矽基材
22...電性元件
23...穿導孔結構
24...保護層
212...第二表面
213...溝槽
215...第一表面
231...第一端
232...第二端
233...外絕緣層
234...導體
235...第二中心槽
242...穿孔
243...第二表面
246...第一表面
Claims (17)
- 一種半導體製程,包括:(a)提供一半導體元件,該半導體元件包括一矽基材及至少一導電孔結構,該導電孔結構係位於該矽基材內;(b)移除部分該矽基材,以形成一第一表面,使得該導電孔結構突出於該矽基材之第一表面,而形成一穿導孔結構;(c)形成一保護層於該矽基材之第一表面,該保護層係為感光材料,且具有一上表面,其中該保護層包括一第一部分及一第二部分,該第一部分覆蓋該穿導孔結構,該第二部分之頂部之水平高度係低於該穿導孔結構之頂部之水平高度;(d)提供一光罩於該保護層之上方,以遮住部分該保護層;(e)提供一光源,以照射未被遮住之部分該保護層;及(f)移除部分該保護層,使得該穿導孔結構顯露於該保護層之第一表面。
- 如請求項1之製程,其中該步驟(a)中,該矽基材具有至少一溝槽,該導電孔結構係位於該溝槽內。
- 如請求項1之製程,其中該步驟(a)中,該矽基材具有一上表面,該步驟(b)之前,更包括一從該矽基材之上表面移除部分該矽基材,以形成一第三表面之步驟,該導電孔結構顯露於該矽基材之第三表面,該步驟(b)中,從該 矽基材之第三表面移除部分該矽基材,以形成該矽基材之第一表面。
- 如請求項1之製程,其中該步驟(c)中,係利用旋轉塗佈(Spin Coating)或噴霧塗佈(Spray Coating)方式形成該保護層。
- 如請求項1之製程,其中該步驟(c)中,該保護層之材質係為正型光阻,該步驟(d)中,該光罩遮住該保護層之第二部分,且顯露該保護層之第一部分,該步驟(e)中,該保護層之第一部分經該光源照射後,其分子鍵斷裂,該步驟(f)中,利用一顯影液,移除部分該保護層之第一部分。
- 如請求項1之製程,其中該步驟(c)中,該保護層之材質係為負型光阻,該步驟(d)中,該光罩遮住該保護層之第一部分,且顯露該保護層之第二部分,該步驟(e)中,該保護層之第二部分經該光源照射後,其分子鍵產生交聯反應(Cross-linking Reaction)而硬化,該步驟(f)中,利用一顯影液,移除部分該保護層之第一部分。
- 如請求項1之製程,其中該步驟(f)中,該保護層具有一第一表面及至少一穿孔,該穿孔貫穿該保護層,該穿導孔結構係位於該保護層之穿孔內。
- 如請求項1之製程,其中該步驟(f)中,該穿導孔結構突出於該保護層之第一表面。
- 如請求項8之製程,其中該步驟(f)中,該穿導孔結構具有一第一端,該第一端係突出於該保護層之第一表面, 且與該保護層之第一表面之距離為1μm以上。
- 一種半導體元件,包括:一矽基材,具有一第一表面及至少一溝槽,該溝槽係開口於該矽基材之第一表面;一保護層,位於該矽基材之第一表面,該保護層具有一第一表面及至少一穿孔,該穿孔貫穿該保護層;及至少一穿導孔結構,位於該矽基材之溝槽及該保護層之穿孔內,且突出於該保護層之第一表面,其中該穿導孔結構包括一外絕緣層、一導體及一內絕緣層,該外絕緣層係位於該溝槽之側壁,定義出一第二中心槽,該導體係位於該第二中心槽之側壁,定義出一第一中心槽,該內絕緣層填滿該第一中心槽。
- 如請求項10之半導體元件,其中該保護層係為感光材料。
- 如請求項11之半導體元件,其中該保護層係為正型光阻或負型光阻。
- 如請求項10之半導體元件,其中該穿導孔結構具有一第一端,該第一端係突出於該保護層之第一表面,且與該保護層之第一表面之距離為1μm以上。
- 一種具有半導體元件之封裝結構,包括:一基板;一半導體元件,位於該基板上,且電性連接至該基板,包括:一矽基材,具有一第一表面及至少一溝槽,該溝槽 係開口於該矽基材之第一表面;一保護層,位於該矽基材之第一表面,該保護層具有一第一表面及至少一穿孔,該穿孔貫穿該保護層;及至少一穿導孔結構,位於該矽基材之溝槽及該保護層之穿孔內,且突出於該保護層之第一表面,其中該穿導孔結構包括一外絕緣層、一導體及一內絕緣層,該外絕緣層係位於該溝槽之側壁,定義出一第二中心槽,該導體係位於該第二中心槽之側壁,定義出一第一中心槽,該內絕緣層填滿該第一中心槽;一晶片,位於該半導體元件上,且電性連接至該半導體元件;及一保護材,位於該基板上,包覆該半導體元件及該晶片。
- 如請求項14之封裝結構,其中該保護層係為感光材料。
- 如請求項15之封裝結構,其中該保護層係為正型光阻或負型光阻。
- 如請求項14之封裝結構,其中該穿導孔結構具有一第一端,該第一端係突出於該保護層之第一表面,且與該保護層之第一表面之距離為1μm以上。
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US7863187B2 (en) | 2005-09-01 | 2011-01-04 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
TWI414044B (zh) * | 2009-12-29 | 2013-11-01 | Advanced Semiconductor Eng | 半導體製程、半導體元件及具有半導體元件之封裝結構 |
US20130313710A1 (en) * | 2012-05-22 | 2013-11-28 | Micron Technology, Inc. | Semiconductor Constructions and Methods of Forming Semiconductor Constructions |
TWI503934B (zh) | 2013-05-09 | 2015-10-11 | Advanced Semiconductor Eng | 半導體元件及其製造方法及半導體封裝結構 |
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US20070145518A1 (en) * | 2005-12-28 | 2007-06-28 | Casio Computer Co., Ltd. | Circuit board, semiconductor device, and manufacturing method of circuit board |
TW200932040A (en) * | 2007-11-30 | 2009-07-16 | Sumitomo Chemical Co | Electronic device, display device and method for producing electronic device |
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US7648815B2 (en) * | 2000-09-12 | 2010-01-19 | Pi R&D Co., Ltd. | Negative photosensitive polyimide composition and method for forming image the same |
TWI383251B (zh) * | 2008-01-16 | 2013-01-21 | Eternal Chemical Co Ltd | 感光型聚醯亞胺 |
KR20100021856A (ko) * | 2008-08-18 | 2010-02-26 | 삼성전자주식회사 | 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치 |
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TWI406380B (zh) * | 2009-09-23 | 2013-08-21 | Advanced Semiconductor Eng | 具有穿導孔之半導體元件及其製造方法及具有穿導孔之半導體元件之封裝結構 |
TWI414044B (zh) * | 2009-12-29 | 2013-11-01 | Advanced Semiconductor Eng | 半導體製程、半導體元件及具有半導體元件之封裝結構 |
US8466060B2 (en) * | 2010-04-30 | 2013-06-18 | Alpha & Omega Semiconductor, Inc. | Stackable power MOSFET, power MOSFET stack, and process of manufacture |
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US20070145518A1 (en) * | 2005-12-28 | 2007-06-28 | Casio Computer Co., Ltd. | Circuit board, semiconductor device, and manufacturing method of circuit board |
TW200932040A (en) * | 2007-11-30 | 2009-07-16 | Sumitomo Chemical Co | Electronic device, display device and method for producing electronic device |
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US20110156268A1 (en) | 2011-06-30 |
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