TWI423357B - 積體電路元件的形成方法 - Google Patents

積體電路元件的形成方法 Download PDF

Info

Publication number
TWI423357B
TWI423357B TW099141650A TW99141650A TWI423357B TW I423357 B TWI423357 B TW I423357B TW 099141650 A TW099141650 A TW 099141650A TW 99141650 A TW99141650 A TW 99141650A TW I423357 B TWI423357 B TW I423357B
Authority
TW
Taiwan
Prior art keywords
photoresist film
opening
forming
layer
photoresist
Prior art date
Application number
TW099141650A
Other languages
English (en)
Other versions
TW201207967A (en
Inventor
Chen Cheng Kuo
Chen Shien Chen
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201207967A publication Critical patent/TW201207967A/zh
Application granted granted Critical
Publication of TWI423357B publication Critical patent/TWI423357B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11474—Multilayer masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01038—Strontium [Sr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

積體電路元件的形成方法
本發明係關於一種製造積體電路元件的方法，更特別關於一種製造半導體積體電路中凸塊結構的方法。
現有的積體電路係由橫向排列之百萬個主動元件如電晶體及電容所組成。這些元件在初步製程中彼此絕緣，但在後段製程中將以內連線連接元件以形成功能電路。一般的內連線結構包含橫向內連線如金屬線路，與垂直內連線如通孔與接點。現有的積體電路其效能與密度的上限取決於內連線。在內連線結構的頂部上方，每一晶片表面上各自有對應的接合墊。經由接合墊，晶片可電性連接至封裝基板或其他晶粒。接合墊可應用於打線接合或覆晶接合。在覆晶封裝中，凸塊可在封裝結構的導線架或基板，與晶片的輸出/輸入墊之間形成電性接觸。上述凸塊結構除了凸塊本身，還具有凸塊與輸出/輸入墊之間的凸塊下冶金層(UBM)。UBM通常含有黏著層、阻障層、與潤濕層依序形成於輸入/輸出墊上。凸塊的分類可依材質分為焊料凸塊、金凸塊、銅柱凸塊、或混合金屬凸塊。近來發展的銅柱凸塊技術中，採用銅柱凸塊而非焊料凸塊將電子構件連接至基板。銅柱凸塊的間距較小，其短路橋接的可能性較低，可降低電路的電容負載並提高電子構件的操作頻率。
在採用銅柱的完全覆晶封裝中，不論是測試或組裝後使用均發現熱應力問題如超低介電常數(ELK)之介電材料的分層，或底填材料、保護層、及預焊材料的碎裂。上述材料分層會碎裂的原因為銅柱周圍的上述材料，在熱循環時會產生實質上的熱應力。當積體電路元件的尺寸持續縮減，終端與銅柱之間的間距亦隨之縮減。如此一來，採用銅柱的相關熱應力問題必然增加。在習知採用銅柱的積體電路覆晶封裝中，先以單一光阻層如乾膜或濕膜搭配微影製程在UBM層上定義一開口，再以電鍍法沉積銅層以形成具有垂直側壁或傾斜側壁之銅柱。然而，習知方法難以增加銅柱的底部尺寸，且無法將應力分攤至UBM層與保護層之間的界面。綜上所述，目前亟需一種改良的積體電路覆晶連線如銅柱以解決熱應力的問題。
本發明一實施例提供一種積體電路元件的形成方法，包括形成凸塊下冶金層於半導體基板上；形成光阻結構於凸塊下冶金層上，其中光阻結構包括第一光阻膜與位於第一光阻膜上的第二光阻膜，且第一光阻膜之光敏性不同於第二光阻膜之光敏性；形成開口於光阻結構中以露出部份的凸塊下冶金層，其中開口包括第一開口位於第一光阻膜中及第二開口位於第二光阻膜中，且第一開口之底部直徑大於第一開口之頂部直徑；形成導電層於光阻結構之開口中，且導電層電性連接至露出的部份凸塊下冶金層；以及移除光阻結構，其中導電層形成導電柱。
本發明又一實施例提供一種積體電路元件的形成方法，包括形成凸塊下冶金層於半導體基板上；形成第一光阻膜於凸塊下冶金層上，第一光阻膜具有第一厚度與第一光敏性；形成第二光阻膜於第一光阻膜上，且第二光阻膜具有第二厚度與第二光敏性；其中第二光敏性大於第一光敏性，且第二厚度大於第一厚度；進行曝光製程至第二光阻膜與第一光阻膜；移除未曝光的部份第二光阻膜以形成第一開口；移除未曝光的部份第一光阻膜以露出部份凸塊下冶金層，形成第二開口於第一開口下，以及形成第三開口於第二開口下；其中第一光阻膜圍繞第二開口，且第二開口之底部直徑大於第二開口之頂部直徑；形成銅層於第一開口、第二開口、與第三開口中以電性連接至露出的部份凸塊下冶金層；以及移除第二光阻膜與第一光阻膜，其中銅層形成銅柱。
本發明再一實施例提供一種積體電路元件的形成方法，包括形成凸塊下冶金層於半導體基板上；形成第一光阻膜於凸塊下冶金層上，第一光阻膜具有第一厚度與第一光敏性；形成第二光阻膜於第一光阻膜上，且第二光阻膜具有第二厚度與第二光敏性；其中第一光敏性大於第二光敏性，且第二厚度大於第一厚度；進行曝光製程至第二光阻膜與第一光阻膜；移除曝光的部份第二光阻膜以形成第一開口；移除曝光的部份第一光阻膜以露出部份凸塊下冶金層，形成第二開口於第一開口下，以及形成第三開口於第二開口下；其中第一光阻膜圍繞第二開口，且第二開口之底部直徑大於第二開口之頂部直徑；形成銅層於第一開口、第二開口、與第三開口中以電性連接至露出的部份凸塊下冶金層；以及移除第二光阻膜與第一光阻膜，其中銅層形成銅柱。
下述說明將揭露形成銅柱的方法，其基腳形狀可應用於覆晶組裝、晶圓等級的晶片尺寸封裝(WLCPS)、三維積體電路堆疊、及/或任何進階的封裝技術領域。圖示將搭配標號以說明實施例。圖示及對應說明盡可能採用相同標號標示相同或類似的部份。圖示中結構的形狀及厚度可能會誇大以突顯結構特點。下列說明將直接針對裝置的構成要素或操作要素。可以理解的是，本技藝人士可自行調整或變化未特別顯示或敘述的要素。此外，當某層被在另一層上時，指的可能是直接位於另一層上或兩者間隔有其他層。
在下述說明中，「一實施例」指的是特定特徵、結構、或至少一實施例中包含的實施例所連結的結構。因此，不同段落中的「一實施例」指的不一定是同一實施例。此外，一或多個實施例中的特定特徵、結構、或特點可由任何合適態樣組合。可以理解的是，下述圖示並非依比例繪示，僅用以方便說明而已。
第1A至1G圖係本發明一實施例中，採用負光阻形成積體電路中銅柱的製程剖視圖。如第1圖所示，半導體基板10可用以形成凸塊以製備積體電路元件，且積體電路可形成於半導體基板10中及/或其上。半導體基板10的定義為半導體材料，包括但不限定於基體矽、半導體晶圓、絕緣層上矽(SOI)基板、或矽鍺基板。其他適用於半導體基板10之半導體材料可採用III族、IV族、或V族元素。半導體基板10可更包含複數個絕緣結構(未圖示)，如淺溝槽絕緣(STI)結構或區域氧化矽(LOCOS)結構。絕緣結構可絕緣複數個微電子元件(未圖示)。上述形成於半導體基板10中的微電子元件可為金氧半場效電晶體(MOSFET)、互補式金氧半(CMOS)電晶體、雙極性接面電晶體(BJT)、高電壓電晶體、高頻電晶體、p通道及/或n通道場效電晶體、或其他電晶體，電阻，二極體，電容，電感，熔絲，或其他合適元件。不同的微電子元件的形成方法可包含不同製程如沉積、蝕刻、佈植、微影、回火、或他合適製程。微電子元件可藉由內連線形成積體電路元件如邏輯元件、記憶元件(例如靜態隨機存取記憶體，SRAM)、射頻(RF)元件、輸入/輸出(I/O)元件、單晶片系統(SoC)元件、上述之組合、或其他合適型態的元件。
半導體基板10可具有層間介電層與金屬結構形成於積體電路上。層間介電層可為低介電常數之介電材料、未掺雜之矽酸鹽玻璃(USG)、氮化矽、氮氧化矽、或其他一般常用材料。低介電常數之介電材料其介電常數(k)可小於約3.9，或小於約2.8。金屬結構中的金屬線路可由銅或銅合金組成。金屬結構與層間介電層的形成方法為本技藝人士所熟知，在此不贅述。
導電區12為形成於最頂層之層間介電層上的金屬層。導電區12為導電線路的一部份，其露出的表面可視情況進行平坦化製程如化學機械研磨(CMP)。適用於導電區12的材料可為但不限定於銅、鋁、銅合金、或其他現有的導電材料。在某些實施例中，導電區12作為墊區以用於接合製程，可將每一晶片中的積體電路連接至外部結構。在某些實施例中，導電區12為再佈線層，亦稱為後保護內連線(PPI)線路。
保護層14係形成於半導體基板10上。圖案化保護層14可形成開口露出部份的導電區12，以利後續製程形成凸塊。在某些實施例中，保護層14之組成可為未掺雜矽酸鹽玻璃(USG)、氮化矽、氮氧化矽、氧化矽、或上述之組合。在某些實施例中，保護層14之組成為高分子層如環氧樹脂、聚亞醯胺、雙苯並環丁烷(BCB)、聚苯并噁唑(PBO)、或其他較軟的有機介電材料。
高分子層16係形成於保護層14上。圖案化高分子層16可形成開口露出部份的導電區12，以利後續製程形成凸塊。高分子層16中的開口可小於、等於、或大於保護層14中的開口。在某些實施例中，高分子層16之組成為高分子如環氧樹脂、聚亞醯胺、雙苯並環丁烷(BCB)、聚苯并噁唑(PBO)、或其他較軟的有機介電材料。在某些實施例中，高分子層16為聚亞醯胺層。在某些實施例中，高分子層16為聚苯并噁唑(PBO)層。
第1A圖亦顯示凸塊下冶金(UBM)層18形成於半導體基板10上。UBM層18係形成於導電區12的露出部份上，並延伸至高分子層16上。在某些實施例中，UBM層16包含作為擴散阻障層或黏著層的第一層，其組成可為鈦、鉭、氮化鈦、氮化鉭、或類似物，且其形成方法可為物理氣相沉積法(PVD)或濺鍍法。第一層之沉積厚度介於約500至2000之間。在某些實施例中，UBM層16包含作為晶種層的第二層，其組成可為銅或銅合金，且其形成方法可為PVD或濺鍍法。第二層之沉積厚度介於約500至10000之間。
如第1B圖所示，光阻結構20係形成於UBM層18上。光阻結構20為堆疊結構，包含至少兩層不同光敏性的光阻膜。每一光阻膜可為正光阻膜或負光阻膜，取決於這些光阻膜在曝光時的化學變化性。若光阻膜在曝光後具有較佳的化學穩定性，則此光阻膜為負光阻膜。若採用負光阻，則未曝光之負光阻部份將被顯影移除。若光阻膜在曝光後具有較差的化學穩定性，則此光阻膜為正光阻膜。若採用正光阻，則曝光之正光阻部份將被顯影移除。在一實施例中，光阻結構20包含第一光阻膜22，與位於第一光阻膜22上的第二光阻膜24。第一光阻膜22為負光阻，具有第一光敏性及第一厚度。第二光阻膜24為負光阻，具有第二光敏性及第二厚度。第二光敏性比第一光敏性大，且第一厚度小於第二厚度。舉例來說，第一光阻膜22之第一厚度約介於3μm至15μm之間，而第二光阻膜24之第二厚度約介於40μm至85μm之間。
接著如第1C圖所示，進行單一曝光製程以圖案化光阻結構20，其曝光光源可為深紫外線(DUV)、中紫外線(MUV)、或X光射線。在其他實施例中，光阻結構20之曝光源為電子束微影的能量化電子。搭配光罩26，光子或電子能量可使光阻結構20的曝光部份之組成產生化學變化，例如交聯、斷鏈、或移除支鏈等等。光阻可進行預烘烤或後烘烤製程，這將最大化光阻中曝光部份與未曝光部份之間的化學性質變化差異。由於第一光阻膜22與第二光阻膜24為負光阻，光阻結構20其未曝光的部份將被顯影移除以露出部份的UBM層18。
上述微影製程將形成開口20a於光阻結構20中。開口20a包含藉由移除未曝光的第一光阻膜22所形成的第一開口22a，以及藉由移除未曝光的第二光阻膜24所形成的第二開口24a。第二開口24a具有實質上垂直的側壁24s。在第一開口22a中，更包含被UBM層18露出的部份所包圍之較低部份22a1 ，以及被第一光阻膜22保留的部份所包圍的較高部份22a2 。總體來說，較高部份22a2 其底部直徑D1b 大於頂部直徑D1t ，且第一電阻膜22保留的部份其傾斜的側壁表面22s與UBM層18之夾角θ小於90度。如此一來，鳥嘴開口22b將形成於第一光阻膜22與UBM層18的界面之間。此外，第一開口22a其較高部份22a2的底部直徑比第二開口24a的直徑D2 寬。在某些實施例中，直徑D1b 與直徑D2 的差距大於約3μm。在後續製程中，導電材料將填入開口中，即完成具有基腳形狀的導電柱。
如第1D圖所示，將具有焊料潤濕性的導電材料形成於開口22a及24a中。在某些實施例中，係將銅層28填入第一開22a以接觸其下的UBM層18。沉積銅層28的作法可連續性地將其填入第二開口24a直到預定的高度。在本揭露中，所謂的銅層實質上包含純元素銅、含有無可避免之雜質的銅、或次要成份為鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁、或鋯的銅合金。銅層28的形成方法可為濺鍍、印刷、電鍍、無電電鍍、或化學氣相沉積法(CVD)。舉例來說，電化學電鍍法(ECP)可用以形成銅層28。在某些實施例中，ECP製程之起始沉積速率較慢以達到「填隙」效果，這可幫助電鍍銅層填入鳥嘴開口22b，進而使銅層28之基腳形狀能貼近UBM層18。在一實施例中，銅層28之高度H1 定義為最低表面至最高表面的距離，可大於25μm。在某些實施例中，銅層28之高度H1 大於40μm。舉例來說，銅層28之高度H1 介於約40μm至50μm之間，或介於40μm至70μm之間，但銅層28之高度H1 可大於或小於上述範圍。在某些實施例中，第二開口24a實質上填入銅層28，且銅層28之上表面低於第二光阻膜24的上表面。在其他實施例中(未圖示)，可控制銅層的沉積製程以將其填入開口24a，並使銅層的上表面高於或等高於第二光阻膜24的上表面。
接著如第1E圖所示，蓋層30與焊料層32係成功地形成於第二開口24a中的銅層28其上表面上。在某些實施例中，蓋層30可作為擴散阻障層，以避免銅柱中的銅擴散至接合材料如焊料合金。上述接合材料係用以接合半導體基板10至外部結構。避免銅擴散可增加封裝的接合強度與可信度。蓋層30包含下列材料中至少一者：鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、其他類似材料、或電鍍法沉積之合金。蓋層30之厚度約介於1μm至10μm之間。在某些實施例中，蓋層30為多層結構，其中的每一層包含下列材料中至少一者：鎳、金、鈀、鎳為主合金、金為主合金、或鈀為主合金。在某些實施例中，蓋層30為鎳膜或鎳合金膜，其形成方法可為電極電鍍製程、無電電鍍製程、或含浸電鍍製程。
焊料層32可為錫、錫銀、錫鉛、銅之重量%小於0.3%的錫金銅、錫銀鋅、錫鋅、錫鉍銦、錫銦、錫金、錫鉛、錫銅、錫鋅銦、錫銀錫、或類似物，其形成方法可為電鍍製程。在某些實施例中，焊料層32為無鉛焊料層。在無鉛焊料系統中，焊料層32為銀含量小於3.0重量%的錫銀。在某些實施例中，無鉛焊料層為銀含量小於2.5重量%的錫銀。
接著如第1F圖所示，移除光阻結構20以露出UBM層18。銅層28形成銅柱。接著移除露出的UBM層18。如第1G圖所示，以銅柱(銅層28)作為遮罩，可移除露出的部份UBM層18並露出其下方的高分子層16。
如第1G圖所示，完成的凸塊結構包含圖案化的UBM層18”、銅層28、蓋層30、與焊料層32。銅層28具有剖面為柱狀的上層部份28a、剖面為梯形的中間部份28b、以及被圖案化UBM層18”包圍的底層部份28c。上層部份28a具有寬度W1 及垂直側壁28v。中間部份28b具有頂寬W2 、底寬W3 、及傾斜側壁28s。中間部份28b的底寬W3 大於頂寬W2 ，且底寬W3 亦大於上層部份28a的寬度W1 。上層部份28a之寬度W1 實質上可等同於中間部份28b之底寬W2 。在某些實施例中，中間部份28b的底寬W3 比頂寬W2 大了約3μm。側壁28s自較寬的上部朝較窄的下部傾斜直到接觸圖案化UBM層18”，兩者之夾角小於90度。上述傾斜的側壁28s使柱狀結構其垂直的側壁28v底部具有基腳形狀。此外，銅層28覆蓋圖案化UBM層18”的部份較寬，可保留較多的UBM材料不致被移除。在複雜的積體電路構件中，上述實施例中的銅柱中不同材料如ELK、UBM、底填材料、預焊料、或焊料凸塊上的熱應力，低於習知技藝中單純柱狀銅柱中上述材料上的熱應力。
接著進行再流動製程以形成再流動的焊料層。接著切割半導體基板10，再以焊球或銅凸塊將其固定於封裝基板或另一晶粒上的墊層上，至此完成封裝結構。
上述方法之微影製程中，形成不同光敏性之負光阻膜的堆疊結構於UBM層上。在較低光阻膜中可形成鳥嘴開口，這將使後續形成的銅柱具有基腳形狀。此方法在不需額外化學或電漿製程的情況下，即可輕易定義基腳形狀的尺寸，這將大幅節省製造成本。
第2A-2D圖係本發明一實施例中，採用正光阻形成積體電路中銅柱的製程剖視圖。下述說明將省略與第1A-1G圖類似或相同的部份。
如第2A圖所示，形成光阻結構40於UBM層18上。光阻結構40為堆疊結構，包含至少兩層不同光敏性的光阻膜。在一實施例中，光阻結構40包含第一光阻膜42，與位於第一光阻膜42上的第二光阻膜44。第一光阻膜42為正光阻，具有第一光敏性及第一厚度。第二光阻膜44為正負光阻，具有第二光敏性及第二厚度。第一光敏性比第二光敏性大，且第一厚度小於第二厚度。舉例來說，第一光阻膜42之第一厚度約介於3μm至15μm之間，而第二光阻膜44之第二厚度約介於40μm至85μm之間。
接著如第2B圖所示，進行單一曝光製程以圖案化光阻結構40，其曝光光源可為DUV、MUV、或X光射線。在其他實施例中，光阻結構40之曝光源為電子束微影的能量化電子。搭配光罩36，光子或電子能量可使光阻結構40的曝光部份之組成產生化學變化，例如交聯、斷鏈、或移除支鏈等等。光阻可進行預烘烤或後烘烤製程，這將最大化光阻中曝光部份與未曝光部份之間的化學性質變化差異。由於第一光阻膜42與第二光阻膜44為正光阻，光阻結構40其曝光的部份將被顯影移除。
上述微影製程將形成開口40a於光阻結構40中。開口40a包含藉由移除曝光的第一光阻膜42所形成的第一開口42a，以及藉由移除曝光的第二光阻膜44所形成的第二開口44a。在第一開口42a中，更包含被UBM層18露出的部份所包圍之較低部份42a1 ，以及被第一光阻膜42保留的部份所包圍的較高部份42a2 。總體來說，較高部份42a2 中，第一電阻膜42保留的部份其傾斜的側壁表面42s與UBM層18之夾角θ小於90度。如此一來，鳥嘴開口42b將形成於第一光阻膜42與UBM層18的界面之間。此外，第一開口42a其較高部份42a2 的底部直徑D1b 比第二開口44a的直徑D2 寬。在後續製程中，導電材料將填入開口中，即完成具有基腳形狀的導電柱。
如第2C圖所示，將銅層28填入開口42a及44a中後，接著形成蓋層30與焊料層32。在某些實施例中，ECP製程之起始沉積速率較慢以達到「填隙」效果，這可幫助電鍍銅層填入鳥嘴開口42b，進而使銅層28之基腳形狀能貼近UBM層18。
接著如第2D圖所示，移除光阻結構40以露出UBM層18。意UBM層18突出的銅層28即銅柱。接著蝕刻移除露出的UBM層18，露出其下方的高分子層16。之後進行再流動製程以形成再流動的焊料層。接著切割半導體基板10，再以焊球或銅凸塊將其固定於封裝基板或另一晶粒上的墊層上，至此完成封裝結構。
上述方法之微影製程中，形成不同光敏性之正光阻膜的堆疊結構於UBM層上。在較低光阻膜中可形成鳥嘴開口，這將使後續形成的銅柱具有基腳形狀。此方法在不需額外化學或電漿製程的情況下，即可輕易定義基腳形狀的尺寸，這將大幅節省製造成本。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
θ．．．保留的第一電阻膜側壁與凸塊下冶金層之間的夾角
D1b ．．．第一開口其較高部份之底部直徑
D1t ．．．第一開口其較高部份之頂部直徑
D2 ．．．第二開口的直徑
H1 ．．．銅層高度
W1 ．．．銅層之上層部份的寬度
W2 ．．．銅層之中間部份的頂寬
W3 ．．．銅層之中間部份的底寬
10．．．半導體基板
12．．．導電區
14．．．保護層
16．．．高分子層
18．．．凸塊下冶金層
18”．．．圖案化的凸塊下冶金層
20、40．．．光阻結構
20a、40a．．．開口
22、42．．．第一光阻膜
22a、42a．．．第一開口
22a1 、42a1 ．．．第一開口之較低部份
22a2 、42a2 ．．．第一開口之較高部份
22b、42b．．．鳥嘴開口
22s．．．保留的第一電阻膜側壁表面
24、44．．．第二光阻膜
24a、44a．．．第二開口
24s、44s．．．第二開口的側壁
26、36．．．光罩
28．．．銅層
28a．．．銅層的上層部份
28b．．．銅層的中間部份
28c．．．銅層的底層部份
28s．．．銅層之中間部份的側壁
28v．．．銅層之上層部份的側壁
30．．．蓋層
32．．．焊料層
第1A至1G圖係本發明一實施例中，採用負光阻形成積體電路中銅柱的製程剖視圖；以及
第2A-2D圖係本發明一實施例中，採用正光阻形成積體電路中銅柱的製程剖視圖。
W1 ．．．銅層之上層部份的寬度
W2 ．．．銅層之中間部份的頂寬
W3 ．．．銅層之中間部份的底寬
10．．．半導體基板
12．．．導電區
14．．．保護層
16．．．高分子層
18”．．．圖案化的凸塊下冶金層
28a．．．銅層的上層部份
28b．．．銅層的中間部份
28c．．．銅層的底層部份
28s．．．銅層之中間部份的側壁
28v．．．銅層之上層部份的側壁
30．．．蓋層
32．．．焊料層

Claims (10)

  1. 一種積體電路元件的形成方法，包括：形成一凸塊下冶金層於一半導體基板上；形成一光阻結構於該凸塊下冶金層上，其中該光阻結構包括一第一光阻膜與位於該第一光阻膜上的一第二光阻膜，且該第一光阻膜之光敏性不同於該第二光阻膜之光敏性；形成一開口於該光阻結構中以露出部份的該凸塊下冶金層，其中該開口包括一第一開口位於該第一光阻膜中及一第二開口位於該第二光阻膜中，且該第一開口之底部直徑大於該第一開口之頂部直徑；形成一導電層於該光阻結構之該開口中，且該導電層電性連接至露出的部份該凸塊下冶金層；以及移除該光阻結構，其中該導電層形成一導電柱。
  2. 如申請專利範圍第1項所述之積體電路元件的形成方法，其中該第一光阻膜與該第二光阻膜之組成為負光阻材料，且該第二光阻膜之光敏性大於該第一光阻膜之光敏性。
  3. 如申請專利範圍第1項所述之積體電路元件的形成方法，其中該第一光阻膜與該第二光阻膜之組成為正光阻材料，且該第一光阻膜之光敏性大於該第二光阻膜之光敏性。
  4. 如申請專利範圍第1項所述之積體電路元件的形成方法，其中該第一光阻膜比該第二光阻膜厚，且該第二開口之直徑小於該第一開口之底部直徑。
  5. 如申請專利範圍第1項所述之積體電路元件的形成方法，更包括在移除該光阻結構之步驟前，先形成一蓋層於該開口中的該導電層上，以及形成一焊料層於該蓋層上，其中該蓋層包括鎳或鎳合金兩者中至少一者。
  6. 如申請專利範圍第1項所述之積體電路元件的形成方法，其中該導電層包括銅或銅合金兩者中至少一者。
  7. 一種積體電路元件的形成方法，包括：形成一凸塊下冶金層於一半導體基板上；形成一第一光阻膜於該凸塊下冶金層上，該第一光阻膜具有一第一厚度與一第一光敏性；形成一第二光阻膜於該第一光阻膜上，且該第二光阻膜具有一第二厚度與一第二光敏性；其中該第二光敏性大於該第一光敏性，且該第二厚度大於該第一厚度；進行一曝光製程至該第二光阻膜與該第一光阻膜；移除未曝光的部份該第二光阻膜以形成一第一開口；移除未曝光的部份該第一光阻膜以露出部份該凸塊下冶金層，形成一第二開口於該第一開口下，以及形成一第三開口於該第二開口下；其中該第一光阻膜圍繞該第二開口，且該第二開口之底部直徑大於該第二開口之頂部直徑；形成一銅層於該第一開口、該第二開口、與該第三開口中以電性連接至露出的部份該凸塊下冶金層；以及移除該第二光阻膜與該第一光阻膜，其中該銅層形成一銅柱。
  8. 如申請專利範圍第7項所述之積體電路元件的形成方法，其中該第二開口之側壁與該凸塊下冶金層交會之夾角小於90度，其中該第二開口之底部直徑比該第二開口之頂部直徑大2μm以上。
  9. 一種積體電路元件的形成方法，包括：形成一凸塊下冶金層於一半導體基板上；形成一第一光阻膜於該凸塊下冶金層上，該第一光阻膜具有一第一厚度與一第一光敏性；形成一第二光阻膜於該第一光阻膜上，且該第二光阻膜具有一第二厚度與一第二光敏性；其中該第一光敏性大於該第二光敏性，且該第二厚度大於該第一厚度；進行一曝光製程至該第二光阻膜與該第一光阻膜；移除曝光的部份該第二光阻膜以形成一第一開口；移除曝光的部份該第一光阻膜以露出部份該凸塊下冶金層，形成一第二開口於該第一開口下，以及形成一第三開口於該第二開口下；其中該第一光阻膜圍繞該第二開口，且該第二開口之底部直徑大於該第二開口之頂部直徑；形成一銅層於該第一開口、該第二開口、與該第三開口中以電性連接至露出的部份該凸塊下冶金層；以及移除該第二光阻膜與該第一光阻膜，其中該銅層形成一銅柱。
  10. 如申請專利範圍第9項所述之積體電路元件的形成方法，其中該第二開口之側壁與該凸塊下冶金層交會之夾角小於90度，其中該第二開口之底部直徑比該第二開口之頂部直徑大2μm以上。
TW099141650A 2010-08-12 2010-12-01 積體電路元件的形成方法 TWI423357B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/855,360 US8598030B2 (en) 2010-08-12 2010-08-12 Process for making conductive post with footing profile

Publications (2)

Publication Number Publication Date
TW201207967A TW201207967A (en) 2012-02-16
TWI423357B true TWI423357B (zh) 2014-01-11

Family

ID=45565131

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099141650A TWI423357B (zh) 2010-08-12 2010-12-01 積體電路元件的形成方法

Country Status (3)

Country Link
US (2) US8598030B2 (zh)
CN (1) CN102376638B (zh)
TW (1) TWI423357B (zh)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US8823166B2 (en) 2010-08-30 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar bumps and process for making same
US9105588B2 (en) * 2010-10-21 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer
KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
TWI456676B (zh) * 2012-02-17 2014-10-11 Chipbond Technology Corp 微細間距凸塊製造方法及其結構
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
TWI484610B (zh) * 2012-07-09 2015-05-11 矽品精密工業股份有限公司 半導體結構之製法與導電凸塊
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
TWI473227B (zh) * 2012-11-15 2015-02-11 矽品精密工業股份有限公司 基板之連接結構及其製法
CN103219305B (zh) * 2013-04-18 2016-04-06 南通富士通微电子股份有限公司 凸点底部保护结构
US9295163B2 (en) 2013-05-30 2016-03-22 Dyi-chung Hu Method of making a circuit board structure with embedded fine-pitch wires
JP2014241320A (ja) * 2013-06-11 2014-12-25 ソニー株式会社 半導体装置、半導体装置の製造方法
TWI576870B (zh) 2013-08-26 2017-04-01 精材科技股份有限公司 電感結構及其製作方法
TWI511251B (zh) * 2013-09-06 2015-12-01 矽品精密工業股份有限公司 半導體裝置及其製法與半導體結構
DE112013007511B4 (de) * 2013-10-17 2021-07-22 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung einer Vielzahl von oberflächenmontierbaren Trägervorrichtungen, Anordnung einer Vielzahl von oberflächenmontierbaren Trägervorrichtungen und oberflächenmontierbare Trägervorrichtung
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US10090267B2 (en) * 2014-03-13 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd Bump structure and method for forming the same
CN104952735B (zh) * 2014-03-25 2018-10-16 中芯国际集成电路制造(上海)有限公司 具有金属柱的芯片封装结构及其形成方法
US20150279793A1 (en) 2014-03-27 2015-10-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9214454B2 (en) * 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10269752B2 (en) * 2014-09-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package with UBM and methods of forming
US10147692B2 (en) 2014-09-15 2018-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package with UBM and methods of forming
CN104465426B (zh) * 2014-12-25 2018-04-27 颀中科技（苏州）有限公司 凸块的制作方法
WO2017073350A1 (ja) * 2015-10-30 2017-05-04 株式会社村田製作所 薄膜素子およびその製造方法
CN105977177A (zh) * 2016-05-11 2016-09-28 上海华虹宏力半导体制造有限公司 解决半导体测试失败的半导体结构以及半导体测试方法
US9905522B1 (en) * 2016-09-01 2018-02-27 Semiconductor Components Industries, Llc Semiconductor copper metallization structure and related methods
CN106783637A (zh) * 2016-12-30 2017-05-31 通富微电子股份有限公司 一种芯片及其制造方法
US10593638B2 (en) * 2017-03-29 2020-03-17 Xilinx, Inc. Methods of interconnect for high density 2.5D and 3D integration
JP7117615B2 (ja) * 2017-12-08 2022-08-15 パナソニックＩｐマネジメント株式会社 半導体装置の製造方法
CN109920787B (zh) * 2017-12-12 2021-05-25 中芯国际集成电路制造(北京)有限公司 互连结构的设计方法、装置及制造方法
TWI678743B (zh) * 2018-12-10 2019-12-01 南茂科技股份有限公司 半導體線路結構及其製作方法
US20200411317A1 (en) * 2019-06-26 2020-12-31 Intel Corporation Integrated circuit package assemblies with high-aspect ratio metallization features
KR20210126188A (ko) 2020-04-09 2021-10-20 삼성전자주식회사 반도체 소자
WO2023026984A1 (ja) * 2021-08-26 2023-03-02 ローム株式会社 電子部品

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586322B1 (en) * 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960016007B1 (ko) * 1993-02-08 1996-11-25 삼성전자 주식회사 반도체 칩 범프의 제조방법
US6962771B1 (en) 2000-10-13 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene process
CN101154049A (zh) * 2006-09-29 2008-04-02 中国科学院长春光学精密机械与物理研究所 一种制备光刻胶图形的方法
US8259464B2 (en) * 2010-06-24 2012-09-04 Maxim Integrated Products, Inc. Wafer level package (WLP) device having bump assemblies including a barrier metal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586322B1 (en) * 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers

Also Published As

Publication number Publication date
CN102376638B (zh) 2013-12-25
TW201207967A (en) 2012-02-16
US8716123B2 (en) 2014-05-06
US20120040524A1 (en) 2012-02-16
CN102376638A (zh) 2012-03-14
US8598030B2 (en) 2013-12-03
US20140051244A1 (en) 2014-02-20

Similar Documents

Publication Publication Date Title
TWI423357B (zh) 積體電路元件的形成方法
US10734347B2 (en) Dummy flip chip bumps for reducing stress
TWI411080B (zh) 半導體元件、封裝結構、及半導體元件的形成方法
US9685372B2 (en) Method of forming Cu pillar bump with non-metal sidewall spacer and metal top cap
US9355977B2 (en) Bump structures for semiconductor package
TWI552297B (zh) 半導體裝置及其製造方法
CN102403290B (zh) 半导体组件及制造半导体组件的方法
TWI459523B (zh) 封裝裝置、積體電路元件及其製作方法
US8669174B2 (en) Multi-die stacking using bumps with different sizes
US10128206B2 (en) Conductive pillar structure
US10163862B2 (en) Package structure and method for forming same
KR102650296B1 (ko) 범프 구조물을 갖는 반도체 디바이스 및 반도체 디바이스의 제조 방법
US8581399B2 (en) Metal bump structure
US10157831B2 (en) Semiconductor device having a conductive via structure
TWI419285B (zh) 基板上的凸塊結構與其形成方法
US20190273054A1 (en) Substrate structure and method for fabricating the same
CN118116893A (zh) 半导体封装结构及其形成方法
CN115565980A (zh) 半导体装置结构及其形成方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees