TWI402957B - 半導體元件及其製法 - Google Patents

半導體元件及其製法 Download PDF

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TWI402957B
TWI402957B TW098144942A TW98144942A TWI402957B TW I402957 B TWI402957 B TW I402957B TW 098144942 A TW098144942 A TW 098144942A TW 98144942 A TW98144942 A TW 98144942A TW I402957 B TWI402957 B TW I402957B
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semiconductor substrate
liner
semiconductor device
fabricating
semiconductor
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TW201027704A (en
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Ming Fa Chen
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Taiwan Semiconductor Mfg
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Description

半導體元件及其製法
本發明係有關於一種積體電路(integrated circuit)，且特別是有關於一種具有矽通孔(through-silicon via)之半導體元件。
自從積體電路(integrated circuit,IC)發明以來，由於各種電子元件(例如：電晶體、二極體、電阻、電容等)的積體密度(integration density)持續改善，致使半導體工業經歷了快速的成長。積體密度(integration density)的改善主要係來自於最小特徵尺寸(minimum feature size)的遞減，因而能夠將更多元件整合在一指定區域中。
這些積體密度(integration density)的改善基本上是二維(2D)空間的改善，改善這些積體元件在半導體晶圓表面上所佔據的體積。雖然在微影(lithography)製程方面的技術改革已大幅改善二維(2D)積體電路(IC)結構，然而在二維空間內可達成之密度仍有其物理上的極限，而這些極限之一就是製作這些元件所需要之最小尺寸。此外，當越多元件需設置於單一晶片時，則需要越複雜的晶片設計。
為了更進一步增加電路密度，已有研究開始發展三維(3D)積體電路(IC)。在一典型的三維(3D)積體電路(IC)構裝製程中，將兩晶粒(die)黏接在一起，並在基材上的每一晶粒(die)與接觸墊(contact pad)之間形成電性連接(electrical connection)。例如，試圖將兩晶粒(die)以彼此頂端對頂端的方式互相接合。隨後再將此堆疊好的晶粒(die)接合到一載體基材(carrier substrate)上，並利用銲線(wire bond)接合使每一晶粒(die)上的接觸墊(contact pad)與載體基材(carrier substrate)上的接觸墊(contact pad)之間形成電性連接。然而，為了形成銲線連接(wire bonding)，此種研究需要一面積大於晶粒(die)的載體基材(carrier substrate)。
最近有越來越多的研究著重於矽通孔(through-silicon via,TSVs)。一般而言，藉由蝕刻一通過基材的垂直通道，並將導電材料(例如銅)填充於該通道中而形成矽通孔(TSVs)。在將導電材料(例如銅)填充於該通道中之前，沿著該通道的側壁形成一介電質襯層(liner)，該介電質襯層(liner)通常為四乙基矽酸鹽(tetra-ethyl ortho-silicate,TEOS)。然而，四乙基矽酸鹽(TEOS)的介電常數(dielectric constant)約為4.2，因此造成潛在的大電容。此大電容可能會對電阻電容(RC)電路的效能表現產生負面影響。
因此業界亟需要一種形成矽通孔(TSVs)較佳的結構與方法。
為減輕、解決或預防讓上述及其他問題，並且實現技術上的優勢，下文特舉出本發明之實施例，其提供具有矽通孔(through-silicon via)之半導體元件。
本發明提供一種半導體元件，包括：一具有一電路側(circuit side)與一相對於該電路側之背側(backside)之半導體基材；一矽通孔延伸穿過該半導體基材；以及一第一介電層設置於該矽通孔與該半導體基材之間，其中該第一介電層延伸至該半導體基材之背側表面之至少一部分上。
本發明另外提供一種半導體元件之製法，包括以下步驟，其中該製法包括：提供一半導體基材，其中該半導體基材具有一第一側與相對於該第一側之第二側；形成一開口從該半導體基材之第一側延伸到該半導體基材之中；形成一第一襯層(liner)沿著該開口之側邊；形成一導電材料於該開口中的第一襯層之上；薄化該半導體基材之第二側，因而曝露至少一部分之第一襯層；移除介於該導體材料與該半導體基材之間的至少一部分第一襯層；以及移除之後，形成一第二襯層於該導電材料與該半導體基材之間。
本發明又包括一種半導體元件之製法，包括以下步驟：提供一半導體基材，其中該半導體基材具有一自電路側(circuit side)延伸且部分穿過該半導體基材之矽通孔，以及一介於該半導體基材與該矽通孔之間的一第一襯層；薄化該半導體基材之背側，因而曝露至少一部分之第一襯層；移除介於該矽通孔與該半導體基材之間的至少一部分第一襯層，因而形成一位於該半導體基材背側之上且圍繞該該矽通孔之開口；以及形成一第二襯層於該開口中。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
以下特舉出本發明之實施例，並配合所附圖式作詳細說明。以下實施例的元件和設計係為了簡化所揭露之發明，並非用以限定本發明。
第1圖到第4圖顯示形成一具有矽通孔(through-silicon via)的晶粒(die)之中間階段，其中矽通孔(through-silicon via)適用於三維(3D)積體電路(例如：一堆疊晶粒結構(stacked die configuration))或一背側接合結構(backside bonding configuration)。在本發明之各實施例與圖式之中，相同的元件用相同的元件參考符號標示。
請參見第1圖，此圖顯示一半導體基材110具有電路112形成於其中。半導體基材110可包括，例如摻雜或未摻雜的矽塊材(bulk silicon)，或一絕緣層上覆半導體(semiconductor-on-insulator,SOI)基材的主動層(active layer)。一般而言，一絕緣層上覆半導體(SOI)基材包括一半導體材料層(例如矽)形成於一絕緣體層上，其中絕緣體層材料可能包括，例如一埋藏氧化層(buried-oxide layer,BOX)或是一氧化矽層。此絕緣體層通常形成在基材上，一般如矽基材或玻璃基材上，也可使用其他基材，例如多層(multi-layered)基材或梯度(gradient)基材。
形成於半導體基材110上的電路112可為適用於特殊應用之任何類型的電路。在一實施例中，此電路包括形成於基材上之電子元件，且此電子元件上覆蓋一或多層介電層。可於介電層之間形成金屬層，藉以傳遞電子元件之間的電子訊號。電子元件也可形成在一或多層介電層中。
舉例而言，電路112可包含多種N型金屬-氧化物半導體(N-type metal-oxide semiconductor,NMOS)及/或P型金屬-氧化物半導體(P-type metal-oxide semiconductor,PMOS)元件，例如電晶體、電容、電阻、二極體、光電二極體(photo-diodes)、保險絲等等，上述元件相互連接以進行一或多種功能。此功能可包括記憶體結構、處理器結構(processing structures)、感測器、放大器、配電系統(power distribution)、輸入/輸出電路(input/output circuitry)等等。本發明所屬技術領域中具有通常知識者應可了解，上述實施例僅為進一步解釋所揭露之發明，並非用以限定本發明。對於一指定的應用，也可使用其他合適的電路。
第1圖也顯示層間介電層(inter-layer dielectric,ILD)116。此層間介電層(ILD)116之組成材料可包括一低介電常數(low-K)材料，例如磷矽玻璃(phosphosilicate glass,PSG)、硼磷矽玻璃(borophosphosilicate glass,BPSG)、氟矽玻璃(fluorinated silicate glass,FSG)、碳氧化矽(SiOx Cy )、旋轉塗佈式玻璃(Spin-On-Glass)、旋轉塗佈式高分子(Spin-On-Polymers)、碳化矽(silicon carbon)材料及其化合物、複合材料或上述之組合等等。而此層間介電層(ILD)116之形成方法可使用此技術領域中所熟知的任何合適方法，例如旋轉塗佈法(spinning)、化學氣相沉積法(chemical vapor deposition,CVD)及電漿增強型化學氣相沉積法(plasma-enhanced CVD,PECVD)。惟須注意的是，層間介電層(ILD)116可包括複數層介電層。
接觸插塞(contact)118係穿透層間介電層(ILD)116而形成，以提供對於電路112之電性接觸(electrical contact)。此接觸插塞(contact)118之形成，例如，係利用微影(photolithography)技術在層間介電層(ILD)116上沉積並圖案化一光阻材料，藉此露出一部分的層間介電層(ILD)116以將其轉變成接觸插塞(contact)118。可利用蝕刻製程，例如非等向性乾式蝕刻製程(anisotropic dry etch process)在層間介電層(ILD)116中製造開口。此開口較佳使用擴散阻障層(diffusion barrier layer)及/或黏著層作為襯層，並且填充導電材料。此擴散阻障層(diffusion barrier layer)較佳包括一或多層之氮化鉭(tantalum nitride,TaN)、鉭(tantalum,Ta)、氮化鈦(titanium nitride,TiN)、鈦(titanium,Ti)、鎢化鈷(CoW)等等。而導電材料包括銅、鎢、鋁、銀及上述之組合，或其他類似之材料，以形成如第1圖所顯示之接觸插塞(contact)118。
一或多層之金屬間介電層(inter-metal dielectric,IMD)120及其相關的金屬層(圖中未顯示)形成於層間介電層(ILD)116上。一般而言，係利用此一或多層之金屬間介電層(IMD)120及其相關的金屬層使電路彼此互相連接，藉以形成外部電性接觸(external electricalconnection)。形成此金屬間介電層(IMD)120的材料較佳為低介電常數(low-K)材料，例如以電漿增強型化學氣相沉積法(PECVD)技術或高密度電漿化學氣相沉積(high-density plasma CVD,HDPCVD)等等方法所形成的氟矽玻璃(FSG)，且此金屬間介電層(IMD)120可能包括中間蝕刻停止層(intermediate etch stop layers)。在金屬間介電層(IMD)的最上層形成接點(contact)122以提供一外部電性連接(external electrical connection)。
值得注意的是，一或多層之蝕刻停止層(etch stop layers)(圖中並未顯示)係形成於相鄰的兩介電層之間，例如，層間介電層(ILD)116與金屬間介電層(IMD)120之間。一般而言，蝕刻停止層(etch stop layers)係於形成通孔(vias)及/或接觸插塞(contact)時，提供停止蝕刻製程的機制。形成此蝕刻停止層(etch stop layers)的材料較佳為具有與相鄰之層(例如，位於下方的半導體基材110、位於上方的層間介電層(ILD)116及金屬間介電層(IMD)120)不同蝕刻選擇性之介電材料。在一實施例中，形成蝕刻停止層(etch stop layers)的材料可包括氮化矽(silicon nitride SiN)、碳氮化矽(silicon nitricarbide,SiCN)、碳氧化矽(silicon oxycarbide,SiCO)、氮化碳(carbon nitride,CN)及上述之組合，或類似之材料，且此蝕刻停止層(etch stop layers)係藉由化學氣相沉積(CVD)或電漿增強型化學氣相沉積法(PECVD)技術所形成。
第1圖中亦顯示出一矽通孔(through-silicon via)124，其係藉由任意適當方法所形成。舉例而言，藉由一或多次之蝕刻製程、研磨、雷射製程等等，形成延伸至半導體基材中110的開口(openings)。此開口較佳於其內側形成一襯層，例如一第一襯層(first liner)126，此襯層係作為隔離層。第一襯層126較佳包括一或多層之四乙基矽酸鹽(TEOS)，然而也可使用其他材料。如同下文之詳細說明，由於在隨後的製程步驟中，將移除一部分之第一襯層126，因此第一襯層126需使用一既容易加工又容易移除，同時對其他結構造成很少傷害或幾乎不造成傷害之材料。
可於第一襯層(first liner)126之表面上形成且圖案化得到保護層130，例如一聚亞醯胺(polyimide)材料。之後藉由例如電鍍(electroplating)技術將導電材料(例如銅、鎢、鋁、銀及其組合等等)填充於開口中，以形成矽通孔124。也可使用其他材料，包括導電擴散阻障層(conductive diffusion barrier layer)，例如氮化鉭(tantalum nitride,TaN)、鉭(tantalum,Ta)、氮化鈦(titanium nitride,TiN)、鈦(titanium,Ti)、鎢化鈷(CoW)，或類似之材料。
接觸插塞(contact)132，例如由銅、鎢、錫銅合金(CuSn)、錫金合金(AuSn)、金銦合金(InAu)、錫鉛合金(PbSn)，或類似之材料所形成的金屬凸塊(metal bumps)，與導線(conductive line)128形成電性接觸，並且利用黏著劑(adhesive)136與載體基材(carrier substrate)134相黏接。一般而言，在後續的製程步驟中，此載體基材134提供暫時的機械與結構支撐。在此方法中，將可降低甚或避免對半導體基材110所造成的傷害。載體基材134可包括，例如玻璃、氧化矽、氧化鋁或類似之材料。黏著劑136可為任何適合之黏著劑，例如一紫外線(UV)膠，當其曝露於紫外線中將會喪失其黏著性。
值得注意的是，第一襯層126所選用的材料必須使第一襯層126與其週遭材料(例如半導體基材110、矽通孔124及任何相關的層間介電層(ILD)116及金屬間介電層(IMD)120及/或蝕刻停止層(etch stop layers)之材料)具有高蝕刻選擇性(high-etch selectivity)。如同下文之詳細說明，在隨後的製程步驟中將移除第一襯層126，高蝕刻選擇性(high-etch selectivity)將使第一襯層126的移除對其他層材料造成很少傷害或幾乎不造成傷害。
值得注意的是，矽通孔124在圖式中係自金屬間介電層(IMD)120之上表面延伸至半導體基材110中，此結構僅為示範之用，因此也可採用其他的排列方式。在另一實施例中，矽通孔124係自層間介電層(ILD)116或半導體基材110之上表面開始延伸。例如，在一實施例中，於形成接觸插塞(contact)118之後，藉由一或多次之蝕刻製程、研磨、雷射製程或其他類似製程，產生延伸至半導體基材中110之開口而形成矽通孔124。上述開口較佳於其內側形成一當作隔離層的襯層，例如第一襯層(first liner)126，並於開口中填充一如上文所述之導電材料。隨後於矽通孔上形成金屬間介電層(IMD)120，並且視需要的利用金屬層(metallization layers)對矽通孔產生外部電性連接。
圖示中的範例也顯示，用以形成矽通孔124的導電材料延伸至介電層(例如金屬間介電層(IMD)120)上表面。在本實施例中，矽通孔124與導線128可以由單一導電層形成，且此導線128係使接點(contact)122與矽通孔124相互連接。在其他實施例中，矽通孔124可不與半導體基材110上之電路相互連接。在本實施例中，矽通孔124提供一電性連接，使形成於另一半導體基材(圖中未顯示)上之電路與基材背側(backside)或基材電路側(circuit side)相互連接。
依據本發明之一實施例，第2圖顯示一薄化製程(thinning process)，其實施在半導體基材110背側(backside)上，藉以曝露第一襯層(first liner)126。此薄化製程可藉由蝕刻製程及/或平坦化製程，例如機械研磨(mechanical grinding)製程或是化學機械研磨(chemical mechanical polishing,CMP)製程。舉例而言，初始階段可實施平坦化製程，例如機械研磨或化學機械研磨(CMP)製程，以曝露第一襯層126，隨後可實施一或多次對於第一襯層126與半導體基材110具有高蝕刻速率選擇性(etch-rate selectivity)之濕式蝕刻製程，以留下從半導體基材110背側(backside)延伸突出的矽通孔124，如第2圖所示。此蝕刻製程可為，例如，使用溴化氫/氧氣(HBr/O2 )電漿、溴化氫/氯氣/氧氣(HBr/Cl2 /O2 )電漿、六氟化硫/氯氣(SF6 /Cl2 )電漿、六氟化硫(SF6 )電漿等等之乾式蝕刻製程。值得注意的是，在其他實施例中，矽通孔124可能不從半導體基材110背側(backside)延伸出來。
依據本發明之一實施例，第3圖顯示一蝕刻製程，其作用在於移除至少一部分之第一襯層126。實施一或多次對於第一襯層126與其週遭材料(例如半導體基材110、層間介電層(ILD)116、金屬間介電層(IMD)120之材料、矽通孔124之導電材料及/或蝕刻停止層(etch stop layers)之材料)具有高蝕刻速率選擇性(etch-rate selectivity)之濕式蝕刻製程，結果可於矽通孔124周圍形成一氣隙(air gap)310。
在一實施例中，第一襯層126係由四乙基矽酸鹽(tetra-ethyl ortho-silicate,TEOS)所形成，可藉由，例如，使用二氟化二鹵(X2 F2 )電漿之乾式蝕刻製程移除此第一襯層(first liner)126，也可藉由濕式蝕刻製程將其移除。
在一實施例中，第3圖也顯示氣隙(air gap)310延伸至矽通孔124之整個深度，並且延伸至金屬間介電層(IMD)120之表面上。在此實施例中，氣隙(air gap)310延伸至金屬間介電層(IMD)120(或是層間介電層(ILD)116)之上表面。其他表面，例如由與第一襯層126具有高蝕刻速率選擇性之材料所形成的接點(contact)122，可能導致蝕刻製程的停止。此蝕刻製程也可為時間控制式蝕刻(timed etch)，藉由控制蝕刻時間以控制第一襯層(first liner)126移除的量。
依據本發明之一實施例，第4圖顯示一第二襯層(second liner)410形成於半導體基材110(或是可能形成於半導體基材110表面上之原生氧化層(native oxide))背側(backside)上，並且介於矽通孔124之導電材料與其週遭材料之間。形成此第二襯層(second liner)410的材料較佳為低介電常數(low-K)材料或超低介電常數(extra low-K,ELK)材料。此第二襯層(second liner)410也可使用聚亞醯胺(polyimide)材料。一般而言，低介電常數(low-K)材料具有一介電常數低於約3.5，而超低介電常數(extra low-K,ELK)材料則具有一介電常數低於約2.8。本發明所屬技術領域中具有通常知識者應了解使用一低介電常數材料(例如低介電常數(low-K)材料或超低介電常數(extra low-K,ELK)材料)與四乙基矽酸鹽(tetra-ethyl ortho-silicate,TEOS)相比，可降低介電常數，進而可降低電容。
適合的低介電常數(low-K)材料包括氟矽玻璃(fluorinated silicate glass,FSG)、含碳或尚含有氮、氫、氧及上述之組合之介電材料。可藉由，例如旋轉塗佈製程(spin coating process)形成此第二襯層410。形成第二襯層410之後，可實施固化步驟，例如可利用紫外光(UV)進行紫外光固化步驟，固化低介電常數(low-K)材料或超低介電常數(extra low-K,ELK)材料，也可使用其他固化方法。
如第4圖所示，形成第二襯層410之材料延伸至半導體基材110背側(backside)上，從而提供介於矽通孔124延伸突出部分與半導體基材110之間的絕緣層。值得注意的是，在一實施例中，為了使矽通孔124從第二襯層(second liner)410之上表面延伸突出，可能需要進行另一蝕刻製程。特別是當第二襯層410係藉由形成順應層(conformal layer)的方法形成時，此第二襯層410可能延伸至矽通孔124突出部分之上。在本實施例中，可沉積並圖案化罩幕(mask)，以曝露出第二襯層410位於矽通孔124突出部分之上，並且實施蝕刻製程以移除第二襯層410曝露的部分，因而曝露出矽通孔124。若第二襯層410係藉由自平坦化(self-planarizing)製程(例如旋塗製程(spin-on process))形成，則不需實施上述製程。
之後，為完成適用於特定領域之半導體元件，也可實施其他後段製程(back-end-of-line,BEOL)。例如，可移除載體基材(carrier substrate)134，可於基材電路側(circuit side)及背側(backside)形成凸塊底層金屬(under-bump metallization)及接觸插塞(contact)，可形成封裝材料(encapsulant)，可實施切割(singulation)製程以分割出單一晶粒(die)，可實施晶圓級(wafer-level)或晶粒級(die-level)堆疊等等。值得注意的是，本發明所列舉之實施例可應用於多種不同情況。例如，本發明所列舉之實施例可應用於晶粒對晶粒(die-to-die)接合結構(bonding configuration)、晶粒對晶圓(die-to-wafer)接合結構(bonding configuration)或晶圓對晶圓(wafer-to-wafer)接合結構(bonding configuration)。
本發明所屬技術領域中具有通常知識者應了解上述製程使用一低介電常數(low-K)襯層(liner)或超低介電常數(extra low-K,ELK)襯層，而不需擔心其他製程中對低介電常數(low-K)材料造成的傷害。例如，因為第二襯層(second liner)係於製程的後期形成，因此第二襯層在蝕刻製程(例如乾式蝕刻製程、濕式蝕刻製程、化學機械研磨(CMP)等等)中將不會受到傷害。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
110．．．半導體基材
112．．．電路系統
116．．．層間介電層(inter-layer dielectric,ILD)
118．．．接觸插塞(contact)
120．．．金屬間介電層(inter-metal dielectric,IMD)
122．．．接點(contact)
124．．．矽通孔(through-silicon via)
126．．．第一襯層(first liner)
128．．．導線(conductive line)
130．．．保護層
132．．．接觸插塞(contact)
134．．．載體基材(carrier substrate)
136．．．黏著劑(adhesive)
310．．．氣隙(air gap)
410．．．第二襯層(second liner)
第1~4圖為一系列剖面圖，用以說明本發明之半導體元件之一實施例之製程中間階段。
110．．．半導體基材
112．．．電路系統
116．．．層間介電層(inter-layer dielectric,ILD)
118．．．接觸插塞(contact)
120．．．金屬間介電層(inter-metal dielectric,IMD)
122．．．接點(contact)
124．．．矽通孔(through-silicon via)
126．．．第一襯層(first liner)
128．．．導線(conductive line)
132．．．接觸插塞(contact)
134．．．載體基材(carrier substrate)
136．．．黏著劑(adhesive)
410．．．第二襯層(second liner)

Claims (17)

  1. 一種半導體元件，包括：一具有一電路側(circuit side)與一相對於該電路側之背側(backside)之半導體基材；一矽通孔(through-silicon via)延伸穿過該半導體基材；以及一第一介電層設置於該矽通孔與該半導體基材之間，其中該第一介電層延伸至該半導體基材之背側表面之至少一部分上，其中至少一部份之第一介電層延伸到該半導體基材之電路側上，且該第一介電層介於該半導體基材與一導線之間。
  2. 如申請專利範圍第1項所述之半導體元件，其中該第一介電層之介電常數低於約3.5。
  3. 如申請專利範圍第1項所述之半導體元件，其中該矽通孔之一部分從該半導體基材之背側(backside)延伸突出。
  4. 如申請專利範圍第1項所述之半導體元件，其中該矽通孔之一部分從該第一介電層延伸突出。
  5. 如申請專利範圍第1項所述之半導體元件，其中該第一介電層延伸至該半導體基材電路側之一第二介電層之上。
  6. 一種半導體元件之製法，包括以下步驟：提供一半導體基材，其中該半導體基材具有一第一側與相對於該第一側之第二側；形成一開口從該半導體基材之第一側延伸到該半導 體基材之中；形成一第一襯層(liner)沿著該開口之側壁；形成一導電材料於該開口中的第一襯層之上；薄化該半導體基材之第二側，因而曝露至少一部分之第一襯層；移除介於該導體材料與該半導體基材之間的至少一部分第一襯層以及移除至少一部分位於該半導體基材電路側之一介電層上之該第一襯層；以及移除之後，形成一第二襯層於該導電材料與該半導體基材之間，其中該第二襯層延伸至該半導體基材第一側之該介電層上。
  7. 如申請專利範圍第6項所述之半導體元件之製法，其中該第二襯層包括一介電常數低於約3.5之材料。
  8. 如申請專利範圍第6項所述之半導體元件之製法，其中該第一襯層包括一介電常數高於約3.5之材料。
  9. 如申請專利範圍第6項所述之半導體元件之製法，其中該第二襯層包括聚亞醯胺(polyimide)。
  10. 如申請專利範圍第6項所述之半導體元件之製法，其中該薄化該半導體基材之第二側包括蝕刻該半導體基材之第二側，使得一部分之導電材料從該半導體基材之第二側延伸突出。
  11. 一種半導體元件之製法，包括以下步驟：提供一半導體基材，其中該半導體基材具有一自電路側延伸且部分穿過該半導體基材之矽通孔，以及一介於該半導體基材與該矽通孔之間的一第一襯層； 薄化該半導體基材之背側，因而曝露至少一部分之第一襯層；移除介於該矽通孔與該半導體基材之間的至少一部分第一襯層以及移除至少一部分位於該半導體基材電路側之一介電層上之該第一襯層，因而形成一位於該半導體基材背側之上且圍繞該該矽通孔之開口；以及形成一第二襯層於該開口中。
  12. 如申請專利範圍第11項所述之半導體元件之製法，其中該第二襯層延伸至該半導體基材背側之一部分上。
  13. 如申請專利範圍第11項所述之半導體元件之製法，其中該第二襯層包括一介電常數低於該第一襯層之介電材料。
  14. 如申請專利範圍第11項所述之半導體元件之製法，其中該第二襯層延伸至該半導體基材電路側之一部分上。
  15. 如申請專利範圍第11項所述之半導體元件之製法，其中該提供該半導體基材包括形成該矽通孔，其中該矽通孔穿過一或多層位於該半導體基材電路側之介電層。
  16. 如申請專利範圍第11項所述之半導體元件之製法，其中該第二襯層係由超低介電常數(extra low-K,ELK)材料所組成。
  17. 如申請專利範圍第11項所述之半導體元件之製法，其中該第二襯層包括聚亞醯胺(polyimide)。
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US20150287664A1 (en) 2015-10-08
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