TWI395542B - 印刷電路板與電子應用 - Google Patents

印刷電路板與電子應用 Download PDF

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TWI395542B
TWI395542B TW098146470A TW98146470A TWI395542B TW I395542 B TWI395542 B TW I395542B TW 098146470 A TW098146470 A TW 098146470A TW 98146470 A TW98146470 A TW 98146470A TW I395542 B TWI395542 B TW I395542B
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panel
electrical conductor
conductor
disposed
printed circuit
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TW098146470A
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TW201105229A (en
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Han Kim
Chang-Sup Ryu
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Samsung Electro Mech
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  • Engineering & Computer Science (AREA)
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Description

印刷電路板與電子應用
本發明主張韓國專利申請案10-2009-0069666號的利益，於2009年7月29日對韓國智慧財產局提出申請，此處揭示的內容完全參照其整體。
本發明關於一種印刷電路板及一種電子產品。
當電子產品的運作頻率越來越高，電磁干擾(EMI)已被視為慢性的雜訊問題。特別是，電子產品的運作頻率已達到幾十個MHz，或甚至幾個GHz，使得EMI的問題更為嚴重。隨之而來的，尋找此問題的解決方法係迫切需要的。在一面板發生的EMI問題中，對雜訊問題的解決，特別對發生於面板的邊緣，並未被有效的研究，使得完全隔絕面板的雜訊係困難的。
EMI雜訊是指一雜訊，當一個電子電路、零件、或部件經轉換至另一電子電路、零件、或部件所產生的一電磁(EM)波時，其由干擾所導致而創造一雜訊問題。EMI雜訊可廣泛的被分類為兩種型態，如輻射雜訊(於第1圖的元件符號為10及30)及傳導雜訊(於第1圖的元件符號為20)。
從一電子產品的一面板所輻射的EMI雜訊通常可由使用一屏蔽外罩(第2圖中的40)來覆蓋面板的上部份而屏蔽，或由附加一EMI場吸收器(第3圖中的42)來吸收EMI雜訊。然而，在使用屏蔽外罩40的情況下，因為天線效應產生一新的輻射雜訊10，所以屏蔽所有向面板外輻射的EMI係困難的，且對EMI場吸收器42可吸收的頻率範圍存在著限制，使得尋找一有效屏蔽的方法係迫切需要的。
屏蔽外罩40於自我附加具有一些問題。再者，不僅屏蔽外罩的厚度受到限制，屏蔽外罩也增加了輕型電子裝置的重量。又，在EMI場吸收器42的情況下，發展一種可屏蔽EMI雜訊的各種頻率的材料係困難的，且發展此材料可耗費較長時間，因而增加產品的成本。
因此，尋找可立即吸收各種頻率、輕易的被應用而無任何天線效應、且於製造過程具成本效益的解決方式，係迫切需要的。
本發明提供一種印刷電路板及一種電子產品，其可立即吸收各種頻率、輕易的被應用而無任何天線效應、且於製造過程具成本效益。
本發明的一態樣提供包含一第一面板的一印刷電路板，其具有一電子零件固定於其上；及一第二面板，其經安置於該第一面板的一上表面，且覆蓋該第一面板的一上表面的至少一部分，且其中一EBG結構被***該第二面板，使得從該第一面板向上輻射的一雜訊被屏蔽。
第二面板可由黏著劑的方式被黏附於第一面板的上表面，且可與一屏蔽外罩相耦合，該屏蔽外罩覆蓋第一面板的上表面的至少一部分。在此，屏蔽外罩可與第一面板的地線連接，且第二面板的EBG結構可被接地於屏蔽外罩。又，於屏蔽外罩中可形成一裸孔，且第二面板與屏蔽外罩的一部分能以使得裸孔被覆蓋的方式相耦合。在此，裸孔可形成於電子零件的一上表面中。
電子零件可被固定於第一面板的一表面，且第二面板可被堆疊於第一面板的上表面，同時與電子零件的位置相符合的一部分呈敞開。
第二面板可包含一第一導電體及一第二導電體，其分別的經佈置於一不同表面、一第三導電體，其經佈置於與第二導電體不同的一表面、及一縫合貫孔(via)組件，其透過第二導電體所佈置的表面，將第一導電體連接至第三導電體，且其中縫合貫孔係與第二導電體電性地分離(electrically separated from)。
第二面板可包含一對第四導電體，其分別的經佈置於一相同表面、一第五導電體，其經佈置於第四導電體不同的一表面、一第六導電體，其經佈置於第四導電體及第五導電體之間的一表面、及一縫合貫孔組件，其透過第五導電體，將第四導電體之一對互相連接，且其中縫 合貫孔組件係與第六導電體電性地分離。
第二面板亦可具有與第一面板的外形相符合的一經折曲外形。
本發明的另一態樣提供一電子產品，其包含一機殼、一第一面板，其被置於機殼內部、及一第二面板，其具有一EBG結構***其中，且其第二面板與機殼的面對著第一面板的一內部相耦合，並且屏蔽從第一面板輻射的一雜訊。
第二面板可包含一第一導電體及一第二導電體，其分別的經佈置於一不同表面、一第三導電體，其經佈置於與第二導電體不同的一表面、及一縫合貫孔組件，其透過第二導電體所佈置的表面，將第一導電體連接至第三導電體，且其中縫合貫孔係與第二導電體電性地分離。
第二面板可包含一對第四導電體，其分別的經佈置於一相同表面、一第五導電體，其經佈置於與等第四導電體不同的一表面、一第六導電體，其經佈置於第四導電體及第五導電體之間的一表面、及一縫合貫孔組件，其透過第五導電體，將第四導電體之一對互相連接，縫合貫孔組件係與第六導電體電性地分離。
第二面板可具有與第一面板的外形相符合的一經折曲外形。
本發明額外的態樣及優點在某種程度上將於以下的說明書中提出，且在某種程度上對於說明書將是明顯的，或可由實現本發明而習得。
雖本發明允許多種改變及許多實施例，於說明書內文將詳述並於圖式中將圖示特定的實施例。然而，此舉並非意欲限制本發明於特定的實現模式，且將可瞭解不背離本發明的精神及技術範疇的所有改變、均等、及替換被包含於本發明。在本發明的說明書中，當相關技術的某些詳細解說被視為其可能非必要的混淆本發明的重點時，將被省略。
根據本發明的某些實施例，參照隨附的圖式，以下將詳述一印刷電路板及一電子產品。那些相同或相符合的零件，不論圖式的號碼，係以相同的元件符號表達，且省略多餘的說明。
根據本發明的實施例，一印刷電路板提供一結構，其中從一電子零件110或驅動固定於一面板的電子零件的一驅動電路所輻射的一EMI雜訊，可由覆蓋面板的上表面的另一面板來屏蔽(電子零件110被固定於其上)，其中***一EGB結構。此處根據本發明的實施例，印刷電路板包含一第一面板100，其具有一電子零件110固定於其上，及一第二面板200，其經安置於第一面板100的一上表面，且覆蓋第一面板100的上表面的至少一部分，且其中***一EBG結構(參照第10至14圖的元件符號280a、280b、280c、及280d)，其***之方式使得從第一面板向上輻射的一雜訊被屏蔽。
第二面板200係為不同於第一面板100的一分別面板，而電子零件110固定於其上，且因具有EBG結構280a、280b、280c、及280d被***其中，而可屏蔽一雜訊。此處，EBG結構可由一金屬層、一貫孔及一樣板所構成，其被形成於面板內部。
如此，根據此實施例的印刷電路板，藉由僅附加第二面板200而非使用一昂貴的吸收器(第3圖的42)以便屏蔽從第一面板100向上輻射的雜訊，可提供一所欲或甚至更佳的雜訊屏蔽效應，而比使用一吸收器較低的成本。而且，如此僅使用一屏蔽外罩(第2圖的40)遠超過於傳統技術的雜訊屏蔽效應，因為不會發生天線效應。
各種可能的EBG結構的實施例，其被***第二面板200，將敘述於下。
由使用一黏著劑290，第二面板200可與第一面板100的上表面相耦合。更具體而言，若電子零件110被固定於第一第一面板100的表面(如第4圖中所示)第二面板200可透過黏著劑290與電子零件110的上表面相耦合。一抗焊劑270可經形成於一相反表面，其上不塗抹黏著劑290，使得形成EBG結構的各種樣板可被保護。
同時如第5圖所示，在第一面板100的上表面被屏蔽外罩300所覆蓋的情況下，第二面板200可藉由與屏蔽外罩300相耦合而覆蓋第一面板100的上表面。
而且，在屏蔽外罩300透過一焊料(未顯示)連接至第一面板100的地線的情況下，藉由使第二面板200的EBG結構接地於屏蔽外罩300，EGB結構可連接至第一面板的地線(未顯示)。在此配置下，可獲得更廣的地線，因而改善雜訊屏蔽效應。
此處如第6圖所示，在第二面板的EBG結構的一部分(例如一金屬層或樣板)經佈置以黏附於屏蔽外罩300之後，第二面板可由使用一固著方式(例如一黏著膠帶205)而被固著於屏蔽外罩300。在第6圖中，黏著膠帶205覆蓋第二面板200的整個上表面，但視設計說明書而定，其亦可僅覆蓋第二面板200的一部分應為顯而易見的。
雖第二面板200可與屏蔽外罩300的整個下或上表面相耦合，其第二面板200僅與屏蔽外罩300的特定一部分相耦合亦係可能的。在此情況下，如第6圖所示，一裸孔310可形成於屏蔽外罩300中，且第二面板200可經耦合以便覆蓋裸孔310。如此，藉由選擇性的佈置第二面板200於一特定部份，由使用者所欲的部份雜訊可選擇性的被屏蔽，且可預防第二面板200的過度使用，使得成本節省可被預期。
考慮到雜訊係通常從一電子零件向上輻射，裸孔可經形成於與電子零件的上側相符合的屏蔽外罩的一部分之中。然而，本發明並非限於此實施例應為顯而易見的，且裸孔的位置、數量、及形狀可視設計說明書而定而被修改。
同時，若問題係一雜訊從電子零件110周圍的一驅動電路輻射，而非一雜訊從固定於第一面板100的電子零件110的上表面輻射，第二面板200可具有與電子零件110的一部分相符合的開口，且接著被堆疊於第一面板100的上表面的一部分。在此方式下，如第7圖所示，第二面板200可被***於每兩個電子零件110之間，且因此可預防印刷電路板的總厚度非必要的變得太厚。
同時，若第一面板100具有一矩形以外的形狀，第二面板200亦可具有周圍經折曲與第一面板100的形狀相符合的一形狀。舉例而言，如第8圖所示，第二面板200的一部分可具有一半圓形狀與第一面板100的外部形狀相符合，或一三角形，或類似的，視情況而定。
根據本發明前述的實施例，印刷電路板可經應用於各種電子產品，例如行動電話及其他行動裝置。在此情況下，上述的第二面板200可與一電子產品1000的一機殼400的內部相耦合，如第9圖所示。在此情況下，被EBG結構***的第二面板200，可輕易的被置於電子產品1000的機殼400上而不具有一額外的屏蔽外罩。
緊接著，各種可能的前述EBG結構的實施例，其被***第二面板200，將敘述於下。
首先，第10圖顯示一縫合貫孔型EBG結構。根據本實施例的一能帶間隙結構280a可包含一第一導電體230a-1及一第二導電體210a，其各者經佈置於一不同表面；一第三導電體230a-2，其經佈置在不同於第二導電體210a的一表面；一縫合貫孔組件240a，其透過其上佈置有第二導電體210a、但與第二導電體210a電性地分離的表面，將第一導電體230a-1連接至第三導電體230a-2。
以下所述係第10圖所顯示的結構，可作用為隔絕一特定頻率能帶的一信號的電磁能帶間隙結構的一原理。可用一介質層220a***第二導電體210a及第一與第三導電體230a-1與230a-2之間。此形成一電容零件在第二導電體210a及第一與第三導電體230a-1與230a-2之間，且於鄰接的第一與第三導電體230a-1與230a-2之間。另外，一電感零件由縫合貫孔組件240a，透過連接一第一貫孔241a→一連接樣板243a→一第二貫孔242a，被形成於兩個鄰接的導電體230a-1與230a-2之間。此處，電容零件的值可視各種因素而改變，例如第二導電體210a及第一與第三導電體230a-1與230a-2之間的分隔距離，及兩個鄰接的導電體230a-1與230a-2之間的分隔距離；介質材料的介質常數形成介質層220a及導電體的大小、形狀及區域。而且，電感零件的值可視各種因素而改變，例如第一貫孔241a、第二貫孔242a及連接樣板243a的形狀、長度、深度、寬度及區域。因此，適當地調整及設計各種前述的因素，可使第10圖的結構作用為用於移除或隔絕一目標頻率能帶的一特定雜訊或一特定信號的電磁能帶間隙結構(例如一能帶終止濾波器)。此可輕易的透過第11圖的均等電路而被瞭解。
將第11圖的均等電路與第10圖的電磁能帶間隙結構 作比較，一電感零件L1與第一貫孔241a相符合，且一電感零件L2與第二貫孔242a相符合。一電感零件L3與連接樣板243a相符合。C1係位於第一與第三導電體230a-1與230a-2，及任何其他可置於該第一與第三導電體230a-1與230a-2及第二導電體210a之上的介質層旁邊的一電容零件。C2及C3係位於被置於與連接樣板243a同樣平面表面的第二導電體210a及被置於連接樣板243a及第二導電體210a下方的平面表面的任何其他介質層的旁邊的電容零件。
顯示於第10圖的電磁能帶間隙結構280a可作用為一能帶終止濾波器，其根據以上均等電路，隔絕一特定頻率能帶的信號。換言之，如第11圖的均等電路所見，於一低頻率能帶(參照第11圖中的參考記號「x」)的一信號及於一高頻率能帶(參照第11圖中的參考記號「y」)的一信號可通過電磁能帶間隙結構，且於一特定頻率能帶(參照第11圖中的參考記號「z1」、「z2」、及「z3」)介於低頻率能帶及高頻率能帶範圍之間的信號，由電磁能帶間隙結構隔絕。
如第12圖所示係一EBG結構280b的另一實施例，其包含：一對第四導電體210b，其分別地經佈置於一相同表面；一第五導電體230b，其經佈置於不同於第四導電體210b的一表面；一第六導電體220b，其經佈置於在第四導電體210b及第五導電體230b之間的一表面；及一縫合貫孔組件240b，其透過第五導電體230b，將一對 第四導電體210b互相連接，但與第六導電體220b電性地分離。
在第12圖的EBG結構中，其係第10圖的EBG結構280a的修改，不僅於第四導電體210b及第六導電體220b之間，也於第五導電體230b及第六導電體220b之間形成一額外的電容零件。此外，將第四導電體210b連接到第五導電體230b的貫孔240b可有足夠長度以獲得電感零件的一有效值。因此，隔絕一特定頻率能帶中的一信號的效力可被改善。
如第13圖所示的本發明的另一實施例係一蕈狀EBG 280c。蕈狀EBG 280c具有一結構，其中多個蕈形狀的EBG細胞服務區(參照第13圖的元件符號230c)經***至兩個金屬層210c及220c之間，其作用為，舉例而言，一電源層及一接地層。第13圖為了圖示的方便，僅顯示四個EBG細胞服務區230c。
參照第13圖，在蕈狀EBG 280c中，額外形成一金屬片231c於一第一金屬層210c及一第二金屬層220c之間，其各者作用為接地層且另一者作用為電源層，且用一貫孔232c將第一金屬層210c連接至金屬片230c的蕈狀結構230c，被重複安排。在此，一第一介質層215c被***於第一金屬層210c及金屬片231c之間，且一第二介質層225c被***於金屬片231c及第二金屬層220c之間。
在此蕈狀EBG 280c中，一電容零件由第二金屬層 220c、第二介質層225c及金屬片231c而形成，且一電感零件由貫孔232c將第一金屬層210c連接至金屬片231c而形成，其透過第一介質層215c，在第一金屬層210c及第二金屬層220c之間被連接於一L-C串聯，從而使得蕈狀EBG 280c作用為能帶終止濾波器的一類型。
如第14圖所示的本發明的另一實施例係一共面EBG 280d。在共面EBG 280d中，多個特定的EBG細胞服務區樣板(參照第14圖的元件符號220d)被重複安排遍及任何作用為電源層或接地層的金屬層。第14圖為了圖示的方便，亦僅顯示四個EBG細胞服務區220d。
參照第14圖，共面EBG 280d具有一形式，其中任何金屬層210d及多個金屬片221d(其被置於另一平面表面)，藉由金屬分支222d，透過金屬片的一特定部份(在圖14的情況為各金屬片的一角落的末端)彼此連結。
在此，金屬片221d具有一大的尺寸構成的低阻抗區域，且金屬分支具有一小的尺寸構成的高阻抗區域。因此，共面EBG 280d透過低阻抗區域及高阻抗區域的交替重複的結構，變成作用為可隔絕一特定頻率的雜訊的一能帶終止濾波器。
如此的共面EBG結構280d具有一優點，即其一電磁能帶間隙結構可由僅使用兩個層來構成。
雖然EBG結構(其被***第二面板200)已敘述四個範例280a、280b、280c、及280d，其它對EBG結構的修改亦可被***第二面板200應是顯而易見的。 當本發明的精神參照特定的實施例已被詳述，實施例僅具說明意圖且不應限制本發明。那些技藝人士將瞭解可改變或修改實施例而未背離本發明的範疇及精神。
如此，許多上述之外的實施例可於所附的申請專利範圍中被尋找到。
10‧‧‧輻射雜訊
20‧‧‧傳導雜訊
30‧‧‧輻射雜訊
40‧‧‧屏蔽外罩
42‧‧‧吸收器
100‧‧‧第一面板
110‧‧‧電子零件
200‧‧‧第二面板
205‧‧‧黏著膠帶
270‧‧‧抗焊劑
290‧‧‧黏著劑
300‧‧‧屏蔽外罩
310‧‧‧裸孔
400‧‧‧機殼
1000‧‧‧電子產品
210a‧‧‧第二導電體
220a‧‧‧介質層
230a-1‧‧‧第一導電體
230a-2‧‧‧第三導電體
240a‧‧‧縫合貫孔組件
241a‧‧‧第一貫孔
242a‧‧‧第二貫孔
243a‧‧‧連接樣板
280a‧‧‧EBG結構
210b‧‧‧第四導電體
220b‧‧‧第六導電體
230b‧‧‧第五導電體
240b‧‧‧縫合貫孔組件
280b‧‧‧EBG結構
210c‧‧‧第一金屬層
215c‧‧‧第一介質層
220c‧‧‧第二金屬層
225c‧‧‧第二介質層
230c‧‧‧細胞服務區
231c‧‧‧金屬片
232c‧‧‧貫孔
280c‧‧‧蕈狀EBG結構
210d‧‧‧金屬層
220d‧‧‧細胞服務區
221d‧‧‧金屬片
222d‧‧‧金屬分支
280d‧‧‧共面EBG結構
第1至3圖係為橫剖面圖，圖示根據相關技術的一印刷電路板。
第4至7圖係為橫剖面圖，圖示根據本發明的一些實施例的印刷電路板。
第8圖係一平面圖，圖示根據本發明的一實施例的一印刷電路板的一第二面板。
第9圖係一橫剖面圖，圖示根據本發明的一實施例的一電子產品。
第10至14圖顯示根據本發明的一些實施例，***一印刷電路板的EBG結構。
100．．．第一面板
110．．．電子零件
200．．．第二面板
270．．．抗焊劑
290．．．黏著劑

Claims (10)

  1. 一種印刷電路板，其包含：一第一面板，其具有一電子零件固定於其上；一第二面板，其經安置於該第一面板的一上表面，且覆蓋該第一面板的一上表面的至少一部分，一EBG結構被***該第二面板，使得從該第一面板向上輻射的一雜訊被屏蔽；及一屏蔽外罩，該屏蔽外罩覆蓋該第一面板的該上表面的至少一部分，其中該第二面板與該屏蔽外罩相耦合，該屏蔽外罩與該第一面板的一地線連接，且該第二面板的該EBG結構被接地於該屏蔽外罩。
  2. 如申請範圍第1項之印刷電路板，其中該第二面板由黏著劑的方式被黏附於該第一面板的該上表面。
  3. 如申請範圍第1項之印刷電路板，其中於該屏蔽外罩中形成一裸孔，且該第二面板與該屏蔽外罩的一部分相耦合，此一方式使得該裸孔被覆蓋。
  4. 如申請範圍第3項之印刷電路板，其中該裸孔被形成於該電子零件的一上表面。
  5. 如申請範圍第1項之印刷電路板，其中： 該電子零件被固定於該第一面板的一表面；且該第二面板被堆疊於該第一面板的該上表面，同時與該電子零件的該位置相對應的一部分呈敞開。
  6. 如申請範圍第1項之印刷電路板，其中該第二面板包含：一第一導電體及一第二導電體，分別地經佈置於一不同表面；一第三導電體經佈置於與該第二導電體不同的一表面；及一縫合貫孔組件，其透過該第二導電體所佈置的該表面，將該第一導電體連接至該第三導電體，該縫合貫孔與該第二導電體電性地分離。
  7. 如申請範圍第1項之印刷電路板，其中該第二面板包含：一對第四導電體分別地經佈置於一相同表面；一第五導電體經佈置於與該等第四導電體不同的一表面；一第六導電體經佈置於該等第四導電體及該第五導電體之間的一表面；及一縫合貫孔組件，其透過該第五導電體將該等第四導電體之一對互相連接，該縫合貫孔組件係與該第六導電體電性地分離。
  8. 如申請範圍第1項之印刷電路板，其中該第二面板具有與該第一面板的外形相對應的一經折曲外形。
  9. 一種電子產品包含：一機殼；置於該機殼內部的一第一面板；及一第二面板，該第二面板具有一EBG結構***其中，其中該第二面板與該機殼的面對著該第一面板的一內部相耦合，並且屏蔽從該第一面板輻射的一雜訊，及其中該第二面板包含：一對第四導電體，該對第四導電體經分別地佈置於一相同表面上；一第五導電體，該第五導電體經佈置於與該等第四導電體不同的一表面上；一第六導電體，該第六導電體經佈置於該等第四導電體及該第五導電體之間的一表面；及一縫合貫孔組件，該縫合貫孔組件透過該第五導電體將該對第四導電體之兩者彼此互相連接，該縫合貫孔組件係與該第六導電體電性地分離。
  10. 如申請範圍第9項之電子產品，其中該第二面板具有與該第一面板的外形相對應的一經折曲外形。
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103081576B (zh) * 2010-09-30 2015-11-25 日本电气株式会社 配线基板和电子设备
CN102856304B (zh) * 2011-06-27 2015-06-24 成都锐华光电技术有限责任公司 一种半导体芯片封装结构
JP5751079B2 (ja) * 2011-08-05 2015-07-22 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5670392B2 (ja) 2012-07-27 2015-02-18 株式会社東芝 回路基板
US9312607B2 (en) * 2013-02-12 2016-04-12 Raytheon Company Load spreading interposer
KR20140103789A (ko) * 2013-02-19 2014-08-27 엘지전자 주식회사 이동 단말기
ES2656009T3 (es) 2013-03-15 2018-02-22 Flextronics Ap Llc Procedimiento de revestimiento con materia pulverizada y aparato para absorber interferencias electromagnéticas (EMI)
JP2015023194A (ja) * 2013-07-19 2015-02-02 株式会社東芝 半導体装置
US10070547B2 (en) * 2014-02-26 2018-09-04 Sparton Corporation Control of electric field effects in a printed circuit board assembly using embedded nickel-metal composite materials
JP6336307B2 (ja) 2014-03-18 2018-06-06 キヤノン株式会社 電子回路
US10403973B2 (en) * 2014-04-22 2019-09-03 Intel Corporation EBG designs for mitigating radio frequency interference
TWI565400B (zh) * 2014-07-01 2017-01-01 華碩電腦股份有限公司 電磁帶隙結構與具有電磁帶隙結構的電子裝置
US10321553B2 (en) * 2014-08-04 2019-06-11 Cisco Technology, Inc. Shield to improve electromagnetic interference (EMI) suppression capability
JP6273182B2 (ja) 2014-08-25 2018-01-31 株式会社東芝 電子機器
JP5937190B2 (ja) * 2014-12-12 2016-06-22 株式会社東芝 回路基板
JP6394482B2 (ja) * 2015-04-28 2018-09-26 京セラドキュメントソリューションズ株式会社 電子機器
WO2017004486A1 (en) * 2015-07-02 2017-01-05 Laird Technologies, Inc. Stretchable and/or flexible emi shields and related methods
US9999121B2 (en) 2016-04-25 2018-06-12 Laird Technologies, Inc. Board level shields with virtual grounding capability
JP6611065B2 (ja) * 2016-07-27 2019-11-27 国立大学法人 岡山大学 印刷配線板
KR102528687B1 (ko) * 2016-09-06 2023-05-08 한국전자통신연구원 전자기 밴드갭 구조물 및 그 제조 방법
CN210074170U (zh) * 2017-04-03 2020-02-14 株式会社村田制作所 高频模块
KR20190006359A (ko) * 2017-07-10 2019-01-18 엘지전자 주식회사 전자장치
JP6921705B2 (ja) * 2017-10-13 2021-08-18 株式会社東芝 電子機器
KR102442131B1 (ko) 2018-01-26 2022-09-13 삼성전자 주식회사 안테나 장치 및 안테나 장치를 포함하는 전자 장치
US20190297758A1 (en) * 2018-03-23 2019-09-26 Intel IP Corporation Electromagnetic shielding cap, an electrical system and a method for forming an electromagnetic shielding cap
KR102063469B1 (ko) * 2018-05-04 2020-01-09 삼성전자주식회사 팬-아웃 반도체 패키지
US11201119B2 (en) * 2018-06-06 2021-12-14 At&S Austria Technologie & Systemtechnik Aktiengesellschaft RF functionality and electromagnetic radiation shielding in a component carrier
KR102551803B1 (ko) * 2018-10-19 2023-07-06 삼성전자주식회사 배선을 따라 유전체가 채워질 수 있는 이격 공간을 갖도록 배치된 도전성 부재를 포함하는 전자 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6377464B1 (en) * 1999-01-29 2002-04-23 Conexant Systems, Inc. Multiple chip module with integrated RF capabilities
TW200808136A (en) * 2006-07-26 2008-02-01 Inventec Corp A layout design for a multilayer printed circuit board
TWI296493B (en) * 2005-05-19 2008-05-01 Univ Nat Sun Yat Sen Embedded power plane for suppressing noise and multi-layer structure using the same

Family Cites Families (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152780A (ja) * 1991-12-02 1993-06-18 Matsushita Electric Ind Co Ltd 電磁波遮蔽用シールド
JPH0553269U (ja) * 1991-12-17 1993-07-13 日本無線株式会社 高周波シールド構造を有する多層配線基板
JPH0579995U (ja) * 1992-04-03 1993-10-29 日本無線株式会社 高周波シールド構造を有する多層配線基板
US5886597A (en) * 1997-03-28 1999-03-23 Virginia Tech Intellectual Properties, Inc. Circuit structure including RF/wideband resonant vias
JPH11135977A (ja) 1997-10-28 1999-05-21 Sony Corp 電子回路
JP2004022587A (ja) 2002-06-12 2004-01-22 Denso Corp 筐体
US7215007B2 (en) * 2003-06-09 2007-05-08 Wemtec, Inc. Circuit and method for suppression of electromagnetic coupling and switching noise in multilayer printed circuit boards
US20050104678A1 (en) * 2003-09-11 2005-05-19 Shahrooz Shahparnia System and method for noise mitigation in high speed printed circuit boards using electromagnetic bandgap structures
US7030463B1 (en) * 2003-10-01 2006-04-18 University Of Dayton Tuneable electromagnetic bandgap structures based on high resistivity silicon substrates
US20050224912A1 (en) * 2004-03-17 2005-10-13 Rogers Shawn D Circuit and method for enhanced low frequency switching noise suppression in multilayer printed circuit boards using a chip capacitor lattice
US20050205292A1 (en) * 2004-03-18 2005-09-22 Etenna Corporation. Circuit and method for broadband switching noise suppression in multilayer printed circuit boards using localized lattice structures
US7102581B1 (en) * 2004-07-01 2006-09-05 Rockwell Collins, Inc. Multiband waveguide reflector antenna feed
US7136029B2 (en) * 2004-08-27 2006-11-14 Freescale Semiconductor, Inc. Frequency selective high impedance surface
US7215301B2 (en) * 2004-09-08 2007-05-08 Georgia Tech Research Corporation Electromagnetic bandgap structure for isolation in mixed-signal systems
US7253788B2 (en) * 2004-09-08 2007-08-07 Georgia Tech Research Corp. Mixed-signal systems with alternating impedance electromagnetic bandgap (AI-EBG) structures for noise suppression/isolation
JP4843611B2 (ja) * 2004-10-01 2011-12-21 デ，ロシェモント，エル．，ピエール セラミックアンテナモジュール及びその製造方法
JP4676238B2 (ja) * 2005-04-18 2011-04-27 株式会社日立製作所 バックプレーンバス用メインボード、および、それを用いたルータシステム、ストレージシステム
US7209082B2 (en) * 2005-06-30 2007-04-24 Intel Corporation Method and apparatus for a dual band gap wideband interference suppression
US7408512B1 (en) * 2005-10-05 2008-08-05 Sandie Corporation Antenna with distributed strip and integrated electronic components
US7626216B2 (en) * 2005-10-21 2009-12-01 Mckinzie Iii William E Systems and methods for electromagnetic noise suppression using hybrid electromagnetic bandgap structures
JP4325630B2 (ja) * 2006-03-14 2009-09-02 ソニー株式会社 ３次元集積化装置
TW200818451A (en) * 2006-06-02 2008-04-16 Renesas Tech Corp Semiconductor device
KR100723531B1 (ko) * 2006-06-13 2007-05-30 삼성전자주식회사 반도체 패키지 기판
TWI312592B (en) * 2006-06-30 2009-07-21 Ind Tech Res Inst Antenna structure with antenna radome and method for rising gain thereof
US8060457B2 (en) * 2006-09-13 2011-11-15 Georgia Tech Research Corporation Systems and methods for electromagnetic band gap structure synthesis
US20080072204A1 (en) * 2006-09-19 2008-03-20 Inventec Corporation Layout design of multilayer printed circuit board
US20080068818A1 (en) * 2006-09-19 2008-03-20 Jinwoo Choi Method and apparatus for providing ultra-wide band noise isolation in printed circuit boards
KR101265245B1 (ko) 2006-11-01 2013-05-16 에이전시 포 사이언스, 테크놀로지 앤드 리서치 이중적층형 ｅｂｇ 구조체
WO2008062562A1 (fr) * 2006-11-22 2008-05-29 Nec Tokin Corporation Structure de bande interdite électromagnétique, étiquette d'identification par radiofréquence, filtre antiparasite, feuille d'absorption de bruit et tableau de connexions à fonction d'absorption de bruit
US8081138B2 (en) * 2006-12-01 2011-12-20 Industrial Technology Research Institute Antenna structure with antenna radome and method for rising gain thereof
US20080158840A1 (en) * 2006-12-27 2008-07-03 Inventec Corporation DC power plane structure
US7839654B2 (en) * 2007-02-28 2010-11-23 International Business Machines Corporation Method for ultimate noise isolation in high-speed digital systems on packages and printed circuit boards (PCBS)
KR100851075B1 (ko) * 2007-04-30 2008-08-12 삼성전기주식회사 전자기 밴드갭 구조물 및 인쇄회로기판
KR100851065B1 (ko) * 2007-04-30 2008-08-12 삼성전기주식회사 전자기 밴드갭 구조물 및 인쇄회로기판
KR100851076B1 (ko) 2007-04-30 2008-08-12 삼성전기주식회사 전자기 밴드갭 구조물 및 인쇄회로기판
KR100838244B1 (ko) * 2007-06-22 2008-06-17 삼성전기주식회사 전자기 밴드갭 구조물 및 인쇄회로기판
US8310840B2 (en) 2007-08-07 2012-11-13 Samsung Electro-Mechanics Co., Ltd. Electromagnetic bandgap structure and printed circuit board
US8169790B2 (en) 2007-08-07 2012-05-01 Samsung Electro-Mechanics Co., Ltd. Electromagnetic bandgap structure and printed circuit board
DE102008041072B4 (de) 2007-08-07 2013-04-18 Samsung Electro - Mechanics Co., Ltd. Elektromagnetische Bandabstandsstruktur und Schaltungsplatine
KR100920824B1 (ko) * 2007-09-14 2009-10-08 삼성전기주식회사 인쇄회로기판 및 전자기 밴드갭 구조물의 제조방법
KR100913363B1 (ko) * 2007-09-18 2009-08-20 삼성전기주식회사 멀티 비아를 포함하는 전자기 밴드갭 구조물 및인쇄회로기판
US8159832B2 (en) * 2007-09-21 2012-04-17 Nokia Corporation Electromagnetic band gap structures and method for making same
KR100914440B1 (ko) * 2007-09-28 2009-08-28 삼성전기주식회사 단차가 형성된 전도층을 갖는 인쇄회로기판
KR100879375B1 (ko) * 2007-09-28 2009-01-20 삼성전기주식회사 캐비티 캐패시터가 내장된 인쇄회로기판
KR100867150B1 (ko) * 2007-09-28 2008-11-06 삼성전기주식회사 칩 캐패시터가 내장된 인쇄회로기판 및 칩 캐패시터의 내장방법
TWI375499B (en) * 2007-11-27 2012-10-21 Asustek Comp Inc Improvement method for ebg structures and multi-layer board applying the same
JP2009135154A (ja) * 2007-11-28 2009-06-18 Sony Corp 電磁波遮蔽具
KR100998720B1 (ko) 2007-12-07 2010-12-07 삼성전기주식회사 전자기 밴드갭 구조물 및 인쇄회로기판
DE102008045055A1 (de) 2007-12-07 2009-06-10 Samsung Electro-Mechanics Co., Ltd., Suwon Elektromagnetische Bandgap-Struktur und Leiterplatte
WO2009082003A1 (ja) 2007-12-26 2009-07-02 Nec Corporation 電磁バンドギャップ素子及びそれを用いたアンテナ並びにフィルタ
KR20090079428A (ko) * 2008-01-17 2009-07-22 삼성전자주식회사 파워 플레인 및 접지 플레인 노이즈를 감소시키는 구조를갖는 기판 및 이를 포함하는 전자 시스템
US8164006B2 (en) * 2008-03-19 2012-04-24 Samsung Electro-Mechanics Co., Ltd. Electromagnetic bandgap structure and printed circuit board
US8022861B2 (en) * 2008-04-04 2011-09-20 Toyota Motor Engineering & Manufacturing North America, Inc. Dual-band antenna array and RF front-end for mm-wave imager and radar
US7733265B2 (en) * 2008-04-04 2010-06-08 Toyota Motor Engineering & Manufacturing North America, Inc. Three dimensional integrated automotive radars and methods of manufacturing the same
US7830301B2 (en) * 2008-04-04 2010-11-09 Toyota Motor Engineering & Manufacturing North America, Inc. Dual-band antenna array and RF front-end for automotive radars
KR101086856B1 (ko) * 2008-04-16 2011-11-25 주식회사 하이닉스반도체 반도체 집적 회로 모듈 및 이를 구비하는 ｐｃｂ 장치
US20110012697A1 (en) * 2008-04-22 2011-01-20 Koichi Takemura Electro-magnetic band-gap structure, method for manufacturing the same, filter element and printed circuit board having embedded filter element
US8013258B2 (en) * 2008-06-11 2011-09-06 Mediatek Inc. Shielding device
JP5380919B2 (ja) * 2008-06-24 2014-01-08 日本電気株式会社 導波路構造およびプリント配線板
KR100956689B1 (ko) * 2008-06-27 2010-05-10 삼성전기주식회사 전자기 밴드갭 구조물 및 인쇄회로기판
US20100060527A1 (en) * 2008-09-10 2010-03-11 International Business Machines Corporation Electromagnetic band gap tuning using undulating branches
US8288660B2 (en) * 2008-10-03 2012-10-16 International Business Machines Corporation Preserving stopband characteristics of electromagnetic bandgap structures in circuit boards
KR100999550B1 (ko) * 2008-10-08 2010-12-08 삼성전기주식회사 전자기 밴드갭 구조물
US8344503B2 (en) * 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
KR100999518B1 (ko) * 2008-11-26 2010-12-08 삼성전기주식회사 전자기 밴드갭 구조물 및 회로 기판
KR101018785B1 (ko) * 2008-11-28 2011-03-03 삼성전기주식회사 전자기 밴드갭 구조물 및 회로 기판
KR101046716B1 (ko) * 2008-11-28 2011-07-06 삼성전기주식회사 전자기 밴드갭 구조물 및 회로 기판
US8467737B2 (en) * 2008-12-31 2013-06-18 Intel Corporation Integrated array transmit/receive module
JP5326649B2 (ja) * 2009-02-24 2013-10-30 日本電気株式会社 アンテナ、アレイアンテナ、プリント基板、及びそれを用いた電子装置
KR101038236B1 (ko) * 2009-09-16 2011-06-01 삼성전기주식회사 전자기 밴드갭 구조를 구비하는 인쇄회로기판
KR101023541B1 (ko) * 2009-09-22 2011-03-21 삼성전기주식회사 Ｅｍｉ 노이즈 저감 인쇄회로기판
KR101021552B1 (ko) * 2009-09-22 2011-03-16 삼성전기주식회사 Ｅｍｉ 노이즈 저감 인쇄회로기판
KR101092590B1 (ko) * 2009-09-23 2011-12-13 삼성전기주식회사 전자기 밴드갭 구조를 구비하는 인쇄회로기판
KR20110134200A (ko) * 2010-06-08 2011-12-14 삼성전기주식회사 전자기 밴드갭 구조물을 포함하는 ｅｍｉ 노이즈 차폐 기판

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6377464B1 (en) * 1999-01-29 2002-04-23 Conexant Systems, Inc. Multiple chip module with integrated RF capabilities
TWI296493B (en) * 2005-05-19 2008-05-01 Univ Nat Sun Yat Sen Embedded power plane for suppressing noise and multi-layer structure using the same
TW200808136A (en) * 2006-07-26 2008-02-01 Inventec Corp A layout design for a multilayer printed circuit board

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US20110026234A1 (en) 2011-02-03
DE102009055342A1 (de) 2011-02-17
US8432706B2 (en) 2013-04-30
JP2012138644A (ja) 2012-07-19
JP2011035367A (ja) 2011-02-17
US20130229779A1 (en) 2013-09-05
KR101007288B1 (ko) 2011-01-13
CN101990361A (zh) 2011-03-23
TW201105229A (en) 2011-02-01
DE102009055342B4 (de) 2013-11-21

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