TWI261328B - Circuit device - Google Patents
Circuit device Download PDFInfo
- Publication number
- TWI261328B TWI261328B TW093139760A TW93139760A TWI261328B TW I261328 B TWI261328 B TW I261328B TW 093139760 A TW093139760 A TW 093139760A TW 93139760 A TW93139760 A TW 93139760A TW I261328 B TWI261328 B TW I261328B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- chip
- resin
- layer
- circuit device
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 229920005989 resin Polymers 0.000 claims description 58
- 239000011347 resin Substances 0.000 claims description 58
- 239000004020 conductor Substances 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 abstract description 9
- 230000001070 adhesive effect Effects 0.000 abstract description 9
- 238000007667 floating Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 47
- 235000012431 wafers Nutrition 0.000 description 41
- 239000000463 material Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 8
- 238000000576 coating method Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000001746 injection moulding Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000004519 grease Substances 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 241000282376 Panthera tigris Species 0.000 description 1
- 235000010627 Phaseolus vulgaris Nutrition 0.000 description 1
- 244000046052 Phaseolus vulgaris Species 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 206010036790 Productive cough Diseases 0.000 description 1
- 235000009827 Prunus armeniaca Nutrition 0.000 description 1
- 244000018633 Prunus armeniaca Species 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical compound [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- 238000005065 mining Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000004091 panning Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 210000003802 sputum Anatomy 0.000 description 1
- 208000024794 sputum Diseases 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 239000010902 straw Substances 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/2908—Plural core members being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
1261328 九、發明說明: 【發明所屬之技術領域】 本毛明係關於-種疊層複數個Ica咖rated circuii; ’積體電路) 於上層疊層有更詳而言之’係關 义a 土 ’屯位被固疋之1C晶片之電路裝置。 【先前技術】 隨著半導體積體電路之高積體化、小型化,層疊(stack typek電路裝置作為高積體1(:成為備受矚目之構成之 、— Ο 第6圖係表示習知層疊型電路裝置構成之剖視圖。 在基板150之一方的面設有複數條配線156,第 曰曰片151由接著構件丨5 9加以固著。另在其上隔著絕緣性、 接,構件160疊層有第2IC晶片152。各IC晶片151、152 的衣面刀別设有電極墊(未圖示),透過接合線(Bonding Wlre)153等連接到設於基板150上之配線156。各配線156 透過設於基板15〇之貫通孔別連接到設於基板15〇背面之❿ 焊球等之外部端子][54。 該等疊層1C晶片151、152及接合線153、配線156 係由密封樹脂1 55密封從而加以封裝化(例如:參閱專利文 獻 1)。 .
[專利文獻1] 、 曰本專利特開2002-3681 89號公報 【發明内容】 [發明所欲解決之課題] 316613 1261328 、在j述層豐型電路裝置中,第2IC晶片152之固著係 為了 ”第1IC晶片151絕緣而透過黏晶片犲乜叶 s曰heet)或絕緣性接著劑等接著構件1㈣著。亦即,第w 晶片152之基板係以浮置狀態安裝。 =^如·右想在弟2iC晶片152採用雙極(Blpolar) 1C寺之固疋基板電 層於上層時,A板,時,當將該晶片叠 充分…,/ 會成為浮動狀態,而會有不能得到 兄刀之4寸性之問題。 :具有雙極ic等以固定電位 裝置中,當Μ晶私壯0士 」i L <迅路 在田丁思 固定電位而使用之1C她是配f 在取下層,而限制了層疊安裝之通用性。“疋配置 定+卜對方、不成進行層疊安裝的電路裝置,传將以固 面積之問題。 在大料面上b Μ存在增大安裝 [用以解決課題之手段] 本發明係鐾於上述問題而研發成者 =定電位圖案之複數個導電圖案、含有包括:含1 晶月之複數個ic晶片、以 土电位被固定 位被固定之ic晶片固定於前述導;^層,將前述基板電 上層的方式疊層安裝前述複數個H ’、,以該IC晶片為 層連接到前述固定電位圖宰而 s亚糟由將該導體 另,特徵為前述複數個導電::二之電路展置。 另,特徵為前述複數個導電圓=71支持基板上者。 而埋入絕緣性樹脂,從而得以被支持者V面露出之方式 -^66/3 1261328 付做為前述禕韋 另,特徵為在前述導體ir案以;!緣性樹脂密封者。 置有絕緣層者。 · g /、下層之則述1 c晶片之間配 [發明的效果广述固疋電位係GND電位或者VDD電位。 猎由本發明,在將複數個 中,可將固定基板電位之Ic曰…::女衣之毛路裝置 層以上。 ss片以非洋置狀態疊層於第2 匕可提回含有基板電位固 曰 之層疊封裝之通用神,π 士々 疋之1C日日片的笔路裝置 ic a u .. 同呤降低安裝面積,且可維持哕箄 比日日片之稞晶片的特性。 *対-亥寺 【實施方式】 、 ”第1圖至第5圖,說明本發明之-實施形態。, :圖係表示本實施形態之電路裝置之剖視圖。 :路裝置2。由複數個導電圖案、複數個Μ晶片 蛉脰層構成。複數個I c晶片包括 曰 U日日乃已栝有基板電位固定之ίΓ傷 : 只Μ形態中以叠層安裝基板電位固定之iC曰片 轉其他1C晶片4之兩個晶片為例加以說明。 日日 複數個導電圖案2以預定配線圖案由支持材 導電圖案2可為將印刷基板等絕緣性基板作為支持材1而 形成於其表面者,也可為將絕緣性樹脂作為支持材^而埋 二其崎持。另,將導線架(lead fr繼)作為支' 化’導電圖案2為導線。 $甩圖架2至少含有一個被施加GND電位(或者v卯 316613 7 l26l328 笔位)之固定電位圖案。 圖案加以說明。 、 ,疋電位圖案以下係以GNI: 作為第1層之第1IC晶片 表面側具有電極墊(未圖示),北而果日日片(hrechlp),在 2。另,第1 1C曰Η / 月面例如固著於導雷FI安 C日日片4與支持材1間之固^ 电0/卞
晶片4之構成而以絕 者係错由第1IC 外,第1IC晶片4亦可依^構^性之接著材料3固著。此 」依具構成而不固定於 第11C晶片4之電極墊係藉由、:圖案2上。 合線10等連接。 、疋之¥電圖案2與接 第1IC晶片4表面隔著絕緣性 置有導體層6。導體層6必須 =寺絕緣層5而配 bond)之壓接的預定強产此八文打線接合(wire 胺、糊崎為麵ΓΓΓΓΓΓ板、聚酿亞 導電猪而接著,或形成金屬蒸㈣U㈣=料作為 另,導體層δ如果以鋼箔 成 不要芯部,而直接固著於定的強度,也可 用之接人@^ , 、、^彖層5。使用銅箔時,藉由選 合區域實行預定之鍍覆處理等。 ‘月豆層6上藉由導電姓姑一
曰片8 ^ 9ΤΓ 接者劑7固著有第2層之第2IC 日日8。弟21C晶片8係為如雔搞+曰雕一 電位於基板(晶片背面)而使:。二:…的施加固定 之裸晶片。另,在本說明蚩中 ^片’例如:類比1C . 曰中’以下雖以類比1C晶片為例 ^兄明’但亚不限於此,如上所述,也可為必須向基板 乃a力ϋ固定雷付之 了 ρ曰y Γ 日日。另’所謂固定電位在這裡係指 _電位、VDD電位等電位不變之電位。 316613 1261328
的導電,案:與接合線1。等::财(未θ不)’透過預疋 B安? M曾6透過接合線1 0等連接到GND圖案2a。GND 咖+ 4過導體層6與G仙圓案2a將基板固定於 到充分之特性。 …為非呈浮置狀態,故可得 芦妒/理用I視顯像機使用之電路裝置有時會將數位i 3=…與收訊用ic晶片—體塑模。· 此#,弟UC晶片4為數位信號處
晶片δ為收訊用Ic晶片。 用曰片,弟2IC 雙極電晶料之類比1C-般雖用於固定A板之帝 位,但如第6圖所示,在習知 处 土 电 唯掊名m —千y 且、、,口構中,因不能將基板 、准持在固疋電位,故报難將類tbIC層疊在上層。 但,稭由本實施形態,可使
况晶片8背面(基板),而向導6接觸到上層之第滅 卜卜叮你扣, ^紅層6施加GND電位。由I Π/^晶片不喪失裸w狀態㈣性 層,而k南層疊安裝之通用性,同時可 1曰方、上 型化。 戶、見女I面積之小 接著,參閱第2圖及第3 方法之-例。 U纟不本貫施形態之製造 第1步驟以閱第2圖(A)):準備 案2a之導電圖案2之支持材卜在 ::固-電位圖 印刷基板等絕緣性基板作為支持材 ^ %圖案2係以將 1 形成於其表面者為 316613 9 Ϊ261328 心以說明,但也可將絕緣性樹 t以支持。另’將導線架作為支持材"2埋入其中 導線。 1化,導電圖案2為 第2步驟(參閱第 劑3。此0士 ^ ))·在導電圖案2上塗佈接荽 此吩,按照被安裝之第uc 土怖接者 性/導電性之任—者。妒 日日片之用途,可為絕緣 ^ 者然後,固著第1IC曰^ 弟3步驟(參閱第3圖(^ 導體層6為靖板6a為芯部,而'在體層6。在此, ,鐘膜6b之構造。然後在 板:;:紹寻金< 有絕緣性接著片5。 、7基板6a)背面黏貼
之後,如第3圖(B)所示,將遭雕麻e 晶片4上,由"…“體層6承載於第1IC uc曰月4# 接著片5(或接著劑)固著。另,在第 比曰日月4表面配置右雷扠 社弟 其電極墊—般之圖案。°,故導體層6自然形成露出 上塗參二第3圖(C)):然後,在金屬蒸賴b 丄土仰¥兒性接著劑7等。 此時,導電性接著固著第2IC晶片8。i 區域份以進行塗佈等。 mi接合之固者 然後,將第11C晶片4 + 及第兒極墊與預定的導電圖案2、 =妾另:極塾9與預定的導電圖案2以接合線 連接γ到將導體層6與GND圖案2a以接合線10等 運接’付到如第1同成一 過施加_、VDD等:定:之結構。對於固定電位圖案係透 電位。 D寺固疋電位,而固定第2IC晶片8之基板 316613 )0 I261328 接著’參閱第4圖至第5圖,說明上述電路裝置之封 I例。 首先,參閱第4圖,第4圖(A)係不需要設置安裝基板 土恶的電路裝置,第4圖(B)係使用具有導電圖案之樹脂 片進行過封裝者,第4圖(〇係使用多層配線構造的基板時 之剖視圖。 间、…例如°」在具有所期望的導電圖案之支持基 =上將如圖所不之元件安裝、塑模後,剝去支持基板。 於封^藉由將銅落半钱刻、安裝元件、塑模後,將存在 、封4肢背面之銅箔回蝕( 穿孔導線chbaGk)而達成。另,也可將 在此,叶用二下金屬模具抵接,進行塑模而達成。 亦二::種半钱刻法時為例加以說明。 如弟4圖(A)所示,導雨 31 , 3 .; 係為以CU為主要材料之導兩a 路出。此犄導電圖案2 落、或由Fe,等合金構成Γ導二:為主要材料之導電 電材料,特別是以可钱刻+ y白寺,但也可為其他導 此時,在製造步驟中,在:材料為佳。 方式設置未達到導電落厚二狀導電落,藉由以半钱刻 案2。且分離槽32充填雄槽32,從而形成 之彎曲結構相嵌合而堅固結Γ^31,與導電圖案側面 下方之導電蕩蝕刻,導…透過將分離槽 樹脂31支持者。 卞2分別分離,而為由絕緣性 即,絕緣性樹〜導電圖宰 '面露出,密封電路 1261328 ^置20、接合線10。絕緣型樹脂31可採用透過轉注成型 〜形成之熱硬化性樹脂、或透過射出 (叫^◦請ldlng)形成之熱可塑性樹脂。具體來 况’可使用裱氧樹脂等熱硬化性樹脂、或聚醯亞胺 硫驗等熱可塑性樹脂。另,絕緣性樹脂如果為使用全屬模 ==樹脂、或透過浸潰、塗佈而可包覆之樹 可 =所有的樹脂。該封裝體中,絕緣性樹脂31 =寻,同時也具有支持整個電路模組之功用。由此,; 以絕緣性樹脂31密封,可防止電路裝置自導電圖案 於導其用途以絕緣性或導電性接著劑3固著 方、W圖案(land)2上,在電極墊係 案2連接。另’對於導體層6也 、,泉10,與GND圖案2a連接。 要σ 再者,絕緣性樹脂31之厚度可調整為 之接合㈣之最頂部包覆請…為自該 慮到強度而加厚或減薄。 /子又也可考 構。】緣::脂31背面與導電圖案2背面實質上為相同結 在月面设有將所期望之區域予以門 :广阻焊劑)33,在露出之導電圖案2: 材料而形成背面電極34,作為電路裝置加以完Γ 之配⑷圖⑻所示結構,可提高導電嶋 導電圖案2係與電路裝置2。-體埋入絕緣性樹脂31 3】661:1 1261328 :以破支持。後面將敘述,但此時之導 在絕緣樹月旨4丨# ; β I、旨 、电圖木2係準備 ” 曰41表面形成導電膜42之絕緣樹脂Μ μ * 將導電膜4?岡安儿/ 來树力曰月43,透過 :胰42 ®案化(paUerning)而形成。 ^ 絕緣樹脂4]之材料係為由聚 等高分子構威之脂或環氧樹脂 了於其中混入填充物(illl W生亦 矽、顧Up . 柯ηΎ以坻用玻璃、 虱化鋁、氮化鋁、碳化矽、氮化 (sheet^ 乃次日守為10// m至1〇〇 产 LinSJ 4 為25㈣。 左右。另,市面銷售者最小膜厚· “蛉電肤42最好係以〜為主要材料者、A卜Fe、Fe-r、 s a知之導線架材料,可為以 1 覆於絕緣樹脂2,或點貼透…、鑛法或滅射法包 落。 ^⑽㈣法或鑛覆法形成之金屬 導電=2係以所希望之圖案的光阻㈣覆導電 ,亚猎由化學蝕刻形成所希望之圖案。 、 導電圖案2露出接人蜱^ ㈣r 、良之固者區域,而將其他部分以 保瞍(0僧coat)樹脂44包覆。保護樹脂44係 :: 解之環氧樹脂等以絲網印 ' ,合训/谷 熱硬化者。了、·”刷㈤咖如⑷附^並使之 另’在固著區域上考慮到接合性而形成虬、 膜45。該鍍覆膜45例如將彳早嗜冉Ht ^ &寺k復 例如將保濩树脂44作為遮罩,而在 者區域上進行選擇性地無電解電鍍。 $路衣置20以裸晶片的形態用接著劑3晶片接合(he 316613 1261328 bond)到保護樹脂44上。 黾路衣置2 〇之各電極墊及導體 10連接到導電圖案2及__2£1之_6=過接合線 絕緣樹腊片43係由絕緣性樹脂31 圖案2也埋入絕緣性樹月S31。塑模方法可;’由此,導電 射出成型、塗佈、浸潰等。但考慮到量產^用^主成型、 注成型、射出成型。 屋丨生,取好選用轉 背面係露出絕緣樹脂片43之背面 絕緣樹㈣之期望位置形成開口,在導 分設置外部電極34。 路出部 藉由該結構,電路裝置2〇與其下之導+ 樹脂44作電枓π绦抖、首+卸也 之圖案2以保護 可自由酉^義緣,故導電圖案2即使在電路裝置之下也 說明電:案:之絕緣樹脂片43時為例加以 於此,也可為在第4圖⑴之導 上以保護樹脂44包覆之結構。另,亦 。木2 ——等支持基板上之導:::可㈣ 脂44包覆之構造,因不論在 由 以保邊樹 配線在電路裝置下方,故可實現 接著’第4圖(物現導電圖案 二二。 者。再者,與第4圖⑻相同構成要 二構 省略說明。 尤用;J 付5虎,並 八^確2與電路裝置2。-體埋入絕緣性樹脂31Γ 後面將敎述,但此時之導電賴係備有蝴 1261328 性樹脂41表面之實杯入 背面也實質於全部區域^成第第】導電膜42a、且名 .透過將該等導電膜42圖案化^^之絕緣樹脂月 絕緣性樹脂41、導帝Γ 4? 乂成。 情形相同,導電圖宰 材料係與第4圖(β)時的 案。 復透過化學姓刻形成期㈣ 另’在第4圖(C)中,蕤 緣樹脂41分離成上岸、胃9連接手段46將隔著絕 多層連接細係二:覆 膜在此雖採用Cu,但也 貝通孔47者。鍍覆 安裝面側之導電圖荦=:“Ag,等。 他部分以保護樹脂44包覆 口線10之固著區域,其 电路裝置20以裸晶片^讀仏。 bond)到保護樹脂44上。 心用接者弹Μ晶片接合(die 、車接二i路裝置2〇之電極墊及導體層6透過接八吃 連接到導電圖案2及GND圖案以。 逐^接。線10 導4Γ'脂片43由絕緣性樹脂31包覆,由此,由第i 以一體支持。 -口…埋入絕緣性樹脂31,而得 由絕緣樹脂下方之第2導電膜42b構成之導電圖 :二爾樹脂31露出,但透過以絕緣性樹脂3ι包:: 分、.'巴~、片43而得以-體支持,透過多層連接手 ^ 第1導電膜423構成之導電圖案2電性連接,從而實= 316613 15 1261328 層配線結構。下層之導電圖案2露出形成外部電極34之部 分,將以溶劑溶解之環氧樹脂等進行絲網印刷,以保護樹 脂48包覆大部分,而透過焊材的回焊或焊膏(solder cream) 之絲網印刷在該露出部分設置外部電極34。 另,外部電極34也可用將第2導電膜42b蝕刻,且在 其表面以金或鈀鍍覆膜包覆之凸塊(Bump)電極達成。 接著,利用第5圖來表示使用支持基板之晶片尺寸封 裝之一例。第5圖(A)係於第4圖(C)所示之封裝體中去掉 保護樹脂44時之封裝體,第5圖(B)係表示3層以上之多 層配線結構之情形。 支持基板51係例如為玻璃環氧基板等絕緣性基板。再 者,支持基板51也可採用可撓性片。 在玻璃環氧基板51的表面壓著Cu箔,而配置已圖案 化之導電圖案2,在基板51背面設有外部連接用背面電極 34。且,透過貫通孔TH,電性連接導電圖案2與背面電極 34 ° 基板51表面係透過接著劑3固著裸露的電路裝置 20。在電路裝置20之電極墊及導體層6壓著有接合線10, 與導電圖案2、GND圖案2a連接。 且,電路裝置20、導電圖案2、接合線1 0係由絕緣性 樹脂31密封,與基板51 —體得以支持。絕緣性樹脂31 之材料可採用透過轉注成型法形成之熱硬化性樹脂、或透 過射出成型法形成之熱可塑性樹脂。由此,透過以絕緣性 樹脂31密封全部,可防止電路裝置自基板分離。 16 316613 1261328 另—方面,支持基板51可使用陶瓷基板,此時, 圖案^背面電極嶋由導電”(paste)在基板51 = 面”月面即刷 '燒結而設置’透過貫通孔TH連接,夢由: 緣性樹脂31 —體支持基板31與電路裝置2卜 另#如第5圖⑻所示’於複數個各支持基板51均設 -己▲層構成之導電圖案2,透過貫通孔 藉此即使在有支持基— 樹脂ΐ模=略㈣’但也可在支持基板採用導線架進行 :,、:用金屬盒(。咖)或其他盒裝材料密封。 但透過在欲將其缸^且釘衣…構為例加以說明, 導體層t:導二=成固定電位之丨。晶片背面設置 … t層6與固定電位圖案2a連接,也可杏規 二以上之層®封裝。$,作為第2IC晶片8之,比』曰 片也可為複數層層疊結構。 颂匕1C日日 【圖式簡單說明】 弟1圖係表示本發明電路裝置之剖視圖。 圖⑴及⑻係表示本發明電路裝置之製造方法之 4 第 剖視圖 第 剖視圖 第 圖(A)一(C)係表示本發明電路裝置 之製造方法之 圖(A )至⑹係表*本發”料置之封裝 體例之 剖視圖 第5圖⑷及⑻輪本發明㈣置之封裝體例之 3Ϊ66Ι3 17 1261328 剖視圖。 第6圖係表示習知電 [主要元件符號說明】 1 支持材 2 a 固定電位圖条 4 第1IC晶片 6 導體層 8 第2IC晶片 20 電路裝置 32 分離槽 34 背面電極 43 樹脂片 45 鍍覆膜 47 貫通孔 ΤΗ 貫通孔 置之剖視圖。 導電圖案 接著劑 絕緣層 導電性接著劑 接合線 | 絕緣性樹脂 、41 絕緣樹脂 導電膜 ~ 、4 8 保護樹脂 · 多層連接機構 基板 18 316613
Claims (1)
- ^328 r、. Ψ請專利範圍: 〜锺電路裝置,係具備·- 广位圓案之複數個導電圖案; h 電位被Μ之^晶片的複數個1(:晶片 導體層,其中 層上:::二板曰電位被固定之ic晶片固著於前述導體 ic θ曰片二晶片為上層的方式疊層安裝前述複數個 二片專:將該導體層連接到前述固定電。 p圖案係設於支持基板。路衣置,其中,㈣複數個 、申請專利範圍第1項之電路 導電圖案係將背面露出之方气而/、中,前述複數個 4轉。 式而埋入絕緣性樹脂,而被 ★申請專利範圍第1項之電路 導電圖案以絕緣性樹脂密封。…、中,賴數個 利範圍第1項之電路裝置,其中,在前述導體 ,下層之前述IC晶片之間配置有絕緣層。 二請專利範圍第1項之電路裝置,其中,前述固定· 位為GND電位或VDD電位。 足兒 ^ »66 ] 3 19
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004092561A JP2005277356A (ja) | 2004-03-26 | 2004-03-26 | 回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200532823A TW200532823A (en) | 2005-10-01 |
TWI261328B true TWI261328B (en) | 2006-09-01 |
Family
ID=34988802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093139760A TWI261328B (en) | 2004-03-26 | 2004-12-21 | Circuit device |
Country Status (5)
Country | Link |
---|---|
US (1) | US7405486B2 (zh) |
JP (1) | JP2005277356A (zh) |
KR (1) | KR100613790B1 (zh) |
CN (1) | CN100536127C (zh) |
TW (1) | TWI261328B (zh) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4094614B2 (ja) * | 2005-02-10 | 2008-06-04 | エルピーダメモリ株式会社 | 半導体記憶装置及びその負荷試験方法 |
JP2006261485A (ja) * | 2005-03-18 | 2006-09-28 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP4748648B2 (ja) * | 2005-03-31 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4707548B2 (ja) * | 2005-12-08 | 2011-06-22 | 富士通セミコンダクター株式会社 | 半導体装置、及び半導体装置の製造方法 |
US7872356B2 (en) | 2007-05-16 | 2011-01-18 | Qualcomm Incorporated | Die stacking system and method |
JP5103245B2 (ja) * | 2008-03-31 | 2012-12-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7851928B2 (en) * | 2008-06-10 | 2010-12-14 | Texas Instruments Incorporated | Semiconductor device having substrate with differentially plated copper and selective solder |
TW201041105A (en) * | 2009-05-13 | 2010-11-16 | Advanced Semiconductor Eng | Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package |
US20100289132A1 (en) * | 2009-05-13 | 2010-11-18 | Shih-Fu Huang | Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package |
US8367473B2 (en) * | 2009-05-13 | 2013-02-05 | Advanced Semiconductor Engineering, Inc. | Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof |
TWI425603B (zh) * | 2009-09-08 | 2014-02-01 | Advanced Semiconductor Eng | 晶片封裝體 |
US20110084372A1 (en) | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US8786062B2 (en) | 2009-10-14 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and process for fabricating same |
TWI523188B (zh) * | 2009-11-30 | 2016-02-21 | 精材科技股份有限公司 | 晶片封裝體及其形成方法 |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
TWI463622B (zh) * | 2010-03-04 | 2014-12-01 | Advanced Semiconductor Eng | 具有單側基板設計的半導體封裝及其製造方法 |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8895440B2 (en) * | 2010-08-06 | 2014-11-25 | Stats Chippac, Ltd. | Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
CN103268868A (zh) * | 2013-04-27 | 2013-08-28 | 华中科技大学 | 一种表面贴装用气密性金属外壳 |
JP6242665B2 (ja) * | 2013-11-08 | 2017-12-06 | 新光電気工業株式会社 | 半導体装置 |
KR20160090705A (ko) * | 2015-01-22 | 2016-08-01 | 에스케이하이닉스 주식회사 | 패키지 기판 및 이를 이용한 반도체 패키지 |
JP7179019B2 (ja) * | 2017-12-20 | 2022-11-28 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置 |
JP6927179B2 (ja) * | 2018-10-12 | 2021-08-25 | Tdk株式会社 | 電気部品の積層体とその製造方法 |
US20210118838A1 (en) * | 2019-10-16 | 2021-04-22 | Nanya Technology Corporation | Chip-package device |
CN111342814B (zh) * | 2020-02-10 | 2021-09-21 | 诺思(天津)微***有限责任公司 | 一种体声波滤波器和多工器以及电子设备 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100277438B1 (ko) | 1998-05-28 | 2001-02-01 | 윤종용 | 멀티칩패키지 |
US6437446B1 (en) * | 2000-03-16 | 2002-08-20 | Oki Electric Industry Co., Ltd. | Semiconductor device having first and second chips |
JP3488888B2 (ja) * | 2000-06-19 | 2004-01-19 | アムコー テクノロジー コリア インコーポレーティド | 半導体パッケージ用回路基板の製造方法及びそれを用いた半導体パッケージ用回路基板 |
TW459363B (en) * | 2000-11-22 | 2001-10-11 | Kingpak Tech Inc | Integrated circuit stacking structure and the manufacturing method thereof |
US20020140073A1 (en) * | 2001-03-28 | 2002-10-03 | Advanced Semiconductor Engineering, Inc. | Multichip module |
JP4544784B2 (ja) | 2001-06-11 | 2010-09-15 | Okiセミコンダクタ株式会社 | 半導体スタックドパッケージ及びその製造方法 |
US7034388B2 (en) * | 2002-01-25 | 2006-04-25 | Advanced Semiconductor Engineering, Inc. | Stack type flip-chip package |
US6833287B1 (en) * | 2003-06-16 | 2004-12-21 | St Assembly Test Services Inc. | System for semiconductor package with stacked dies |
-
2004
- 2004-03-26 JP JP2004092561A patent/JP2005277356A/ja active Pending
- 2004-12-21 TW TW093139760A patent/TWI261328B/zh not_active IP Right Cessation
-
2005
- 2005-01-21 US US11/040,931 patent/US7405486B2/en not_active Expired - Fee Related
- 2005-01-27 KR KR1020050007455A patent/KR100613790B1/ko not_active IP Right Cessation
- 2005-01-28 CN CNB200510006103XA patent/CN100536127C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR100613790B1 (ko) | 2006-08-22 |
TW200532823A (en) | 2005-10-01 |
JP2005277356A (ja) | 2005-10-06 |
KR20050095550A (ko) | 2005-09-29 |
US20050212110A1 (en) | 2005-09-29 |
CN100536127C (zh) | 2009-09-02 |
CN1674277A (zh) | 2005-09-28 |
US7405486B2 (en) | 2008-07-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI261328B (en) | Circuit device | |
TW535462B (en) | Electric circuit device and method for making the same | |
US6207473B1 (en) | Process for manufacturing semiconductor wafer, process for manufacturing semiconductor chip, and IC card | |
TW594889B (en) | Wafer level package method and chip packaged by this method | |
TWI313914B (en) | Semiconductor device and a method for manufacturing thereof | |
TWI374531B (en) | Inter-connecting structure for semiconductor device package and method of the same | |
TW511422B (en) | Method for manufacturing circuit device | |
US8435837B2 (en) | Panel based lead frame packaging method and device | |
US20170005057A1 (en) | Chip package | |
TW200903784A (en) | Image sensor package and fabrication method thereof | |
EP1906446A2 (en) | Semiconductor device and manufacturing method thereof | |
TW200818358A (en) | Manufacturing method of semiconductor device | |
US11862600B2 (en) | Method of forming a chip package and chip package | |
TW200805620A (en) | Method of packaging a plurality of integrated circuit devices and semiconductor package so formed | |
TW540148B (en) | Method for making circuit device | |
US20040124516A1 (en) | Circuit device, circuit module, and method for manufacturing circuit device | |
CN101393877A (zh) | 制造半导体器件的方法 | |
TWI260059B (en) | Circuit device | |
TW200532750A (en) | Circuit device and method for making same | |
US20050263482A1 (en) | Method of manufacturing circuit device | |
TWI246364B (en) | Method for making a semiconductor device | |
JP2003273281A (ja) | チップパッケージ及びその製造方法 | |
US11075180B2 (en) | Semiconductor device and method of manufacturing the semiconductor device | |
TW200952135A (en) | Integrated circuit package module and method of the same | |
TW544742B (en) | Semiconductor device and method of production of same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |