CN100536127C - 电路装置 - Google Patents

电路装置 Download PDF

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Publication number
CN100536127C
CN100536127C CNB200510006103XA CN200510006103A CN100536127C CN 100536127 C CN100536127 C CN 100536127C CN B200510006103X A CNB200510006103X A CN B200510006103XA CN 200510006103 A CN200510006103 A CN 200510006103A CN 100536127 C CN100536127 C CN 100536127C
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China
Prior art keywords
chip
circuit arrangement
conductive pattern
conductor layer
substrate
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Expired - Fee Related
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CNB200510006103XA
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English (en)
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CN1674277A (zh
Inventor
加藤敦史
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of CN1674277A publication Critical patent/CN1674277A/zh
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Abstract

一种电路装置，在叠层安装时，由于上层IC芯片和下层IC芯片通过绝缘性粘接剂等绝缘，故当在上层堆积模拟IC芯片时，衬底构成设置状态，不能得到所希望特性。在IC芯片上配置导电层，并在导电层上固定模拟IC芯片。导电层通过利用接合引线等连接在固定电位图案上，可在模拟IC芯片背面(衬底)上施加固定电位。由此，可实现在上层层积模拟IC芯片的安装结构，提高含有模拟IC芯片的电路装置的叠层安装的通用性，同时，降低安装面积，且可提高特性。

Description

电路装置
技术领域
本发明涉及层积多个IC芯片的电路装置，特别是涉及在上层层积衬底电位固定的IC芯片的电路装置。
背景技术
伴随半导体集成电路的高集成化、小型化，叠层型电路装置是作为高集成IC被注目的结构之一。
图6是现有叠层型电路装置结构的剖面图。
在衬底150的一侧面上设置多个配线156，利用粘接部件159固定第一IC芯片151。然后，在其上介由绝缘性粘接部件160层积第二IC芯片152。在各IC芯片151、152表面上分别设置电极焊盘(未图示)，并通过接合引线153等与设于衬底150上的配线156连接。各配线156介由设于衬底150上的通孔TH连接在设于衬底150背面的焊球等外部端子154上。
这些层积IC芯片151、152及接合引线153、配线156由密封树脂155密封，而封装化(例如参照专利文献1)。
专利文献1：特开2002-368189号公报
在上述这样的叠层型电路装置中，第二IC芯片152的固定，为与第一IC芯片151绝缘而通过芯片附着片(ダイアタツチシ一ト)或绝缘性粘接剂等粘接部件160固定。即，第二IC芯片152的衬底以浮置状态安装。
但是，在例如第二IC芯片152上想要采用双极IC等、固定衬底电位而使用的IC芯片时，当在上层层积该芯片时，衬底电位形成浮置状态，不能得到充分的特性。
因此，在双极IC等、含有以固定电位使用的IC的电路装置中，在叠层安装时，以固定电位使用的IC总是配置在最下层，叠层安装的通用性有限。
另外，关于不能进行叠层安装的装置，是将以固定电位使用的IC大致配置在平面上等，也有安装面积增大的问题。
发明内容
本发明是鉴于所述问题点而开发的，本发明的第一方面提供一种电路装置，其包括：含有固定电位图案的多个导电图案；含有固定衬底电位的IC芯片的多个IC芯片；导体层，将固定所述衬底电位的IC芯片固定在所述导体层上，将该IC芯片作为上层，层积安装所述多个IC芯片，该导体层连接在所述固定电位图案上。
所述多个导电图案设在所述支承衬底上。
另外，将所述多个导电图案的背面露出，埋入在绝缘树脂内，并由该绝缘树脂支承。
所述多个导电图案由绝缘树脂密封。
在所述导体层和下层的所述IC芯片之间配置有绝缘层。
另外，所述固定电位是GND电位或VDD电位。
根据本发明，在层积安装多个IC芯片的电路装置中，可将固定衬底电位的IC芯片在不浮置状态下层积两层以上。
由此，可在提高含有固定衬底电位的IC芯片的电路装置的叠层安装的通用性的同时，降低安装面积，且维持该IC芯片的裸片特性。
附图说明
图1是本发明电路装置的剖面图；
图2(A)、(B)是表示本发明电路装置制造方法的剖面图；
图3(A)、(B)、(C)是表示本发明电路装置制造方法的剖面图；
图4(A)、(B)、(C)是表示本发明电路装置封装例的剖面图；
图5(A)、(B)是表示本发明电路装置封装例的剖面图；
图6是现有电路装置的剖面图。
符号说明
1   支承件
2   导电图案
2a  固定电位图案
3   粘接剂
4   第一IC芯片
5   绝缘层
6   导体层
7   导电性粘接剂
8   第二IC芯片
10  接合引线
20  电路装置
31  绝缘树脂
33  绝缘树脂
34  背面电极
41  绝缘树脂
42  导电膜
43  树脂片
44  外敷树脂
45  镀敷膜
46  多层连接装置
47  通孔
48  外敷树脂
51  衬底
TH  通孔
具体实施方式
参照图1～图5说明本发明的一实施例。
图1是本发明实施例电路装置的剖面图。
电路装置20由多个导电图案、多个IC芯片、导体层构成。在多个IC芯片中含有固定衬底电位的IC芯片，在本实施例中，以层积安装固定衬底电位的IC芯片8和其它IC芯片4两个芯片为例进行说明。
多个导电图案2以规定的配线图案利用支承件1支承。导电图案2可以是将印刷线路板等绝缘性衬底作为支承件1而形成在其表面上的导电图案，也可以是将绝缘树脂作为支承件1埋入其中并被支承。另外，在使引线架作为支承件1时，导电图案2是引线。
导电图案2至少含有一个施加GND电位(或VDD电位)的固定电位图案2a。另外，固定电位图案以下作为GND图案进行说明。
第一层的第一IC芯片4是裸片，在表面侧具有电极焊盘(未图示)，背面被固定在例如导电图案2上。另外，第一IC芯片4和支承件1的固定根据第一IC芯片4的结构由绝缘性或导电性粘接材料3固定。另外，第一IC芯片4根据其结构也可以不固定在导电图案2上。
第一IC芯片4的电极焊盘和规定的导电图案2利用接合引线10等连接。
在第一IC芯片4表面介由绝缘性粘接剂等绝缘层5配置有导体层6。导体层6必须具有承受引线接合的压装的规定强度，以例如硅衬底、聚酰亚胺、环氧树脂等为心件，在其表面粘接铝等作为导电箔，或形成金属蒸镀膜等。
另外，只要通过铜箔等能得到规定的强度，则可不需要心件，并直接固定在绝缘层5上，形成导体层6。在使用铜箔时，根据采用的接合引线要在引线接合区域施行规定的镀敷处理等。
在导体层6上利用导电性粘接剂7固定第二层的第二IC芯片8。第二IC芯片8是如双极晶体管等这样在衬底(芯片背面)施加固定电位使用的IC芯片，例如是模拟IC的裸片。另外，在本说明书中，以以下模拟IC芯片为例进行说明，但不限于此，如上所述，只要是需要在衬底上施加固定电位的IC芯片即可。另外，固定电位在此指GND电位、VDD电位等电位不变动的电位。
在第二IC芯片8的表面也设置电极焊盘(未图示)，利用接合引线10等与规定的导电图案2连接。
而且，导体层6利用接合引线10等连接在GND图案2a上。GND图案2a是如前所述施加固定电位的导电图案，由此，第二IC芯片8介由导体层6和GND图案2a将衬底固定为GND电位。即第二IC芯片8由于不构成浮置状态，故可得到充分的特性。
例如，在数字电视接收机中使用的电路装置中，有将数字信号处理用IC芯片和接收用IC芯片一体模制的情况。此时，第一IC芯片4是数字信号用IC芯片，第二IC芯片8是接收用IC芯片。
双极晶体管等模拟IC通常将衬底电位固定使用，但如图6，在现有的叠层结构中，由于不能将衬底形成固定电位，故在上层叠置模拟IC是困难的。
但是，根据本实施例，可使导体层6与上层第二IC芯片8的背面(衬底)接触，并在导体层6上施加GND电位。由此，可不使裸片的状态的特性降低而在上层层积模拟IC芯片，可提高叠层安装的通用性，同时，可实现安装面积的小型化。
其次，参照图2及图3说明本实施例制造方法之一例。
第一工序(参照图2(A))：准备设置含有固定电位图案2a的导电图案2的支承件1。在此，导电图案2以将印刷线路板等绝缘性衬底作为支承件1在其表面形成的导电图案为例说明，但也可以以绝缘树脂为支承件1，在其中埋入并支承导电图案。另外，在将引线架作为支承件1时，导电图案2形成引线。
第二工序(参照图2(B))：在导电图案2上涂敷粘接剂3。此时，可以根据安装的第一IC芯片的用途，选择绝缘性/导电性之一。然后，固定第一IC芯片4。
第三工序(参照图3(A))：其次，准备导体层6。在此，导体层6形成以硅衬底6a为心件，在表面上形成例如铝等金属蒸镀膜6b的结构。然后，导体层6(硅衬底6a)背面粘附绝缘性粘接片5。
然后，如图3(B)，将导体层6搭载在第一IC芯片4上，利用绝缘性粘接片5(或粘接剂)固定。另外，由于在第一IC芯片4表面上配置有电极焊盘，故导体层6当然形成该电极焊盘露出这样的图案。
第四工序(参照图3(C))：然后，在金属蒸镀膜6b上涂敷导电性粘接剂7等。在其上固定第二IC芯片8。此时，在导体层6上留下引线接合的固定区域涂敷导电性粘接剂7等。
然后，利用接合引线10等连接第一IC芯片4的电极焊盘和规定的导电图案2、及第二IC芯片8的电极焊盘9和规定的导电图案2。然后，导体层6通过接合引线10等与GND图案2a连接，得到图1所示的结构。通过在固定电位图案上施加GND、VDD等固定电位，固定第二IC芯片8的衬底电位。
其次，参照图4～图5说明所述电路装置的封装例。
首先，参照图4，图4(A)是不需要安装衬底的类型的电路装置，图4(B)是使用具有导电图案的树脂片进行封装的装置，图4(C)是使用多层配线结构衬底时的剖面图。
图4(A)中，可在具有例如所希望的导电图案的支承衬底上如图所示安装、模制元件后，剥离支承衬底。另外，可半蚀刻铜箔，安装、模制元件后，蚀刻存在于封装件背面的铜箔来实现。另外，在使冲切的引线架的背面接触下模具的同时进行模制也可以实现。在此，以采用第二次半蚀刻的情况为例进行说明。
即，如图4(A)，导电图案2被埋入绝缘树脂31内，并被其支承，背面从绝缘树脂31露出。此时，导电图案2是以Cu为主材料的导电箔、以Al为主材料的导电箔、或由Fe-Ni等合金构成的导电箔等，但也可以采用其它导电材料，最好为可蚀刻的导电材料。
此时，在制造工序中，通过利用半蚀刻在片状导电箔上设置未达到导电箔厚度的分离槽32，形成导电图案2。然后，分离槽32内填充绝缘树脂31，与导电图案侧面的弯曲结构嵌合，而紧固地结合。然后，通过蚀刻分离槽32下方的导电箔，将导电图案2一一分离，并利用绝缘树脂31支承。
即，绝缘树脂31使导电图案2的背面露出，密封电路装置20、接合引线10。绝缘树脂31可采用通过传递模制形成的热硬性树脂或通过注入模制形成的热塑性树脂。具体地说，可使用环氧树脂等热硬性树脂、聚酰亚胺树脂、聚苯硫醚等热塑性树脂。另外，绝缘树脂只要为了使用模具固定的树脂、可由浸渍、涂敷而覆盖的树脂，则可采用所有树脂。在该封装件中，绝缘树脂31密封电路装置20等，同时，还具有支承电路模块整体的作用。这样，通过利用绝缘树脂密封整体，可防止电路装置从导电图案2分离。
电路装置20根据其用途，被绝缘性或导电性粘接剂3固定在导电图案(接合面)2上，在电极焊盘上热压装接合引线10，与导电图案2连接。另外，在导体层6上也热压装接合引线10，与GND图案2a连接。
另外，调整绝缘树脂31的厚度，从电路装置20的接合引线10的最顶端起覆盖大约100μm左右。该厚度也可以根据强度而增厚、减薄。
绝缘树脂31的背面和导电图案2的背面形成实质上一致的结构。而且，在背面设置在所希望的区域开口的绝缘树脂(例如焊锡保护剂)33，在露出的导电图案2上覆盖焊锡等导电材料，形成背面电极34，完成电路装置。
其次，根据图4(B)的结构，可提高导电图案2的配线自由度。
导电图案2与电路装置20一体被埋入绝缘性树脂31内，被其支承。此时的导电图案2通过准备在绝缘树脂41的表面形成导电膜42的绝缘树脂片43并构图导电膜42而形成，这一点后述。
绝缘树脂41的材料利用由聚酰亚胺树脂或环氧树脂等高分子构成的绝缘材料构成。另外，考虑热传导性，也可以在其中混入填充物。材料可考虑玻璃、氧化硅、氧化铝、氮化铝、硅碳化物、氮化硼等。绝缘树脂41的膜厚在涂敷膏状物质形成片的铸造法时为10～100μm程度。另外，市售的25μm为最小膜厚。
导电膜42最好为以Cu为主材料的材料或Al、Fe、Fe-Ni、或公知的引线架的材料，利用镀敷法、蒸镀法或喷溅法覆盖在绝缘树脂2上，也可以粘贴利用压延法或镀敷法形成的金属箔。
导电图案2利用所希望图案的光致抗蚀剂覆盖导电膜42上，通过化学蚀刻形成所希望的图案。
导电图案2使接合引线的固定区域露出，利用外敷树脂44覆盖其它的部分。外敷树脂44是通过网印粘附利用溶剂溶解的环氧树脂等并使其热硬化的树脂。
另外，考虑接合性，在固定区域上形成Au、Ag等镀敷膜45。该镀敷膜45以例如外敷树脂44为掩膜，在固定区域上选择地进行无电解镀敷。
电路装置20通过粘接剂3在裸片状态下被安装在外敷树脂44上。
而且，电路装置20的各电极焊盘及导体层6利用接合引线10连接在导电图案2及GND图案2a的固定区域上。
绝缘树脂片43被绝缘性树脂31覆盖，由此，导电图案2也被埋入绝缘性树脂31内。模制的方法可以通过传递模制、注入模制、涂敷、浸渍等进行。但是，在考虑批量生产时，最好通过传递模制、注入模制进行。
背面露出绝缘树脂片43的背面即绝缘树脂41，将绝缘树脂41的所希望位置开口，在导电图案2的露出部分设置外部电极34。
根据该结构，电路装置20和其下的导电图案2被外敷树脂44电绝缘，故导电图案2在电路装置之下也可以自由地配线。
以上，以形成导电图案2的绝缘树脂片43的情况为例进行了说明，但不限于此，也可以是利用外敷树脂44覆盖图4(A)的导电图案2上的结构。另外，也可以是利用外敷树脂44覆盖挠性板等支承衬底上设置的导电图案2上的结构，无论何种情况，均可以在电路装置的下方对导电图案2进行配线，故可实现配线自由度提高的封装件。
其次，图4(C)是实现导电图案2的多层配线结构的图示。另外，与图4(B)相同的构成要素利用同一符号表示，省略说明。
导电图案2与电路装置20一体地被埋入绝缘性树脂31内，并被其支承。此时的导电图案2如下形成，准备在绝缘树脂41表面的实质上整个区域上形成第一导电膜42a，并在背面也在实质上整个区域上形成第二导电膜42b的绝缘树脂片43，对这些绝缘膜42构图而形成。
绝缘树脂41、导电膜42的材料与图4(B)的情况相同，导电图案2利用所希望图案的光致抗蚀剂覆盖第一导电膜42a、第二导电膜42b上，并通过化学蚀刻形成所希望的图案。
另外，在图4(C)中，利用多层连接装置46电连接介由绝缘树脂41分离为上层、下层的导电图案2。多层连接装置46是在通孔47内埋入Cu等镀敷膜的装置。镀敷膜在此采用Cu，但也可以采用Au、Ag、Pd等。
安装面侧的导电图案2使接合引线10的固定区域露出，利用外敷树脂44覆盖其它部分，并在固定区域上设置镀敷膜45。
电路装置20在裸片状态下由粘接剂9装在外敷树脂44上。
而且，电路装置20的电极焊盘及导体层6通过接合引线10连接在导电图案2及GND图案2a上。
绝缘树脂片43被绝缘树脂31覆盖，由此，由第一镀敷膜42a构成的导电图案2也被埋入绝缘性树脂31内，并被其一体地支承。
绝缘树脂下方的由第二导电膜42b构成的导电图案2从绝缘树脂31露出，但通过利用绝缘树脂31覆盖绝缘片43的一部分而被一体地支承，和第一导电膜42a构成的导电图案2介由多层连接装置12电连接，实现多层配线结构。下层的导电图案2将形成外部电极34的部分露出，网印利用溶剂溶解的环氧树脂等，利用外敷树脂48覆盖大部分，并利用焊锡的回流或焊锡膏的网印在该露出部分设置外部电极34。
另外，即使是蚀刻第二导电膜42b，利用金或钯镀敷膜覆盖其表面的凸起电极也可以实现外部电极34。
其次，图5表示使用支承衬底的芯片尺寸封装之一例。图5(A)是在图4(C)所示的封装中不需要外敷树脂44时的封装件，图5(B)是三层以上的多层配线结构的情况。
支承衬底51是例如玻璃环氧树脂衬底等绝缘性衬底。另外，作为支承衬底51采用挠性板也同样。
在玻璃环氧树脂衬底51的表面压装Cu箔，配置构图后的导电图案2，并在衬底51背面设置外部连接用背面电极34。然后，介由通孔TH电连接导电图案2和背面电极34。
在衬底51表面利用粘接剂3固定裸的电路装置20。在电路装置20的电极焊盘和导体层6上压装接合引线10，与导电图案2、GND图案2a连接。
然后，电路装置20、导电图案2、接合引线10由绝缘树脂31密封并与衬底51被一体地支承。绝缘树脂31的材料可采用利用传递模制形成的热硬性树脂或利用注入模制形成的热塑性树脂。这样，通过利用绝缘树脂31密封整体，可防止电路装置从衬底分离。
另一方面，支承衬底51也可以使用陶瓷衬底，此时，导电图案2及背面电极34通过导电膏在衬底51的表面和背面印刷、烧结设置，并介由通孔TH连接，利用绝缘树脂31一体地支承衬底31和电路装置20。
另外，如图5(B)，设置多个在每个支承衬底51上作为配线层的导电图案2，通过介由通孔TH将上层和下层的导电图案2连接，即使在具有支承衬底51时，也可以形成多层配线结构。
另外，图示省略，支承衬底也可以采用引线架，并进行树脂模制，也可以通过金属壳或其它壳件进行密封。
另外，本实施例以两层叠层安装结构为例进行了说明，但通过在以衬底电位作为固定电位的IC芯片的背面设置导体层6，并将导体层6与固定电位图案2连接，也可以进行两层以上的叠层安装。另外，作为第二IC芯片8的模拟IC芯片也可以是多层叠置的结构。
另外，在图3(A)中，是在安装第一IC芯片4后设置导体层6，但也可以在第一IC芯片处于晶片状态时设置。
通常，第一IC芯片4是在形成最上层的电极例如电极焊盘等后覆盖钝化膜。然后，使钝化膜的一部分开口，露出电极焊盘。
但是，也可以在开口之前，要在晶片整个面上介由绝缘层(粘接性绝缘树脂)5层积晶片尺寸的导体层6，并如图3(A)所示，按规定尺寸对导体层6构图。然后，在整个面上层积导电性粘接剂7，使导电性粘接剂7、粘接性绝缘树脂5、钝化膜开口，露出第一IC芯片4的电极焊盘。这样，可预先准备载置导体层6的第一IC芯片4，可简化安装工序。
相反，也可以在第二IC芯片8的背面形成导体层6。此时，由于接合引线10要固定在导体层6上，故必须使导体层6的尺寸大于第二IC芯片8。也就是说，单独切割晶片状态的第二IC芯片8，然后，在第二IC芯片8的背面设置导电性粘接剂7、导体层6、粘接性绝缘树脂5。并且，也可以在处于晶片状态的第一IC芯片4上层积第二IC芯片8。

Claims (6)

1、一种电路装置，其特征在于，包括：含有固定电位图案的多个导电图案；含有固定衬底电位的IC芯片的多个IC芯片；导体层，其中，经由所述导体层层积安装所述多个IC芯片，将固定所述衬底电位的IC芯片固定在所述导体层上，将该IC芯片作为上层，该导体层与所述固定电位图案连接。
2、如权利要求1所述的电路装置，其特征在于，所述多个导电图案被设置在支承衬底上。
3、如权利要求1所述的电路装置，其特征在于，所述多个导电图案露出背面埋入绝缘性树脂并被其支承。
4、如权利要求1所述的电路装置，其特征在于，所述多个导电图案由绝缘性树脂密封。
5、如权利要求1所述的电路装置，其特征在于，在所述导体层和下层的所述IC芯片之间配置有绝缘层。
6、如权利要求1所述的电路装置，其特征在于，所述固定电位是GND电位或VDD电位。
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