TWI425603B - 晶片封裝體 - Google Patents

晶片封裝體 Download PDF

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Publication number
TWI425603B
TWI425603B TW098130284A TW98130284A TWI425603B TW I425603 B TWI425603 B TW I425603B TW 098130284 A TW098130284 A TW 098130284A TW 98130284 A TW98130284 A TW 98130284A TW I425603 B TWI425603 B TW I425603B
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TW
Taiwan
Prior art keywords
metal foil
chip package
wafer
foil layer
patterned metal
Prior art date
Application number
TW098130284A
Other languages
English (en)
Other versions
TW201110286A (en
Inventor
Kuang Hsiung Chen
Pao Ming Hsieh
Yuan Chang Su
Shih Fu Huang
Karl Appelt Bernd
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW098130284A priority Critical patent/TWI425603B/zh
Priority to US12/607,405 priority patent/US8330267B2/en
Publication of TW201110286A publication Critical patent/TW201110286A/zh
Application granted granted Critical
Publication of TWI425603B publication Critical patent/TWI425603B/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Description

晶片封裝體
本發明是有關於一種封裝體，且特別是有關於一種高製程良率的晶片封裝體。
半導體工業是近年來發展速度最快之高科技工業之一，隨著電子技術的日新月異，高科技電子產業的相繼問世，使得更人性化、功能更佳的電子產品不斷地推陳出新。
目前，在半導體製程當中，由於半導體晶片相當精密，故常以封裝的方式來保護半導體晶片。晶片封裝的方法是先將一晶片配置於一承載器上，然後打線連接晶片與承載器，之後再於承載器上形成一包覆晶片與導線的封裝膠體，以形成一晶片封裝體。
晶片封裝體的主要功能包括：(1)提供晶片多個電性連接至外部電子元件的電流路徑；(2)晶片的多個高密度的接點可分別電性連接至承載器的多個低密度接點，並透過這些低密度接點與外部電子元件電性連接；(3)將晶片產生的熱能發散至外界；(4)保護晶片免於受到外界環境的污染。
本發明提供一種晶片封裝體，其圖案化金屬箔層(metal foil)可穩固地承載晶片。
本發明提出一種晶片封裝體包括一圖案化金屬箔層、一第一圖案化介電層、一晶片、一黏著層、多條導線以及一封裝膠體。圖案化金屬箔層具有相對的一第一表面與一第二表面。第一圖案化介電層配置於圖案化金屬箔層的第二表面上，其中第一圖案化介電層具有多個第一開口以暴露出至少部分圖案化金屬箔層，並形成下方對外電性連接的複數個第二接點。晶片配置於圖案化金屬箔層的第一表面上。黏著層配置於晶片與圖案化金屬箔層之間。導線分別連接晶片與圖案化金屬箔層，其中部分第一圖案化介電層位於導線與圖案化金屬箔層相接之處的下方，且部分第一圖案化介電層和導線與圖案化金屬箔層係為重疊於一平面。封裝膠體配置於第一表面上，並覆蓋晶片與導線。
本發明提出一種晶片封裝體包括一圖案化金屬箔層、一第一圖案化介電層、一晶片、一黏著層、多條導線以及一封裝膠體。圖案化金屬箔層具有相對的一第一表面與一第二表面，圖案化金屬箔層包括一晶片座與多個引腳，引腳配置於晶片座的周邊。第一圖案化介電層配置於圖案化金屬箔層的第二表面上，其中第一圖案化介電層具有多個第一開口以暴露出至少部分圖案化金屬箔層，並形成下方對外電性連接的複數個第二接點，且部分第一開口位於晶片座之正下方並暴露出晶片座。晶片配置於圖案化金屬箔層的第一表面上，並位於晶片座上。黏著層配置於晶片與圖案化金屬箔層之間。導線分別連接晶片與圖案化金屬箔層，且至少部分導線與引腳相連接。封裝膠體配置於第一表面上，並覆蓋晶片與導線。
本發明提出一種晶片封裝體包括一圖案化金屬箔層、一圖案化介電層、一晶片、多個導電凸塊以及一封裝膠體。圖案化金屬箔層具有相對的一第一表面與一第二表面。圖案化介電層配置於圖案化金屬箔層的第二表面上，其中圖案化介電層具有多個開口以暴露出至少部分圖案化金屬箔層，並形成下方對外電性連接的複數個接點。晶片配置於第一表面上。導電凸塊配置於晶片與圖案化金屬箔層之間。封裝膠體配置於第一表面上，並覆蓋晶片與導電凸塊。
基於上述，由於本發明之圖案化金屬箔層與圖案化介電層所構成的承載板可穩固地承載晶片，且承載板相當薄，故可減少晶片封裝體的整體厚度，而有助於使晶片封裝體朝向輕、薄的方向發展。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1至圖4與圖6至圖10分別繪示本發明之多個實施例之晶片封裝體的剖面圖。圖5A繪示本發明之一實施例之晶片封裝體的剖面圖，圖5B繪示圖5A之晶片封裝體的仰視圖。圖11繪示圖10之晶片封裝體的仰視圖。
請參照圖1，本實施例之晶片封裝體100包括一圖案化金屬箔層110、一晶片120、多條導線130、一圖案化介電層140、一封裝膠體150以及一黏著層160。本實施例之晶片封裝體100例如為一四方扁平無引腳封裝體。
圖案化金屬箔層110具有相對的一第一表面112與一第二表面114。在本實施例中，圖案化金屬箔層110包括一晶片座116與多個引腳118，其中晶片座116為一連續之導電層。晶片120配置於晶片座116上並位於第一表面112上，引腳118配置於晶片座116的周邊。圖案化金屬箔層110的材質包括銅或是其他導電性質良好的材料，圖案化金屬箔層110可具有至少一無訊號之接墊(dummy pad)(未繪示)及至少一無訊號之金屬導線(dummy trace)(未繪示)。
導線130連接晶片120與圖案化金屬箔層110，其中導線130的材質包括金、銅或鋁。詳細而言，在本實施例中，一些導線130可連接引腳118與晶片120，另一些導線130可選擇性地連接晶片座116與晶片120，以使晶片120接地。此外，為使晶片120可固定在圖案化金屬箔層110上，可在晶片120與圖案化金屬箔層110之間配置一黏著層160，且黏著層160的材質可為絕緣材料(例如樹脂)。
圖案化介電層140配置於第二表面114上並具有多個開口142，開口142暴露出部分第二表面114並形成對外電性連接的多個第二接點E2。在本實施例中，圖案化介電層140與圖案化金屬箔層110的總厚度T的範圍約在40微米～130微米之間。在本實施例中，圖案化介電層140與圖案化金屬箔層110可構成一承載板。
在本實施例中，為避免第二接點E2受到外界環境污染或氧化，可在第二接點E2上形成一表面處理層170，表面處理層170之材料包括鎳/金、化鎳鈀金、銀、錫及其合金、錫膏或有機化合物。封裝膠體150可配置於第一表面112上，並覆蓋晶片120、導線130、圖案化金屬箔層110以及圖案化介電層140。
值得注意的是，由於本實施例之圖案化金屬箔層110與圖案化介電層140所構成的承載板可穩固地承載晶片120，且承載板相當薄，故可減少晶片封裝體100的整體厚度，而有助於使晶片封裝體100朝向輕、薄的方向發展。再者，本實施例之圖案化金屬箔層110亦相當薄，故可降低製作成本。
請參照圖2，本實施例之晶片封裝體100A的結構相似於圖1的晶片封裝體100的結構，兩者的差異之處在於本實施例之圖案化介電層140A的一些開口142A是位於晶片120下方並暴露出晶片座116。開口142A可位於晶片座116的正下方。在本實施例中，可在開口142A所暴露出的第二接點E2以及晶片座116上形成一表面處理層170A。
如此一來，晶片120於運作中所產生的熱可傳導到晶片座116，再從暴露出晶片座116的開口142A傳導到外界環境中。此外，當一些導線130連接於晶片座116以及晶片120之間時，晶片120可電性連接到晶片座116，再經由晶片座116之被開口142A所暴露出的部分電性連接至其他的電子元件(例如線路板)。
請參照圖3，本實施例之晶片封裝體100B的結構相似於圖1的晶片封裝體100的結構，兩者的差異之處在於本實施例之部分圖案化介電層140B是位於導線130與圖案化金屬箔層110相接之處D的下方。換言之，圖案化金屬箔層110、導線130與圖案化介電層140B可重疊於一平面。如此一來，圖案化介電層140B可支撐圖案化金屬箔層110之受到打線衝擊壓力的部分，以使圖案化金屬箔層110不至於產生過大的變形並提高打線製程的良率。此外，在本實施例中，可選擇性地使二導線130連接至同一引腳118上。
請參照圖4，本實施例之晶片封裝體100C的結構相似於圖3的晶片封裝體100B的結構，兩者的差異之處在於本實施例之圖案化介電層140C的一些開口142C是位於晶片120下方並暴露出晶片座116。
請同時參照圖5A與圖5B，本實施例之晶片封裝體100D的結構相似於圖3的晶片封裝體100B的結構，兩者的差異之處在於本實施例之圖案化介電層140D的多個開口142D是位於圖案化金屬箔層110的外緣，且這些開口142D為多個開孔。
請參照圖6，本實施例之晶片封裝體100E的結構相似於圖5的晶片封裝體100D的結構，兩者的差異之處在於本實施例之圖案化介電層140E的一些開口142E是位於晶片120下方並暴露出晶片座116。
請參照圖7，本實施例之晶片封裝體100F的結構相似於圖1的晶片封裝體100的結構，兩者的差異之處在於本實施例之晶片封裝體100F還包括一圖案化介電層190。圖案化介電層190配置於圖案化金屬箔層110的第一表面112上，並貫穿圖案化金屬箔層110而與圖案化介電層140相連。在本實施例中，圖案化介電層190、140與圖案化金屬箔層110的總厚度T1的範圍約在40微米～130微米之間。
圖案化介電層190具有多個開口192，且開口192暴露出部分第一表面112，以形成上方對外電性連接的多個第一接點E1。在本實施例中，圖案化介電層190覆蓋部分晶片座116，且圖案化介電層190之材料係為防銲綠漆(solder mask，SM)、液晶聚合物(liquid crystal polyester，LCP)、或聚丙烯(polypropylene，PP)。導線130是由晶片120經開口192連接至圖案化金屬箔層110。在其他實施例中，圖案化介電層140的部分開口(未繪示)可位於晶片座116正下方並暴露出晶片座116。
請參照圖8，本實施例之晶片封裝體100G的結構相似於圖7的晶片封裝體100F的結構，兩者的差異之處在於本實施例之部分圖案化介電層140G是位於開口192下方。如此一來，圖案化介電層140G可支撐圖案化金屬箔層110之受到打線衝擊壓力的部分，以使圖案化金屬箔層110不至於產生過大的變形並提高打線製程的良率。
此外，在本實施例中，圖案化介電層190可具有多個開口192，而這些開口192其中之二可暴露出同一引腳118，且可選擇性地使二導線130分別通過前述二開口192而連接至同一引腳118。
請參照圖9，本實施例之晶片封裝體100H的結構相似於圖8的晶片封裝體100G的結構，兩者的差異之處在於本實施例之部分圖案化介電層140H的開口142H是位於圖案化金屬箔層110的外緣。
請同時參照圖10與圖11，本實施例之晶片封裝體100I的結構相似於圖1的晶片封裝體100的結構，兩者的差異之處在於本實施例之圖案化金屬箔層110I具有多個引腳118I，且晶片120是配置於引腳118I上。值得注意的是，在圖11中，區域B是代表位於晶片120下方的區域。
在本實施例中，引腳118I包括向內展開(fan in)的引腳118J，引腳118J是由晶片120的外圍向晶片120的下方延伸。詳細而言，晶片120是配置於引腳118J上，且導線130I連接晶片120與引腳118J的打線部A1，其中圖案化介電層140I之位於晶片120的下方(即區域B)的開口142I可暴露出引腳118J之承載晶片120的部分。換言之，本實施例可藉由調整引腳118J的配置方式以及圖案化介電層140I的開口142I的位置，而使晶片封裝體100I之對外電性連接的接點位於晶片120下方，以增加前述接點之可配置的面積以及降低前述接點的密度。
此外，在本實施例中，引腳118I還可包括向外展開(fan out)的引腳118K，引腳118K是朝向遠離晶片120的方向延伸。詳細而言，導線130J連接晶片120與引腳118K的打線部A2，且圖案化介電層140I之位於晶片120外圍的開口142I可暴露出引腳118K。換言之，本實施例可藉由調整引腳118K的配置方式以及圖案化介電層140I的開口142I的位置，而使晶片封裝體100I之對外電性連接的接點位於晶片120外圍。
另外，在本實施例中，可選擇性地在圖案化介電層140I的多個開口142I中分別配置多個銲球180，並使銲球180與引腳118I電性連接。銲球180例如為一無訊號之銲球(dummy ball)(未繪示)。
圖12繪示本發明另一實施例之晶片封裝體的剖面圖。圖13繪示圖12之晶片封裝體的仰視圖。圖14繪示本發明另一實施例之晶片封裝體的剖面圖。圖15繪示圖14之晶片封裝體的仰視圖。
請同時參照圖12與圖13，本實施例之晶片封裝體200包括一圖案化金屬箔層210、一晶片220、多個導電凸塊230、一圖案化介電層240以及一封裝膠體250。圖案化金屬箔層210具有相對的一第一表面212與一第二表面214。晶片220配置於第一表面212上。在本實施例中，圖案化金屬箔層210包括多個引腳218，引腳218具有一承載晶片220的承載端218A以及一朝向遠離晶片220的方向延伸的外延端218B。
導電凸塊230配置於晶片220與圖案化金屬箔層210之間，以電性連接晶片220與圖案化金屬箔層210，導電凸塊230例如為銅柱(copper pillar)、銅凸塊(copper stud bump)或金凸塊(golden stud bump)。在本實施例中，為保護導電凸塊230不受外界環境的污染或損害並使晶片220與圖案化金屬箔層210之間的接合更為穩固，可在晶片220與圖案化金屬箔層210之間配置一底膠260，以包覆導電凸塊230並連接晶片220與圖案化金屬箔層210。封裝膠體250配置於第一表面212上，並覆蓋晶片220、導電凸塊230、底膠260與圖案化金屬箔層210。
圖案化介電層240配置於第二表面214上並具有多個開口242，開口242暴露出部分第二表面214，並形成下方對外電性連接的多個接點E。在本實施例中，一些開口242是位於晶片220的周邊並暴露出引腳218的外延端218B，另一些開口242是位於晶片220下方並暴露出位於晶片220下方的引腳218。
在本實施例中，可在接點E上形成一表面處理層270。此外，在本實施例中，可將多個銲球280分別配置在圖案化介電層240的多個開口242中，並使銲球280電性連接至圖案化金屬箔層210。
請同時參照圖14與圖15，本實施例之之晶片封裝體200A的結構相似於圖12的晶片封裝體200的結構，兩者的差異之處在於本實施例之圖案化介電層240A的多個開口242A皆位於晶片220的外圍。換言之，圖案化介電層240A的所有開口242A皆位於晶片220之下方區域B的外圍。
在本實施例中，晶片封裝體200A的多個引腳218皆為向外展開式(fan out)的引腳，以使晶片封裝體200A之對外電性連接的接點皆位於晶片220外圍。如圖15所示，導電凸塊230與引腳218的連接之處C皆位於晶片220之下方區域B中，而引腳218向遠離晶片220的方向延伸，且開口242A暴露出引腳218之遠離晶片220的一端。
綜上所述，由於本發明之圖案化金屬箔層與圖案化介電層所構成的承載板可穩固地承載晶片，且承載板相當薄，故可減少晶片封裝體的整體厚度，而有助於使晶片封裝體朝向輕、薄的方向發展。再者，本發明之圖案化金屬箔層亦相當薄，故可降低製作成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、100A、100B、100C、100D、100E、100F、100G、100H、100I、200、200A．．．晶片封裝體
110、110I、210．．．圖案化金屬箔層
112、212．．．第一表面
114、214．．．第二表面
116．．．晶片座
118、118I、118J、118K、218．．．引腳
120、220．．．晶片
130、130I、130J．．．導線
140、140A、140B、140C、140D、140E、140G、140H、140I、190、240、240A．．．圖案化介電層
142、142A、142C、142D、142E、142H、142I、192、242、242A．．．開口
150、250．．．封裝膠體
160．．．黏著層
170、170A、270．．．表面處理層
180、280．．．銲球
218A．．．承載端
218B．．．外延端
230．．．導電凸塊
260．．．底膠
A1、A2．．．打線部
B．．．區域
C．．．導電凸塊與引腳的連接之處
D．．．導線與圖案化金屬箔層相接之處
E．．．接點
E1．．．第一接點
E2．．．第二接點
T、T1．．．總厚度
圖1至圖4與圖6至圖10分別繪示本發明之多個實施例之晶片封裝體的剖面圖。
圖5A繪示本發明之一實施例之晶片封裝體的剖面圖。
圖5B繪示圖5A之晶片封裝體的仰視圖。
圖11繪示圖10之晶片封裝體的仰視圖。
圖12繪示本發明另一實施例之晶片封裝體的剖面圖。
圖13繪示圖12之晶片封裝體的仰視圖。
圖14繪示本發明另一實施例之晶片封裝體的剖面圖。
圖15繪示圖14之晶片封裝體的仰視圖。
100．．．晶片封裝體
110．．．圖案化金屬箔層
112．．．第一表面
114．．．第二表面
116．．．晶片座
118．．．引腳
120．．．晶片
130．．．導線
140．．．圖案化介電層
142．．．開口
150．．．封裝膠體
160．．．黏著層
170．．．表面處理層
E2．．．第二接點
T．．．總厚度

Claims (40)

  1. 一種晶片封裝體，包括：一圖案化金屬箔層，具有相對的一第一表面與一第二表面；一第一圖案化介電層，配置於該圖案化金屬箔層的該第二表面上，其中該第一圖案化介電層具有多個第一開口以暴露出至少部分該圖案化金屬箔層，並形成下方對外電性連接的複數個第二接點；一第二圖案化介電層，配置於該圖案化金屬箔層上方，其中該第二圖案化介電層係至少暴露出部分該圖案化金屬箔層，以形成上方對外電性連接的複數個第一接點，且該圖案化金屬箔層、該第一圖案化介電層與該第二圖案化介電層的總厚度範圍約在40微米~130微米之間；一晶片，配置於該圖案化金屬箔層的該第一表面上；一黏著層，配置於該晶片與該圖案化金屬箔層之間；多條導線，分別連接該晶片與該圖案化金屬箔層，其中部分該第一圖案化介電層位於該些導線與該圖案化金屬箔層相接之處的下方；以及一封裝膠體，配置於該第一表面上，並覆蓋該晶片與該些導線。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該第二圖案化介電層之材料係為防銲綠漆、液晶聚合物或聚丙烯。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該圖案化金屬箔層包括：多個引腳，該些引腳至少其中之一延伸至該晶片下方，且該些導線至少其中之一連接該晶片與該引腳，該些第一開口至少其中之一位於該晶片下方，以暴露出該引腳之延伸至該晶片下方的部分。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該圖案化金屬箔層包括：多個引腳，該些引腳至少其中之一向遠離該晶片的方向延伸，該些導線至少其中之一連接該晶片與該些引腳其中之一，且該些第一開口至少其中之一位於該晶片外圍並暴露出該引腳。
  5. 如申請專利範圍第1項所述之晶片封裝體，其中部分該些第一開口位於該圖案化金屬箔層的外緣，且該些第一開口為多個開孔。
  6. 如申請專利範圍第1項所述之晶片封裝體，其中該第一圖案化介電層之材料係為防銲綠漆、液晶聚合物或聚丙烯。
  7. 如申請專利範圍第1項所述之晶片封裝體，其中該些導線的材質包括金、銅或鋁。
  8. 如申請專利範圍第1項所述之晶片封裝體，更包括：多個焊球，分別配置於該些第一開口中並與該圖案化金屬箔層連接。
  9. 如申請專利範圍第8項所述之晶片封裝體，其中該些銲球包括至少一無訊號之銲球(dummy ball)。
  10. 如申請專利範圍第1項所述之晶片封裝體，其中該圖案化金屬箔層具有至少一無訊號之接墊(dummy pad)。
  11. 如申請專利範圍第1項所述之晶片封裝體，其中該圖案化金屬箔層具有至少一無訊號之金屬導線(dummy trace)。
  12. 一種晶片封裝體，包括：一圖案化金屬箔層，具有相對的一第一表面與一第二表面，該圖案化金屬箔層包括：一晶片座；多個引腳，配置於該晶片座的周邊；一第一圖案化介電層，配置於該圖案化金屬箔層的該第二表面上，其中該第一圖案化介電層具有多個第一開口以暴露出至少部分該圖案化金屬箔層，並形成下方對外電性連接的複數個第二接點，且部分該些第一開口位於該晶片座之正下方並暴露出該晶片座，該圖案化金屬箔層與該第一圖案化介電層的總厚度範圍約在40微米~130微米之間；一晶片，配置於該圖案化金屬箔層的該第一表面上，並位於該晶片座上；一黏著層，配置於該晶片與該圖案化金屬箔層之間；多條導線，分別連接該晶片與該圖案化金屬箔層，且 至少部分該些導線與該些引腳相連接；以及一封裝膠體，配置於該第一表面上，並覆蓋該晶片與該些導線。
  13. 如申請專利範圍第12項所述之晶片封裝體，其中該晶片座為一連續之導電層。
  14. 如申請專利範圍第12項所述之晶片封裝體，更包括：一表面處理層，至少覆蓋該些晶片座與該些第二接點之表面及側壁。
  15. 如申請專利範圍第14項所述之晶片封裝體，該表面處理層之材料係包括鎳/金、化鎳鈀金、銀、錫及其合金、錫膏或有機化合物。
  16. 如申請專利範圍第12項所述之晶片封裝體，更包括：一第二圖案化介電層，配置於該圖案化金屬箔層上方，其中該第二圖案化介電層係至少暴露出部分該圖案化金屬箔層，以形成上方對外電性連接的複數個第一接點。
  17. 如申請專利範圍第16項所述之基板，其中該第二圖案化介電層之材料係為防銲綠漆、液晶聚合物或聚丙烯。
  18. 如申請專利範圍第16項所述之晶片封裝體，其中該圖案化金屬箔層、該第一圖案化介電層與該第二圖案化介電層的總厚度範圍約在40微米~130微米之 間。
  19. 如申請專利範圍第16項所述之晶片封裝體，其中該晶片座被部分該第二圖案化介電層覆蓋。
  20. 如申請專利範圍第12項所述之晶片封裝體，其中該晶片座為一連續之導電層。
  21. 如申請專利範圍第12項所述之晶片封裝體，其中部分該些第一開口位於該圖案化金屬箔層的外緣，且該些第一開口為多個開孔。
  22. 如申請專利範圍第12項所述之晶片封裝體，其中該第一圖案化介電層之材料係為防銲綠漆、液晶聚合物或聚丙烯。
  23. 如申請專利範圍第12項所述之晶片封裝體，其中該些導線的材質包括金、銅或鋁。
  24. 如申請專利範圍第12項所述之晶片封裝體，更包括：多個焊球，分別配置於該些第一開口中並與該圖案化金屬箔層連接。
  25. 如申請專利範圍第24項所述之晶片封裝體，其中該些銲球包括至少一無訊號之銲球(dummy ball)。
  26. 如申請專利範圍第12項所述之晶片封裝體，其中該圖案化金屬箔層具有至少一無訊號之接墊(dummy pad)。
  27. 如申請專利範圍第12項所述之晶片封裝體，其中該圖案化金屬箔層具有至少一無訊號之金屬導線 (dummy trace)。
  28. 一種晶片封裝體，包括：一圖案化金屬箔層，具有相對的一第一表面與一第二表面；一圖案化介電層，配置於該圖案化金屬箔層的該第二表面上，其中該圖案化介電層具有多個開口以暴露出至少部分該圖案化金屬箔層，並形成下方對外電性連接的複數個接點，該圖案化金屬箔層與該圖案化介電層的總厚度範圍約在40微米~130微米之間。；一晶片，配置於該第一表面上；多個導電凸塊，配置於該晶片與該圖案化金屬箔層之間；以及一封裝膠體，配置於該第一表面上，並覆蓋該晶片與該些導電凸塊。
  29. 如申請專利範圍第28項所述之晶片封裝體，其中該圖案化金屬箔層包括：多個引腳，各該引腳具有一承載晶片的承載端以及一朝向遠離晶片的方向延伸的外延端，且該些開口分別暴露出該些引腳的外延端並位於該晶片的周邊。
  30. 如申請專利範圍第28項所述之晶片封裝體，其中部分該些開口位於該晶片下方。
  31. 如申請專利範圍第28項所述之晶片封裝體，更包括：多個焊球，分別配置於該些開口中並與該圖案化金屬 箔層連接。
  32. 如申請專利範圍第28項所述之晶片封裝體，更包括：一底膠，配置於該晶片與該圖案化金屬箔層之間並包覆該些導電凸塊。
  33. 如申請專利範圍第28項所述之晶片封裝體，更包括：一表面處理層，至少覆蓋該些接點。
  34. 如申請專利範圍第33項所述之晶片封裝體，該表面處理層之材料係包括鎳/金、化鎳鈀金、銀、錫及其合金、錫膏或有機化合物。
  35. 如申請專利範圍第28項所述之晶片封裝體，其中該些導電凸塊包括銅柱(copper pillar)、銅凸塊(copper stud bump)或金凸塊(golden stud bump)。
  36. 如申請專利範圍第28項所述之晶片封裝體，更包括：一第二圖案化介電層，配置於該圖案化金屬箔層上方，其中該第二圖案化介電層係至少暴露出部分該圖案化金屬箔層，以形成上方對外電性連接的複數個第一接點。
  37. 如申請專利範圍第36項所述之晶片封裝體，其中該第二圖案化介電層之材料係為防銲綠漆、液晶聚合物或聚丙烯。
  38. 如申請專利範圍第36項所述之晶片封裝體， 其中該圖案化金屬箔層、該圖案化介電層與該第二圖案化介電層的總厚度範圍約在40微米~130微米之間。
  39. 如申請專利範圍第28項所述之晶片封裝體，其中該圖案化金屬箔層具有至少一無訊號之接墊(dummy pad)。
  40. 如申請專利範圍第28項所述之晶片封裝體，其中該圖案化金屬箔層具有至少一無訊號之金屬導線(dummy trace)。
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