TWI242857B - Alternative flip chip in leaded molded package design and method for manufacture - Google Patents

Alternative flip chip in leaded molded package design and method for manufacture Download PDF

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TWI242857B
TWI242857B TW093103044A TW93103044A TWI242857B TW I242857 B TWI242857 B TW I242857B TW 093103044 A TW093103044 A TW 093103044A TW 93103044 A TW93103044 A TW 93103044A TW I242857 B TWI242857 B TW I242857B
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Taiwan
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die
lead frame
frame structure
window
molding material
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TW093103044A
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English (en)
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TW200425438A (en
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Romel N Manatad
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Fairchild Semiconductor
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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    • H01L23/495—Lead-frames or other flat leads
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

1242857 玖、發明說明： 【發明所屬之技術領城】 相關申請案的交叉參考 此專利申請案係為2003年2月11曰提交的美國專利申 5請案60/446,918號的非臨時專利申請案，該案以引用方式整 體併入本文中。 本發明係有關於交替倒裝晶片引線模塑封裝體設計及 其製造方法。 【先前技術 10 發明背景 一種位於引線模塑封裝體中的倒裝晶片（FLMP)描述 於美國專利申請案09/464,717號。在一習知的FLMP封裝體 中，一矽晶粒的背側經由一模塑材料中的一窗而露出。晶 粒的背側大致與一諸如PC板等電路基材直接呈熱性及電性 15 接觸。 當製造FLMP封裝體時，在晶粒附接至一引線框結構之 後進打-板塑程序。為了使晶粒背側與模滲料或模溢料保 持分開，設計封裝體不使間隙出現在模腔穴與石夕晶粒背側 之間。製造期間，晶粒在模工具夾固期間與一模工具產生 2〇接觸。因為晶粒很脆且因為封裝體很薄，需要考慮到曰粒 破裂及晶粒與引線框之間產生斷路之可能性。 本發明的實施例可解決上述及其他問題。 L 明内容3 發明概要 1242857 本發明的實施例有關半導體封裝體及用於製造半導體 封裝體之方法。 本發明的一實施例係有關一種用於製造一半導體封裝 體之方法，包含：（a)將一模塑材料模塑在一具有一晶粒附 5 接區及複數個引線之引線框結構周圍，其中晶粒附接區經 由板塑材料中的一 _而路出，（b)在(a)之後’利用一倒裂晶 片安裝程序將一半導體晶粒安裝至晶粒附接區。 本發明的另一實施例有關一半導體封裝體，包含：（a) 一引線框結構，其包含一晶粒附接區及複數個引線；（b)_ 10 模塑材料’其模塑在引線框結構的至少一部分周圍，且其 中模塑材料包含一窗；及(c)一半導體晶粒，其安裝在晶粒 附接區上。 本發明的另一實施例有關一電性總成，包含：一半導 體封裝體，包含(a)—引線框結構，其包含一晶粒附接區及 15複數個引線；（b)一模塑材料，其模塑在引線框結構的至少 一部分周圍且其中模塑材料包含—窗，及(c)一半導體晶 粒，其包含一食I在晶粒附接區上之邊緣，其中半導體晶 粒位於窗内，且其中一間隙出現在邊緣與模塑材料之間了 及一電路基材’其巾半導體封㈣安裝至電路基材。 20 T文進一步詳細地描述本發明的這些及其他實施例。 圖式簡單說明 第1 (a)圖顯不根據本發明一實施例之一半導體封裝體 的俯視立體圖； 第1(b)圖顯示第1(a)圖的封裝體之仰視立體圖； 1242857 第糊_示安裝在—電路基材上之第1(a)及1(b)圖中 的半導體封裝體之側剖視圖； 第1⑻圖顯示只有-晶极之—封裝體組態； f圖顯Μ有兩晶粒之—封裝體組態； 第3(a)圖,、、、負轉據本發明另—實施例之封裝體的俯視 立體圖； 料b)_示第3(a)圖的封裝體之仰視立體圖； 第（）圖.、、、員不具有-頭板結構之第3⑻圖的封裝體之 俯視立體圖； 1〇 糊圖顯示第3⑷及冲)圖的封裝體之側剖視圖； …第4⑷至4(f)圖顯示一封裳體在形成時的各種不同圖 不， 弟5圖_根據本發明的一實施例之一封農體的分解 圖。 15彡些及其他實_進-步詳細地描述於“詳細描述” 【實施令式】 較佳實施例之詳細說明 本發明的實施财，LMP封裝體之—”設計及製 造方法。本發明的實施射，域消除了铸體晶粒在模 塑程序期間所經歷的機械應力。如上述，封裝體製造期間 之機械應力會導致晶粒裂痕或銲料裂痕。本發明的實施例 亦消除了胁的暴露背側上產生模滲料或污毕之可 能性。顧本發日㈣實_可能生成㈣的封裝體（譬如小 1242857 於約0.5公厘高度），其中在標準FLMP製造方法中難以達成 此作用。部分實施例中，藉由封裝體頂表面上的一開口亦 可選擇性使用一諸如熱板結構等額外散熱器來提供更好的 散熱。 5 半導體封裝體可使用一預鍍及/或預成形銅基引線框 結構、一用於產生一預模塑引線框結構之預模塑技術、一 銲料凸塊或非銲料凸塊式半導體晶粒、及一中間銲膏。下 文說明使用各特性之細節及利益。 首先，銅是一種優良的電及熱導體，所以本發明實施 10 例中偏好採用銅引線框結構。部分實施例中，引線框結構 可預鍍有諸如NiPdAu等金屬。因為完成的封裝體在形成之 後不需暴露於諸如鍍覆化學物等化學物，預鍍及引線框結 構降低了封裝體對於化學物的暴露。藉由一引線框結構的 預鍍，亦可讓引線框結構承受高的迴銲溫度而不融化。藉 15 由將引線框結構預成形，亦消除了封裝體由於引線成形程 序所吸收的機械應力。 第二，本發明實施例中，可利用一種預模塑技術來形 成一預模塑的引線框結構。預模塑的引線框結構是本發明 實施例的一種理想特性。預模塑的引線框結構中，引線框 20 結構及模塑材料可鎖定在一起。預模塑的引線框結構可提 供一用於晶粒附接之暴露的引線框表面而不用任何的膜或 卷帶。可能依據汲、閘及源部連接至電路基材（譬如PC板) 之封裝體組態來維持晶粒背側相對於引線框結構的暴露引 線之平面性。預模塑的引線框結構包括用於接收一晶粒之 1242857 第-窗，及-用於接收一諸如熱板結構等散熱器（以供進— 步散熱)之選擇性第二窗。 第二，晶粒中一陣列的凸塊可作為一電晶體晶粒之源 及閘電終端。其亦作為晶粒與引線框結構之間的機械性及 5熱性應力吸收器。習知的几嫌封裝體中，&塊為高狀以提 t、可使才果塑材料流動於石夕晶粒與引線框結構之間的足夠 空=。對於標準FLMP封裝體而言軟銲料凸塊亦很理想，以 I里P牛低在;^塑私序期間藉由晶粒吸收之壓縮應力。相較 來兒本I明的貫施例中，因為在晶粒附接至引線框結構 10之月J進仃拉塑，可使用任何的凸塊材料及較短的高度。凸 塊的材料及高㈣與模塑程序考量因素獨立無關。 本發明的實施例中，封裝體可使用最低達010公厘厚 1的夕曰曰粒。並且’使用銲膏將一晶粒上的凸塊(特別是非 &料凸塊）_合至引線框結構以提供—電性及機械性連 接 鬼及鲜T可為Pb基或為無？13銲料材料，在部分實 -、有超過26G C的融化溫度。凸塊可包含—種諸如銅 及金專非銲料材料。 、、"本，明的實施例亦提供符合所需要的f腳位排列組態 、、’"單封U巾容許多個晶粒之引線框結構變異例。 …p的^例亦在模塑材料中設置-頂窗口以提供-散 熱Μ項二部分實施例中，亦可能使用-較薄的引線框結 構車又相模塑材料、一較薄的晶粒及較短凸塊，藉以 產生具有0.5〇公厘或更小厚度的封裝體。 第Ha)圖顯示根據本發明❸一實施例之一封裝體1〇〇。 1242857 封裝體100包括-模塑材料22且其在封裝體1〇〇頂上具有兩 個孔20。可設置孔20用以提供從封裝體1〇〇中的晶粒之更好 散熱作用。可使用譬如環氧樹脂模塑材料等任何適當的模 塑材料22。封裝體100亦包括數個引線24，包括一問引線 5 24(g)及複數個源引線24⑻。圖示的封裝體1〇〇具有七個源 引線及一個閘引線。其他封裝體實施例可具有更多或更少 個引線。 封裝體100中的引線24可能身為一引線框結構的一部 分。此處所用的“引線框結構，，係指一種自引線框衍生之結 10構。一典型的引線框結構包括一源引線結構及一閘引線結 構。源引線結構及閘引線結構的各者可具有一或多個引線。 第1(b)圖顯示封裝體1〇〇的仰側視圖。封裝體1〇〇可包括 半^體aa粒30。半導體晶粒3〇的一背側3〇(a)可顯示一穿 過模塑材料22中之窗。對應於晶粒3〇中的一電晶體汲區之 15晶粒30的背側30(a)係可受到金屬化且可位於引線框結構的 一晶粒之遠端。晶粒3〇的相對前側可能對應於或包括一源 區及一閘區且可能緊鄰引線框結構的晶粒附接區。晶粒背 側30(a)提供一電終端，且可能與模塑材料22底表面呈共面 狀並與引線24端點呈共面狀。模塑材料22中的窗稍微大於 20 晶粒的外邊緣(及平面性尺寸）。 一小間隙11出現在模塑材料22與晶粒30外邊緣之間。 此小間隙11亦可讓晶粒3 〇對於模塑材料2 2獨立地熱性膨脹 及收縮。如圖所示，間隙U可能延伸於晶粒3〇整體周邊。 模塑材料並未出現在用於耦合引線框結構與晶粒3 〇之銲接 1242857 部之間。 第⑹圖顯不一電性總成103之侧剖視圖。第1(a)及1(b) 回斤丁的封衣體1〇〇安裝在第叫圖的一電路基材％上。可 使用諸如63 Sn/3 7Pb等銲料(未圖示）將晶粒3〇背側及引線24 5端點電性輕合至電路基材55中的一或多個傳導區。如圖所 不，一小間隙11出現在模塑材料22與晶粒3〇外邊緣之間。 第1(d)圖顯示引線框結構38。凸塊34亦顯示將晶粒 附接至引線框結構36。開孔38可出現在引線框結構％中以 讓一模塑材料22流過及鎖定至引線框結構％。 1〇 根據本發明較佳實施例之半導體封裝體所使用的半導 體晶粒包括垂直功率電晶體。垂直功率電晶體包括vdm〇s 電晶體。VDMOS電晶體係為一具有擴散而成的兩或更多個 半導體區之MOSFET。其具有一源區、一汲區及一閘。此 几件為垂直的原因在於源區及汲區位於半導體晶粒的相對 15表面上。閘可能為一溝道狀閘結構或一平面性閘結構，且 形成於與源區相同的表面上。因為溝道狀閘結構比平面性 閘結構更窄且佔用更少空間，故偏好採用溝道狀閘結構。 操作期間，一VDMOS元件中從源區至汲區之電流流動係大 致垂直於晶粒表面。 20 第2圖顯示一在單一模塑材料中具有兩個半導體晶粒 30(a)、30(b)及兩個對應的引線框結構36(a)、36(b)之封裝體 101。各引線框結構36(a)、36(b)包括一閘引線及複數個源 引線。開孔38位於引線框結構36(a)、36(b)的晶粒附接區 中。其他實施例中，可在每個封裝體中具有甚至更多個引 11 1242857 線框結構及甚至更多晶粒。 第3(a)圖顯示本發明另一實施例之俯視圖。封裝體ι〇〇 包括用於暴露一引線框結構24的頂表面24(x)之一模塑材料 22中的一頂窗58。頂表面24(x)可能是與晶粒所附接的表面 5呈現相對之表面。 第3(b)圖顯示第3(a)圖所示的封裝體1〇〇之仰視圖。封 裝體100包括身為模塑材料22中另—窗之—晶粒3G。如圖所 示’晶粒背側30(a)經由模塑材料22露出。因此，封裝體1〇〇 可具有位於封裝體100相對側上之第一及第二窗。 10 第3(C)圖顯示一用於耦合至引線框結構24的頂表面 24(x)之金屬板結構52。如圖所示，金屬板結構％具有一呈 平面狀且耗合至引線框結構的頂表面24(χ)之第一部，並呈 有一沿封裝體100側往下延伸之腳。金屬板結構52的腳可提 供封裝體1G0對於—τ方電路基材（未圖示）之額外電性及/ 15 或熱性連接。 第3(d)圖顯示不具有金屬板結構之職體⑽的側剖視 Θ 士圊所示，一間隙15出現在晶粒30的外邊緣與模塑材 料22之間。如圖所示，模塑材料22的底表面與晶⑽⑷及 引線24(s)端點呈共面狀。並且，如第3⑷圖所示，在用於 20耦合引線框結構及晶粒3〇的接合部之間不具有模塑材料。 可以任何適當的方式製造上述實施例。譬如，第一程 序流程選項可能包括下列程序：1·預模塑/去間口 /去溢料程 序，2· —水噴注去溢料程序，3·銲料配送/倒裝晶片附接程 序，及4·-礙鮮程序。迴輝程序之後可能為:九引線切割/測 12 Π42857 試/標記程序，及Β·切分/上卷帶及捲軸程序。迴銲程序之後 或者可能為切分/測試/標記/上卷帶及捲轴程序。另一範例 中，第二程序流程選項如下：1·預模塑/去閘口 /去溢料/引線 切割程序，2.銲料配送/倒裝晶片附接程序，及3·一迴銲程 5序。迴銲程序之後可進一步為A·—測試/標記程序，及B.切 分/上卷帶/及捲軸程序。IR迴銲程序之後或者可為切分/測 試/標記/上卷帶及捲軸程序。這些個別程序為熟習該技術者 所瞭解。 芩照第4(a)至4(e)圖，第一步驟係將模塑材料22模塑至 1〇引線框結構24上。參照第4(a)圖，將引線框結構24裝載至一 模工具60内，模工具60具有一經過設計可符合預定封裝厚 度、形式及引線框暴露之腔穴。可讓一模塑材料液體化並 進入模腔穴内並在模工具60的模塑晶粒之間產生固體化。 模塑之後，所形成的模塑條(如果此引線框為一條引線框中 15之許多引線框的-者）經過-去閘口/去溢料程序以移除引 線或引線框結構上的過多模料。如果模塑條需要進一步清 理，模塑的條可經歷一水喷注去溢料程序。如果不需要2 -步清理一程序選項係完全地㈣】所有的經延伸引線， 而召下連接至引線框結構的晶粒附接墊側之繫桿。可在半 20導體晶粒附接至引線框結構之前完成此作用。 -模塑引線框結構99顯示於第4(b)圖且包括一模塑材 料22及-引線框結構。如圖所示，—用於接收一晶粒之較 大的窗98係位於模塑材料22中。窗％暴露出引線框結構μ 的晶粒附接區97。 13 1242857 苓照第4(c)圖，可進行一銲料配送程序及一倒裝晶片附 接程序。譬如含有95Pb/5Sn的凸塊34(a)可以第—陣列沉積 在晶粒30上。譬如含有88Pb/10Sn/2Ag的銲料材料34(b)可以 第一陣列沉積在引線框結構2 4的晶粒附接區的暴露表面 5上。凸塊材料34(a)可具有比銲膏材料34(b)更高的融化溫度 (用於將完成的封裝體附接至一電路基材之銲料可具有比 凸塊或銲膏材料更低的融化溫度）。如第4(c)圖所示，凸塊 式晶粒30翻轉倒裝，而凸塊及銲膏材料34(a)、34(b)陣列對 準且接合以形成用於接合引線框結構24及晶粒30之一陣列 10的接合部。如圖所示，半導體晶粒30配合在模塑材料22中 的窗内，且一小間隙位於晶粒3〇與模塑材料22中的窗邊緣 之間。因為已經進行模塑程序，晶粒3〇背側不具有任何殘 留的模塑材料。 如第4(d)圖所示，晶粒附接至引線框結構之後，組合物 15 前進至一迴銲烤爐以融化銲膏且將凸塊式矽晶粒内聚性附 接至預模塑的引線框。熟習該技術者可以選擇適當的迴銲 溫度。 參照第4(e)及4(f)圖，可完成電性測試及進一步處理。 第一途徑係在進行切分然後上卷帶及捲軸程序之前進行剝 20 離測試及標記。如果引線仍未切割，可在剝離測試之前完 成引線切割。第二途徑先進行引線切割及切分程序，然後 在進行一上卷帶及捲軸程序之前進行單元測試及標記。第 4(f)圖顯示位於一卷帶及捲軸程序中之一封裝體。 第5圖顯示一封裝體的分解圖。如圖所示，封裝體包括 14 1242857 一耦合至一引線框結構24之模塑材料22，一具有一陣列凸 塊34(a)的半導體晶粒30以一銲膏材料34(b)耦合至引線框 結構24。 請注意，本發明不限於上述較佳實施例，熟習該技術 5 者顯然可在本發明的精神及範圍内作出變化及修改。並 且，本發明的任一或多項實施例可與本發明的一或多項實 施例合併而不脫離本發明之精神與範圍。 所有上述美國臨時及非臨時專利申請案及公開案皆以 引用方式整體併入本文中。 10 【圖式簡單說明】 第1(a)圖顯示根據本發明一實施例之一半導體封裝體 的俯視立體圖； 第1(b)圖顯示第1(a)圖的封裝體之仰視立體圖； 第1(c)圖顯示安裝在一電路基材上之第1(a)及1(b)圖中 15 的半導體封裝體之側剖視圖； 第1(d)圖顯示只有一晶粒之一封裝體組態； 第2圖顯示具有兩晶粒之一封裝體組態； 第3(a)圖顯示根據本發明另一實施例之封裝體的俯視 立體圖； 20 第3(b)圖顯示第3(a)圖的封裝體之仰視立體圖； 第3(c)圖顯示具有一頭板結構之第3(a)圖的封裝體之 俯視立體圖； 第3(d)圖顯示第3(a)及3(b)圖的封裝體之側剖視圖； 第4(a)至4(f)圖顯示一封裝體在形成時的各種不同圖 15 1242857 不， 第5圖顯示根據本發明的一實施例之一封裝體的分解 圖。 【圖式之主要元件代表符號表】 11…小間隙 34(b)…銲膏材料 15…間隙 36,36⑻，36(b)…引線框結構 20···孔 38···開孔 22…模塑材料 52…金屬板結構 24…引線 55···電路基材 24(g)···閘引線 58…頂窗 24(s)…源引線 60…模工具 24(x)…頂表面 98…較大的窗 30,30(b)…半導體晶粒 99···模塑引線框結構 30⑻…背側 100,101…封裝體 34⑻…凸塊材料 103…電性總成 16

Claims (1)

1242857 拾、申請專利範圍： 1. -種用於製造-半導體封裝體之方法，包含： ⑷將-模塑材料模塑在—具有—晶粒附接區及複 數個引線之引線框結構周圍’其中該晶粒附接區經由該 模塑材料中的一窗而露出；及 (b)在(a)之後，使用_倒裝晶片安裝程序將一半導 體晶粒安裝至該晶粒附接區。 2·如申請專利範圍第1 Jg 員之方法，其中該半導體晶粒包含 一垂直功率MOSFET。 10 15 20 3·如申請專利範圍第iJg 貢之方法’其中該等複數個引線包 括至少-源引線及至少_閘引線。 4.如申請專利範圍第1之方法，進一步包含，在⑼之後： 使位於。亥引線框的晶粒附接區與該半導體晶粒之 間的銲料進行迴鋒。 5·如申請專利範圍第1項之方法，其中該晶粒附接區包含 至少一開孔。 6.如申請專利顧第1項之方法，其中該《包含將該引 線框結構放置在一模塑工具中。 7·如申請專利範圍第1項之方法，進—步包含將銲料沉積 在該引線框結構的晶粒附接區上及該窗内。 申°月專利耗圍第1項之方法，其中該等複數個引線包 含—源引線及一閘引線。 9·如申請專利範圍第1項之方法，進-步包含： 將-熱板結構轉至該引線框結構。 17 1242857 ίο. —種半導體封裝體，包含： (a) —引線框結構，其包含一晶粒附接區及複數個引 線； (b) —模塑材料，其模塑在該引線框結構的至少一部 5 分周圍，且其中該模塑材料包含一窗；及 (c) 一半導體晶粒’其包含一安裝在該晶粒附接區上 的邊緣，其中該半導體晶粒位於該窗内，及 其中一間隙出現在該半導體晶粒的邊緣與該模塑 材料之間。 10 11.如申請專利範圍第10項之半導體封裝體，其中該引線框 結構包含銅。 12. 如申請專利範圍第10項之半導體封裝體，其中該半導體 晶粒含有一包括一源區、一閘區及一汲區之垂直功率電 晶體，其中該源區及該閘區緊鄰該晶粒附接區且該汲區 15 位於該晶粒附接區的遠處。 13. 如申請專利範圍第10項之半導體封裝體，其中該半導體 封裝體包含凸塊及位於該半導體晶粒與該引線框結構 之間的銲接部。 14. 如申請專利範圍第10項之半導體封裝體，其中該窗具有 20 比該半導體晶粒側向尺寸更大之尺寸。 15. 如申請專利範圍第10項之半導體封裝體，其中該模塑材 料包含一環氧樹脂模塑材料。 16. 如申請專利範圍第10項之半導體封裝體，其中該窗為一 第一窗且其中該模塑材料包含一第二窗，該第二窗暴露 18 1242857 出與該晶粒附接區相對之該引線框結構的一表面。 17. 如申請專利範圍第16項之半導體封裝體，進一步包含一 經由該第二窗耦合至該引線框結構之散熱器。 18. 如申請專利範圍第10項之半導體封裝體，進一步包含用 5 於耦合該半導體晶粒及該引線框結構之一陣列的接合 部，其中該陣列的接合部包含具有不同融化溫度之一銲 料或非銲料凸塊材料及一銲膏材料。 19. 一種電性總成，包含： 一半導體封裝體，包含(a)—引線框結構，其包含一 10 晶粒附接區及複數個引線，（b)—模塑材料，其模塑在該 引線框結構的至少一部分周圍且其中該模塑材料包含 一窗，及(c)一半導體晶粒，其包含一安裝在該晶粒附接 區上的邊緣，其中該半導體晶粒位於該窗内，且其中一 間隙出現在該邊緣與該模塑材料之間；及 15 一電路基材，其中該半導體封裝體安裝至該電路基 材。 20. 如申請專利範圍第19項之電性總成，進一步包含用於耦 合該半導體晶粒之銲料。 19
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JP4699353B2 (ja) 2011-06-08
WO2004073031A2 (en) 2004-08-26
TW200425438A (en) 2004-11-16
US20040157372A1 (en) 2004-08-12
JP2006517744A (ja) 2006-07-27
KR101050721B1 (ko) 2011-07-20
CN1748307A (zh) 2006-03-15
DE112004000258T5 (de) 2006-02-02
CN100576523C (zh) 2009-12-30
US7586178B2 (en) 2009-09-08

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