CN1748307A - 有引线模制组件设计中的选择性倒装芯片及制造方法 - Google Patents

有引线模制组件设计中的选择性倒装芯片及制造方法 Download PDF

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CN1748307A
CN1748307A CNA2004800037212A CN200480003721A CN1748307A CN 1748307 A CN1748307 A CN 1748307A CN A2004800037212 A CNA2004800037212 A CN A2004800037212A CN 200480003721 A CN200480003721 A CN 200480003721A CN 1748307 A CN1748307 A CN 1748307A
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R·N·马纳塔德
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Fairchild Semiconductor Corp
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Abstract

本发明揭示了一半导体组件。该组件包括引线架构件，其包括一小片连接区域以及多根引线。模制材料压制在引线架构件的至少一部分周围，并包含一窗口。包含边缘的半导体小片安装在小片连接区域上，并在窗口内。该半导体小片边缘和模制材料之间存在缝隙。

Description

有引线模制组件设计中的选择性倒装芯片及制造方法
对相关申请的交叉引用
本发明申请是2003年2月11日提出申请的美国专利申请60/446,918号的非临时专利申请，通过引用全部内容包括在此。
背景技术
美国专利申请09/464,717号中描述了倒装芯片引线模块组件(FLMP)。在传统FLMP组件中，硅片的背面通过模制材料上的一窗口露出。该小片的背面和电路基底，例如PC板我基本直接的热和电气接触。
当制造FLMP组件时，在小片附着到引线架构件上之后，进行模制流程。为使小片的背面在漏压制或溢料中保持清洁，把组件设计在模腔和硅芯的背面之间不存在空隙。在制造过程中，通过模制工具采用模制工具定位后，来小片由模制工具接触。因为小片易碎且组件较薄，所以要考虑小片破裂以及小片和引线架断接的可能性。
本发明的实施例解决这些及其它问题。
发明内容
本发明的实施例涉及半导体组件和制造半导体组件的方法。
本发明的一个实施例涉及一种制造半导体组件的方法，其包括：(a)把模制材料压制在引线架构件周围，该引线架构件含有小片连接区域以及多根引线，其中小片连接区域通过模制材料上的窗口露出；和(b)在(a)之后，利用倒装芯片压制流程将半导体小片安装在小片连接区域。
本发明的另一实施例涉及一种半导体组件，其包括：(a)一种含有小片连接区域和多根引线的引线架构件；(b)压制在引线架构件的至少一部分周围的模制材料，其中模制材料包括一窗口；以及(c)安装在小片连接区域上的半导体小片。
本发明的另一实施例涉及一种电子组合件，其包括：半导体组件，其包括(a)引线架构件，其包含小片连接区域和多根引线的，b)压制在引线架构件的至少一部分周围的模制材料，其中模制材料包括一窗口，以及(c)压制在小片连接区域上的包含边缘的半导体小片，其中该半导体小片在窗口内，且其中边缘和模制材料之间存在缝隙；和电路基底，其中半导体组件安装在电路基底上。
本发明的这些及其它实施例将在下面进一步具体描述。
(4)附图说明
图1(a)示出对应本发明的一实施例的半导体组件的上视图。
图1(b)示出图1(a)中的组件的下视图。
图1(c)示出图1(a)和1(b)中的半导体组件安装在电路基底上的侧面截面图。
图1(d)示出只有1小片的组件构造。
图2示出有2小片的组件构造。
图3(a)示出对应本发明的另一实施例的组件的上视图。
图3(b)示出图3(a)中的组件的下视图。
图3(c)示出图3(a)中的组件的带散热片构件的上视图。
图3(d)示出图3a)和3(b)中的组件的侧面截面图。
图4(a)-(f)示出组件形成时的多个示意图。
图5示出对应本发明的一实施例的组件的分解图。
这些及其它实施例将在以下具体实施方式中进一步详细描述。
具体实施方式
本发明的实施例涉及FLMP组件的制造的可选择设计及方法。在发明的实施例中，在压制期间由半导体小片所经受的机械压力几乎消除了。如上所述，在制造组件期间的机械压力可能导致小片破裂或焊接破裂。本发明的实施例也消除了在小片的暴露背面上的漏压制或压制树脂污染的可能性。利用本发明的实施例，可能产生更薄的组件(例如高度小于0.5mm)，这在标准FLMP制造方法中很难做到。在某些实施例中，在组件的上表面上的开口也提供了可供选择使用的额外热吸收器，例如散热片构件，以提供更好的散热。
半导体组件可采用预镀及/或预形成的铜基的引线架构件、一种产生预压制引线架构件的预压制技术、一种焊接突起或非焊接突起的半导体小片，以及中间的焊膏。以下解释了采用这些特征的细节和益处。
首先，因为铜是电和热的良导体，因此本发明的实施例倾向选择铜引线架构件。在某些实施例中，引线架构件可先用镍钯金等金属预镀。预镀引线架构件可减小组件在化学物中的暴露，因为完成的组件在形成后不需要暴露在化学物，比如电镀化学物中。预镀引线架构件也允许我们使引线架构件经受高的回流温度而不熔化。预形成引线架构件也消除了由于引线形成过程而将被组件吸收的机械压力。
第二，在本发明的实施例中，可采用预压制技术来形成预模制引线架构件。预模制引线架构件是本发明所需的特征。在该预模制引线架构件中，引线架构件和模制材料可以固定在一起。预模制的引线架构件可提供暴露的引线架表面，用于小片接触而不需要采用任何薄膜或带子。有可能保持小片背面对于引线架构件中暴露的引线的平面性，这取决于对电路基底(例如PC板)的漏极、栅极、和源极连接的组件配置。预压制引线架构件包括第一窗口，用于接收小片，以及可选择的第二窗口，用于接收热吸收器，例如散热片构件(用于进一步散热)。
第三，小片中突起阵列可用作晶体小片的源极和栅极的电气终端。其也用作在小片和引线架构件之间的机械和热压力的吸收器。在传统FLMP组件中，突起很高，从而为模制材料提供足够的空间以在硅小片和引线架构件之间流动。软的焊接突起对于标准FLMP组件来说是理想的，用以使压制期间被小片吸收的压缩应力最小化。相比较而言，在本发明的实施例中，可以采用任何突起材料和采用较低的突起，因为压制在小片附着到引线架构件之前进行。突起的材料和高度独立于压制流程需要考虑的问题。
在本发明的实施例中，组件可采用厚度小至0.10mm的硅小片。焊膏也用来将小片上的突起(特别是非焊接的突起)连接到引线架构件上，以提供电气和机械连接。在某些实施例中，该突起和焊膏可以是铅基的或无铅的焊接材料，其熔化温度超过260C。突起可包括诸如铜和金的非焊接材料。
本发明的实施例也提供引线架构件的变化，以满足所需的电气引脚引出的配置，并允许多个小片在单个组件中。本发明的实施例还提供开在模制材料上的顶窗，以提供热吸收选择。在某些实施例中，也可能采用更薄的引线架构件、更薄的模制材料、更薄的小片，以及更低的突起，从而可制造出厚度在0.50mm或更小的组件。
图1(a)示出根据本发明一实施例的组件100。组件100包括模制材料22，其在组件100上方有2个开口20。开口20被提供，使组件100中的小片更好地散热。可使用任何合适的模制材料22包括例如，环氧模制材料。组件100也包括许多引线24，其中包括栅极引线24(g)和多根源极引线24(s)。所示的组件100含有7根源极引线和1根栅极引线。其它组件实施例可含有更多或更少引线。
组件100中的引线24可以是引线架构件中的一部分。在此采用的短语“引线架构件”代表源自引线架的构件。典型的引线架构件包括源极引线结构和栅极引线结构。各个源极引线结构和栅极引线结构可有一根或多根引线。
图1(b)示出组件100的下側视图。组件100包括半导体小片30。半导体小片30的背面30(a)可通过模制材料22上的窗口露出。对应于小片30的晶体管漏极区的小片30的背面30(a)可进行金属喷涂，且远离引线架构件的小片连接区域。与之相对的小片30的正面可对应于或包括源极区和栅极区，且靠近引线架构件的小片连接区域。小片背面30(a)提供一电气端子，并可与模制材料22的底面以及引线24的末端共面。模制材料22上的窗口比小片30的外边缘(和平面尺寸)稍大。
在模制材料22和小片30外边缘之间存在一小缝隙11。该小缝隙11也允许小片30热胀缩，与模制材料22无关。如图所示，缝隙11可沿着小片30的整个***伸展。连接引线架构件和小片30的焊接点之间不存在模制材料。
图1(c)示出一电气组合件103的截面图。图1(a)和1(b)中示出的组件100安装在图1(c)中的电路基底55上。诸如63Sn/37Pb的焊料(未显示)被用来将小片30的背面和引线24的末端连接到电路基底55上的一个或多个导电区域。如其中所示的，小缝隙11存在于模制材料22和小片30的外边缘之间。
图1(d)示出引线架构件36。同样示出突起34将小片30附着到引线架构件36上。引线架构件36中存在孔隙38，让模制材料22流经通过，并固定引线架构件36。
根据本发明的较佳实施例的半导体组件中采用的半导体小片含有垂直的功率管。垂直的功率管包括VDMOS晶体管。VDMOS晶体管是具有2个或多个由扩散形成的半导体区域的MOSFET。它包括源极区，漏极区，以及栅极。该器件是垂直的，其源极区和漏极区在半导体小片的相对面上。栅极可以是沟道栅极结构或平面栅极结构，且形成在和源极同一表面。较佳的是沟道栅极结构，因为沟道栅极结构比平面栅极结构更窄，占用更少空间。在工作期间，在VDMOS中从源极区到漏极区的电流的流动几乎和小片表面垂直。
图2示出组件101，在单一模制材料中有2个小片30(a)、30(b)及其对应的引线架构件36(a)、36(b)。各个引线架构件36(a)、36(b)包括一栅极引线和多根源极引线。孔隙38在引线架构件36(a)、36(b)的小片连接区域中。在其它实施例中，每个组件可以有更多引线架构件和更多小片。
图3(a)示出本发明的另一实施例的上视图。组件100包括在模制材料22上的顶窗58，其露出引线架构件24的上表面24(x)。上表面24(x)可以是和小片附接的表面相对的表面。
图3(b)示出图3(a)中示出的组件100的下侧视图。组件100包括小片30，其在模制材料22的另一个窗口中。如图所示，小片的背面30(a)通过模制材料22露出。这样，组件100在组件100在相对面上，有第一和第二窗口。
图3(c)示出金属板构件52，其连接到引线架构件24的上表面24(x)上。如图所示，金属板构件52具有第一部分，其为平面，且连接到引线架构件的上表面24(x)上，还具有一引脚，其向下延伸到组件100的侧面。金属板构件52的该脚可为组件100提供到下面的电路基底(未显示)的额外电气及/或热连接。
图3(d)示出没有金属板构件的组件100的截面图。如图所示，在小片30的外边缘和模制材料22之间存在一缝隙15。如图所示，模制材料22的底面和小片背面30(a)以及引线24(s)的末端共面。同样，如图3(d)所示，在连接引线架构件和小片30的连接点之间没有模制材料。
以上描述的实施例可以用任何合适的方式来制造。例如，第一工艺流程选择可包括以下工艺：1.预压制/打浇口/去毛边工艺，2.喷水去毛边工艺，3.焊料分配/倒装芯片连接工艺，和4.回流工艺。回流工艺后跟的是：A.引线剪切/测试/标记工艺，和B.单一化(singulate)/卷带(tape and reel)工艺。回流工艺可选择后跟单一化/测试/标记/卷带工艺。在另一例子中，第二工艺流程选择如下：1.预压制/打浇口/去毛边/引线剪切工艺，2.焊接分配/倒装芯片接触工艺，和3.回流工艺。回流工艺可进一步后跟A.测试/标记工艺，和B.单一化/卷带工艺。IR回流工艺可选择后跟单一化/测试/标记/卷带工艺。这些单独的工艺对本领域普通人员来说是了解的。
参照图4(a)到4(e)，第一步是将模制材料22压制到引线架构件24上。参照图4(a)，引线架构件24通过一空腔来装入具有空腔的模制工具60内，该空腔被设计来满足所需的预定组件厚度、形式和引线架暴露程度。模制材料允许液化，进入压制空腔并在模制工具60中压制的小片之间凝固。模制之后，形成的模制条(若引线架是一条引线架的许多引线架中的一个)经过打浇口/去毛边工艺而除去在引线或引线架构件上多余的模制料。若该模制条需要进一步清理，模制条可经过喷水去毛边工艺。若不需要进一步清理，一种工艺选择是完全切除延长的引线，而留下连接到引线架构件的小片连接焊区的側面上的连接条。这一流程可先于半导体小片附着到引线架构件上而完成。
图4(b)示出压制的引线架构件99，其包括模制材料22以及引线架构件。如图所示，用于接收小片的相对较大的窗口98在模制材料22上。窗口98露出引线架构件24的小片连接区域97。
参照图4(c)，可执行焊接分配工艺和倒装芯片连接工艺。含有诸如95Pb/5Sn的突起34(a)以第一阵列沉积在小片30上。含有诸如88Pb/10Sn/2Ag的焊接材料34(b)以第二阵列沉积在引线架构件24的小片连接区域的暴露面上。突起材料34(a)可具有比焊膏材料34(b)更高的熔化温度。(用来将完成的组件附接到电路基底的焊料可有比突起和焊膏材料都低的熔化温度)如图4(c)所示，有突起的小片30被翻转，突起和焊膏材料阵列34(a)，34(b)被对齐并结合形成连接点阵列，把引线架构件24和小片30相连接。如图所示，半导体小片30安装在模制材料22上的窗口内，且一小缝隙在小片30和模制材料22上的窗口边缘之间。小片30的背面不含任何残留模制材料，因为已经进行了模制流程。
如图4(d)所示，在小片附接到引线架构件之后，该组合体进入回流炉以熔化焊膏并将有突起的硅芯粘着到预模制引线架上。本领域熟练人员可选择合适的回流温度。
参照图4(e)和4(f)，可完成电气测试和进一步处理。第一种方法是在执行单一化之前执行条测试和标记，接着是卷带流程。若引线仍未切除，引线切除可在条测试之前完成。第二种方法是先执行引线切除和单一化流程，接着在执行卷带流程之前做单元测试和标记。图4(f)示出卷带流程中的组件。
图5示出组件的分解图。如图所示，该组件包括连接到引线架构件24的模制材料22。有着突起阵列34(a)的半导体小片30用焊膏材料34(b)连接引线架构件24。
应当指出，本发明并不局限于以上描述的较佳实施例，且显而易见的是本领域熟练人员可在本发明的精神和范围内实施更改和修正。而且在不违背本发明的精神和范围条件下，本发明的任一或多个实施例可和本发明的一个或更多
实施例相结合。
就所有情形而言，以上提及的所有美国临时的或非临时的专利申请和公开物的全部内容通过引用包括在内。

Claims (20)

1.一种用于制造半导体组件的方法，其特征在于，所述方法包括：
(a)将模制材料压制在具有一小片连接区域和多根引线的引线架构件周围，其中小片连接区域通过模制材料上的一窗口露出；和
(b)在(a)之后，利用倒装芯片安装工艺将半导体小片安装在小片连接区域上。
2.如权利要求1所述的方法，其特征在于，所述半导体小片包含一垂直的功率MOSFET。
3.如权利要求1所述的方法，其特征在于，所述多根引线包括至少一根源极引线和至少一根栅极引线。
4.如权利要求1所述的方法，其特征在于，所述方法还包括，在(b)之后：
回流在引线架的小片连接区域和半导体小片之间的焊料。
5.如权利要求1所述的方法，其特征在于，所述小片连接区域包含至少一个孔隙。
6.如权利要求1所述的方法，其特征在于，压制包括将引线架构件放置在模制工具中。
7.如权利要求1所述的方法，其特征在于，所述方法还包括在引线架构件的小片连接区域上，以及窗口内沉积焊料。
8.如权利要求1所述的方法，其特征在于，所述多根引线包括源极引线和栅极引线。
9.如权利要求1所述的方法，其特征在于，所述方法还包括：
将散热片构件附着到引线架构件上。
10.一种半导体组件，其特征在于，所述半导体组件包括：
(a)引线架构件，其包含一小片连接区域和多根引线；
(b)模制材料，其压制在引线架构件的至少一部分周围，其中模制材料含有窗口；和
(c)半导体小片，其包括安装在小片连接区域中的边缘，其中半导体小片在窗口内，和
其中缝隙存在于半导体小片的边缘和模制材料之间。
11.如权利要求10所述的半导体组件，其特征在于，所述引线架构件包含铜。
12.如权利要求10所述的半导体组件，其特征在于，所述半导体小片包含垂直的功率管，其包括源极区、栅极区和漏极区，其中所述源极区和所述栅极区靠近小片连接区域，所述漏极区远离小片连接区域。
13.如权利要求10所述的半导体组件，其特征在于，半导体组件在半导体小片和引线架构件之间含有突起和焊接连接点。
14.如权利要求10所述的半导体组件，其特征在于，所述窗口有着比半导体小片的横向尺寸更大的尺寸。
15.如权利要求10所述的半导体组件，其特征在于，所述模制材料包括环氧模制材料。
16.如权利要求10所述的半导体组件，其特征在于，所述窗口是第一窗口，且所述模制材料含有第二窗口，第二窗口露出引线架构件的一表面，其和小片连接区域在相对面上。
17.如权利要求16中的半导体组件，其特征在于，还包括一热吸收器，其通过第二窗口连接到引线架构件上。
18.如权利要求10所述的半导体组件，其特征在于，还包括连接半导体小片和引线架构件的连接阵列，其中所述连接阵列包括焊接的或非焊接的突起材料以及焊膏材料，其含有不同的熔化温度。
19.一电气组合件，其包括：
半导体组件，其包括(a)引线架构件，其包括一小片连接区域和多根引线，(b)压制在引线架构件的至少一部分周围的模制材料，其中该模制材料包括一窗口，和(c)半导体小片，其包括安装在小片连接区域上的边缘，其中该半导体小片在窗口内，且一缝隙存在于该边缘和模制材料之间；和
电路基底，其中半导体组件安装在该电路基底上。
20.如权利要求19中的电气组合件，其特征在于，还包括连接半导体小片的焊料。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515335A (zh) * 2012-06-21 2014-01-15 英飞凌科技股份有限公司 电热冷却器件及其制造方法

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7217594B2 (en) * 2003-02-11 2007-05-15 Fairchild Semiconductor Corporation Alternative flip chip in leaded molded package design and method for manufacture
TW200514484A (en) * 2003-10-08 2005-04-16 Chung-Cheng Wang Substrate for electrical device and methods of fabricating the same
KR100541654B1 (ko) * 2003-12-02 2006-01-12 삼성전자주식회사 배선기판 및 이를 이용한 고체 촬상용 반도체 장치
US20060255479A1 (en) * 2005-05-10 2006-11-16 Texas Instruments Incorporated Magnetic assist manufacturing to reduce mold flash and assist with heat slug assembly
WO2007004133A2 (en) * 2005-07-05 2007-01-11 Koninklijke Philips Electronics N. V. Microchip assembly produced by transfer molding
EP1785916B1 (de) * 2005-11-14 2009-08-19 Tyco Electronics France SAS Smartcard-Körper, Smartcard und Herstellungsverfahren
US7285849B2 (en) * 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
US20090057852A1 (en) * 2007-08-27 2009-03-05 Madrid Ruben P Thermally enhanced thin semiconductor package
US7545032B2 (en) * 2006-07-10 2009-06-09 Stats Chippac Ltd. Integrated circuit package system with stiffener
US8106501B2 (en) * 2008-12-12 2012-01-31 Fairchild Semiconductor Corporation Semiconductor die package including low stress configuration
US7768105B2 (en) * 2007-01-24 2010-08-03 Fairchild Semiconductor Corporation Pre-molded clip structure
KR101391925B1 (ko) * 2007-02-28 2014-05-07 페어차일드코리아반도체 주식회사 반도체 패키지 및 이를 제조하기 위한 반도체 패키지 금형
KR101489325B1 (ko) * 2007-03-12 2015-02-06 페어차일드코리아반도체 주식회사 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법
US7659531B2 (en) * 2007-04-13 2010-02-09 Fairchild Semiconductor Corporation Optical coupler package
US7683463B2 (en) 2007-04-19 2010-03-23 Fairchild Semiconductor Corporation Etched leadframe structure including recesses
US7763958B1 (en) * 2007-05-25 2010-07-27 National Semiconductor Corporation Leadframe panel for power packages
US7714418B2 (en) * 2007-07-23 2010-05-11 National Semiconductor Corporation Leadframe panel
US7902657B2 (en) * 2007-08-28 2011-03-08 Fairchild Semiconductor Corporation Self locking and aligning clip structure for semiconductor die package
US7737548B2 (en) 2007-08-29 2010-06-15 Fairchild Semiconductor Corporation Semiconductor die package including heat sinks
US20090057855A1 (en) * 2007-08-30 2009-03-05 Maria Clemens Quinones Semiconductor die package including stand off structures
US7727813B2 (en) 2007-11-26 2010-06-01 Infineon Technologies Ag Method for making a device including placing a semiconductor chip on a substrate
US20090140266A1 (en) * 2007-11-30 2009-06-04 Yong Liu Package including oriented devices
US7589338B2 (en) * 2007-11-30 2009-09-15 Fairchild Semiconductor Corporation Semiconductor die packages suitable for optoelectronic applications having clip attach structures for angled mounting of dice
KR20090062612A (ko) * 2007-12-13 2009-06-17 페어차일드코리아반도체 주식회사 멀티 칩 패키지
US7781872B2 (en) * 2007-12-19 2010-08-24 Fairchild Semiconductor Corporation Package with multiple dies
US7714419B2 (en) * 2007-12-27 2010-05-11 Stats Chippac Ltd. Integrated circuit package system with shielding
US20090166826A1 (en) * 2007-12-27 2009-07-02 Janducayan Omar A Lead frame die attach paddles with sloped walls and backside grooves suitable for leadless packages
US8106406B2 (en) 2008-01-09 2012-01-31 Fairchild Semiconductor Corporation Die package including substrate with molded device
US7626249B2 (en) * 2008-01-10 2009-12-01 Fairchild Semiconductor Corporation Flex clip connector for semiconductor device
US20090194856A1 (en) * 2008-02-06 2009-08-06 Gomez Jocel P Molded package assembly
KR101524545B1 (ko) * 2008-02-28 2015-06-01 페어차일드코리아반도체 주식회사 전력 소자 패키지 및 그 제조 방법
US7768108B2 (en) * 2008-03-12 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die package including embedded flip chip
US8018054B2 (en) * 2008-03-12 2011-09-13 Fairchild Semiconductor Corporation Semiconductor die package including multiple semiconductor dice
KR101519062B1 (ko) * 2008-03-31 2015-05-11 페어차일드코리아반도체 주식회사 반도체 소자 패키지
US20090278241A1 (en) * 2008-05-08 2009-11-12 Yong Liu Semiconductor die package including die stacked on premolded substrate including die
US7855439B2 (en) * 2008-08-28 2010-12-21 Fairchild Semiconductor Corporation Molded ultra thin semiconductor die packages, systems using the same, and methods of making the same
US7829988B2 (en) * 2008-09-22 2010-11-09 Fairchild Semiconductor Corporation Stacking quad pre-molded component packages, systems using the same, and methods of making the same
US8314499B2 (en) * 2008-11-14 2012-11-20 Fairchild Semiconductor Corporation Flexible and stackable semiconductor die packages having thin patterned conductive layers
US8193618B2 (en) 2008-12-12 2012-06-05 Fairchild Semiconductor Corporation Semiconductor die package with clip interconnection
US7816784B2 (en) * 2008-12-17 2010-10-19 Fairchild Semiconductor Corporation Power quad flat no-lead semiconductor die packages with isolated heat sink for high-voltage, high-power applications, systems using the same, and methods of making the same
US7973393B2 (en) * 2009-02-04 2011-07-05 Fairchild Semiconductor Corporation Stacked micro optocouplers and methods of making the same
US8222718B2 (en) * 2009-02-05 2012-07-17 Fairchild Semiconductor Corporation Semiconductor die package and method for making the same
TWI453831B (zh) 2010-09-09 2014-09-21 台灣捷康綜合有限公司 半導體封裝結構及其製造方法
US8421204B2 (en) 2011-05-18 2013-04-16 Fairchild Semiconductor Corporation Embedded semiconductor power modules and packages
DE102012104882B4 (de) 2012-06-05 2017-06-08 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von optoelektronischen Halbleiterbauteilen und damit hergestelltes optoelektronisches Halbleiterbauteil
US9589929B2 (en) * 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
JP6201626B2 (ja) * 2013-10-23 2017-09-27 スミダコーポレーション株式会社 電子部品及び電子部品の製造方法
EP2947692B1 (en) * 2013-12-20 2020-09-23 Analog Devices, Inc. Integrated device die and package with stress reduction features
USD756942S1 (en) * 2015-05-06 2016-05-24 Xiamen Sanan Optoelectronics Technology Co., Ltd. Light-emitting diode package
USD761215S1 (en) * 2015-05-06 2016-07-12 Xiamen Sanan Optoelectronics Technology Co., Ltd. Package for light-emitting diode
US10287161B2 (en) 2015-07-23 2019-05-14 Analog Devices, Inc. Stress isolation features for stacked dies
US11127716B2 (en) 2018-04-12 2021-09-21 Analog Devices International Unlimited Company Mounting structures for integrated device packages
US10867894B2 (en) * 2018-10-11 2020-12-15 Asahi Kasei Microdevices Corporation Semiconductor element including encapsulated lead frames
US11901309B2 (en) * 2019-11-12 2024-02-13 Semiconductor Components Industries, Llc Semiconductor device package assemblies with direct leadframe attachment
US11664340B2 (en) 2020-07-13 2023-05-30 Analog Devices, Inc. Negative fillet for mounting an integrated device die to a carrier
US20240213124A1 (en) * 2022-12-22 2024-06-27 Wolfspeed, Inc. Power electronics package layouts, structures, and/or configurations for one or more power devices and processes implementing the same

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US122247A (en) * 1871-12-26 Improvement in machines for laying bridge-cables
US197278A (en) * 1877-11-20 Improvement in hen-houses
US11005A (en) * 1854-06-06 Berth-knee former
US41242A (en) * 1864-01-12 Improvement in breech-loading fire-arms
US66959A (en) * 1867-07-23 John b
US193080A (en) * 1877-07-17 Improvement in elliptic springs
US100962A (en) * 1870-03-22 Joseph f
US173684A (en) * 1876-02-15 Improvement in dies for making split nuts
US107126A (en) * 1870-09-06 Improvement in binding attachment for harvesters
US66950A (en) * 1867-07-23 cove ed ale
US192935A (en) * 1877-07-10 Improvement in milk-coolers
US42403A (en) * 1864-04-19 Improvement in band-ruffles
US56364A (en) * 1866-07-17 Improvement in coffins
US775786A (en) * 1904-07-26 1904-11-22 John F Spitt Non-refillable bottle.
US6094058A (en) * 1991-06-04 2000-07-25 Micron Technology, Inc. Temporary semiconductor package having dense array external contacts
JPH0575799U (ja) * 1992-03-23 1993-10-15 ティーディーケイ株式会社 圧電ブザー
JPH08213537A (ja) * 1995-02-01 1996-08-20 Toppan Printing Co Ltd リードフレーム構造体およびそれを用いた半導体装置
US5789809A (en) * 1995-08-22 1998-08-04 National Semiconductor Corporation Thermally enhanced micro-ball grid array package
US5637916A (en) * 1996-02-02 1997-06-10 National Semiconductor Corporation Carrier based IC packaging arrangement
US5869883A (en) * 1997-09-26 1999-02-09 Stanley Wang, President Pantronix Corp. Packaging of semiconductor circuit in pre-molded plastic package
US6423623B1 (en) * 1998-06-09 2002-07-23 Fairchild Semiconductor Corporation Low Resistance package for semiconductor devices
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
JP4260263B2 (ja) * 1999-01-28 2009-04-30 株式会社ルネサステクノロジ 半導体装置
JP2000244077A (ja) * 1999-02-24 2000-09-08 Matsushita Electric Ind Co Ltd 樹脂成形基板と電子部品組み込み樹脂成形基板
US6720642B1 (en) 1999-12-16 2004-04-13 Fairchild Semiconductor Corporation Flip chip in leaded molded package and method of manufacture thereof
US6392290B1 (en) * 2000-04-07 2002-05-21 Siliconix Incorporated Vertical structure for semiconductor wafer-level chip scale packages
JP3846158B2 (ja) * 2000-05-24 2006-11-15 松下電工株式会社 鏡筒及びこれを用いた撮像装置
JP2002289768A (ja) * 2000-07-17 2002-10-04 Rohm Co Ltd 半導体装置およびその製法
US6661082B1 (en) * 2000-07-19 2003-12-09 Fairchild Semiconductor Corporation Flip chip substrate design
JP3418373B2 (ja) * 2000-10-24 2003-06-23 エヌ・アール・エス・テクノロジー株式会社 弾性表面波装置及びその製造方法
US6798044B2 (en) 2000-12-04 2004-09-28 Fairchild Semiconductor Corporation Flip chip in leaded molded package with two dies
US6753605B2 (en) 2000-12-04 2004-06-22 Fairchild Semiconductor Corporation Passivation scheme for bumped wafers
US6469384B2 (en) 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6777786B2 (en) * 2001-03-12 2004-08-17 Fairchild Semiconductor Corporation Semiconductor device including stacked dies mounted on a leadframe
US6472251B1 (en) * 2001-04-09 2002-10-29 Delphi Technologies, Inc. Method for integrated circuit packaging
US6683375B2 (en) * 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
US6633030B2 (en) * 2001-08-31 2003-10-14 Fiarchild Semiconductor Surface mountable optocoupler package
US6797530B2 (en) * 2001-09-25 2004-09-28 Kabushiki Kaisha Toshiba Semiconductor device-manufacturing method for manufacturing semiconductor devices with improved heat radiating efficiency and similar in size to semiconductor elements
US6891256B2 (en) * 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
US6566749B1 (en) * 2002-01-15 2003-05-20 Fairchild Semiconductor Corporation Semiconductor die package with improved thermal and electrical performance
AU2003218085A1 (en) 2002-03-12 2003-09-29 Fairchild Semiconductor Corporation Wafer-level coated copper stud bumps
US7122884B2 (en) 2002-04-16 2006-10-17 Fairchild Semiconductor Corporation Robust leaded molded packages and methods for forming the same
US6836023B2 (en) 2002-04-17 2004-12-28 Fairchild Semiconductor Corporation Structure of integrated trace of chip package
US7061077B2 (en) 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
US7217594B2 (en) 2003-02-11 2007-05-15 Fairchild Semiconductor Corporation Alternative flip chip in leaded molded package design and method for manufacture
US7261717B2 (en) * 2003-09-11 2007-08-28 Skeletal Kinetics Llc Methods and devices for delivering orthopedic cements to a target bone site
US7196159B2 (en) * 2004-10-04 2007-03-27 Shell Oil Company Process for producing polytrimethylene terephthalate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515335A (zh) * 2012-06-21 2014-01-15 英飞凌科技股份有限公司 电热冷却器件及其制造方法
CN103515335B (zh) * 2012-06-21 2017-04-26 英飞凌科技股份有限公司 电热冷却器件及其制造方法

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