TW428103B - A circuit and method for fully on-chip wafer level burn-in test - Google Patents

A circuit and method for fully on-chip wafer level burn-in test

Info

Publication number
TW428103B
TW428103B TW088108591A TW88108591A TW428103B TW 428103 B TW428103 B TW 428103B TW 088108591 A TW088108591 A TW 088108591A TW 88108591 A TW88108591 A TW 88108591A TW 428103 B TW428103 B TW 428103B
Authority
TW
Taiwan
Prior art keywords
wafer burn
voltage
test
generating
signal
Prior art date
Application number
TW088108591A
Other languages
English (en)
Inventor
Young-June Nam
Young-Hee Kim
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW428103B publication Critical patent/TW428103B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
TW088108591A 1998-05-25 1999-05-25 A circuit and method for fully on-chip wafer level burn-in test TW428103B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980018886A KR100278926B1 (ko) 1998-05-25 1998-05-25 풀리 온 칩 웨이퍼 레벨 번-인 테스트 회로 및그 방법

Publications (1)

Publication Number Publication Date
TW428103B true TW428103B (en) 2001-04-01

Family

ID=19537730

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088108591A TW428103B (en) 1998-05-25 1999-05-25 A circuit and method for fully on-chip wafer level burn-in test

Country Status (4)

Country Link
US (1) US6169694B1 (zh)
JP (1) JP3774081B2 (zh)
KR (1) KR100278926B1 (zh)
TW (1) TW428103B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI831222B (zh) * 2022-05-25 2024-02-01 華邦電子股份有限公司 用以控制壓力電壓的測試電路以及半導體記憶裝置

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW432574B (en) * 2000-01-19 2001-05-01 Yang Wen Kun Wafer level burn in device and method
CA2308820A1 (en) * 2000-05-15 2001-11-15 The Governors Of The University Of Alberta Wireless radio frequency technique design and method for testing of integrated circuits and wafers
US6560729B1 (en) * 2000-07-03 2003-05-06 Advanced Micro Devices, Inc. Automated determination and display of the physical location of a failed cell in an array of memory cells
KR100380344B1 (ko) * 2000-08-09 2003-04-14 삼성전자주식회사 패키지 번인 테스트가 가능한 반도체 장치 및 패키지 번인테스트방법
JP2003007100A (ja) * 2001-06-20 2003-01-10 Hitachi Ltd 半導体記憶装置
KR100772720B1 (ko) * 2001-12-29 2007-11-02 주식회사 하이닉스반도체 반도체메모리장치의 번-인회로
KR100432886B1 (ko) * 2002-01-30 2004-05-22 삼성전자주식회사 높은 주파수의 웨이퍼 테스트 동작을 수행하는 반도체메모리 장치
US6724214B2 (en) * 2002-09-13 2004-04-20 Chartered Semiconductor Manufacturing Ltd. Test structures for on-chip real-time reliability testing
US7106644B2 (en) * 2003-12-01 2006-09-12 Elite Semiconductor Memory Technology, Inc. Memory device and method for burn-in test
CN100421184C (zh) * 2004-03-03 2008-09-24 晶豪科技股份有限公司 用于预烧测试的存储器装置以及方法
US7321482B2 (en) * 2004-03-19 2008-01-22 Hewlett-Packard Development Company, L.P. Sub-circuit voltage manipulation
KR100671752B1 (ko) 2006-01-13 2007-01-19 삼성전자주식회사 반도체 메모리 장치의 웨이퍼 번인 테스트 전류 생성 방법및 이를 이용한 반도체 장치.
KR100816230B1 (ko) * 2006-11-15 2008-03-21 동부일렉트로닉스 주식회사 반도체기판 전압 및 전류 검사장치
CN103543344B (zh) * 2012-07-10 2016-07-20 上海斐讯数据通信技术有限公司 一种解决电容屏失效的方法及电容屏异常侦测电路
CN111323689B (zh) * 2018-12-13 2022-08-09 联华电子股份有限公司 测试键检测电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2829135B2 (ja) * 1990-12-27 1998-11-25 株式会社東芝 半導体記憶装置
JPH06243677A (ja) 1993-02-19 1994-09-02 Hitachi Ltd 半導体記憶装置とメモリ装置及びその品種設定方法
KR0119887B1 (ko) 1994-06-08 1997-10-30 김광호 반도체 메모리장치의 웨이퍼 번-인 테스트 회로
KR0135108B1 (ko) 1994-12-13 1998-04-25 김광호 스트레스 테스트 회로를 포함하는 반도체 메모리 장치
US5592422A (en) 1995-06-07 1997-01-07 Sgs-Thomson Microelectronics, Inc. Reduced pin count stress test circuit for integrated memory devices and method therefor
JP3734853B2 (ja) * 1995-06-27 2006-01-11 株式会社ルネサステクノロジ 半導体記憶装置
US5619462A (en) 1995-07-31 1997-04-08 Sgs-Thomson Microelectronics, Inc. Fault detection for entire wafer stress test
US5557573A (en) 1995-08-21 1996-09-17 Sgs-Thomson Microelectronics, Inc. Entire wafer stress test method for integrated memory devices and circuit therefor
KR0172344B1 (ko) 1995-09-15 1999-03-30 김광호 웨이퍼 번인 테스트회로 및 그 방법
US5852581A (en) 1996-06-13 1998-12-22 Micron Technology, Inc. Method of stress testing memory integrated circuits
JP3839873B2 (ja) * 1996-07-03 2006-11-01 株式会社ルネサステクノロジ 半導体集積回路装置
KR100220949B1 (ko) * 1996-11-06 1999-09-15 김영환 웨이퍼 번-인 회로

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI831222B (zh) * 2022-05-25 2024-02-01 華邦電子股份有限公司 用以控制壓力電壓的測試電路以及半導體記憶裝置

Also Published As

Publication number Publication date
KR19990086097A (ko) 1999-12-15
US6169694B1 (en) 2001-01-02
JP3774081B2 (ja) 2006-05-10
KR100278926B1 (ko) 2001-01-15
JP2000030495A (ja) 2000-01-28

Similar Documents

Publication Publication Date Title
TW428103B (en) A circuit and method for fully on-chip wafer level burn-in test
TW368657B (en) Integrated circuit memory device having built-in self test circuit with monitor and tester modes
JPH08304515A (ja) パッケージ状態で直流電圧テスト可能な半導体メモリ装置
US5892386A (en) Internal power control circuit for a semiconductor device
US6857093B2 (en) Semiconductor integrated circuit device capable of self-testing internal power supply currents provided to internal circuits integrated on chip
RU95103443A (ru) Полупроводниковая интегральная схема и способ подачи на нее нагружающего напряжения
TW374929B (en) Integrated circuit having a function of testing memory using stress voltage and method of testing memory of the same
EP1333446A3 (en) Circuit and method for testing a ferroelectric memory device
US20060164116A1 (en) Internal reference voltage generation for integrated circuit testing
TW200605088A (en) Apparatus and method for testing semiconductor memory device
US6903595B2 (en) High voltage transfer circuit
US6744271B2 (en) Internal generation of reference voltage
US5942808A (en) Semiconductor device with plural power supply circuits, plural internal circuits, and single external terminal
US6535440B2 (en) Apparatus and method for package level burn-in test in semiconductor device
US6356490B1 (en) Semiconductor device, testing device thereof and testing method thereof
TW363241B (en) A wafer burn-in circuit for a semiconductor memory device
US5349586A (en) Stand by control circuit
KR100311972B1 (ko) 반도체 메모리 장치의 모드신호 발생장치
US5412337A (en) Semiconductor device providing reliable conduction test of all terminals
KR100696856B1 (ko) 평판표시장치의 ｔｃｐ 출력핀 접속 오류 테스트 장치 및방법과 평판표시장치의 오류 테스트 시스템
KR100345956B1 (ko) 강제동작기능 부착의 제어장치 및 반도체 집적회로장치
US7250809B2 (en) Boosted voltage generator
US10396709B2 (en) Method and apparatus for in-situ health monitoring of solar cells in space
KR20070019403A (ko) 전원전압 공급회로 및 이를 구비한 반도체 장치
US6898543B2 (en) In-system testing of an oscillator

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees