TW324800B - Dual-directory virtual cache and control method thereof - Google Patents

Dual-directory virtual cache and control method thereof

Info

Publication number
TW324800B
TW324800B TW085114360A TW85114360A TW324800B TW 324800 B TW324800 B TW 324800B TW 085114360 A TW085114360 A TW 085114360A TW 85114360 A TW85114360 A TW 85114360A TW 324800 B TW324800 B TW 324800B
Authority
TW
Taiwan
Prior art keywords
tag
memory
address
virtual
physical
Prior art date
Application number
TW085114360A
Other languages
English (en)
Inventor
Heung Kim Han
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW324800B publication Critical patent/TW324800B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW085114360A 1995-11-17 1996-11-21 Dual-directory virtual cache and control method thereof TW324800B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950041977A KR970029072A (ko) 1995-11-17 1995-11-17 이중 디렉토리 가상 캐쉬 및 그 제어 방법

Publications (1)

Publication Number Publication Date
TW324800B true TW324800B (en) 1998-01-11

Family

ID=19434528

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085114360A TW324800B (en) 1995-11-17 1996-11-21 Dual-directory virtual cache and control method thereof

Country Status (4)

Country Link
JP (1) JP3116215B2 (zh)
KR (1) KR970029072A (zh)
GB (1) GB2307319B (zh)
TW (1) TW324800B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6598128B1 (en) * 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US7191291B2 (en) 2003-01-16 2007-03-13 Ip-First, Llc Microprocessor with variable latency stack cache
US7139877B2 (en) 2003-01-16 2006-11-21 Ip-First, Llc Microprocessor and apparatus for performing speculative load operation from a stack memory cache
US7139876B2 (en) 2003-01-16 2006-11-21 Ip-First, Llc Microprocessor and apparatus for performing fast speculative pop operation from a stack memory cache
US7136990B2 (en) 2003-01-16 2006-11-14 Ip-First, Llc. Fast POP operation from RAM cache using cache row value stack
US8612690B2 (en) * 2012-01-17 2013-12-17 Qualcomm Incorporated Method for filtering traffic to a physically-tagged data cache
US10831664B2 (en) 2017-06-16 2020-11-10 International Business Machines Corporation Cache structure using a logical directory
US10698836B2 (en) 2017-06-16 2020-06-30 International Business Machines Corporation Translation support for a virtual cache
US10606762B2 (en) 2017-06-16 2020-03-31 International Business Machines Corporation Sharing virtual and real translations in a virtual cache

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8823077D0 (en) * 1988-09-30 1988-11-09 Int Computers Ltd Data processing apparatus
GB2260429B (en) * 1991-10-11 1995-05-24 Intel Corp Versatile cache memory
DE69427734T2 (de) * 1993-10-29 2002-05-23 Advanced Micro Devices Inc Linearadressierter Mikroprozessorcachespeicher

Also Published As

Publication number Publication date
GB2307319B (en) 2000-05-31
GB2307319A (en) 1997-05-21
JP3116215B2 (ja) 2000-12-11
KR970029072A (ko) 1997-06-26
JPH1091521A (ja) 1998-04-10
GB9623913D0 (en) 1997-01-08

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