DE69427734T2 - Linearadressierter Mikroprozessorcachespeicher - Google Patents
Linearadressierter MikroprozessorcachespeicherInfo
- Publication number
- DE69427734T2 DE69427734T2 DE69427734T DE69427734T DE69427734T2 DE 69427734 T2 DE69427734 T2 DE 69427734T2 DE 69427734 T DE69427734 T DE 69427734T DE 69427734 T DE69427734 T DE 69427734T DE 69427734 T2 DE69427734 T2 DE 69427734T2
- Authority
- DE
- Germany
- Prior art keywords
- linearly addressed
- microprocessor cache
- cache
- microprocessor
- addressed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14638193A | 1993-10-29 | 1993-10-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69427734D1 DE69427734D1 (de) | 2001-08-23 |
DE69427734T2 true DE69427734T2 (de) | 2002-05-23 |
Family
ID=22517116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69427734T Expired - Fee Related DE69427734T2 (de) | 1993-10-29 | 1994-09-20 | Linearadressierter Mikroprozessorcachespeicher |
Country Status (4)
Country | Link |
---|---|
US (3) | US5623619A (de) |
EP (1) | EP0651332B1 (de) |
JP (1) | JPH07160580A (de) |
DE (1) | DE69427734T2 (de) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69427734T2 (de) * | 1993-10-29 | 2002-05-23 | Advanced Micro Devices Inc | Linearadressierter Mikroprozessorcachespeicher |
US5890221A (en) * | 1994-10-05 | 1999-03-30 | International Business Machines Corporation | Method and system for offset miss sequence handling in a data cache array having multiple content addressable field per cache line utilizing an MRU bit |
US6813699B1 (en) | 1995-06-02 | 2004-11-02 | Transmeta Corporation | Speculative address translation for processor using segmentation and optional paging |
US5920713A (en) * | 1995-10-06 | 1999-07-06 | Advanced Micro Devices, Inc. | Instruction decoder including two-way emulation code branching |
KR970029072A (ko) * | 1995-11-17 | 1997-06-26 | 김주용 | 이중 디렉토리 가상 캐쉬 및 그 제어 방법 |
US5848287A (en) | 1996-02-20 | 1998-12-08 | Advanced Micro Devices, Inc. | Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches |
US5790821A (en) * | 1996-03-08 | 1998-08-04 | Advanced Micro Devices, Inc. | Control bit vector storage for storing control vectors corresponding to instruction operations in a microprocessor |
US5822560A (en) * | 1996-05-23 | 1998-10-13 | Advanced Micro Devices, Inc. | Apparatus for efficient instruction execution via variable issue and variable control vectors per issue |
KR19980032776A (ko) * | 1996-10-16 | 1998-07-25 | 가나이 츠토무 | 데이타 프로세서 및 데이타 처리시스템 |
KR100204024B1 (ko) * | 1996-11-06 | 1999-06-15 | 김영환 | 페이지 경계에 걸리는 분할 라인을 한 사이클에 억세스할 수 있는 컴퓨팅 시스템 |
US6175906B1 (en) | 1996-12-06 | 2001-01-16 | Advanced Micro Devices, Inc. | Mechanism for fast revalidation of virtual tags |
US6189074B1 (en) | 1997-03-19 | 2001-02-13 | Advanced Micro Devices, Inc. | Mechanism for storing system level attributes in a translation lookaside buffer |
US5933629A (en) | 1997-06-12 | 1999-08-03 | Advanced Micro Devices, Inc. | Apparatus and method for detecting microbranches early |
US6157986A (en) * | 1997-12-16 | 2000-12-05 | Advanced Micro Devices, Inc. | Fast linear tag validation unit for use in microprocessor |
US6446189B1 (en) | 1999-06-01 | 2002-09-03 | Advanced Micro Devices, Inc. | Computer system including a novel address translation mechanism |
US6279080B1 (en) * | 1999-06-09 | 2001-08-21 | Ati International Srl | Method and apparatus for association of memory locations with a cache location having a flush buffer |
US6438664B1 (en) | 1999-10-27 | 2002-08-20 | Advanced Micro Devices, Inc. | Microcode patch device and method for patching microcode using match registers and patch routines |
US6442707B1 (en) | 1999-10-29 | 2002-08-27 | Advanced Micro Devices, Inc. | Alternate fault handler |
CN100354820C (zh) * | 1999-12-31 | 2007-12-12 | 英特尔公司 | 外部微代码 |
US6510508B1 (en) | 2000-06-15 | 2003-01-21 | Advanced Micro Devices, Inc. | Translation lookaside buffer flush filter |
US6665788B1 (en) | 2001-07-13 | 2003-12-16 | Advanced Micro Devices, Inc. | Reducing latency for a relocation cache lookup and address mapping in a distributed memory system |
US6859868B2 (en) * | 2002-02-07 | 2005-02-22 | Sun Microsystems, Inc. | Object addressed memory hierarchy |
US7958374B2 (en) * | 2002-03-19 | 2011-06-07 | Shansun Technology Company | Digital information protecting method and apparatus, and computer accessible recording medium |
US9081725B2 (en) | 2002-03-19 | 2015-07-14 | Shansun Technology Company | Digital information protecting method and apparatus, and computer accessible recording medium |
US6957317B2 (en) * | 2002-10-10 | 2005-10-18 | Intel Corporation | Apparatus and method for facilitating memory data access with generic read/write patterns |
US20040103255A1 (en) * | 2002-11-25 | 2004-05-27 | Howlett Warren Kurt | Memory sub-array selection monitoring |
US20040181626A1 (en) * | 2003-03-13 | 2004-09-16 | Pickett James K. | Partial linearly tagged cache memory system |
JP3936672B2 (ja) * | 2003-04-30 | 2007-06-27 | 富士通株式会社 | マイクロプロセッサ |
US7873776B2 (en) * | 2004-06-30 | 2011-01-18 | Oracle America, Inc. | Multiple-core processor with support for multiple virtual processors |
US7685354B1 (en) * | 2004-06-30 | 2010-03-23 | Sun Microsystems, Inc. | Multiple-core processor with flexible mapping of processor cores to cache banks |
US9280473B2 (en) * | 2004-12-02 | 2016-03-08 | Intel Corporation | Method and apparatus for accessing physical memory from a CPU or processing element in a high performance manner |
US7630388B2 (en) * | 2005-05-04 | 2009-12-08 | Arm Limited | Software defined FIFO memory for storing a set of data from a stream of source data |
WO2006117504A1 (en) * | 2005-05-04 | 2006-11-09 | Arm Limited | Use of a data engine within a data processing apparatus |
US7920584B2 (en) * | 2005-05-04 | 2011-04-05 | Arm Limited | Data processing system |
US20070005933A1 (en) * | 2005-06-29 | 2007-01-04 | Kopec Brian J | Preventing multiple translation lookaside buffer accesses for a same page in memory |
US20090248919A1 (en) * | 2008-03-25 | 2009-10-01 | Jerzy Szwagrzyk | Method for external fifo acceleration |
US9740494B2 (en) | 2011-04-29 | 2017-08-22 | Arizona Board Of Regents For And On Behalf Of Arizona State University | Low complexity out-of-order issue logic using static circuits |
US9367477B2 (en) | 2014-09-24 | 2016-06-14 | Intel Corporation | Instruction and logic for support of code modification in translation lookaside buffers |
US20170255569A1 (en) * | 2016-03-01 | 2017-09-07 | Qualcomm Incorporated | Write-allocation for a cache based on execute permissions |
US11853231B2 (en) | 2021-06-24 | 2023-12-26 | Ati Technologies Ulc | Transmission of address translation type packets |
Family Cites Families (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3781808A (en) * | 1972-10-17 | 1973-12-25 | Ibm | Virtual memory system |
AT354159B (de) * | 1975-02-10 | 1979-12-27 | Siemens Ag | Assoziativspeicher mit getrennt assoziierbaren bereichen |
US4155119A (en) * | 1977-09-21 | 1979-05-15 | Sperry Rand Corporation | Method for providing virtual addressing for externally specified addressed input/output operations |
US4179737A (en) * | 1977-12-23 | 1979-12-18 | Burroughs Corporation | Means and methods for providing greater speed and flexibility of microinstruction sequencing |
US4161784A (en) * | 1978-01-05 | 1979-07-17 | Honeywell Information Systems, Inc. | Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands |
US4384343A (en) * | 1979-02-12 | 1983-05-17 | Honeywell Information Systems Inc. | Firmware controlled search and verify apparatus and method for a data processing system |
US4453212A (en) * | 1981-07-13 | 1984-06-05 | Burroughs Corporation | Extended address generating apparatus and method |
US4928223A (en) * | 1982-10-06 | 1990-05-22 | Fairchild Semiconductor Corporation | Floating point microprocessor with directable two level microinstructions |
AU3229484A (en) * | 1983-09-07 | 1985-03-14 | Amdahl Corporation | Time shared translation buffer |
US4807115A (en) * | 1983-10-07 | 1989-02-21 | Cornell Research Foundation, Inc. | Instruction issuing mechanism for processors with multiple functional units |
JPH0658631B2 (ja) * | 1983-12-19 | 1994-08-03 | 株式会社日立製作所 | デ−タ処理装置 |
DE3588166T2 (de) * | 1984-07-31 | 1998-02-12 | Texas Instruments Inc | Entwurf einer Cache-Hierarchie zur Anwendung in einer Speicherverwaltungseinheit |
US4972338A (en) * | 1985-06-13 | 1990-11-20 | Intel Corporation | Memory management for microprocessor system |
US5133062A (en) * | 1986-03-06 | 1992-07-21 | Advanced Micro Devices, Inc. | RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory |
CA1286784C (en) * | 1986-08-27 | 1991-07-23 | Joseph A. Petolino, Jr. | Cache storage queue |
US4992934A (en) * | 1986-12-15 | 1991-02-12 | United Technologies Corporation | Reduced instruction set computing apparatus and methods |
US4926322A (en) * | 1987-08-03 | 1990-05-15 | Compag Computer Corporation | Software emulation of bank-switched memory using a virtual DOS monitor and paged memory management |
US5222230A (en) * | 1988-01-29 | 1993-06-22 | Texas Instruments Incorporated | Circuitry for transferring data from a data bus and temporary register into a plurality of input registers on clock edges |
US5056006A (en) * | 1988-09-12 | 1991-10-08 | General Electric Company | Parallel processor with single program storage and sequencer and simultaneous instruction processing |
JP2810068B2 (ja) * | 1988-11-11 | 1998-10-15 | 株式会社日立製作所 | プロセッサシステム、コンピュータシステム及び命令処理方法 |
US5155816A (en) * | 1989-02-10 | 1992-10-13 | Intel Corporation | Pipelined apparatus and method for controlled loading of floating point data in a microprocessor |
US5155820A (en) * | 1989-02-21 | 1992-10-13 | Gibson Glenn A | Instruction format with designations for operand lengths of byte, half word, word, or double word encoded in address bits |
US5226126A (en) * | 1989-02-24 | 1993-07-06 | Nexgen Microsystems | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags |
CA2016068C (en) * | 1989-05-24 | 2000-04-04 | Robert W. Horst | Multiple instruction issue computer architecture |
US5136697A (en) * | 1989-06-06 | 1992-08-04 | Advanced Micro Devices, Inc. | System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache |
EP0415366B1 (de) * | 1989-08-28 | 1997-06-11 | Nec Corporation | Mikroprozessor mit Pipeline-Predecodereinheit und -Hauptdecodereinheit |
US5255377A (en) * | 1989-11-13 | 1993-10-19 | Intel Corporation | Interface for arbitrating access to the paging unit of a computer processor |
US5185868A (en) * | 1990-01-16 | 1993-02-09 | Advanced Micro Devices, Inc. | Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy |
US5226130A (en) * | 1990-02-26 | 1993-07-06 | Nexgen Microsystems | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency |
JP2822588B2 (ja) * | 1990-04-30 | 1998-11-11 | 日本電気株式会社 | キャッシュメモリ装置 |
US5201056A (en) * | 1990-05-02 | 1993-04-06 | Motorola, Inc. | RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output |
DE69130588T2 (de) * | 1990-05-29 | 1999-05-27 | Nat Semiconductor Corp | Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür |
US5325499A (en) * | 1990-09-28 | 1994-06-28 | Tandon Corporation | Computer system including a write protection circuit for preventing illegal write operations and a write poster with improved memory |
GB2260429B (en) * | 1991-10-11 | 1995-05-24 | Intel Corp | Versatile cache memory |
US5473348A (en) * | 1992-06-09 | 1995-12-05 | Kabushiki Kaisha Toshiba | Apparatus and method of controlling paging unit of coprocessor built in display control system |
US5467473A (en) * | 1993-01-08 | 1995-11-14 | International Business Machines Corporation | Out of order instruction load and store comparison |
US5454117A (en) * | 1993-08-25 | 1995-09-26 | Nexgen, Inc. | Configurable branch prediction for a processor performing speculative execution |
IE80854B1 (en) * | 1993-08-26 | 1999-04-07 | Intel Corp | Processor ordering consistency for a processor performing out-of-order instruction execution |
DE69427734T2 (de) * | 1993-10-29 | 2002-05-23 | Advanced Micro Devices Inc | Linearadressierter Mikroprozessorcachespeicher |
-
1994
- 1994-09-20 DE DE69427734T patent/DE69427734T2/de not_active Expired - Fee Related
- 1994-09-20 EP EP94306885A patent/EP0651332B1/de not_active Expired - Lifetime
- 1994-10-24 JP JP6257826A patent/JPH07160580A/ja not_active Withdrawn
-
1995
- 1995-07-24 US US08/506,509 patent/US5623619A/en not_active Expired - Lifetime
-
1997
- 1997-01-08 US US08/780,263 patent/US5761691A/en not_active Expired - Lifetime
- 1997-11-17 US US08/971,805 patent/US6240484B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6240484B1 (en) | 2001-05-29 |
EP0651332B1 (de) | 2001-07-18 |
DE69427734D1 (de) | 2001-08-23 |
US5761691A (en) | 1998-06-02 |
US5623619A (en) | 1997-04-22 |
EP0651332A1 (de) | 1995-05-03 |
JPH07160580A (ja) | 1995-06-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8339 | Ceased/non-payment of the annual fee |