GB9623913D0 - Dual directory virtual cache memory and method for contol thereof - Google Patents

Dual directory virtual cache memory and method for contol thereof

Info

Publication number
GB9623913D0
GB9623913D0 GBGB9623913.2A GB9623913A GB9623913D0 GB 9623913 D0 GB9623913 D0 GB 9623913D0 GB 9623913 A GB9623913 A GB 9623913A GB 9623913 D0 GB9623913 D0 GB 9623913D0
Authority
GB
United Kingdom
Prior art keywords
contol
cache memory
virtual cache
directory virtual
dual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB9623913.2A
Other versions
GB2307319B (en
GB2307319A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of GB9623913D0 publication Critical patent/GB9623913D0/en
Publication of GB2307319A publication Critical patent/GB2307319A/en
Application granted granted Critical
Publication of GB2307319B publication Critical patent/GB2307319B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB9623913A 1995-11-17 1996-11-18 Dual-directory virtual cache memory and method for control thereof Expired - Fee Related GB2307319B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950041977A KR970029072A (en) 1995-11-17 1995-11-17 Dual Directory Virtual Cache and Its Control Method

Publications (3)

Publication Number Publication Date
GB9623913D0 true GB9623913D0 (en) 1997-01-08
GB2307319A GB2307319A (en) 1997-05-21
GB2307319B GB2307319B (en) 2000-05-31

Family

ID=19434528

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9623913A Expired - Fee Related GB2307319B (en) 1995-11-17 1996-11-18 Dual-directory virtual cache memory and method for control thereof

Country Status (4)

Country Link
JP (1) JP3116215B2 (en)
KR (1) KR970029072A (en)
GB (1) GB2307319B (en)
TW (1) TW324800B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6598128B1 (en) * 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US7191291B2 (en) 2003-01-16 2007-03-13 Ip-First, Llc Microprocessor with variable latency stack cache
US7139877B2 (en) 2003-01-16 2006-11-21 Ip-First, Llc Microprocessor and apparatus for performing speculative load operation from a stack memory cache
US7139876B2 (en) 2003-01-16 2006-11-21 Ip-First, Llc Microprocessor and apparatus for performing fast speculative pop operation from a stack memory cache
US7136990B2 (en) 2003-01-16 2006-11-14 Ip-First, Llc. Fast POP operation from RAM cache using cache row value stack
US8612690B2 (en) * 2012-01-17 2013-12-17 Qualcomm Incorporated Method for filtering traffic to a physically-tagged data cache
US10831664B2 (en) 2017-06-16 2020-11-10 International Business Machines Corporation Cache structure using a logical directory
US10698836B2 (en) 2017-06-16 2020-06-30 International Business Machines Corporation Translation support for a virtual cache
US10606762B2 (en) 2017-06-16 2020-03-31 International Business Machines Corporation Sharing virtual and real translations in a virtual cache

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8823077D0 (en) * 1988-09-30 1988-11-09 Int Computers Ltd Data processing apparatus
GB2260429B (en) * 1991-10-11 1995-05-24 Intel Corp Versatile cache memory
DE69427734T2 (en) * 1993-10-29 2002-05-23 Advanced Micro Devices Inc Linearly addressed microprocessor cache

Also Published As

Publication number Publication date
GB2307319B (en) 2000-05-31
GB2307319A (en) 1997-05-21
JP3116215B2 (en) 2000-12-11
KR970029072A (en) 1997-06-26
JPH1091521A (en) 1998-04-10
TW324800B (en) 1998-01-11

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20061118