TW312817B - - Google Patents

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TW312817B
TW312817B TW085100647A TW85100647A TW312817B TW 312817 B TW312817 B TW 312817B TW 085100647 A TW085100647 A TW 085100647A TW 85100647 A TW85100647 A TW 85100647A TW 312817 B TW312817 B TW 312817B
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Taiwan
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film
semiconductor substrate
seconds
insulating film
semiconductor
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TW085100647A
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Toshiba Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
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    • H01L21/31608—Deposition of SiO2
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/902—Capping layer

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  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)

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經濟部中央揉準局貝工消費合作社印製 A7 ___B7__ 五、發明説明（1 ) 〔產業上之利用領域〕 本發明係與半導體裝置之製造方法有關，尤其與具有 多層配線構造之半導體裝置之層間絕緣膜之形成方法有關 〔先前之技術〕 隨著半導體裝置之集成度之增大，在基板上形成多層 配線材料之所謂多餍配線化逐漸進展，具有此種多層配線 構造之半導體裝置之製造工程益形複雜化，長工程化。 尤其多層配線之形成工程對半導體裝置之製造價格所 佔比例大，爲圖半導體裝置之成本降低，多層配線工程之 低減化要求益形增高。 茲說明先前之多層配線之形成工程，首先在半導體基 板上之絕緣膜上堆積下層配線用之第1配線材料後，實施 下層配線之成型，在該下層配線上形成第1絕緣膜*並將 絕緣膜埋進下層配線相互間。此時，由於前述下層配線之 圓型在第1絕緣膜表面存在段差，以至在此後之上層配線 用之第2配線材料堆積時及上層配線之成型時產生不良影 響，而有招致因上層配線段部之斷線，短路等重大缺陷之 虞。 故通常，在前述第1絕緣膜上堆稹第2配線材料前， 將其底之第1絕緣膜表面以電阻蝕刻予以平坦化，緩和段 差後，在其上形成第2絕緣膜》 如上述第1絕緣膜及第2絕緣膜積層之先前之層間絕 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -4 - --------—裝------訂------4 (請先閲讀背面之注意事項再填寫本頁) 312817 A7 B7 經濟部中央標串局貝工消費合作社印製 五、發明説明（2 ) 緣膜膜之形成工程係第1次成膜—平坦化—第2次成膜， 故工程數多，成爲對如前述多層配線工程低減化要求之大 障礙。 又，已知如上述第1絕緣膜表面平坦化之方法外，亦 有在第1絕緣膜上形成SpinOnGlass(SOG)膜，以 緩和上層配線材料底之段差之方法。 惟此方法，在形（燒）成SOG膜時需多數次熱處理 工程，爲確保上層配線之信賴性，需以電池蝕刻去除 S 0 G膜之不需要部份，結果工程數加多，仍無法充份對 應如前述多層配線工程低減化之要求。 最近，爲對應如前述多層配線工程低減化之要求之技 術之一，有如在形成層間絕緣膜時，將S i H4氣體與氧 化劑之Η 2 〇 2 (過氧化强水）在低溫（例如約0 °C )真空 中反應，以在下層配線配線上形成自行流動型（Re flow )之絕緣膜（以下稱Re flow絕緣膜）之方法受到注目。 該方法因可同時達成下層配線之配線相互間絕緣膜之 埋進及絕緣膜表面之平坦化，以1次成膜即可完成至平坦 化之工程，故可實現多層配線工程之低減化。 然而，如上述Re flow Si〇2膜之形成方法，由其反應 形態可知，因在絕緣膜之成膜中產生水份（Η 20 )，絕 緣膜中含多量水份，故成膜中或其後需要熱處理（例如 4 5 0 °C 3 0分）時膜中水份急激放出，絕緣膜裂開（ 以下稱產生裂痕）。 圓4表實例以如上述Re flow Si〇2膜之形成方法形成 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) " ' (請先閱讀背面之注意事項再填寫本頁) 丨裝. 訂 .^ 經濟部中央橾準局貝工消费合作杜印製 A7 B7 五、發明説明（3 ) 之Re flow Si 〇2膜產生裂痕狀況之數據。此時，以Re flow Si〇2膜膜之膜厚’及在Re flow Si〇2膜上以等離子 CVD (氣相成長）法形成SiO膜（以下，稱蓋膜）時 之蓋膜厚爲參數，成膜後以4 5 0 °C實施3 0分熱處理時 之裂痕產生狀況。 由圖4可知，蓋膜不存在時，及蓋膜存在時均在Re flow Si 〇2膜之膜厚爲1 . 1 以上時產生裂痕。換言 之，Re flow Si〇2膜之膜厚之裂痕有上限，本例爲1 . 〇 μ m故膜厚上限低。 惟使用如前述之Re flow Si〇2膜膜時，爲了充份緩和 (平坦化）上層配線材料之底之段差，有確保相當程度膜 厚之必要，且提髙裂痕耐性厚爲重要。 又在Re flow Si 〇2膜上部以通常之等離子CV D法形 成層間絕緣膜時，因半導體晶片未十份昇溫，故形成溫蝕 刻率遲之絕緣膜》由此，在層間絕緣膜形成後實施之開接 觸孔或Beer孔用之蝕刻中，層間絕緣膜與Re flow Si 〇2膜之界面成異常之蝕刻形狀，使其後形成之上層配線 之敷層惡化，成爲招致上層配線導通不良之原因。 〔發明欲解決之課題〕 如上述先前之多餍配線工程中之層間絕緣膜形成工程 採用Re flow絕緣膜形成技術時所得之Re flow 8〖〇2膜 ，即使考慮其平坦化所需膜厚惟爲了裂痕耐性有將上限抑 低之問題。 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -裝· 經濟部中央揉準局员工消費合作社印製 3ί28ΐ7 A7 B7 五、發明説明（4 ) 又，在上述Re flow Si〇2膜上部之層間絕緣膜形成 後實施之開貫穿孔或Beer孔用之蝕刻時層間絕緣膜與 Re flow Si 〇2膜之界面成爲異常之蝕刻形狀，使上層配 線之敷層惡化，而有成爲招致上層配線導通不良原因之問 題。 本發明爲解決上述問題而爲其目的在提供可製造提高 半導體裝置之多層配線工程中之層間絕緣膜形成工程採用 Re flow絕緣膜形成技術時所得Re flow Si〇2膜之裂痕 耐性，確保考慮Re flow Si〇2膜之平坦化所需膜厚，且 層間絕緣膜形成後所形成之上層配線之信賴性髙之半導體 裝置之半導體裝置之製造方法。 〔解決課題之方法〕 本發明之半導體裝置之製造方法，其特徵爲，具備： 將S i H4氣體及H202導入收容形成絕緣膜後之半導體 基板之反應室內，將上述S i H4氣體及H2 0 2於6 5 0 P. a以下真空中，一1 〇°C以上+ 1 〇°C以下溫度範圍內 至相反應，在半導體基板上形成Reflow形狀之0. 4
Aim以上，1. 4#m以下厚度之Refi〇w S i 02膜 3 4之工程，及其後將半導體基板放置於所定真空中3 0 秒以上之工程，及將半導體基板放置於3 0 0 °C以上， 4 5 0 °C未滿高溫中1 2 0秒以上，6 0 0秒未滿時間之 工程。 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） -7 - --------裝-- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央樣準局貝工消费合作社印製 __B7_ 五、發明説明（5 ) 〔作用〕 多層配線工程中之層間絕緣膜形成工程採用Re flow絕緣膜形成技術，形成Re flow Si〇2膜後放置於所定 真空中所定時間以上，更放置於所定高溫中所定時間以上 ，控制Re flow Si 〇2膜中之水份，即可提髙裂痕耐性。 由於如上述提高Re flow Si〇2膜之裂痕耐性，可確保 考慮Re flow絕緣膜平坦化所需膜厚，故可提高層間絕緣 膜表面之平坦性，更使層間絕緣膜形成後所形成之上層配 線微細化。 而且可防止層間絕緣膜形成後實施之開接觸孔或B_eer 孔用之蝕刻之異常蝕刻，不致使其後形成之上層配線之敷 層惡化，或招致上層配線之導通不良，而可提高上層配線 之信賴性。 (實施例） 以下參照圖詳細說明本發明之一實施例。 圖1 (a)概略表示本發明之半導體裝置之製造方法 使用之半導體製造裝置構成之一例。 圖1 (a)中，10係等離子CVD裝置，20係減 壓CVD裝置，，1係收容半導體基板之卡匣裝載機室，2 係在上述卡匣裝載室1與前述等離子CVD裝置1〇之反 應室或減壓CVD裝置2 0之反應室間搬送（搬入搬出） 半導體基板之機械人臂。 上述等離子CVD裝置1 0具有通常之構造，以圖1 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X 297公釐）_ a _ (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 經濟部中央榡準局員工消費合作杜中裝 A7 B7 五、發明説明（6 ) (b)概略表示其構成之一例。圖1 (b)中，11係反 應室（Chamber )’ 12 係上部電極（Shower head )， 2 3係下部電極（Table ) ，24係排氣口，25係 S i H4氣體供給徑路，2 6係H202供給徑路。 圖2 ( a )至（e )表示本發明之半導體裝置之製造 方法有關之多層配線工程中之層間絕緣膜形成工程採用 Re flow絕緣膜形成技術之多層配線工程之一例。 以下，參與圖1及圖2，說明本發明之半導體裝置之 製造方法有關之層間絕緣膜形成工程採用Re flow絕緣膜 形成技術之多層配線工程之一例。 首先，如圖2 (a)所示在半導體基板（通常，矽晶 片）3 0上之絕緣膜3 1上將下層配線用之第1配線材料 (例如鋁）例如以濺射法堆積後，使用照相繪圖技術及反 應性離子蝕刻（R I E )技術實施第1配線材料之成型以 形成下層配線3 2。 其次，將絕緣膜埋進上述下層配線3 2並將絕緣膜堆 積於上述下層配線上以形成層間絕緣膜。 在上述層間絕緣膜之形成工程，於前述卡匣裝載機室 1內之例如石英板上配置前述下層配線形成後之半導體基 板3 0 » 其次使用真空泵（未圖示）將卡匣裝載機室1內設定 爲所定真空狀態，以機械人臂2將前述半導體基板3 0搬 入等子CVD裝置1 0之反應室1 1內。將該等離子 CVD裝置1 〇之反應室1 1內設定爲約3 0 0 °C，將 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） (請先閎讀背面之注意事項再填寫本頁，> •裝· •訂 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（7 ) 1 I 0 • 1 β m 以 上 ( 本 例 中 爲 1 0 0 η m ) 厚 度 之 第 1 絕 緣 1 膜 即 第 1 等 離 子 S i 0 2 膜 3 3 形 成 於 半 導 體 基 板 2 0 上 1 1 全 面 〇 1 I 請 ) 其 次 以 機 械 人 臂 2 f 將 -1 L·, 刖 述 半 導 體 基 板 3 0 白 等 離 子 先 閲 1 | 讀 I 1 C V D 裝 置 之 反 niff 應 室 1 1 內 搬 送 至 減 壓 C V D 裝 置 之 反 應 背 1 1 之 1 室 2 1 內 9 而 白 S i Η 4 氣 體 供 應 源 及 Η 2 〇 2 供 rrbe 應 源 徑 * 1 事 1 S i Η 4 氣 體 供 給 徑 路 2 5 及 Η 2 〇 2 供 給 徑 路 2 6 將 項 再 填 1 S i Η 4 氣 體 及 Η 2 〇 2 導 入 該 減 壓 C V D 裝 置 之 反 應 室 寫 本 袭 頁 1 2 1 內 以 6 5 0 P a 以 下 真 空 中 — 1 0 °C 以 上 + 1 0 1 I °C 以 下 之 溫 度 範 圍 內 ( 例 如 0 °C ) 互 相 反 應 如 圖 2 ( b 1 1 ) 所 示 在 上 述 半 導體 基 板 3 0 上 形 成 具 有 Re f low 形 狀 1 1 之 0 4 β m 以 上 1 1 • 4 β τη 以 下 厚 度 之 Re f low Si〇2 訂 1 膜 3 4 〇 1 I 其 次 如 圖 2 ( C ) 所 示 將 上 述 半 導 體 HJ7» 基 板 3 0 放 置 1 I 於 上 述 減 壓 C V D 裝 置 之 反 應 室 1 1 內 6 5 P a 以 下 真 1 级 空 中 〇 1 I 再 用 機 械 人 臂 2 » 白 減 壓 C V D 裝 置 之 反 gift 應 室 2 1 內 1 將 前 述 半 導 體 基 板 3 0 搬 送 至 等 離 子 C V D 裝 置 之 反 ntf： 應 室 1 1 1 1 內 〇 而 如 圖 2 ( d ) 所 示 放 置 於 等 離 子 C V D 裝 置 1 1 1 0 之 反 應 室 內 3 0 0 °C 以 上 4 5 0 °C 未 滿 高 溫 ( 本 1 例 爲 3 0 0 °c ) 中 1 2 0 秒 以 上 6 0 0 秒 未 Mt m 時 間 ( 本 1 例 爲 1 2 0 秒 ) 〇 I 然 後 如 圖 2 ( e ) 所 示 將 0 . 3 β m 以 上 ( 本 例 1 1 I 爲 3 0 0 η m ) 厚 度 之第 2 絕緣膜 即 第 2 等 離 子 S 1 0 2 1 1 本纸張尺度適用中國國家揉準（CNS)A4規格（210X297公釐）_ 1Λ
~ 1U 經濟部中央梯準局員工消费合作杜印裝 A7 B7 五、發明説明（8 ) 膜35形成於半導體基板30上全面。 而後，自上述半導體製造裝置取出上述半導體基板 3 0，使用別之半導體製造裝置實施4 5 0 °C，3 0分之 爐中退火。 然後，在層間絕緣膜實施開接觸孔或 Beer用之蝕刻 ，堆積上層配線用之第2配線材料後實施成型以形成上層 配線。 兹以圖3表示由上述實施例所得Re flow Si 〇2膜3 4 之成膜後實施4 5 0°C 3 0分之熱處理時，以將等離子 S i 〇2膜（蓋膜）形成於Re flow Si 〇2膜3 4之膜厚及 Re f low Si 〇2膜上時之蓋膜厚爲參數，實測產生裂痕狀況 之結果。 由圖3可知，本實施例所得Re flow Si〇2膜3 4，其 蓋膜不存在時之裂痕特性與先前例相比並不變，惟蓋膜存 在時不產生裂痕之膜厚上限，自先前例之約1. 0#m上 昇至約2. 0#m，提高裂痕耐性· 依上述實施例，多層配線工程中之層間絕緣膜形成工 程採用Re flow絕緣膜形成技術，形成Re flow Si〇2膜 3 4後放置真空中所定時間以上，更在所定高溫中放置所 定時間以上。 即使因而在Re flow 8丨〇2膜3 4之形成工程，絕緣膜 之成膜中產生水份，絕緣膜中含水份，惟控制減低絕緣膜 中之水份，可得裂痕耐性良好之Re flow Si 〇2膜3 4。 由於如上述提髙Re flow Si〇2膜之裂痕耐性，即可確 本紙張尺度適用中國國家揉準（CNS)A4规格（ 210X297公釐）_ ^ I.---------裝-- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央橾準局貝工消費合作社印製 A7 _B7 _ 五、發明説明（9 ) 保考慮Re flow Si〇2膜平坦化所需之膜厚》 故，可提高層間絕緣膜表面平坦化，不致在層間絕緣 膜形成後之上層配線材料堆積時及上層配線之成型時有不 良影響，而可防止因上層配線段部之斷線，短路等重大欠 陷之虞。 又，依上述實施例，以通常之等離子CVD法在Re flow Si 〇2膜上部形成層間絕緣膜時，因充份昇高半導體 晶片之溫度，故不致形成濕蝕刻率遲之絕緣膜，層間絕緣 膜形成後實施之開貫穿孔或Beer孔用之蝕刻中，層間絕 緣膜與Re flow Si 〇2膜之界面，蝕刻形狀不致成爲異常， 亦不致使其後形成之上層配線之敷層惡化，或招致上層配 線之導通不良。 〔發明之效果〕 如上述依本發明之半導體裝置之製造方法，因可提高 多層配線工程中之層間絕緣膜形成工程採用Re flow絕緣 膜形成技術時所得之Re flow Si 〇2膜之裂痕耐性，確保考 慮Re flow Si〇2膜之平坦化所需之膜厚，故可提高層間絕 緣膜之表面平坦性，使形成於層間絕緣膜形成後之上層配 線更微細化。 而且可防止層間絕緣膜‘形成後實施之用貫穿孔或Beer 孔用蝕刻之異常蝕刻*不致使其後形成之上層配線之敷層 惡化，或招致上層配線之導通不良，而可提髙上層配線之 信賴性。 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）_ 19 _ ：.. "~~!~ (請先閲讀背面之注意事項再填寫本頁) -裝- 訂 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（10 ) 圖示之簡單說明： 圖1 :概略表示本發明之半導體裝置之製造方法使用 之半導體製造裝置之一例之構成說明圖。 圖2:表示本發明之半導體裝置之製造方法有關之層 間絕緣膜形成工程採用Re flow絕緣膜形成技術之多層配 線工程之一例之斷面圖。 圖3 :表示就圖1工程所得Re flow Si 〇2膜，以其膜 厚及Re flow Si〇2膜上形成之蓋膜膜厚爲參數實施熱處理 時之裂痕發生狀況予以實測結果之圖。 圖4 :表示就先前之半導體裝置製造時，多層配線工 程中之層間絕緣膜形成工程採用Re flow絕緣膜形成技術 時所得之Re flow Si〇2膜，以其膜厚及Re flow Si〇2膜上 形成之蓋膜膜厚爲參數實施熱處理時之裂痕發生狀況予以 實測結果之圖。 〔·符號說明〕 1…卡匣裝載室，2…機械人臂，1 0…等離子 <：¥0裝置，11、21-反應室（（：1^1^61')，12、 2 2…上部電極（Shower head )，1 3、2 3…下部 電極（Table )，1 4、2 4…排氣口，1 5…處堙氣體 供應徑路，1 6…富周波電力供應徑路，2 0…減壓 CVD裝置，25…SiH4氣體供應徑路，26··. H20 2供應徑路，3 0…半導體基板，3 1…絕緣膜， 本紙張又度適用中國國家橾準（CNS)A4規格（ 210X297公釐）_ 13 _ I- i I I n 111 (請先聞讀背面之注意事項再填寫本頁) A7 B7 312817 五、發明説明（11 ) 3 2…下層配線，3 3…第1等離子S i 0 2膜 Re flow Si〇2膜，3 5 …第 2 等子 S i 02 膜。 3 4 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) -裝. 訂 本紙張尺度適用中國國家標準（CNS)A4規格（ 210X297公釐）_ 14 _

Claims (1)

  1. A8 B8 C8 D8 經濟部中央揉準局貝工消费合作社印製 六、 申請專利範圍 1 1 — 種 半 導 體 裝 置 之 製 造 方 法 » 其 特 徵 爲 具 備 1 將 S i Η 4 氣, 體 及 Η 2 〇 2 導 入 收 容 形 成 m 1 絕 緣 膜 後 之 半.* • 1 導 體 基 板 之 反 應 室 內 將 上 述 S i Η 4 氣 體 及 Η 2 〇 2 於 請 1 6 5 1 0 Ρ a .以 下 真 空 中 — 1 0 °c 以 上 + 1 0 °C 以 下 溫 度 閲 η 1 I 範 圍 內 至 相 反 應 在 半 導 體 基 板 上 形 成 Ref low 形 狀 之 背 τέ 之 1 1 4 注 | 0 β m 以 上 1 1 M m以下厚度之R e f 1 0 w S 0 2 意 事 1 膜 3 4 之 工 程 及 其 後 將 半 導 體 基 板 放 置 於 所 定 真 空 中 項 再 填 3 0 秒 以 上 之 工 程 及 將 半 導 體 基 板 放 置 於 3 0 0 °c 以 上 寫 本 裝 頁 1 > 4 5 0 °c 未 滿 高 溫 中 1 2 0 秒 以 上 6 0 0 秒 未 滿 時 間 1 I 之 工 程 〇 1 1 I 2 如 串 請 專 利 範 圍 第 1 項 所 述 之 半 導 體 裝 置 之 製 造 1 方 法 更 具 備 刖 述 放 置 1 2 0 秒 以 上 6 0 0 秒 未 滿 時 訂 1 間 之 工 程 後 在 -1 -刖 述 Re f low S i 0 2 膜 上 形 成 第 2 絕 緣 膜. 1 1 之 工 程 〇 1 I 3 如 串 請 專 利 範 圍 第 2 項 所 述 之 半 導 體 裝 置 之 製 造 L 方 法 其 中 在 刖 述 第 2 絕 緣 膜 形 成 後 實 施 4 5 0 °c 1 | 3 0 分 之 爐 中 退 火 〇 1 1 4 一 種 半 導 體 Ηαζ. 裝 置 之 製 造 方 法 具 備 將 形 成 配 線 1 1 層 之 半 導 體 基 板 搬 入 等 離 子 C V D 裝 置 中 之 工 程 及 將 1 1 0 • 1 β m 以 上 厚 度 之 第 1 等 離 子 S i 0 2 膜 形 成 於 前 述 1 I 半 導 體 基 板 上 之 工 程 及 白 前 述 等 離 子 C V D 裝 置 將 刖 述 1 半 導 體 基 板 搬 送 至 減 壓 C V D 裝 置 之 工 程 及 將 S i Η 4 1 1 I 氣 體 » 及 Η 2 0 2 導 入 * 刖 述 減 壓 C V D 裝 置 內 使 此 等 1 1 I S 1 Η 4. 氣 體 及 Η 2 〇 2 在 6 5 0 Ρ a 以 下 真 空 中 1 1 本紙張尺度逍用中國國家梂準（CNS ) A4規格（210X297公釐） ~ 15 - ^12817 A8 B8 C8 D8 々、申請專利範圍 一 1 0°C以上+ 1 〇以下之溫度範圍內互相反應，在上述 半導體基板上形成具有Re flow形狀之.0 . 4 以上， 1. 4μιη以下厚度之Re fi〇w S i 〇2膜之工程，及前 述Re flow S i 02膜形成後，將前述半導體基板放置於 前述減壓CVD裝置.中3 0秒鐘之工程，及自前述減壓 C VD裝置將前述半導體基板搬送於前述等離子C VD裝 置之工程，及將前述半導體基板放置3 0 0°C以上， 4 5 0°C末滿溫度中1 2 0秒以上，6 0 0秒未滿時間之 工程。 5. 如申請專利範圍第4項所述之半導體裝置之製造 方法，更具備：前述120秒以上，600秒未滿時間放 置之工程後，在前述Re flow S i 02膜上形成第2等離 子S i 0 2膜。 6. 如申請專利範圍第5項所述之半導體裝置之製造 方法，在前述第2等離子S i 02膜形成後，實施450 °C，3 0分之爐中退火。 11 — — — — 裝 II 訂— 务 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局貞工消费合作社印裝 本紙張尺度逋用中國國家標準（CNS ) A4规格（210X297公釐）
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CN1082721C (zh) 2002-04-10
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DE69522195T2 (de) 2002-04-18
EP0720212B1 (en) 2001-08-16
US5683940A (en) 1997-11-04
US6153542A (en) 2000-11-28
CN1134604A (zh) 1996-10-30
SG42823A1 (en) 1997-10-17
KR0184378B1 (ko) 1999-04-15
JPH08181276A (ja) 1996-07-12
DE69522195D1 (de) 2001-09-20

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