TW201841470A - 半導體裝置及電力轉換裝置 - Google Patents

半導體裝置及電力轉換裝置 Download PDF

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Publication number
TW201841470A
TW201841470A TW106143097A TW106143097A TW201841470A TW 201841470 A TW201841470 A TW 201841470A TW 106143097 A TW106143097 A TW 106143097A TW 106143097 A TW106143097 A TW 106143097A TW 201841470 A TW201841470 A TW 201841470A
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Taiwan
Prior art keywords
electrode
semiconductor device
gate
control
resistance
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TW106143097A
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English (en)
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小嶋勇介
橫井芳彦
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日商瑞薩電子股份有限公司
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Publication of TW201841470A publication Critical patent/TW201841470A/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/168—Modifications for eliminating interference voltages or currents in composite switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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    • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08148—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in composite switches
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    • H01L21/8232—Field-effect technology
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    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
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    • H03K2217/0081—Power supply means, e.g. to the switch driver

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Conversion In General (AREA)
  • Inverter Devices (AREA)
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Abstract

本發明提供一種不使閘極驅動電路複雜化且不使開關延遲增大而能夠抑制斷開時產生突波電壓之半導體裝置。 半導體裝置10具有以下構成：藉由具備用以控制於第1主電極DE與第2主電極SE之間流動之電流之複數個控制電極GE1、GE2、GE3，等效地將複數個電晶體Q1、Q2、Q3並列連接。而且，來自共通之控制端子GT之控制信號之傳輸路徑之電阻值依每一控制電極GE1、GE2、GE3而不同。

Description

半導體裝置及電力轉換裝置
本發明係關於一種半導體裝置，該半導體裝置例如可較佳用作電力轉換裝置等中之開關元件。
於電力轉換裝置或雙向開關等中使用之半導體開關元件中，重要的是抑制斷開時之突波電壓而不使開關延遲增大。 例如於日本專利特開平10-075164號公報(專利文獻1)中，揭示有使半導體開關裝置之閘極驅動電路雙工化之構成。當斷開時，第1閘極驅動電路自斷開初期起動作，第2閘極驅動電路於特定時間後動作。 上述專利文獻1亦揭示有於閘極驅動電路追設斷開初期專用電路之構成作為另一實施形態。斷開初期專用電路於開關電路之共通端子與接地位準之間具有放電路徑。 [先前技術文獻] [專利文獻] [專利文獻1]日本專利特開平10-075164號公報
[發明所欲解決之問題] 於上述專利文獻1所揭示之構成之情形時，設置有2個斷開用電路，故而存在閘極驅動電路之構成變得複雜之問題。其他課題及新穎之特徵自本說明書之記述及隨附圖式當可明瞭。 [解決問題之技術手段] 一實施形態之半導體裝置係將用以控制流動於第1主電極及第2主電極之主電流之控制電極分割為複數個。而且，來自共通之控制端子之控制信號之傳輸路徑之電阻值依經分割之各個控制電極而不同。 [發明效果] 根據上述實施形態，可提供一種能夠抑制斷開時之突波電壓而不使閘極驅動電路複雜化並且不使開關延遲增大之半導體裝置。
以下，參照圖式，對各實施形態進行詳細說明。再者，對相同或相當之部分標註相同參照符號，不重複對其進行說明。 ＜第1實施形態＞ [半導體裝置之概略構成] 圖1係表示根據第1實施形態之半導體裝置之構成之等效電路。參照圖1，半導體裝置10係使N通道MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金屬氧化物半導體場效應電晶體)變化而成者。以下，將MOSFET亦稱為MOS電晶體。 半導體裝置10具備作為第1主電極之汲極電極DE、作為第2主電極之源極電極SE、作為複數個控制電極部之閘極電極部GE1、GE2、GE3、及電阻元件R2、R3。以下，於對閘極電極部GE1、GE2、GE3統稱之情形時或表示不特定者之情形時，記作閘極電極部GE。 等效地，半導體裝置10可認為係3個N通道MOS電晶體Q1、Q2、Q3並列連接而成者。MOS電晶體Q1、Q2、Q3共有汲極電極DE，並且共有源極電極SE。根據供給至MOS電晶體Q1、Q2、Q3之各個閘極電極部GE之閘極控制信號，控制MOS電晶體Q1、Q2、Q3之開關。以下，於對MOS電晶體Q1、Q2、Q3統稱之情形時或表示不特定者之情形時，存在記作MOS電晶體Q之情況。 作為主電流之汲極電流Id於汲極電極DE與源極電極SE之間流動。等效地，汲極電流Id分別對應於複數個閘極電極部GE1、GE2、GE3分流成複數個汲極電流成分Id1、Id2、Id3。根據供給至所對應之各閘極電極部GE之閘極控制信號控制各汲極電流成分Id1、Id2、Id3。實際上，於各閘極電極部GE之附近之通道流動之電流成分由該閘極電極部GE控制。 圖1亦表示有與MOS電晶體Q1、Q2、Q3逆並列(反向偏壓方向並且並列)連接之換流用二極體PD1、PD2、PD3。二極體PD1、PD2、PD3可為由垂直式MOS電晶體構成半導體裝置10之情形時之寄生二極體，亦可為與MOS電晶體Q1、Q2、Q3獨立形成之二極體。 半導體裝置10為了與外部連接，而具備汲極端子DT、源極端子ST、及閘極端子GT。汲極電極DE與汲極端子DT連接，源極電極SE與源極端子ST連接。作為主電流，汲極電流Id自汲極端子DT流至源極端子ST。 對閘極端子GT輸入用以控制汲極電流Id之閘極控制信號。通常，於半導體裝置10之外部之閘極信號輸入端子GIT與閘極端子GT之間連接有電阻元件R1。電阻元件R1與半導體裝置10一併安裝於印刷基板上。藉由調整電阻元件R1之電阻值，可事後調整突波電壓之大小及開關速度。 閘極電極部GE1不經由電阻元件R2、R3而直接與閘極端子GT連接。閘極電極部GE2經由電阻元件R2與閘極電極部GE1連接。閘極電極部GE3經由電阻元件R3與閘極電極部GE2連接。閘極端子GT與閘極電極部GE1之間之電阻值小於電阻元件R2、R3之電阻值中之任一者。因此，閘極電極部GE1、GE2、GE3之各者與閘極端子GT之間之控制信號路徑之電阻值針對每一閘極電極部GE而不同。於圖1之情形時，依照閘極電極部GE1、GE2、GE3之順序，閘極電阻變大。 圖2係圖1之變化例之等效電路。圖2之變化例之半導體裝置10M於如下方面與圖1之半導體裝置10不同：設置有電阻元件R4、R5、R6來代替圖1之電阻元件R2、R3。參照圖2，閘極電極部GE1經由電阻元件R4與閘極端子GT連接。閘極電極部GE2經由電阻元件R5與閘極端子GT連接。閘極電極部GE3經由電阻元件R6與閘極端子GT連接。 此處，電阻元件R6之電阻值係設為大於電阻元件R5之電阻值，電阻元件R5之電阻值係設為大於電阻元件R4之電阻值。如此，閘極電極部GE1、GE2、GE3之各者與閘極端子GT之間之控制信號路徑之電阻值針對每一閘極電極而不同，其等之電阻值之關係與圖1之情形時相同。然而，關於電阻元件所占之面積，圖2之情形時較大。即，圖1之構成具有能夠削減電阻元件所需之面積之優點。 圖2之其他方面係與圖1相同，故而對相同或相當部分標註相同參照符號，不重複進行說明。 [半導體裝置之動作] 其次，對圖1之半導體裝置10之斷開時之動作進行說明。首先，對先前之半導體開關元件之斷開時之問題進行說明。 一般而言，因存在於半導體電路之配線等之電感L，於半導體開關元件之斷開時，根據暫態流過半導體開關元件之電流i之變化率di/dt產生突波電壓L･(di/dt)。突波電壓成為半導體電路之故障之原因。若於閘極電極連接相對較大之閘極電阻，則能夠充分地抑制突波電壓，但若如此，由於該較大之閘極電阻，會使半導體開關元件之開關發生明顯延遲。如以下所說明般，本實施形態之半導體裝置10能夠抑制突波電壓並且亦抑制因閘極電阻引起之延遲量之增大。 圖3係表示圖1之半導體裝置之動作之時序圖。圖3中自上而下依序表示有閘極信號輸入端子GIT中之閘極輸入電壓Vin、閘極電極部GE1、GE2、GE3中之閘極電壓Vg1、Vg2、Vg3、汲極電流Id、及汲極電壓Vd。 參照圖1及圖3，於時刻t0，閘極輸入電壓Vin自高位準變化成低位準作為閘極控制信號。閘極控制信號經由電阻元件R1到達閘極電極部GE1，經由電阻元件R1、R2到達閘極電極部GE2，經由電阻元件R1、R2、R3到達閘極電極部GE3。圖1之等效電路中之流至MOS電晶體Q1、Q2、Q3之各者之汲極電流成分Id1、Id2、Id3係將整體之汲極電流Id分流而成者，故而其大小小於整體之汲極電流Id。 進而，藉由使各MOS電晶體Q1、Q2、Q3之閘極電阻之值不同而使信號之延遲量不同，故而閘極電壓Vg1、Vg2、Vg3變化之時序錯開。具體而言，於圖3之情形時，閘極電阻最小之MOS電晶體Q1於時刻t1開始斷路。閘極電阻第二小之MOS電晶體Q2於下一時刻t2開始斷路。閘極電阻最大之MOS電晶體Q3於下一時刻t3開始斷路。 如上所述，本實施形態之半導體裝置具有藉由將閘極電極分割成複數個，等效地將複數個MOS電晶體Q並列連接之構成。藉此，將汲極電流Id分流而成之電流成分流至各個MOS電晶體Q，故而能夠減小流至各個MOSFET之汲極電流成分。進而，藉由使各閘極電極部GE之閘極電阻之大小不同，各個MOS電晶體Q斷路之時序錯開。藉此，即便加快斷路速度，亦能夠減小電流i之變化率di/dt，故而能夠抑制突波之峰值電壓。又，能夠使各閘極電極部GE之閘極電阻之大小小於先前之單一之閘極電阻之情形時，故而各MOS電晶體Q之閘極電壓Vg下降至臨限值電壓之前之閘極電荷放電時間縮短。其結果，能夠縮短半導體裝置10整體之斷路時間。 [半導體裝置之具體構造] 以下，對採用垂直式構造之溝槽式閘極型MOSFET作為半導體裝置10之例進行說明。藉由使用垂直式構造之MOSFET，幾乎無需對先前之構造進行變更即可實現圖1之構成之半導體裝置10。 圖4係表示與圖1之等效電路對應之半導體裝置之構造之一例之俯視圖。圖5係沿圖4之切斷線V-V之剖視圖。圖6係沿圖4之切斷線VI-VI之剖視圖。於以下之說明中，將平行於半導體基板SUB之方向設為X方向及Y方向，將垂直於半導體基板SUB之方向設為Z方向。再者，圖4中未圖示層間絕緣層21及閘極絕緣膜23。又，為了易於圖解，圖4～圖6之各部之尺寸與實際之尺寸非為比例關係。 參照圖4～圖6，半導體裝置10主要以N型半導體基板SUB為基礎而形成。N型半導體基板SUB具有將用作N+ 型汲極層27之N+ 型半導體層及用作N- 型漂移層26之N- 型半導體層積層而成之雙層構造。於以下之說明中，將N型半導體基板SUB之+Z方向側之面稱為第1主面33或表面(前面)，將-Z方向側之面稱為第2主面34或背面。N+ 型半導體層為第2主面34側，N- 型半導體層為第1主面33側。 如圖5所示，半導體裝置10自靠近N型半導體基板SUB之第1主面33之側起包含N+ 型源極層24及P型基極層25作為形成於N- 型漂移層26之雜質層。再者，P型基極層25之周邊部未由N+ 型源極層24覆蓋。於該P型基極層25之周邊部之上，介隔閘極絕緣膜23而形成有外周閘極電極12。 於半導體裝置10，形成自第1主面33貫通N+ 型源極層24及P型基極層25直至N- 型漂移層26之內部之複數個溝槽(槽)30。俯視半導體基板SUB，複數個溝槽30於Y方向延伸，於X方向排列配置。於包含各溝槽30之內表面在內之半導體基板SUB之第1主面33之整面形成閘極絕緣膜23。介隔閘極絕緣膜23而形成亦填充於各溝槽30之內部之閘極電極即溝槽式閘極電極12A～12F。閘極電極12A～12F於Y方向延伸。 溝槽式閘極電極12A、12B與圖1之閘極電極部GE1對應地，經由下述之金屬閘極配線11A相互電性連接。同樣地，溝槽式閘極電極12C、12D與圖1之閘極電極部GE2對應地，經由下述之金屬閘極配線11B相互電性連接。溝槽式閘極電極12E、12F與圖1之閘極電極部GE3對應地，經由下述之金屬閘極配線11C相互電性連接。 如此，各閘極電極部GE由相互電性連接之複數個電極元件構成。各電極元件對應於溝槽式閘極電極12A～12F各者。複數個電極元件間之電阻值小於圖1之電阻元件R2、R3中之任一者之電阻值。 半導體裝置10進而包含上述外周閘極電極12、層間絕緣層21及電阻層18、19。 電阻層18以連接閘極電極12B之端部與閘極電極12C之端部之間之方式，例如由多晶矽形成。電阻層19以連接閘極電極12D之端部與閘極電極12E之端部之間之方式，例如由多晶矽形成。電阻層18對應於圖1之電阻元件R2，電阻層19對應於圖1之電阻元件R3。 層間絕緣層21以覆蓋閘極電極12A～12F、電阻層18、19及外周閘極電極12之方式，形成於閘極絕緣膜23上。 半導體裝置10進而包含金屬源極電極16、金屬汲極電極29、金屬閘極配線11A、11B、11C、及閘極墊11P。金屬閘極配線11A與閘極墊11P係一體形成。以下，於將金屬閘極配線11A、11B、11C統稱之情形時或表示不特定者之情形時，記作金屬閘極配線11。 金屬源極電極16形成於層間絕緣層21之上，經由複數個接觸電極17與N+ 型源極層24及P型基極層25連接。該等接觸電極17配置於相鄰之溝槽30之間及配置於最端部之溝槽30之外側。各接觸電極17貫通層間絕緣層21、閘極絕緣膜23、及N+ 型源極層24到達P型基極層25之內部。金屬源極電極16對應於圖1之源極電極SE。 金屬汲極電極29與半導體基板SUB之背面側之N+ 型汲極層27相接而形成。金屬汲極電極29對應於圖1之汲極電極DE。 金屬閘極配線11A大致於X方向延伸，分別經由接觸電極15A、15B與閘極電極12A、12B之端部連接。金屬閘極配線11A係與閘極墊11P一體形成。閘極墊11P進而經由接觸電極14與外周閘極電極12連接。 金屬閘極配線11B於X方向延伸，分別經由接觸電極15C、15D與閘極電極12C、12D之端部連接。金屬閘極配線11C於X方向延伸，分別經由接觸電極15E、15F與閘極電極12E、12F之端部連接。因此，金屬閘極配線11A與金屬閘極配線11B經由電阻層18連接，金屬閘極配線11B與金屬閘極配線11C經由電阻層19連接。 以下，將上述半導體裝置10之構成之特徵與先前構成之情形時進行比較而進行說明。於先前之溝槽式閘極型MOSFET中，複數個溝槽式閘極電極12A～12F之端部經由共通之金屬閘極配線11相互連接。與此相對，於本實施形態之半導體裝置10中，將金屬閘極配線11分割成複數個，相鄰之金屬閘極配線彼此經由電阻層18或19連接。藉此，能夠實現如下圖1之等效電路之構成：複數個溝槽式閘極電極12A～12F分割成分別對應於複數個閘極電極部GE之複數個組，並且相鄰之閘極電極部GE之間由對應於電阻元件R之電阻層連接。再者，於垂直式MOSFET之構造之情形時，汲極電流於各溝槽式閘極電極12A～12F之附近之通道區域流動，故而汲極電流必然分流成分別對應於複數個閘極電極部GE之複數個電流成分。圖4～圖6之其他方面係與先前構成之情形時相同。因此，能夠幾乎不對先前之製造製程進行變更地製造本實施形態之半導體裝置10。 [半導體裝置之製造方法] 以下，對本實施形態之半導體裝置10之製造方法之一例進行簡單說明。 圖7係表示圖4～圖6所示之半導體裝置之製造方法之一例之流程圖。參照圖4～圖7，首先準備單晶矽之N型矽半導體基板SUB(圖7之步驟S101)。 然後，自N型半導體基板SUB之第1主面33側形成溝槽30(步驟S102)。具體而言，使用微影步驟，於第1主面33上形成溝槽形成用硬質遮罩膜，利用該硬質遮罩膜進行各向異性乾式蝕刻，藉此形成溝槽30。於溝槽30形成後，藉由濕式蝕刻將硬質遮罩膜去除。 然後，例如藉由熱氧化，於N型半導體基板SUB之第1主面33及溝槽30之內面之大致整個面形成閘極絕緣膜23(步驟S103)。 然後，以將溝槽30掩埋之方式，於閘極絕緣膜23上之大致整個面，例如藉由CVD(Chemical Vapor Deposition，化學氣相沈積)等形成例如摻磷之摻雜多晶矽(Doped Poly-Silicon)膜。閘極電極12A～12F及外周閘極電極12以外之無用之部分之摻雜多晶矽膜例如藉由濕式蝕刻而去除。藉此，形成閘極電極12A～12F及外周閘極電極12(步驟S104)。 然後，於半導體基板SUB之第1主面33側之大致整個面形成多晶矽膜。藉由對所形成之多晶矽膜中之成為電阻層18、19之部分離子佈植雜質而電阻化。其後，例如藉由濕式蝕刻將電阻層18、19以外之部分之多晶矽膜去除。形成電阻層18、19(步驟S105)。 然後，將使用微影步驟而形成之抗蝕膜作為遮罩，離子佈植P型雜質。其後，藉由熱擴散形成P型基極層25(步驟S106)。藉由灰化等將無用之抗蝕膜去除。 然後，將使用微影步驟而形成之抗蝕膜作為遮罩，離子佈植N型雜質。藉此，於P型基極層25之上部區域形成N+ 型源極層24(步驟S107)。藉由灰化等將無用之抗蝕膜去除。 然後，於N- 型半導體基板SUB之第1主面33側之大致整個面，藉由CVD或塗佈等形成層間絕緣層21(步驟S108)。作為層間絕緣層21之材料，例如可使用PSG(phosphsilicate Glass，磷矽玻璃)膜、BPSG(Borophosphsilicate Glass，硼磷矽玻璃)膜、NSG(Non-doped Silicate Glass，非摻雜矽玻璃)膜、SOG(Spin-On-Glass，旋塗玻璃)膜或其等之複合膜等。 然後，於相鄰之溝槽30之間及配置於最端部之溝槽30之外側形成用於與金屬源極電極16連接之接觸槽31(步驟S109)。具體而言，例如將使用微影步驟而形成之抗蝕膜作為遮罩，藉由各向異性乾式蝕刻等形成接觸槽31。藉由灰化等將無用之抗蝕膜去除。 然後，於閘極電極12A～12F之端部形成用於與金屬閘極配線11A～11C之連接之接觸孔，並且於外周閘極電極12之上部形成用於與閘極墊11P之連接之接觸槽(步驟S110)。具體而言，例如將使用微影步驟而形成之抗蝕膜作為遮罩，藉由各向異性乾式蝕刻等形成接觸孔等。藉由灰化等將無用之抗蝕膜去除。 然後，於N型半導體基板SUB之第1主面33側之大致整個面，藉由濺鍍成膜等形成鋁系金屬厚膜。繼而，藉由使用微影步驟及蝕刻對金屬厚膜進行蝕刻，形成閘極墊11P、金屬閘極配線11A～11C、金屬源極電極16、及接觸電極17、15A～15F、14(步驟S111)。 然後，藉由對N型半導體基板SUB之第2主面34(背面)進行磨削，調整基板之厚度(步驟S112)。 然後，於N型半導體基板SUB之第2主面34之大致整個面，藉由濺鍍成膜等形成金屬汲極電極29(步驟S113)。藉由以上步驟，完成圖4～圖6之構成之半導體裝置10。 [效果] 如上所述，本實施形態之半導體裝置10以MOSFET為基礎而構成，具有藉由將閘極電極部GE分割成複數個，等效地將複數個MOSFET並列連接之構成。進而，本實施形態之半導體裝置10具有如下特徵：並列連接之各MOSFET之閘極電阻之值不同。藉此，於斷開時能夠使各MOSFET斷路之時序錯開，故而能夠於容許之突波電壓之範圍內，加快各個MOSFET之斷路速度(具體而言，係增大電流變化率di/dt)。其結果，能夠縮短複數個MOSFET整體上之斷路時間。 又，外部連接端子與先前之MOSFET同樣地由閘極端子GT、源極端子ST、及汲極端子DT之3端子構成，故而可直接使用既存之閘極驅動電路而實現抑制突波電壓及防止斷路速度之降低之效果。藉由抑制突波電壓，無需過度確保構成系統之零件之電壓裕度，故而能夠降低零件成本。 [變化例] 於第1實施形態中，係對將閘極電極部GE分割成3個之例進行了說明，但閘極電極部GE之分割個數並不限於3個。 一般而言，半導體裝置具備N個(N為2以上之整數)閘極電極部GE及N－1個電阻元件R。該情形時，半導體裝置具有等效地將分別具有N個閘極電極部GE之N個電晶體並列連接之構成。而且，第1個閘極電極部GE不經由N－1個電阻元件R中之任一者與閘極控制信號接收用閘極端子GT連接。第i＋1個(i為1以上且N－1以下之整數)閘極電極部GE經由第i個電阻元件R與第i個閘極電極部GE連接。藉此，針對每一閘極電極部GE，來自閘極端子GT之閘極控制信號之傳輸路徑之電阻值不同。 進而，於上述之一般構成中，針對各閘極電極部GE由於第1方向延伸並且於第2方向排列配置之複數個電極元件(例如溝槽式閘極電極)構成之情形進行說明。該情形時，若將N個閘極電極部GE於第2方向依照編號順序排列，則於第i個(i為1以上且N－1以下之整數)閘極電極所包含之複數個電極元件中之第2方向之排列順序之最後的電極元件、與第i＋1個閘極電極所包含之複數個電極元件中之第2方向之排列順序之最前的電極元件之間連接第i個電阻元件。 於第1實施形態中，對構成各閘極電極部GE之複數個電極元件各者由溝槽式閘極構成之情形進行了說明，但各電極元件亦可為平面型閘極電極構造。進而，於第1實施形態中，對垂直式MOSFET之情形進行了說明，但於橫式MOSFET之情形亦可應用上述所說明之技術。 於第1實施形態中，對閘極電阻之值依每一經分割之閘極電極部GE而不同之情形進行了說明，但更一般而言，只要各閘極電極部GE之電容與閘極電阻之值之積不同即可。例如藉由變更閘極寬度(具體而言為所包含之溝槽式閘極之個數)，可改變每一閘極電極部GE之電容。 ＜第2實施形態＞ 於第2實施形態中，對以IGBT(Insulated Gate Bipolar Transistor，絕緣閘雙極性電晶體) 為基礎而構成半導體裝置之例進行說明。於第1實施形態中說明之技術並不限於以下所說明之IGBT，可應用於各種電晶體。 圖8係表示根據第2實施形態之半導體裝置之構成之等效電路。參照圖8，半導體裝置40係以IGBT為基礎而構成，具備作為第1主電極之集極電極CE、作為第2主電極之射極電極EE、作為複數個控制電極之閘極電極部GE1、GE2、GE3、電阻元件R2、R3、及二極體D。 與圖1相比，於圖8之情形時，設置有集極電極CE代替汲極電極DE，設置有射極電極EE代替源極電極SE。等效而言，可認為半導體裝置40係將3個IGBTQ11、Q12、Q13並列連接而成者。該情形時，作為主電流之集極電流Ic分別對應於複數個閘極電極部GE1、GE2、GE3而分流成複數個集極電流成分Ic1、Ic2、Ic3。 半導體裝置40為了與外部連接，而具備集極端子CT、射極端子ET、及閘極端子GT。集極端子CT與集極電極CE連接，射極端子ET與射極電極EE連接。閘極端子GT直接連接於閘極電極部GE1，並且經由電阻元件R2與閘極電極部GE2連接。進而，閘極電極部GE2經由電阻元件R3與閘極電極部GE3連接。 於IGBT之情形時，因原理上並無寄生二極體，故而電流換流用二極體D於反向偏壓方向連接於集極端子CT與射極端子ET之間，即，二極體D之陽極連接於射極端子ET。圖8中表示二極體D內置於半導體裝置40之情形，但二極體D亦可安裝於半導體裝置40之外部。 圖8之其他方面係與圖1之情形時相同，故而對相同或相當之部分標註相同參照符號，不重複進行說明。其次，對半導體裝置40之具體構造進行說明。 圖9係表示與圖8之等效電路對應之半導體裝置之構造之一例之俯視圖。圖10係沿圖9之切斷線X-X之剖視圖。圖11係沿圖9之切斷線XI-XI之剖視圖。於以下之說明中，將平行於N- 型半導體基板SUB之方向設為X方向及Y方向，將垂直於N- 型半導體基板SUB之方向設為Z方向。再者，圖9中並未圖示有層間絕緣層51及閘極絕緣膜53。又，為了使圖解變得容易，圖9～圖11之各部之尺寸與實際之尺寸並不存在比例關係。 參照圖9～圖11，半導體裝置40主要以用作N- 型漂移層56之N- 型半導體基板SUB為基礎而形成。於以下之說明中，將N- 型半導體基板SUB之+Z方向側之面稱為第1主面63或表面(前面)，將-Z方向側之面稱為第2主面64或背面。 如圖10所示，半導體裝置40自N- 型半導體基板SUB之靠近第1主面63之側起包含N+ 型射極層54及P型基極層55作為雜質層，自靠近第2主面64之側起包含P+ 型集極層58及N+ 型場停止層57。與圖4～圖6中所說明之MOSFET之情形時相比，構造上之不同在於如下方面：於N- 型半導體基板SUB之第2主面64之最表面進而形成有P+ 型集極層58作為雜質層。 再者，P型基極層55之周邊部未由N+ 型射極層54覆蓋。於該P型基極層55之周邊部之上，介隔閘極絕緣膜53地形成有外周閘極電極42。 於半導體裝置40，形成有自第1主面63貫通N+ 型射極層54及P型基極層55直至N- 型漂移層56之內部之複數個溝槽(槽)60。俯視N- 型半導體基板SUB，複數個溝槽60於Y方向延伸，於X方向排列配置。半導體裝置40包含：閘極絕緣膜53，其形成於各溝槽60之內表面；及作為嵌入電極之溝槽式閘極電極42A～42F，其等介隔閘極絕緣膜53地填充至各溝槽60之內部。 溝槽式閘極電極42A、42B經由下述金屬閘極配線41A相互電性連接，與圖8之閘極電極部GE1相對應。同樣地，溝槽式閘極電極42C、42D經由下述金屬閘極配線41B相互電性連接，與圖8之閘極電極部GE2相對應。溝槽式閘極電極42E、42F經由下述金屬閘極配線41C相互電性連接，與圖8之閘極電極部GE3相對應。 如此，各閘極電極部GE由相互電性連接之複數個電極元件構成。各電極元件對應於溝槽式閘極電極42A～42F之各者。複數個電極元件間之電阻值小於圖8之電阻元件R2、R3中之任一者之電阻值。 半導體裝置40進而包含上述外周閘極電極42、層間絕緣層51及電阻層48、49。 外周閘極電極42及電阻層48、49形成於閘極絕緣膜53之上。電阻層48以連接溝槽式閘極電極42B之端部與溝槽式閘極電極42C之端部之間之方式，例如由多晶矽形成。電阻層49以連接溝槽式閘極電極42D之端部與溝槽式閘極電極42E之端部之間之方式，例如由多晶矽形成。電阻層48對應於圖8之電阻元件R2，電阻層49對應於圖8之電阻元件R3。 層間絕緣層51以覆蓋溝槽式閘極電極42A～42F、電阻層48、49及外周閘極電極42之方式，形成於閘極絕緣膜53上。 半導體裝置40進而包含金屬射極電極46、金屬集極電極59、金屬閘極配線41A、41B、41C、及閘極墊41P。金屬閘極配線41A與閘極墊41P係一體形成。 金屬射極電極46形成於層間絕緣層51之上，經由複數個接觸電極47與N+ 型射極層54及P型基極層55連接。該等接觸電極47配置於相鄰之溝槽60之間及配置於最端部之溝槽60之外側。各接觸電極47貫通層間絕緣層51、閘極絕緣膜53、及N+ 型射極層54到達P型基極層55之內部。金屬射極電極46對應於圖8之射極電極EE。 金屬集極電極59與N- 型半導體基板SUB之背面側之P+ 型集極層58相接而形成。金屬集極電極59對應於圖8之集極電極CE。 金屬閘極配線41A大致於X方向延伸，分別經由接觸電極45A、45B與閘極電極42A、42B之端部連接。金屬閘極配線41A係與閘極墊41P一體形成。閘極墊41P經由接觸電極44與閘極電極42連接。 金屬閘極配線41B於X方向延伸，分別經由接觸電極45C、45D與閘極電極42C、42D之端部連接。金屬閘極配線41C於X方向延伸，分別經由接觸電極45E、45F與閘極電極42E、42F之端部連接。因此，金屬閘極配線41A與金屬閘極配線41B經由電阻層48連接，金屬閘極配線41B與金屬閘極配線41C經由電阻層49連接。 與第1實施形態之MOSFET之情形時同樣地，電阻層48、49以外之半導體裝置40之構成係與先前之溝槽式閘極型之IGBT相同。因此，能夠幾乎不對先前之製造製程進行變更地製造本實施形態之半導體裝置40。 再者，於上述實施形態中，對構成各閘極電極部GE之複數個電極元件之各者由溝槽式閘極構成之情形時進行了說明，但各電極元件亦可為平面型閘極電極構造。 如此，本實施形態之半導體裝置40以IGBT為基礎而構成，具有藉由將閘極電極部GE分割成複數個，等效地將複數個IGBT並列連接之構成。進而，本實施形態之半導體裝置40具有如下特徵：並列連接之各IGBT之閘極電阻之值不同。藉此，於斷開時能夠使各IGBT斷路之時序錯開，故而能夠於容許之突波電壓之範圍內，加快各個IGBT之斷路速度(具體而言，係增大電流變化率di/dt)。其結果，能夠縮短構成半導體裝置40之複數個IGBT整體上之斷路時間。又，外部連接端子與先前之IGBT同樣地由閘極端子GT、射極端子ET、及集極端子CT之3端子構成，故而可直接使用既存之閘極驅動電路而實現抑制突波電壓及防止斷路速度降低之效果。 再者，於第2實施形態中，對針對每一經分割之閘極電極部GE，閘極電阻之值不同之情形時進行了說明，但更普遍而言，只要使各閘極電極部GE之電容與閘極電阻之值之積不同即可。例如藉由變更閘極寬度(具體而言，係所包含之溝槽式閘極之個數)，能夠改變每一閘極電極部GE之電容。 ＜第3實施形態＞ 於第3實施形態中，對將第1實施形態之半導體裝置10用作雙向開關之例進行說明。第2實施形態之半導體裝置40亦同樣地可用作本實施形態之雙向開關。 圖12係表示於充電電池組中使用之雙向開關之例之電路圖。參照圖12，充電電池組70具備雙向開關75、電池(充電電池)72及控制IC(Integrated Circuit，積體電路)73。控制IC73控制雙向開關75之開關，或監視電池72之剩餘量。 雙向開關75具備：半導體裝置10，其作為放電用MOSFET；及半導體裝置71，其與該半導體裝置10反向串列連接，作為充電用MOSFET。 半導體裝置10具有與於第1實施形態中所說明者相同之構成。半導體裝置10之閘極端子GT經由電阻元件R1與控制IC73連接。半導體裝置71具有與先前之MOSFET相同之構造。半導體裝置71之閘極電極部GE71直接連接於閘極端子GT71，閘極端子GT71經由電阻元件R71與控制IC73連接。 於用作放電用之半導體裝置10中，汲極端子DT連接於電池72側，源極端子ST連接於系統側之端子74。於用作充電用之半導體裝置71中，汲極端子DT71連接於端子74側，源極端子ST71連接於電池72。半導體裝置10與半導體裝置71亦可相反順序地連接。 於充電時，根據控制IC73之控制，構成半導體裝置10之MOSFET變成斷開狀態，構成半導體裝置71之MOSFET變成接通狀態。藉此，充電電流通過半導體裝置10之寄生二極體及半導體裝置71之MOSFET自系統側之電源流至電池72。 另一方面，於放電時，根據控制IC73之控制，構成半導體裝置10之MOSFET變成接通狀態，構成半導體裝置71之MOSFET變成斷開狀態。藉此，放電電流通過半導體裝置10之MOSFET及半導體裝置71之寄生二極體PD71自電池72流至系統側。 於因系統之故障等而檢測到過電流之情形時，需要將構成半導體裝置10之MOSFET高速斷開。該情形時，因於充電電池組70之電路內及電池72之胞內存在寄生電感，故而由於因MOSFET之斷開引起之電流斷路，產生突波電壓。 此處，如於第1實施形態中所說明般，半導體裝置10具有藉由將閘極電極部GE分割成複數個，而等效地將複數個MOSFET並列連接之構成。進而，半導體裝置10具有如下特徵：並列連接之各MOSFET之閘極電阻之值不同。藉此，於斷開時能夠使各MOSFET斷路之時序錯開，故而能夠將突波電壓抑制為容許範圍內，並且縮短斷路時間。 ＜第4實施形態＞ 於第4實施形態中，對將第1實施形態之半導體裝置10應用於反相器裝置之開關元件之例進行說明。第1實施形態之半導體裝置10及第2實施形態之半導體裝置40並不限於反相器裝置，可用作各種電力轉換裝置之開關元件。 圖13係表示反相器裝置之構成之電路圖。參照圖13，反相器裝置80具備半導體裝置10UP、10UN、10VP、10VN、10WP、10WN、及分別驅動該等半導體裝置之閘極驅動器GD_UP、GD_UN、GD_VP、GD_VN、GD_WP、GD_WN。再者，反相器裝置80亦可構成為各半導體裝置安裝至同一封裝體而成之電源模塊。 半導體裝置10UP與半導體裝置10UN串列連接於高電壓側電源線81P與低電壓側電源線81N之間。對高電壓側電源線81P與低電壓側電源線81N之間施加直流電壓。同樣地，半導體裝置10VP與半導體裝置10VN串列連接於高電壓側電源線81P與低電壓側電源線81N之間。半導體裝置10WP與半導體裝置10WN串列連接於高電壓側電源線81P與低電壓側電源線81N之間。再者，各半導體裝置之汲極端子DT連接於高電壓側，源極端子ST連接於低電壓側。 U相交流電壓自半導體裝置10UP與半導體裝置10UN之連接節點82U供給至馬達83。V相交流電壓自半導體裝置10VP與半導體裝置10VN之連接節點82V供給至馬達83。W相交流電壓自半導體裝置10WP與半導體裝置10WN之連接節點82W供給至馬達83。 於圖13之構成之情形時，因存在於馬達83之定子繞線及反相器裝置80之配線等之電感，於各半導體裝置之開關時產生突波電壓。於本實施形態之反相器裝置80之情形時，如於第1實施形態中所說明般，各半導體裝置具有藉由將閘極電極部GE分割成複數個，而等效地將複數個MOSFET並列連接之構成。進而，各半導體裝置具有如下特徵：並列連接之各MOSFET之閘極電阻之值不同。藉此，能夠使構成各半導體裝置之MOSFET開關之時序錯開，故而能夠將突波電壓抑制為容許範圍內，並且進行高速開關。 以上，基於實施形態，對由本發明者所完成之發明進行了具體說明，但本發明並不限定於上述實施形態，當然可於不脫離其主旨之範圍內進行各種變更。
10‧‧‧半導體裝置
10M‧‧‧半導體裝置
10UN‧‧‧半導體裝置
10UP‧‧‧半導體裝置
10VN‧‧‧半導體裝置
10VP‧‧‧半導體裝置
10WN‧‧‧半導體裝置
10WP‧‧‧半導體裝置
11‧‧‧金屬閘極配線
11A‧‧‧金屬閘極配線
11B‧‧‧金屬閘極配線
11C‧‧‧金屬閘極配線
11P‧‧‧閘極墊
12‧‧‧外周閘極電極
12A‧‧‧溝槽式閘極(電極元件)
12B‧‧‧溝槽式閘極(電極元件)
12C‧‧‧溝槽式閘極(電極元件)
12D‧‧‧溝槽式閘極(電極元件)
12E‧‧‧溝槽式閘極(電極元件)
12F‧‧‧溝槽式閘極(電極元件)
14‧‧‧接觸電極
15A‧‧‧接觸電極
15B‧‧‧接觸電極
15C‧‧‧接觸電極
15D‧‧‧接觸電極
15E‧‧‧接觸電極
15F‧‧‧接觸電極
16‧‧‧金屬源極電極
17‧‧‧接觸電極
18‧‧‧電阻層
19‧‧‧電阻層
21‧‧‧層間絕緣層
23‧‧‧閘極絕緣膜
24‧‧‧N+型源極層
25‧‧‧P型基極層
26‧‧‧N-型漂移層
27‧‧‧N+型汲極層
29‧‧‧金屬汲極電極
30‧‧‧溝槽
31‧‧‧接觸槽
33‧‧‧第1主面
34‧‧‧第2主面
40‧‧‧半導體裝置
41A‧‧‧金屬閘極配線
41B‧‧‧金屬閘極配線
41C‧‧‧金屬閘極配線
41P‧‧‧閘極墊
42‧‧‧外周閘極電極
42A‧‧‧溝槽式閘極(電極元件)
42B‧‧‧溝槽式閘極(電極元件)
42C‧‧‧溝槽式閘極(電極元件)
42D‧‧‧溝槽式閘極(電極元件)
42E‧‧‧溝槽式閘極(電極元件)
42F‧‧‧溝槽式閘極(電極元件)
44‧‧‧接觸電極
45A‧‧‧接觸電極
45B‧‧‧接觸電極
45C‧‧‧接觸電極
45D‧‧‧接觸電極
45E‧‧‧接觸電極
45F‧‧‧接觸電極
46‧‧‧金屬射極電極
47‧‧‧接觸電極
48‧‧‧電阻層
49‧‧‧電阻層
51‧‧‧層間絕緣層
53‧‧‧閘極絕緣膜
54‧‧‧N+型射極層
55‧‧‧P型基極層
56‧‧‧N-型漂移層
57‧‧‧N+型場停止層
58‧‧‧P+型集極層
59‧‧‧金屬集極電極
60‧‧‧溝槽
63‧‧‧第1主面
64‧‧‧第2主面
70‧‧‧充電電池組
71‧‧‧半導體裝置
72‧‧‧電池
73‧‧‧控制IC
74‧‧‧端子
75‧‧‧雙向開關
80‧‧‧反相器裝置
81N‧‧‧低電壓側電源線
81P‧‧‧高電壓側電源線
82U‧‧‧連接節點
82V‧‧‧連接節點
82W‧‧‧連接節點
83‧‧‧馬達
CE‧‧‧集極電極
CT‧‧‧集極端子
D‧‧‧二極體
DE‧‧‧汲極電極
DT‧‧‧汲極端子
DT71‧‧‧汲極端子
EE‧‧‧射極電極
ET‧‧‧射極端子
GD_UN‧‧‧閘極驅動器
GD_UP‧‧‧閘極驅動器
GD_VN‧‧‧閘極驅動器
GD_VP‧‧‧閘極驅動器
GD_WN‧‧‧閘極驅動器
GD_WP‧‧‧閘極驅動器
GE1‧‧‧閘極電極
GE2‧‧‧閘極電極
GE3‧‧‧閘極電極
GE71‧‧‧閘極電極部
GIT‧‧‧閘極信號輸入端子
GT‧‧‧閘極端子
GT71‧‧‧閘極端子
Ic‧‧‧集極電流
Ic1‧‧‧集極電流成分
Ic2‧‧‧集極電流成分
Ic3‧‧‧集極電流成分
Id‧‧‧汲極電流
Id1‧‧‧汲極電流成分
Id2‧‧‧汲極電流成分
Id3‧‧‧汲極電流成分
PD1‧‧‧二極體
PD2‧‧‧二極體
PD3‧‧‧二極體
PD71‧‧‧寄生二極體
Q1‧‧‧MOS電晶體
Q11‧‧‧IGBT電晶體
Q12‧‧‧IGBT電晶體
Q13‧‧‧IGBT電晶體
Q2‧‧‧MOS電晶體
Q3‧‧‧MOS電晶體
R1‧‧‧電阻元件
R2‧‧‧電阻元件
R3‧‧‧電阻元件
R4‧‧‧電阻元件
R5‧‧‧電阻元件
R6‧‧‧電阻元件
R71‧‧‧電阻元件
S101‧‧‧步驟
S102‧‧‧步驟
S103‧‧‧步驟
S104‧‧‧步驟
S105‧‧‧步驟
S106‧‧‧步驟
S107‧‧‧步驟
S108‧‧‧步驟
S109‧‧‧步驟
S110‧‧‧步驟
S111‧‧‧步驟
S112‧‧‧步驟
S113‧‧‧步驟
SE‧‧‧源極電極
ST‧‧‧源極端子
ST71‧‧‧源極端子
SUB‧‧‧N-型半導體基板
t0‧‧‧時刻
t1‧‧‧時刻
t2‧‧‧時刻
t3‧‧‧時刻
Vd‧‧‧汲極電壓
Vg1‧‧‧閘極電壓
Vg2‧‧‧閘極電壓
Vg3‧‧‧閘極電壓
Vin‧‧‧閘極輸入電壓
X‧‧‧X方向
Y‧‧‧Y方向
Z‧‧‧Z方向
圖1係表示根據第1實施形態之半導體裝置之構成之等效電路。 圖2係圖1之變化例之等效電路。 圖3係表示圖1之半導體裝置之動作之時序圖。 圖4係表示與圖1之等效電路對應之半導體裝置之構造之一例之俯視圖。 圖5係沿圖4之切斷線V-V之剖視圖。 圖6係沿圖4之切斷線VI-VI之剖視圖。 圖7係表示圖4～圖6所示之半導體裝置之製造方法之一例之流程圖。 圖8係表示根據第2實施形態之半導體裝置之構成之等效電路。 圖9係表示與圖8之等效電路對應之半導體裝置之構造之一例之俯視圖。 圖10係沿圖9之切斷線X-X之剖視圖。 圖11係沿圖9之切斷線XI-XI之剖視圖。 圖12係表示於充電電池組使用之雙向開關之例之電路圖。 圖13係表示反相器裝置之構成之電路圖。

Claims (10)

  1. 一種半導體裝置，其具備： 第1主電極； 第2主電極； 複數個控制電極部，其等各自根據控制信號而控制於上述第1主電極與上述第2主電極之間流動之電流；以及 控制端子，其自外部接收上述控制信號；且 該控制電極部之電容與來自上述控制端子之上述控制信號之傳輸路徑之電阻值之積之值依每一上述控制電極部而不同。
  2. 如請求項1之半導體裝置，其中來自上述控制端子之上述控制信號之傳輸路徑之電阻值依每一上述控制電極部而不同。
  3. 如請求項2之半導體裝置，其中上述半導體裝置具備N個(N為2以上之整數)控制電極部作為上述複數個控制電極部， 上述半導體裝置進而具備N－1個電阻元件， 第1個控制電極部不經由上述N－1個電阻元件中之任一者而與上述控制端子連接，且 第i＋1個(i為1以上且N－1以下之整數)控制電極部與第i個控制電極部經由第i個電阻元件連接。
  4. 如請求項3之半導體裝置，其中上述第1主電極設置於基板之第1主面，且 上述第2主電極設置於上述基板之與上述第1主面相反之第2主面。
  5. 如請求項4之半導體裝置，其中各上述控制電極部包含設置於上述基板之上述第1主面側且相互電性連接之複數個電極元件， 上述複數個電極元件各者於沿上述第1主面之第1方向延伸，上述複數個電極元件整體於沿上述第1主面之第2方向並排排列，且 上述複數個電極元件間之電阻值小於上述N－1個電阻元件中之任一者之電阻值。
  6. 如請求項5之半導體裝置，其中各上述電極元件係溝槽式閘極電極。
  7. 如請求項5之半導體裝置，其中於第i個(i為1以上且N－1以下之整數)控制電極部所包含之上述複數個電極元件中之上述第2方向之排列順序之最後的電極元件、與第i＋1個控制電極部所包含之上述複數個電極元件中之上述第2方向之排列順序之最前的電極元件之間，連接第i個電阻元件。
  8. 如請求項1之半導體裝置，其中上述半導體裝置係以MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金屬氧化物半導體場效應電晶體)或IGBT(Insulated Gate Bipolar Transistor，絕緣閘雙極性電晶體)為基礎而構成。
  9. 一種半導體裝置，其具備： 基板； 第1主電極，其設置於上述基板之第1主面； 第2主電極，其設置於上述基板之與上述第1主面相反之第2主面； 複數個控制電極部，其等各自根據控制信號而控制於上述第1主電極與上述第2主電極之間流動之電流；以及 控制端子，其自外部接收上述控制信號；且 該控制電極部之電容與來自上述控制端子之上述控制信號之傳輸路徑之電阻值之積之值依每一上述控制電極部而不同。
  10. 一種電力轉換裝置，其使用請求項1之半導體裝置作為開關元件。
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