CN108242804A - 半导体器件和功率转换器 - Google Patents

半导体器件和功率转换器 Download PDF

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Publication number
CN108242804A
CN108242804A CN201711424028.8A CN201711424028A CN108242804A CN 108242804 A CN108242804 A CN 108242804A CN 201711424028 A CN201711424028 A CN 201711424028A CN 108242804 A CN108242804 A CN 108242804A
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Prior art keywords
semiconductor devices
electrode
gate electrode
coordination
main
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CN201711424028.8A
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Inventor
小嶋勇介
横井芳彦
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN108242804A publication Critical patent/CN108242804A/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/168—Modifications for eliminating interference voltages or currents in composite switches
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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    • H03K2217/0081—Power supply means, e.g. to the switch driver

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

本申请涉及半导体器件和功率转换器。旨在提供一种半导体器件，其能够防止关断时的浪涌电压，而不会使栅极驱动电路复杂化且不会使开关延迟增大。半导体器件具有以下配置，其中通过包括用于控制在第一主电极与第二主电极之间流动的电流的多个控制电极，将多个晶体管等效地并联耦合。来自公共控制端子的控制信号的传输路径的电阻值关于每个控制电极而变化。

Description

半导体器件和功率转换器
相关申请的交叉引用
这里通过参考并入2016年12月27日提交的日本专利申请No.2016-253709的全部公开内容，包括说明书、附图和摘要。
技术领域
例如，本发明涉及一种优选地用作用于功率转换器的开关元件的半导体器件。
背景技术
在用于功率转换器、双向开关等的半导体开关元件中，重要的是抑制关断期间的浪涌电压而不增加开关延迟。
例如，日本未审查专利申请公开No.HEI10(1998)-075164公开了其中栅极驱动电路加倍的半导体开关器件的配置。至于关断，第一栅极驱动电路从关断开始时操作，而第二栅极驱动电路在预定时间后操作。
作为另一实施例，上述日本未审查专利申请公开No.HEI10(1998)-075164还公开了一种配置，其中将专用于关断开始时的电路附加地提供给栅极驱动电路。专用于关断开始时的电路包括开关电路的公共端子和地电平之间的放电路径。
发明内容
在上述日本未审查专利申请公开No.HEI10(1998)-075164中公开的配置中存在的问题是，因为针对关断设置了两个电路，所以栅极驱动电路的配置变得复杂。其他问题和新颖特征将从本申请和附图的描述中变得显而易见。
在根据一个实施例的半导体器件中，用于控制流过第一主电极和第二主电极的主电流的控制电极被划分成多个部分。来自公共控制端子的控制信号的传输路径的电阻值不同于经划分的控制电极中的每一个。
根据上述实施例，可以提供一种能够控制在关断时的浪涌电压而不使栅极驱动电路复杂化并且不增加开关延迟的半导体器件。
附图说明
图1是示出根据第一实施例的半导体器件的配置的等效电路；
图2是图1所示的变形例的等效电路；
图3是示出图1所示的半导体器件的操作的时序图；
图4是示出与图1所示的等效电路对应的半导体器件的结构示例的平面图；
图5是沿着图4所示的剖面线V-V的横截面图；
图6是沿着图4所示的剖面线VI-VI的横截面图；
图7是示出制造图4至图6所示的半导体器件的方法的示例的流程图；
图8是示出根据第二实施例的半导体器件的配置的等效电路；
图9是示出与图8所示的等效电路对应的半导体器件的结构示例的平面图；
图10是沿着图9所示的剖面线X-X的横截面图；
图11是沿着图9所示的剖面线XI-XI的横截面图；
图12是示出在可再充电电池组中使用的双向开关的示例的电路图；以及
图13是示出逆变器器件的配置的电路图。
具体实施方式
以下，参照附图说明本发明的实施例。应该注意的是，相同或相应的部件用相同的数字表示，并且不重复其解释。
第一实施例
[半导体器件的一般配置]
图1是示出根据第一实施例的半导体器件的配置的等效电路。参照图1，半导体器件10是改进的N沟道MOSFET(金属氧化物半导体场效应晶体管)。在下文中MOSFET也被描述为“MOS晶体管”。
半导体器件10包括作为第一主电极的漏极电极DE、作为第二主电极的源极电极SE、作为多个控制电极部分的栅极电极部分GE1、GE2、GE3以及电阻元件R2、R3。应该注意，全部的栅极电极部分GE1、GE2、GE3或其中未指定的一个可以在下文中简称为“栅极电极部分GE”。
等同地，半导体器件10可以被认为是并联耦合的三个N沟道MOS晶体管Q1、Q2、Q3。MOS晶体管Q1、Q2、Q3共用漏极电极DE和源极电极SE。MOS晶体管Q1、Q2、Q3的导通-截止由通过MOS晶体管Q1、Q2、Q3的各栅极电极部分GE供给的栅极控制信号控制。以下，全部的MOS晶体管Q1、Q2、Q3或它们中的任何一个可以简称为“MOS晶体管Q”。
作为主电流的漏极电流Id在漏极电极DE与源极电极SE之间流动。等效地，漏极电流Id被划分成对应于多个栅极电极部分GE1、GE2、GE3的多个漏极电流分量Id1、Id2、Id3。根据提供给每个栅极电极部分GE的栅极控制信号来控制每个漏极电流分量Id1、Id2、Id3。实际上，流过每个栅极电极部分GE附近的沟道的电流分量由对应的栅极电极部分GE控制。
图1还示出了用于换向的二极管PD1、PD2、PD3，其以反向并联(反向偏置方向且并联)方式耦合到MOS晶体管Q1、Q2、Q3。当半导体器件10由垂直MOS晶体管构成时，二极管PD1、PD2、PD3可以是寄生二极管，或者可以是与MOS晶体管Q1、Q2、Q3无关地形成的二极管。
半导体器件10包括漏极端子DT、源极端子ST和栅极端子GT，以耦合到外部。漏极电极DE耦合到漏极端子DT，并且源极电极SE耦合到源极端子ST。作为主电流，漏极电流Id从漏极端子DT流向源极端子ST。
栅极端子GT被输入有栅极控制信号以控制漏极电流Id。通常，电阻元件R1耦合在半导体器件10外部的栅极信号输入端子GIT与栅极端子GT之间。电阻元件R1与半导体器件10一起被安装在印刷电路板上。通过调节电阻元件R1的电阻值，可以事后调节浪涌电压的大小和开关速度。
栅极电极部分GE1直接耦合到栅极端子GT，而没有经由电阻元件R2和R3中的任何一个。栅极电极部分GE2经由电阻元件R2耦合到栅极电极部分GE1。栅极电极部分GE3经由电阻元件R3耦合到栅极电极部分GE2。栅极端子GT与栅极电极部分GE1之间的电阻值小于电阻元件R2或R3的电阻值。因此，每个栅极电极部分GE1、GE2、GE3和栅极端子GT之间的控制信号路径的电阻值关于每个栅极电极部分GE而变化。在图1的情况下，栅极电阻按照栅极电极部分GE1、GE2、GE3的顺序增加。
图2是图1所示的变形例的等效电路。图2所示的半导体器件10M与图1所示的半导体器件10的不同之处在于，设置电阻元件R4、R5、R6，而不是图1中的电阻元件R2、R3。参考图2，栅极电极部分GE1经由电阻元件R4耦合到栅极端子GT。栅极电极部分GE2经由电阻元件R5耦合到栅极端子GT。栅极电极部分GE3经由电阻元件R6耦合到栅极端子GT。
这里假定电阻元件R6的电阻值大于电阻元件R5的电阻值，并且电阻元件R5的电阻值大于电阻元件R4的电阻值。因此，每个栅极电极部分GE1、GE2、GE3和栅极端子GT之间的控制信号路径的电阻值关于每个栅极电极而变化，并且这些电阻值之间的关系与图1所示情况相同。但是，在图2的情况下，电阻元件所占的面积较大。即，图1所示配置是有利的，因为可以减小电阻元件所需的面积。
因为图2中的其他特征与图1中的特征相同，所以相同或相应的部件用相同的标号表示，并且不重复其解释。
[半导体器件的操作]
下面描述图1所示的半导体器件10在关断时的操作。首先描述现有技术的半导体开关元件在关断时遇到的问题。
通常，对于存在于半导体电路的布线等中的电感L，在半导体开关元件关断时根据瞬间流过半导体开关元件的电流i的变化率di/dt产生浪涌电压L·(di/dt)。浪涌电压会导致半导体电路的故障。尽管浪涌电压可以通过将相对高的栅极电阻耦合到栅极电极而被适当地抑制，但是这种高栅极电阻会导致半导体开关元件的开关的显著延迟。如下所述，根据本实施例的半导体器件10可以抑制浪涌电压并且还抑制延迟量的增加。
图3是示出图1所示的半导体器件的操作的时序图。图3从上向下示出了在栅极信号输入端子GIT处的栅极输入电压Vin、在栅极电极部分GE1、GE2、GE3处的栅极电压Vg1、Vg2、Vg3、漏极电流Id和漏极电压Vd。
参照图1和图3，栅极输入电压Vin在时间t0作为栅极控制信号从高电平变为低电平。栅极控制信号经由电阻元件R1到达栅极电极部分GE1，经由电阻元件R1、R2到达栅极电极部分GE2，并经由电阻元件R1、R2、R3到达栅极电极部分GE3。分别流过图1所示的等效电路中的MOS晶体管Q1、Q2、Q3的漏极电流分量Id1、Id2、Id3是经划分的整个漏极电流Id，其小于整个漏极电流Id。
此外，因为通过改变MOS晶体管Q1、Q2、Q3的栅极电阻的值，信号的延迟量可以不同，所以栅极电压Vg1、Vg2、Vg3改变的定时被偏移。具体而言，在图3所示的情况下，具有最低栅极电阻的MOS晶体管Q1在时间t1开始断开。具有第二低栅极电阻的MOS晶体管Q2在随后的时间t2开始断开。具有最高栅极电阻的MOS晶体管Q3在随后的时间t3开始断开。
如上所述，根据本实施例的半导体器件等同地具有通过将栅极电极划分成多个部分而并联耦合多个MOS晶体管Q的配置。这可以减少流过每个MOSFET的漏极电流分量，因为通过划分漏极电流Id产生的电流分量流过每个MOS晶体管Q。此外，通过改变每个栅极电极部分GE中的栅极电阻的大小，每个MOS晶体管Q断开的定时偏移。因此，即使断开速度增加，电流i的变化率di/dt也可以减小，由此抑制浪涌的峰值电压。另外，由于各栅极电极部分GE中的栅极电阻的大小可以小于现有技术中的单个栅极电阻的大小，所以可以降低直到各MOS晶体管Q的栅极电压Vg降低到阈值电压为止时的栅极电荷放电时间。结果，可以在整个半导体器件10中减少断开时间。
[半导体器件的具体结构]
下面，以采用具有垂直结构的沟槽栅极MOSFET作为半导体器件10为例进行说明。使用垂直MOSFET可以实现如图1所示配置的半导体器件10，而几乎不改变现有技术的结构。
图4是表示与图1所示的等效电路对应的半导体器件的结构的示例的平面图。图5是沿着图4所示的剖面线V-V的横截面图。图6是沿着图4所示的剖面线VI-VI的横截面图。在以下描述中，平行于半导体衬底SUB的方向被视为X方向和Y方向，并且垂直于半导体衬底SUB的方向被视为Z方向。应该注意的是，在图4中没有示出层间绝缘层21和栅极绝缘膜23。还要注意的是，为了更好的理解，图4到图6所示部分的尺度与实际尺寸不成比例。
参照图4至图6所示，半导体器件10主要基于N型半导体衬底SUB形成。N型半导体衬底SUB具有包括用作N+型漏极层27的N+型半导体层和用作N-型漂移层26的N-型半导体层的双层结构。在以下描述中，将在+Z方向侧的N型半导体衬底SUB的表面称为第一主表面33或前表面(前表面)，并将-Z方向侧的表面称为第二主表面34或后表面。N+型半导体层位于第二主表面34侧上，N-型半导体层位于第一主表面33侧上。
如图5所示，半导体器件10包括从更靠近N型半导体衬底SUB的第一主表面33侧作为杂质形成在N-型漂移层26上方的N+型源极层24和P型基极层25。应当注意的是，P型基极层25的***没有被N+型源极层24涂覆。在该P型基极层25的***上方经由栅极绝缘膜23形成有***栅极电极12。
半导体器件10形成有从第一主表面33开始穿过N+型源极层24和P型基极层25到达N-型漂移层26内部的多个沟槽(凹槽)30。当从上面看半导体衬底SUB时，沟槽30沿Y方向延伸并沿X方向排列。栅极绝缘膜23形成在包括每个沟槽30的内表面的半导体衬底SUB的整个第一主表面33上方。作为填充的栅极电极的沟槽栅极电极12A至12F也经由栅极绝缘膜23形成在每个沟槽30内部。栅极电极12A至12F沿Y方向延伸。
沟槽栅极电极12A和12B对应于图1中所示的栅极电极部分GE1，并且经由稍后将描述的栅极布线11A而彼此电耦合。类似地，沟槽栅极电极12C和12D对应于图1所示的栅极电极部分GE2，并且经由稍后将描述的栅极布线11B彼此电耦合。沟槽栅极电极12E和12F对应于图1所示的栅极电极部分GE3，并且经由稍后将描述的栅极布线11C彼此电耦合。
以这种方式，每个栅极电极部分GE由彼此电耦合的多个电极元件构成。每个电极元件对应于每个沟槽栅极电极12A至12F。电极元件之间的电阻值小于图1所示的电阻元件R2、R3中的任何一个的电阻值。
半导体器件10还包括前述的***栅极电极12、层间绝缘层21以及电阻层18和19。
电阻层18例如由多晶硅形成，以便耦合栅极电极12B的端部部分和栅极电极12C的端部部分。电阻层19例如由多晶硅形成，以便耦合栅极电极12D的端部部分和栅极电极12E的端部部分。电阻层18对应于图1所示的电阻元件R2，电阻层19对应于图1所示的电阻元件R3。
层间绝缘层21形成在栅极绝缘膜23上方以覆盖栅极电极12A至12F、电阻层18和19以及***栅极电极12。
半导体器件10还包括金属源极电极16、金属漏极电极29、栅极布线11A、11B、11C和栅极焊盘11P。栅极布线11A和栅极焊盘11P一体形成。应该注意，全部的栅极布线11A、11B、11C或其中未指定的栅极布线在下文中可以简称为“栅极布线11”。
金属源极电极16形成在层间绝缘层21上方，并经由多个接触电极17与N+型源极层24和P型基极层25耦合。这些接触电极17布置在相邻的沟槽30之间并且在布置在最外面的沟槽30之外。各接触电极17穿过层间绝缘层21、栅极绝缘膜23和N+型源极层24而到达P型基极层25的内部。金属源极电极16对应于图1所示的源极电极SE。
金属漏极电极29形成为在半导体衬底SUB的后表面侧上与N+型漏极层27邻接。金属漏极电极29对应于图1所示的漏极电极DE。
栅极布线11A大致沿X方向延伸，并分别经由栅极电极12A、12B和接触电极15A、15B的端部部分耦合。栅极布线11A与栅极焊盘11P一体形成。栅极焊盘11P经由接触电极14进一步耦合到***栅极电极12。
栅极布线11B沿X方向延伸，并分别经由栅极电极12C、12D和接触电极15C、15D的端部部分耦合。栅极布线11C沿X方向延伸，并分别经由栅极电极12E、12F和接触电极15E、15F的端部部分耦合。因此，栅极布线11A和栅极布线11B经由电阻层18耦合，栅极布线11B和栅极布线11C经由电阻层19耦合。
在下文中，与现有技术配置相比，描述了上述半导体器件10的配置的特征。在现有技术的沟槽栅极MOSFET中，沟槽栅极电极12A至12F的端部部分经由公共栅极布线11彼此耦合。相反，在根据该实施例的半导体器件10中，栅极布线11被划分为多个部分，并且相邻的栅极布线经由电阻层18或19耦合。这可以实现图1所示的等效电路的配置，其中多个沟槽栅极电极12A至12F被划分为分别对应于多个栅极电极部分GE的多个组，并且相邻的栅极电极部分GE通过对应于电阻元件R的电阻层而耦合。应该注意的是，利用垂直MOSFET的结构，由于漏极电流流过每个沟槽栅极电极12A到12F附近的沟道区域，漏极电流不可避免地被划分成多个电流分量，该多个电流分量对应于多个栅极电极部分GE。图4至图6中的其它特征与现有技术的配置中的相同。因此，根据本实施例的半导体器件10几乎可以在不改变现有技术制造工艺的情况下制造。
[制造半导体器件的方法]
以下，以根据本实施例的半导体器件10的制造方法为例进行说明。
图7是示出制造图4至图6所示的半导体器件的方法的示例的流程图。参照图4至图6，首先制备由硅单晶制成的N型硅半导体衬底SUB(图7中的步骤S101)。
沟槽30从N型半导体衬底SUB的第一主表面33侧形成(步骤S102)。具体地，使用光刻工艺在第一主表面33上方形成用于形成沟槽的硬掩膜，并且使用该硬掩膜执行各向异性干法刻蚀以形成沟槽30。在形成沟槽30之后，硬掩膜通过湿法刻蚀去除。
通过例如热氧化，在N型半导体衬底SUB的几乎整个第一主表面33和沟槽30的几乎整个内表面上方形成栅极绝缘膜23(步骤S103)。
例如掺杂有磷的掺杂多晶硅(掺杂多晶硅)膜几乎形成在整个栅极绝缘膜23上方，以通过CVD(化学气相沉积)等填充沟槽30。除了栅极电极12A至12F和***栅极电极12之外的不必要的掺杂多晶硅膜通过例如湿法刻蚀而被去除。以这种方式，形成栅极电极12A至12F和***栅极电极12(步骤S104)。
在半导体衬底SUB的几乎整个第一主表面33侧上方形成多晶硅膜。通过离子注入杂质使形成的多晶硅膜的要成为电阻层18和19部分成为电阻性。多晶硅膜的除了电阻层18和19之外的剩余部分通过例如湿法刻蚀而被去除。形成电阻层18和19(步骤S105)。
使用通过光刻工艺形成的抗蚀剂膜作为掩膜，离子注入P型杂质。通过热扩散形成P型基极层25(步骤S106)。然后通过灰化等去除不需要的抗蚀剂膜。
使用通过光刻工艺形成的抗蚀剂膜作为掩膜，离子注入N型杂质。以此方式，在P型基极层25的上部区域中形成N+型源极层24(步骤S107)。通过灰化等去除不需要的抗蚀剂膜。
层间绝缘层21通过CVD、涂覆等形成在第一主表面33侧的几乎整个N型半导体衬底SUB上方(步骤S108)。作为层间绝缘层21的材料，例如可以使用PSG(磷硅玻璃)膜、BPSG(硼磷硅玻璃)膜、NSG(非掺杂硅酸盐玻璃)膜、SOG(旋涂玻璃)膜或者它们的复合膜。
在相邻的沟槽30之间以及最外侧的沟槽30之外形成用于与金属源极电极16耦合的接触凹槽31(步骤S109)。具体而言，例如，使用通过光刻工艺形成的抗蚀剂膜，通过各向异性干法刻蚀等形成接触凹槽31。通过灰化等去除不需要的抗蚀剂膜。
在栅极电极12A至12F的端部部分中形成用于与栅极布线11A至11C耦合的接触孔，并且在***栅极电极12之上形成用于与栅极焊盘11P耦合的接触沟(步骤S110)。具体而言，例如，通过使用由光刻工艺形成的抗蚀剂膜的各向异性干法刻蚀等来形成接触孔。通过灰化等去除不需要的抗蚀剂膜。
通过溅射膜形成等在N型半导体衬底SUB的几乎整个第一主表面33侧上方形成基于铝的金属厚膜。随后通过使用光刻工艺和刻蚀来刻蚀金属厚膜，形成栅极焊盘11P、栅极布线11A至11C、金属源极电极16以及接触电极17、15A至15F、14(步骤S111)。
通过研磨N型半导体衬底SUB的第二主表面34(后表面)来调节衬底的厚度(步骤S112)。
然后，通过溅射膜形成等在N型半导体衬底SUB的几乎整个第二主表面34上方形成金属漏极电极29(步骤S113)。通过上述工艺完成具有图4至图6所示配置的半导体器件10。
[效果]
如上所述，根据本实施例的半导体器件10基于MOSFET构成，并且具有以下配置：其中通过将栅极电极部分GE划分成多个部分而将多个MOSFET等效地并联连接。此外，根据本实施例的半导体器件10的特征在于并联耦合的MOSFET的栅极电阻值不同。因为这可以抵消在关断时MOSFET断开的时间，所以可以在可接受的浪涌电压的范围内增加每个MOSFET的断开速度(具体地增加电流变化速率di/dt)。结果，可以减少所有MOSFET的断开时间。
另外，由于与现有技术的MOSFET一样，外部耦合端子由包括栅极端子GT、源极端子ST和漏极端子DT的三个端子构成，所以能够实现抑制浪涌电压并且防止原样使用现有的栅极驱动电路而降低断开速度。抑制浪涌电压消除了过度确保构成***的组件的电压容限的必要性，从而降低了组件成本。
[变形例]
尽管以将栅极电极部分GE划分成三个为例描述了第一实施例，但栅极电极部分GE划分成的数量不一定是三。
通常，半导体器件包括N(N是等于或大于2的整数)个栅极电极部分GE和N-1个电阻元件R。在这种情况下，半导体器件具有以下配置：其中包括N个栅极电极部分GE的N个晶体管分别等效地并联耦合。第一栅极电极部分GE耦合到栅极端子GT用于接收栅极控制信号，而没有经由N-1个电阻元件R中的任何一个。第i+1(i是大于或等于1并且小于或等于N-1的整数)个栅极电极部分GE经由第i电阻元件R耦合到第i个栅极电极部分GE。以此方式，来自栅极端子GT的栅极控制信号的传输路径的电阻值可以关于每个栅极电极部分GE而改变。
此外，关于上述的一般配置给出了描述，其中每个栅极电极部分GE由沿第一方向延伸并沿第二方向排列的多个电极元件(例如，沟槽栅极电极)构成。在这种情况下，如果在第二方向上按照数字顺序排列N个栅极电极部分GE，则第i个(i是大于或等于1且小于或等于N-1的整数)电阻元件耦合在第i+1个栅极电极中所包含的多个电极元件中按第二方向排列顺序的第一个电极元件与第i个栅极电极中所包含的多个电极元件中按第二方向排列顺序的最后一个电极元件之间。
尽管以构成各栅极电极部分GE的各电极元件由沟槽栅极构成的情况为例描述了第一实施例，但各电极元件可以构成为平面栅极电极。此外，虽然以垂直MOSGET为例描述了第一实施例，但是上述技术也可以适用于横向MOSFET。
尽管第一实施例是以栅极电阻值关于每个划分的栅极电极部分GE变化的示例来描述的，但是更一般地，每个栅极电极部分GE的电容值和栅极电阻值的乘积彼此不同即可。例如，通过改变栅极宽度(具体而言，包括沟槽栅极的数量)，可以关于每个栅极电极部分GE改变电容。
第二实施例
以基于IGBT(绝缘栅双极型晶体管)配置半导体器件为例来说明第二实施例。第一实施例中描述的技术不仅可以适用于下面描述的IGBT，而且可以适用于各种类型的晶体管。
图8是示出根据第二实施例的半导体器件的配置的等效电路。参照图8，半导体器件40基于IGBT而被配置，并且包括作为第一主电极的集电极电极CE、作为第二主电极的发射极电极EE、作为多个控制电极的栅极电极部分GE1、GE2、GE3、电阻元件R2、R3和二极管D。
在图8的情况中，与图1相比，代替漏极电极DE而设置集电极电极CE，并且代替源极电极SE而设置发射极电极EE。等同地，半导体器件40可以被视为并联耦合的一组三个IGBTQ11、Q12、Q13。在这种情况下，作为主电流的集电极电流Ic被划分成分别对应于多个栅极电极部分GE1、GE2、GE3的多个集电极电流分量Ic1、Ic2、Ic3。
半导体器件40包括集电极端子CT、发射极端子ET和栅极端子GT，以耦合到外部。集电极端子CT与集电极电极CE耦合，发射极端子ET与发射极电极EE耦合。栅极端子GT直接耦合到栅极电极部分GE1，并经由电阻元件R2间接耦合到栅极电极部分GE2。而且，栅极电极部分GE2经由电阻元件R3与栅极电极部分GE3耦合。
因为IGBT原则上不包括寄生二极管，所以用于电流换向的二极管D在反向偏置方向上耦合在集电极端子CT和发射极端子ET之间，即，二极管D的阳极耦合到发射极端子ET。尽管图8示出了将二极管D并入半导体器件40中的情况，但二极管D也可以安装在半导体器件40的外部。
因为图8中的其他特征与图1中的特征相同，所以相同或相应的部件用相同的标号表示，并且不重复其说明。以下描述半导体器件40的具体结构。
图9是示出与图8所示的等效电路对应的半导体器件的结构的一个示例的平面图。图10是沿着图9所示的剖面线XX截取的横截面图。图11是沿着图9所示的剖面线XI-XI截取的横截面图。在下面的描述中，平行于N-型半导体衬底SUB的方向被认为是X方向和Y方向，并且垂直于N-型半导体衬底SUB的方向被认为是Z方向。应该注意的是，在图9中没有示出层间绝缘层51和栅极绝缘膜53。还要注意的是，为了更好地理解，图9到图11所示部分的尺寸与实际尺寸不成比例。
参照图9至图11，半导体器件40主要基于用作N-型漂移层56的N-型半导体衬底SUB形成。在以下描述中，N-型半导体衬底SUB的在+Z方向侧的表面被称为第一主表面63或前表面(前面)，-Z方向侧的表面被称为第二主表面64或后表面。
如图10所示，作为杂质层，半导体器件40包括从更靠近N-型半导体衬底SUB的第一主表面63侧的N+型发射极层54和P型基极层55，并且包括从更靠近第二主表面64侧的P+型集电极层58和N+型场停止层57。与参考图4至图6描述的MOSFET相比的结构差异在于，P+型集电极层58作为杂质层进一步形成在N-型半导体衬底SUB的第二主表面64的最外面上方。
应该注意的是，P型基极层55的***没有涂覆有N+型发射极层54。经由栅极绝缘膜53在该P型基极层55的***上方形成的是***栅极电极42。
半导体器件40形成有从第一主表面63开始穿过N+型发射极层54和P型基极层55到达N-型漂移层56的内部的多个沟槽(沟)60。当从上面看N-型半导体衬底SUB时，沟槽60沿Y方向延伸并沿着X方向排列。半导体器件40包括在每个沟槽60的内部表面上方形成的栅极绝缘膜53以及经由栅极绝缘膜53填充在每个沟槽60中的作为嵌入电极的沟槽栅极电极42A至42F。
沟槽栅极电极42A和42B经由稍后将描述的栅极布线41A彼此电耦合，并且对应于图8所示的栅极电极部分GE1。类似地，沟槽栅极电极42C和42D经由后述的栅极布线41B彼此电耦合，并且与图8所示的栅极电极部分GE2对应。沟槽栅极电极42E和42F经由后述的栅极布线41C彼此电耦合，并且对应于图8所示的栅极电极部分GE。
以这种方式，每个栅极电极部分GE由彼此电耦合的多个电极元件配置。每个电极元件对应于每个沟槽栅极电极42A至42F。电极元件之间的电阻值小于图8所示的电阻元件R2、R3中的任一个的电阻值。
半导体器件40还包括前述的***栅极电极42、层间绝缘层51以及电阻层48和49。
***栅极电极42以及电阻层48和49形成在栅极绝缘膜53上方。电阻层48由例如多晶硅形成，以便耦合沟槽栅极电极42B的端部部分和沟槽栅极电极42C的端部部分。电阻层49例如由多晶硅形成，以便耦合沟槽栅极电极42D的端部部分和沟槽栅极电极42E的端部部分。电阻层48对应于图8所示的电阻元件R2，电阻层49对应于图8所示的电阻元件R3。
层间绝缘层51形成在栅极绝缘膜53上方以覆盖沟槽栅极电极42A至42F、电阻层48和49以及***栅极电极42。
半导体器件40还包括金属发射极电极46、金属集电极电极59、栅极布线41A、41B、41C和栅极焊盘41P。栅极布线41A和栅极焊盘41P一体形成。
金属发射极电极46形成在层间绝缘层51上方，并且经由多个接触电极47与N+型发射极层54和P型基极层55耦合。这些接触电极47布置在相邻的沟槽60之间并且在布置在最外面的外部沟槽60之外。每个接触电极47穿过层间绝缘层51、栅极绝缘膜53和N+型发射极层54以到达P型基极层55的内部。金属发射极电极46对应于图8所示的发射极电极EE 8。
金属集电极电极59形成为在N-型半导体衬底SUB的后表面侧上邻接P+型集电极层58。金属集电极电极59对应于图8所示的集电极电极CE。
栅极布线41A大致在X方向延伸，并分别经由接触电极45A、45B的端部部分而耦合。栅极布线41A与栅极焊盘41P一体地形成。栅极焊盘41P经由接触电极44耦合到栅极电极42。
栅极布线41B沿X方向延伸，并分别经由栅极电极42C和42D以及接触电极45C和45D的端部部分而耦合。栅极布线41C沿X方向延伸并且分别经由栅极电极42E和42F以及接触电极45E和45F的端部部分而耦合。因此，栅极布线41A和栅极布线41B经由电阻层48耦合，并且栅极布线41B和栅极布线41C经由电阻层49耦合。
与第一实施例中的MOSFET一样，除了电阻层48和49之外，半导体器件40的配置与现有技术的沟槽栅极型IGBT相同。因此，可以在几乎不改变现有技术的制造工艺的情况下制造根据本实施例的半导体器件40。
尽管以配置各栅极电极部分GE的各电极元件由沟槽栅极配置的情况为例描述了上述实施例，但也可以将各电极元件配置为平面栅极电极。
如上所述，根据本实施例的半导体器件40基于IGBT而配置，并具有以下配置：通过将栅极电极部分GE划分成多个部分，将多个IGBT等效地并联布置。此外，根据本实施例的半导体器件40的特征在于，并联耦合的IGBT的栅极电阻值不同。因为这可以偏移在关断时IGBT断开的定时，所以可以在可接受的浪涌电压的范围内增加每个IGBT的断开速度(具体地增加电流变化率di/dt)。结果，可以减少构成半导体器件40的所有IGBT的断开时间。另外，如同现有技术的IGBT那样，由于外部耦合端子由包括栅极端子GT、发射极端子ET、集电极端子CT的三个端子构成，所以与使用现有的栅极驱动电路一样，能够起到抑制浪涌电压并防止降低断开速度的效果。
虽然以栅极电阻值关于各划分的栅极电极部分GE变化为例描述了第二实施例，但更一般地，各栅极电极部分GE的电容值与栅极电阻值的乘积彼此不同即可。例如，通过改变栅极宽度(具体而言，包括的沟槽栅极的数量)，可以关于每个栅极电极部分GE来改变电容。
第三实施例
以使用根据第一实施例的半导体器件10作为双向开关为例来说明第三实施例。根据第二实施例的半导体器件40可以类似地被用作根据本实施例的双向开关。
图12是示出用于可再充电电池组中的双向开关的示例的电路图。参考图12，可再充电电池组70包括双向开关75、电池(可再充电电池)72和控制IC(集成电路)73。控制IC 73控制双向开关75的接通和断开，并监视电池72的水平。
双向开关75包括作为放电MOSFET的半导体器件10和作为与半导体器件10反串联耦合的充电MOSFET的半导体器件71。
半导体器件10具有与第一实施例中所述配置相同的配置。半导体器件10的栅极端子GT经由电阻元件R1与控制IC 73耦合。半导体器件71具有与现有技术的MOSFET相同的结构。半导体器件71的栅极电极部分GE71直接耦合到栅极端子GT71，并且栅极端子GT71经由电阻元件R71耦合到控制IC 73。
在用于放电的半导体器件10中，漏极端子DT耦合到电池72侧，并且源极端子ST耦合到***侧的端子74。在用于充电的半导体器件71中，漏极端子DT71耦合到端子74侧，源极端子ST71连接到电池72。半导体器件10和半导体器件71可以以相反的顺序耦合。
在充电时，根据控制IC 73的控制，构成半导体器件10的MOSFET成为截止状态，并且构成半导体器件71的MOSFET成为导通状态。这允许充电电流从***侧的电源通过半导体器件10中的寄生二极管和半导体器件71中的MOSFET流到电池72。
另一方面，在放电时，根据控制IC 73的控制，构成半导体器件10的MOSFET成为导通状态，并且构成半导体器件71的MOSFET成为截止状态。这允许放电电流通过半导体器件10中的MOSFET和半导体器件71中的寄生二极管PD71从电池72流向***侧。
当由于***故障等而检测到过电流时，构成半导体器件10的MOSFET需要被快速关断。在这种情况下，因为可再充电电池组70的电路中和电池72的单元中存在寄生电感，所以由于MOSFET的关断导致的电流断开造成浪涌电压。
现在，如在第一实施例中所述，半导体器件10具有如下配置，其中通过将栅极电极部分GE划分成多个部分，多个MOSFET被等效地并联耦合。此外，半导体器件10的特征在于并联耦合的MOSFET的栅极电阻值不同。因为这可以偏移在关断时MOSFET断开的定时，所以可以在保持浪涌电压在可接受的范围内的同时减少断开时间。
第四实施例
以将根据第一实施例的半导体器件10应用于逆变器器件的开关元件的示例来说明第四实施例。根据第一实施例的半导体器件10和根据第二实施例的半导体器件40不仅可以用作逆变器器件的开关元件，而且可以用作各种功率转换器的开关元件。
图13是示出逆变器器件的配置的电路图。参考图13，逆变器器件80包括半导体器件10UP、10UN、10VP、10VN、10WP、10WN和分别驱动这些半导体器件的栅极驱动器GD_UP、GD_UN、GD_VP、GD_VN、GD_WP、GD_WN。应该注意的是，逆变器器件80可以被配置为其中半导体器件被安装在同一封装中的功率模块。
半导体器件10UP和半导体器件10UN串联耦合在高电压侧功率线81P和低电压侧功率线81N之间。在高电压侧功率线81P和低电压侧功率线81N之间施加直流电压。类似地，半导体器件10VP和半导体器件10VN串联耦合在高电压侧功率线81P和低电压侧功率线81N之间。半导体器件10WP和半导体器件10WN串联耦合在高电压侧功率线81P和低电压侧功率线81N之间。应该注意的是，每个半导体器件的漏极端子DT耦合到高电压侧，并且源极端子ST耦合到低电压侧。
从半导体器件10UP与半导体器件10UN之间的耦合节点82U向电机83供给U相交流电压。从半导体器件10VP和半导体器件10VN之间的耦合节点82V向电机83供给V相交流电压。从半导体器件10WP与半导体器件10WN之间的耦合节点82W向电机83供给W相。
在图13所示的配置中，当开关各个半导体器件时，浪涌电压由电机83的定子绕组、逆变器器件80的布线等中存在的电感引起。根据本实施例的逆变器器件80具有这样的配置，其中如第一实施例中所述，通过将栅极电极部分GE划分成多个部分，将多个MOSFET等效地并联耦合。此外，每个半导体器件的特征在于并联耦合的MOSFET的栅极电阻值不同。因为这可以偏移配置半导体器件的MOSFET开关的定时，所以使得在将浪涌电压保持在可接受的范围内的同时快速开关是可能的。
尽管基于实施例具体描述了本发明人做出的发明，但不用说，本发明不限于上述实施例，并且可以在不脱离本发明的精神的情况下以各种方式进行修改。

Claims (10)

1.一种半导体器件，包括：
第一主电极；
第二主电极；
多个控制电极部分，每个控制电极部分根据控制信号控制在所述第一主电极和所述第二主电极之间流动的电流；和
控制端子，所述控制端子从外部接收所述控制信号，
其中所述控制电极部分的电容值和所述控制信号的传输路径的电阻值的乘积关于每个控制电极部分而变化。
2.根据权利要求1所述的半导体器件，
其中来自所述控制端子的所述控制信号的所述传输路径的所述电阻值关于所述每个控制电极部分而变化。
3.根据权利要求2所述的半导体器件，
其中所述半导体器件包括作为所述控制电极部分的N个(N是等于或大于2的整数)控制电极部分，
其中所述半导体器件还包括N-1个电阻元件，
其中第一控制电极部分耦合到所述控制端子，而没有经由所述N-1个电阻元件中的任何一个，以及
其中第i+1个(i是等于或大于1且等于或小于N-1的整数)控制电极部分经由第i个电阻元件耦合到第i个控制电极部分。
4.根据权利要求3所述的半导体器件，
其中所述第一主电极设置在衬底的第一主表面上方，以及
其中所述第二主电极设置在所述衬底的与所述第一主表面相对的第二主表面上方。
5.根据权利要求4所述的半导体器件，
其中每个所述控制电极部分设置在所述衬底的所述第一主表面侧上方并且包括彼此电耦合的多个电极元件，
其中每个所述电极元件沿着所述第一主表面在第一方向上延伸，并且所述电极元件大致沿着所述第一主表面平行于第二方向而布置，以及
所述电极元件之间的电阻值小于所述N-1个电阻元件中的任何一个的电阻值。
6.根据权利要求5所述的半导体器件，其中每个所述电极元件是沟槽栅极电极。
7.根据权利要求5所述的半导体器件，
其中第i个(i是等于或大于1且等于或小于N-1的整数)电阻元件耦合在被包括在第i个控制电极部分中的电极元件中沿所述第二方向排列顺序中的最后一个电极元件与被包括在第i+1个控制电极部分的电极元件中沿所述第二方向排列顺序中的第一个电极元件之间。
8.根据权利要求1所述的半导体器件，
其中所述半导体器件是基于MOSFET(金属氧化物半导体场效应晶体管)或IGBT(绝缘栅双极晶体管)配置的。
9.一种半导体器件，包括：
衬底；
第一主电极，设置在所述衬底的第一主表面上方；
第二主电极，设置在所述衬底的与所述第一主表面相对的第二主表面上方；
多个控制电极部分，每个控制电极部分根据控制信号控制在所述第一主电极和所述第二主电极之间流动的电流；和
控制端子，所述控制端子从外部接收所述控制信号，
其中所述控制电极部分的电容值和所述控制信号的传输路径的电阻值的乘积关于每个控制电极部分而变化。
10.一种功率转换器，使用根据权利要求1所述的半导体器件作为开关元件。
CN201711424028.8A 2016-12-27 2017-12-25 半导体器件和功率转换器 Pending CN108242804A (zh)

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